2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $
29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.4 2003/11/20 22:07:28 dillon Exp $
33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/malloc.h>
40 /* #include <sys/mutex.h> */
41 #include <sys/kernel.h>
42 #include <sys/socket.h>
43 #include <sys/sysctl.h>
46 #include <net/if_dl.h>
47 #include <net/if_media.h>
51 #include <netns/ns_if.h>
55 #include <sys/sockio.h>
57 #include <machine/bus.h>
59 #include <machine/resource.h>
61 #include <net/ethernet.h>
62 #include <net/if_arp.h>
64 #include <vm/vm.h> /* for vtophys */
65 #include <vm/pmap.h> /* for vtophys */
66 #include <machine/clock.h> /* for DELAY */
68 #include <net/if_types.h>
69 #include <net/vlan/if_vlan_var.h>
71 #include <bus/pci/pcivar.h>
72 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */
74 #include "../mii_layer/mii.h"
75 #include "../mii_layer/miivar.h"
77 #include "if_fxpreg.h"
78 #include "if_fxpvar.h"
81 #include "miibus_if.h"
84 * NOTE! On the Alpha, we have an alignment constraint. The
85 * card DMAs the packet immediately following the RFA. However,
86 * the first thing in the packet is a 14-byte Ethernet header.
87 * This means that the packet is misaligned. To compensate,
88 * we actually offset the RFA 2 bytes into the cluster. This
89 * alignes the packet after the Ethernet header at a 32-bit
90 * boundary. HOWEVER! This means that the RFA is misaligned!
92 #define RFA_ALIGNMENT_FUDGE 2
95 * Set initial transmit threshold at 64 (512 bytes). This is
96 * increased by 64 (512 bytes) at a time, to maximum of 192
97 * (1536 bytes), if an underrun occurs.
99 static int tx_threshold = 64;
102 * The configuration byte map has several undefined fields which
103 * must be one or must be zero. Set up a template for these bits
104 * only, (assuming a 82557 chip) leaving the actual configuration
107 * See struct fxp_cb_config for the bit definitions.
109 static u_char fxp_cb_config_template[] = {
110 0x0, 0x0, /* cb_status */
111 0x0, 0x0, /* cb_command */
112 0x0, 0x0, 0x0, 0x0, /* link_addr */
143 * Claim various Intel PCI device identifiers for this driver. The
144 * sub-vendor and sub-device field are extensively used to identify
145 * particular variants, but we don't currently differentiate between
148 static struct fxp_ident fxp_ident_table[] = {
149 { 0x1029, "Intel 82559 PCI/CardBus Pro/100" },
150 { 0x1030, "Intel 82559 Pro/100 Ethernet" },
151 { 0x1031, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
152 { 0x1032, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
153 { 0x1033, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
154 { 0x1034, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
155 { 0x1035, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
156 { 0x1036, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
157 { 0x1037, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
158 { 0x1038, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
159 { 0x1039, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
160 { 0x103A, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
161 { 0x103B, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
162 { 0x103C, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
163 { 0x103D, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
164 { 0x103E, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
165 { 0x1050, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
166 { 0x1059, "Intel 82551QM Pro/100 M Mobile Connection" },
167 { 0x1209, "Intel 82559ER Embedded 10/100 Ethernet" },
168 { 0x1229, "Intel 82557/8/9 EtherExpress Pro/100(B) Ethernet" },
169 { 0x2449, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
173 static int fxp_probe(device_t dev);
174 static int fxp_attach(device_t dev);
175 static int fxp_detach(device_t dev);
176 static int fxp_shutdown(device_t dev);
177 static int fxp_suspend(device_t dev);
178 static int fxp_resume(device_t dev);
180 static void fxp_intr(void *xsc);
181 static void fxp_intr_body(struct fxp_softc *sc,
182 u_int8_t statack, int count);
184 static void fxp_init(void *xsc);
185 static void fxp_tick(void *xsc);
186 static void fxp_powerstate_d0(device_t dev);
187 static void fxp_start(struct ifnet *ifp);
188 static void fxp_stop(struct fxp_softc *sc);
189 static void fxp_release(struct fxp_softc *sc);
190 static int fxp_ioctl(struct ifnet *ifp, u_long command,
192 static void fxp_watchdog(struct ifnet *ifp);
193 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm);
194 static int fxp_mc_addrs(struct fxp_softc *sc);
195 static void fxp_mc_setup(struct fxp_softc *sc);
196 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
198 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
200 static void fxp_autosize_eeprom(struct fxp_softc *sc);
201 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
202 int offset, int words);
203 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
204 int offset, int words);
205 static int fxp_ifmedia_upd(struct ifnet *ifp);
206 static void fxp_ifmedia_sts(struct ifnet *ifp,
207 struct ifmediareq *ifmr);
208 static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
209 static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
210 struct ifmediareq *ifmr);
211 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg);
212 static void fxp_miibus_writereg(device_t dev, int phy, int reg,
214 static void fxp_load_ucode(struct fxp_softc *sc);
215 static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
217 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
218 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
219 static __inline void fxp_lwcopy(volatile u_int32_t *src,
220 volatile u_int32_t *dst);
221 static __inline void fxp_scb_wait(struct fxp_softc *sc);
222 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
223 static __inline void fxp_dma_wait(volatile u_int16_t *status,
224 struct fxp_softc *sc);
226 static device_method_t fxp_methods[] = {
227 /* Device interface */
228 DEVMETHOD(device_probe, fxp_probe),
229 DEVMETHOD(device_attach, fxp_attach),
230 DEVMETHOD(device_detach, fxp_detach),
231 DEVMETHOD(device_shutdown, fxp_shutdown),
232 DEVMETHOD(device_suspend, fxp_suspend),
233 DEVMETHOD(device_resume, fxp_resume),
236 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
237 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
242 static driver_t fxp_driver = {
245 sizeof(struct fxp_softc),
248 static devclass_t fxp_devclass;
250 DECLARE_DUMMY_MODULE(if_fxp);
251 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1);
252 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0);
253 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0);
254 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
257 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events");
260 * Inline function to copy a 16-bit aligned 32-bit quantity.
263 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst)
268 volatile u_int16_t *a = (volatile u_int16_t *)src;
269 volatile u_int16_t *b = (volatile u_int16_t *)dst;
277 * Wait for the previous command to be accepted (but not necessarily
281 fxp_scb_wait(struct fxp_softc *sc)
285 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
288 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
289 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
290 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
291 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
292 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
296 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
299 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
300 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
303 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
307 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc)
311 while (!(*status & FXP_CB_STATUS_C) && --i)
314 device_printf(sc->dev, "DMA timeout\n");
318 * Return identification string if this is device is ours.
321 fxp_probe(device_t dev)
324 struct fxp_ident *ident;
326 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
327 devid = pci_get_device(dev);
328 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
329 if (ident->devid == devid) {
330 device_set_desc(dev, ident->name);
339 fxp_powerstate_d0(device_t dev)
341 #if __FreeBSD_version >= 430002
342 u_int32_t iobase, membase, irq;
344 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
345 /* Save important PCI config data. */
346 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4);
347 membase = pci_read_config(dev, FXP_PCI_MMBA, 4);
348 irq = pci_read_config(dev, PCIR_INTLINE, 4);
350 /* Reset the power state. */
351 device_printf(dev, "chip is in D%d power mode "
352 "-- setting to D0\n", pci_get_powerstate(dev));
354 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
356 /* Restore PCI config data. */
357 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4);
358 pci_write_config(dev, FXP_PCI_MMBA, membase, 4);
359 pci_write_config(dev, PCIR_INTLINE, irq, 4);
365 fxp_attach(device_t dev)
368 struct fxp_softc *sc = device_get_softc(dev);
372 int i, rid, m1, m2, prefer_iomap;
375 bzero(sc, sizeof(*sc));
377 callout_handle_init(&sc->stat_ch);
378 sysctl_ctx_init(&sc->sysctl_ctx);
379 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
384 * Enable bus mastering. Enable memory space too, in case
385 * BIOS/Prom forgot about it.
387 val = pci_read_config(dev, PCIR_COMMAND, 2);
388 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
389 pci_write_config(dev, PCIR_COMMAND, val, 2);
390 val = pci_read_config(dev, PCIR_COMMAND, 2);
392 fxp_powerstate_d0(dev);
395 * Figure out which we should try first - memory mapping or i/o mapping?
396 * We default to memory mapping. Then we accept an override from the
397 * command line. Then we check to see which one is enabled.
400 m2 = PCIM_CMD_PORTEN;
402 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
403 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
404 m1 = PCIM_CMD_PORTEN;
410 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
411 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
412 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
413 0, ~0, 1, RF_ACTIVE);
415 if (sc->mem == NULL && (val & m2)) {
417 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
418 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
419 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
420 0, ~0, 1, RF_ACTIVE);
424 device_printf(dev, "could not map device registers\n");
429 device_printf(dev, "using %s space register mapping\n",
430 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
433 sc->sc_st = rman_get_bustag(sc->mem);
434 sc->sc_sh = rman_get_bushandle(sc->mem);
437 * Allocate our interrupt.
440 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
441 RF_SHAREABLE | RF_ACTIVE);
442 if (sc->irq == NULL) {
443 device_printf(dev, "could not map interrupt\n");
448 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
449 fxp_intr, sc, &sc->ih);
451 device_printf(dev, "could not setup irq\n");
456 * Reset to a stable state.
458 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
461 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
462 M_DEVBUF, M_NOWAIT | M_ZERO);
463 if (sc->cbl_base == NULL)
466 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF,
468 if (sc->fxp_stats == NULL)
471 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT);
472 if (sc->mcsp == NULL)
476 * Pre-allocate our receive buffers.
478 for (i = 0; i < FXP_NRFABUFS; i++) {
479 if (fxp_add_rfabuf(sc, NULL) != 0) {
485 * Find out how large of an SEEPROM we have.
487 fxp_autosize_eeprom(sc);
490 * Determine whether we must use the 503 serial interface.
492 fxp_read_eeprom(sc, &data, 6, 1);
493 if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
494 (data & FXP_PHY_SERIAL_ONLY))
495 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
498 * Create the sysctl tree
500 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
501 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
502 device_get_nameunit(dev), CTLFLAG_RD, 0, "");
503 if (sc->sysctl_tree == NULL)
505 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
506 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
507 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I",
508 "FXP driver receive interrupt microcode bundling delay");
509 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
510 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
511 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I",
512 "FXP driver receive interrupt microcode bundle size limit");
515 * Pull in device tunables.
517 sc->tunable_int_delay = TUNABLE_INT_DELAY;
518 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
519 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
520 "int_delay", &sc->tunable_int_delay);
521 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
522 "bundle_max", &sc->tunable_bundle_max);
525 * Find out the chip revision; lump all 82557 revs together.
527 fxp_read_eeprom(sc, &data, 5, 1);
528 if ((data >> 8) == 1)
529 sc->revision = FXP_REV_82557;
531 sc->revision = pci_get_revid(dev);
534 * Enable workarounds for certain chip revision deficiencies.
536 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
537 * some systems based a normal 82559 design, have a defect where
538 * the chip can cause a PCI protocol violation if it receives
539 * a CU_RESUME command when it is entering the IDLE state. The
540 * workaround is to disable Dynamic Standby Mode, so the chip never
541 * deasserts CLKRUN#, and always remains in an active state.
543 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
545 i = pci_get_device(dev);
546 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
547 sc->revision >= FXP_REV_82559_A0) {
548 fxp_read_eeprom(sc, &data, 10, 1);
549 if (data & 0x02) { /* STB enable */
554 "Disabling dynamic standby mode in EEPROM\n");
556 fxp_write_eeprom(sc, &data, 10, 1);
557 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
559 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
560 fxp_read_eeprom(sc, &data, i, 1);
563 i = (1 << sc->eeprom_size) - 1;
564 cksum = 0xBABA - cksum;
565 fxp_read_eeprom(sc, &data, i, 1);
566 fxp_write_eeprom(sc, &cksum, i, 1);
568 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
572 * If the user elects to continue, try the software
573 * workaround, as it is better than nothing.
575 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
581 * If we are not a 82557 chip, we can enable extended features.
583 if (sc->revision != FXP_REV_82557) {
585 * If MWI is enabled in the PCI configuration, and there
586 * is a valid cacheline size (8 or 16 dwords), then tell
587 * the board to turn on MWI.
589 if (val & PCIM_CMD_MWRICEN &&
590 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
591 sc->flags |= FXP_FLAG_MWI_ENABLE;
593 /* turn on the extended TxCB feature */
594 sc->flags |= FXP_FLAG_EXT_TXCB;
596 /* enable reception of long frames for VLAN */
597 sc->flags |= FXP_FLAG_LONG_PKT_EN;
603 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3);
604 device_printf(dev, "Ethernet address %6D%s\n",
605 sc->arpcom.ac_enaddr, ":",
606 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : "");
608 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
609 pci_get_vendor(dev), pci_get_device(dev),
610 pci_get_subvendor(dev), pci_get_subdevice(dev),
612 fxp_read_eeprom(sc, &data, 10, 1);
613 device_printf(dev, "Dynamic Standby mode is %s\n",
614 data & 0x02 ? "enabled" : "disabled");
618 * If this is only a 10Mbps device, then there is no MII, and
619 * the PHY will use a serial interface instead.
621 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
622 * doesn't have a programming interface of any sort. The
623 * media is sensed automatically based on how the link partner
624 * is configured. This is, in essence, manual configuration.
626 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
627 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
628 fxp_serial_ifmedia_sts);
629 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
630 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
632 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
634 device_printf(dev, "MII without any PHY!\n");
640 ifp = &sc->arpcom.ac_if;
641 ifp->if_unit = device_get_unit(dev);
642 ifp->if_name = "fxp";
643 ifp->if_output = ether_output;
644 ifp->if_baudrate = 100000000;
645 ifp->if_init = fxp_init;
647 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
648 ifp->if_ioctl = fxp_ioctl;
649 ifp->if_start = fxp_start;
650 ifp->if_watchdog = fxp_watchdog;
653 * Attach the interface.
655 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
658 * Tell the upper layer(s) we support long frames.
660 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
663 * Let the system queue as many packets as we have available
666 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
672 device_printf(dev, "Failed to malloc memory\n");
681 * release all resources
684 fxp_release(struct fxp_softc *sc)
687 bus_generic_detach(sc->dev);
689 device_delete_child(sc->dev, sc->miibus);
692 free(sc->cbl_base, M_DEVBUF);
694 free(sc->fxp_stats, M_DEVBUF);
696 free(sc->mcsp, M_DEVBUF);
698 m_freem(sc->rfa_headm);
701 bus_teardown_intr(sc->dev, sc->irq, sc->ih);
703 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
705 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem);
707 sysctl_ctx_free(&sc->sysctl_ctx);
709 mtx_destroy(&sc->sc_mtx);
716 fxp_detach(device_t dev)
718 struct fxp_softc *sc = device_get_softc(dev);
721 /* disable interrupts */
722 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
727 * Stop DMA and drop transmit queue.
732 * Close down routes etc.
734 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED);
737 * Free all media structures.
739 ifmedia_removeall(&sc->sc_media);
743 /* Release our allocated resources. */
750 * Device shutdown routine. Called at system shutdown after sync. The
751 * main purpose of this routine is to shut off receiver DMA so that
752 * kernel memory doesn't get clobbered during warmboot.
755 fxp_shutdown(device_t dev)
758 * Make sure that DMA is disabled prior to reboot. Not doing
759 * do could allow DMA to corrupt kernel memory during the
760 * reboot before the driver initializes.
762 fxp_stop((struct fxp_softc *) device_get_softc(dev));
767 * Device suspend routine. Stop the interface and save some PCI
768 * settings in case the BIOS doesn't restore them properly on
772 fxp_suspend(device_t dev)
774 struct fxp_softc *sc = device_get_softc(dev);
781 for (i = 0; i < 5; i++)
782 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
783 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
784 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
785 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
786 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
795 * Device resume routine. Restore some PCI settings in case the BIOS
796 * doesn't, re-enable busmastering, and restart the interface if
800 fxp_resume(device_t dev)
802 struct fxp_softc *sc = device_get_softc(dev);
803 struct ifnet *ifp = &sc->sc_if;
804 u_int16_t pci_command;
809 fxp_powerstate_d0(dev);
811 /* better way to do this? */
812 for (i = 0; i < 5; i++)
813 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
814 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
815 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
816 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
817 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
819 /* reenable busmastering */
820 pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
821 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
822 pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
824 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
827 /* reinitialize interface if necessary */
828 if (ifp->if_flags & IFF_UP)
838 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
846 for (x = 1 << (length - 1); x; x >>= 1) {
848 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
850 reg = FXP_EEPROM_EECS;
851 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
853 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
855 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
861 * Read from the serial EEPROM. Basically, you manually shift in
862 * the read opcode (one bit at a time) and then shift in the address,
863 * and then you shift out the data (all of this one bit at a time).
864 * The word size is 16 bits, so you have to provide the address for
865 * every 16 bits of data.
868 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
873 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
875 * Shift in read opcode.
877 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
882 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
884 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
886 reg = FXP_EEPROM_EECS;
887 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
889 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
891 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
893 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
895 if (autosize && reg == 0) {
896 sc->eeprom_size = data;
904 reg = FXP_EEPROM_EECS;
905 for (x = 1 << 15; x; x >>= 1) {
906 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
908 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
910 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
913 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
920 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
925 * Erase/write enable.
927 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
928 fxp_eeprom_shiftin(sc, 0x4, 3);
929 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
930 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
933 * Shift in write opcode, address, data.
935 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
936 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
937 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
938 fxp_eeprom_shiftin(sc, data, 16);
939 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
942 * Wait for EEPROM to finish up.
944 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
946 for (i = 0; i < 1000; i++) {
947 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
951 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
954 * Erase/write disable.
956 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
957 fxp_eeprom_shiftin(sc, 0x4, 3);
958 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
959 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
966 * Figure out EEPROM size.
968 * 559's can have either 64-word or 256-word EEPROMs, the 558
969 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
970 * talks about the existance of 16 to 256 word EEPROMs.
972 * The only known sizes are 64 and 256, where the 256 version is used
973 * by CardBus cards to store CIS information.
975 * The address is shifted in msb-to-lsb, and after the last
976 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
977 * after which follows the actual data. We try to detect this zero, by
978 * probing the data-out bit in the EEPROM control register just after
979 * having shifted in a bit. If the bit is zero, we assume we've
980 * shifted enough address bits. The data-out should be tri-state,
981 * before this, which should translate to a logical one.
984 fxp_autosize_eeprom(struct fxp_softc *sc)
987 /* guess maximum size of 256 words */
991 (void) fxp_eeprom_getword(sc, 0, 1);
995 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
999 for (i = 0; i < words; i++)
1000 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1004 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1008 for (i = 0; i < words; i++)
1009 fxp_eeprom_putword(sc, offset + i, data[i]);
1013 * Start packet transmission on the interface.
1016 fxp_start(struct ifnet *ifp)
1018 struct fxp_softc *sc = ifp->if_softc;
1019 struct fxp_cb_tx *txp;
1022 * See if we need to suspend xmit until the multicast filter
1023 * has been reprogrammed (which can only be done at the head
1024 * of the command chain).
1026 if (sc->need_mcsetup) {
1033 * We're finished if there is nothing more to add to the list or if
1034 * we're all filled up with buffers to transmit.
1035 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1036 * a NOP command when needed.
1038 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) {
1039 struct mbuf *m, *mb_head;
1043 * Grab a packet to transmit.
1045 IF_DEQUEUE(&ifp->if_snd, mb_head);
1048 * Get pointer to next available tx desc.
1050 txp = sc->cbl_last->next;
1053 * Go through each of the mbufs in the chain and initialize
1054 * the transmit buffer descriptors with the physical address
1055 * and size of the mbuf.
1058 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1059 if (m->m_len != 0) {
1060 if (segment == FXP_NTXSEG)
1062 txp->tbd[segment].tb_addr =
1063 vtophys(mtod(m, vm_offset_t));
1064 txp->tbd[segment].tb_size = m->m_len;
1072 * We ran out of segments. We have to recopy this
1073 * mbuf chain first. Bail out if we can't get the
1076 MGETHDR(mn, M_DONTWAIT, MT_DATA);
1081 if (mb_head->m_pkthdr.len > MHLEN) {
1082 MCLGET(mn, M_DONTWAIT);
1083 if ((mn->m_flags & M_EXT) == 0) {
1089 m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1091 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1097 txp->tbd_number = segment;
1098 txp->mb_head = mb_head;
1100 if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1102 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1106 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1107 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
1109 * Set a 5 second timer just in case we don't hear
1110 * from the card again.
1114 txp->tx_threshold = tx_threshold;
1117 * Advance the end of list forward.
1122 * On platforms which can't access memory in 16-bit
1123 * granularities, we must prevent the card from DMA'ing
1124 * up the status while we update the command field.
1125 * This could cause us to overwrite the completion status.
1127 atomic_clear_short(&sc->cbl_last->cb_command,
1130 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1131 #endif /*__alpha__*/
1135 * Advance the beginning of the list forward if there are
1136 * no other packets queued (when nothing is queued, cbl_first
1137 * sits on the last TxCB that was sent out).
1139 if (sc->tx_queued == 0)
1140 sc->cbl_first = txp;
1145 * Pass packet to bpf if there is a listener.
1148 bpf_mtap(ifp, mb_head);
1152 * We're finished. If we added to the list, issue a RESUME to get DMA
1153 * going again if suspended.
1157 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1161 #ifdef DEVICE_POLLING
1162 static poll_handler_t fxp_poll;
1165 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1167 struct fxp_softc *sc = ifp->if_softc;
1170 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1171 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1174 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1176 if (cmd == POLL_AND_CHECK_STATUS) {
1179 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1180 if (tmp == 0xff || tmp == 0)
1181 return; /* nothing to do */
1183 /* ack what we can */
1185 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1188 fxp_intr_body(sc, statack, count);
1190 #endif /* DEVICE_POLLING */
1193 * Process interface interrupts.
1198 struct fxp_softc *sc = xsc;
1201 #ifdef DEVICE_POLLING
1202 struct ifnet *ifp = &sc->sc_if;
1204 if (ifp->if_ipending & IFF_POLLING)
1206 if (ether_poll_register(fxp_poll, ifp)) {
1207 /* disable interrupts */
1208 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1209 fxp_poll(ifp, 0, 1);
1214 if (sc->suspended) {
1218 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1220 * It should not be possible to have all bits set; the
1221 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1222 * all bits are set, this may indicate that the card has
1223 * been physically ejected, so ignore it.
1225 if (statack == 0xff)
1229 * First ACK all the interrupts in this pass.
1231 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1232 fxp_intr_body(sc, statack, -1);
1237 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count)
1239 struct ifnet *ifp = &sc->sc_if;
1241 struct fxp_rfa *rfa;
1242 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1246 #ifdef DEVICE_POLLING
1247 /* Pick up a deferred RNR condition if `count' ran out last time. */
1248 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1249 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1255 * Free any finished transmit mbuf chains.
1257 * Handle the CNA event likt a CXTNO event. It used to
1258 * be that this event (control unit not ready) was not
1259 * encountered, but it is now with the SMPng modifications.
1260 * The exact sequence of events that occur when the interface
1261 * is brought up are different now, and if this event
1262 * goes unhandled, the configuration/rxfilter setup sequence
1263 * can stall for several seconds. The result is that no
1264 * packets go out onto the wire for about 5 to 10 seconds
1265 * after the interface is ifconfig'ed for the first time.
1267 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1268 struct fxp_cb_tx *txp;
1270 for (txp = sc->cbl_first; sc->tx_queued &&
1271 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1273 if (txp->mb_head != NULL) {
1274 m_freem(txp->mb_head);
1275 txp->mb_head = NULL;
1279 sc->cbl_first = txp;
1281 if (sc->tx_queued == 0) {
1282 if (sc->need_mcsetup)
1286 * Try to start more packets transmitting.
1288 if (ifp->if_snd.ifq_head != NULL)
1293 * Just return if nothing happened on the receive side.
1295 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1299 * Process receiver interrupts. If a no-resource (RNR)
1300 * condition exists, get whatever packets we can and
1301 * re-start the receiver.
1303 * When using polling, we do not process the list to completion,
1304 * so when we get an RNR interrupt we must defer the restart
1305 * until we hit the last buffer with the C bit set.
1306 * If we run out of cycles and rfa_headm has the C bit set,
1307 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1308 * that the info will be used in the subsequent polling cycle.
1312 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1313 RFA_ALIGNMENT_FUDGE);
1315 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1316 if (count >= 0 && count-- == 0) {
1318 /* Defer RNR processing until the next time. */
1319 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1324 #endif /* DEVICE_POLLING */
1326 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0)
1330 * Remove first packet from the chain.
1332 sc->rfa_headm = m->m_next;
1336 * Add a new buffer to the receive chain.
1337 * If this fails, the old buffer is recycled
1340 if (fxp_add_rfabuf(sc, m) == 0) {
1344 * Fetch packet length (the top 2 bits of
1345 * actual_size are flags set by the controller
1346 * upon completion), and drop the packet in case
1347 * of bogus length or CRC errors.
1349 total_len = rfa->actual_size & 0x3fff;
1350 if (total_len < sizeof(struct ether_header) ||
1351 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1352 sizeof(struct fxp_rfa) ||
1353 rfa->rfa_status & FXP_RFA_STATUS_CRC) {
1357 m->m_pkthdr.len = m->m_len = total_len;
1358 ether_input(ifp, NULL, m);
1363 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1364 vtophys(sc->rfa_headm->m_ext.ext_buf) +
1365 RFA_ALIGNMENT_FUDGE);
1366 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1371 * Update packet in/out/collision statistics. The i82557 doesn't
1372 * allow you to access these counters without doing a fairly
1373 * expensive DMA to get _all_ of the statistics it maintains, so
1374 * we do this operation here only once per second. The statistics
1375 * counters in the kernel are updated from the previous dump-stats
1376 * DMA and then a new dump-stats DMA is started. The on-chip
1377 * counters are zeroed when the DMA completes. If we can't start
1378 * the DMA immediately, we don't wait - we just prepare to read
1379 * them again next time.
1384 struct fxp_softc *sc = xsc;
1385 struct ifnet *ifp = &sc->sc_if;
1386 struct fxp_stats *sp = sc->fxp_stats;
1387 struct fxp_cb_tx *txp;
1390 ifp->if_opackets += sp->tx_good;
1391 ifp->if_collisions += sp->tx_total_collisions;
1393 ifp->if_ipackets += sp->rx_good;
1394 sc->rx_idle_secs = 0;
1397 * Receiver's been idle for another second.
1403 sp->rx_alignment_errors +
1405 sp->rx_overrun_errors;
1407 * If any transmit underruns occured, bump up the transmit
1408 * threshold by another 512 bytes (64 * 8).
1410 if (sp->tx_underruns) {
1411 ifp->if_oerrors += sp->tx_underruns;
1412 if (tx_threshold < 192)
1417 * Release any xmit buffers that have completed DMA. This isn't
1418 * strictly necessary to do here, but it's advantagous for mbufs
1419 * with external storage to be released in a timely manner rather
1420 * than being defered for a potentially long time. This limits
1421 * the delay to a maximum of one second.
1423 for (txp = sc->cbl_first; sc->tx_queued &&
1424 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1426 if (txp->mb_head != NULL) {
1427 m_freem(txp->mb_head);
1428 txp->mb_head = NULL;
1432 sc->cbl_first = txp;
1434 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1435 * then assume the receiver has locked up and attempt to clear
1436 * the condition by reprogramming the multicast filter. This is
1437 * a work-around for a bug in the 82557 where the receiver locks
1438 * up if it gets certain types of garbage in the syncronization
1439 * bits prior to the packet header. This bug is supposed to only
1440 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1441 * mode as well (perhaps due to a 10/100 speed transition).
1443 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1444 sc->rx_idle_secs = 0;
1448 * If there is no pending command, start another stats
1449 * dump. Otherwise punt for now.
1451 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1453 * Start another stats dump.
1455 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1458 * A previous command is still waiting to be accepted.
1459 * Just zero our copy of the stats and wait for the
1460 * next timer event to update them.
1463 sp->tx_underruns = 0;
1464 sp->tx_total_collisions = 0;
1467 sp->rx_crc_errors = 0;
1468 sp->rx_alignment_errors = 0;
1469 sp->rx_rnr_errors = 0;
1470 sp->rx_overrun_errors = 0;
1472 if (sc->miibus != NULL)
1473 mii_tick(device_get_softc(sc->miibus));
1476 * Schedule another timeout one second from now.
1478 sc->stat_ch = timeout(fxp_tick, sc, hz);
1482 * Stop the interface. Cancels the statistics updater and resets
1486 fxp_stop(struct fxp_softc *sc)
1488 struct ifnet *ifp = &sc->sc_if;
1489 struct fxp_cb_tx *txp;
1492 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1495 #ifdef DEVICE_POLLING
1496 ether_poll_deregister(ifp);
1499 * Cancel stats updater.
1501 untimeout(fxp_tick, sc, sc->stat_ch);
1504 * Issue software reset, which also unloads the microcode.
1506 sc->flags &= ~FXP_FLAG_UCODE;
1507 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
1511 * Release any xmit buffers.
1515 for (i = 0; i < FXP_NTXCB; i++) {
1516 if (txp[i].mb_head != NULL) {
1517 m_freem(txp[i].mb_head);
1518 txp[i].mb_head = NULL;
1525 * Free all the receive buffers then reallocate/reinitialize
1527 if (sc->rfa_headm != NULL)
1528 m_freem(sc->rfa_headm);
1529 sc->rfa_headm = NULL;
1530 sc->rfa_tailm = NULL;
1531 for (i = 0; i < FXP_NRFABUFS; i++) {
1532 if (fxp_add_rfabuf(sc, NULL) != 0) {
1534 * This "can't happen" - we're at splimp()
1535 * and we just freed all the buffers we need
1538 panic("fxp_stop: no buffers!");
1544 * Watchdog/transmission transmit timeout handler. Called when a
1545 * transmission is started on the interface, but no interrupt is
1546 * received before the timeout. This usually indicates that the
1547 * card has wedged for some reason.
1550 fxp_watchdog(struct ifnet *ifp)
1552 struct fxp_softc *sc = ifp->if_softc;
1554 device_printf(sc->dev, "device timeout\n");
1563 struct fxp_softc *sc = xsc;
1564 struct ifnet *ifp = &sc->sc_if;
1565 struct fxp_cb_config *cbp;
1566 struct fxp_cb_ias *cb_ias;
1567 struct fxp_cb_tx *txp;
1568 struct fxp_cb_mcs *mcsp;
1573 * Cancel any pending I/O
1577 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1580 * Initialize base of CBL and RFA memory. Loading with zero
1581 * sets it up for regular linear addressing.
1583 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1584 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1587 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1590 * Initialize base of dump-stats buffer.
1593 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1594 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1597 * Attempt to load microcode if requested.
1599 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
1603 * Initialize the multicast address list.
1605 if (fxp_mc_addrs(sc)) {
1607 mcsp->cb_status = 0;
1608 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL;
1609 mcsp->link_addr = -1;
1611 * Start the multicast setup command.
1614 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
1615 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1616 /* ...and wait for it to complete. */
1617 fxp_dma_wait(&mcsp->cb_status, sc);
1621 * We temporarily use memory that contains the TxCB list to
1622 * construct the config CB. The TxCB list memory is rebuilt
1625 cbp = (struct fxp_cb_config *) sc->cbl_base;
1628 * This bcopy is kind of disgusting, but there are a bunch of must be
1629 * zero and must be one bits in this structure and this is the easiest
1630 * way to initialize them all to proper values.
1632 bcopy(fxp_cb_config_template,
1633 (void *)(uintptr_t)(volatile void *)&cbp->cb_status,
1634 sizeof(fxp_cb_config_template));
1637 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
1638 cbp->link_addr = -1; /* (no) next command */
1639 cbp->byte_count = 22; /* (22) bytes to config */
1640 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1641 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1642 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1643 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1644 cbp->type_enable = 0; /* actually reserved */
1645 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1646 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1647 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1648 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1649 cbp->dma_mbce = 0; /* (disable) dma max counters */
1650 cbp->late_scb = 0; /* (don't) defer SCB update */
1651 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
1652 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
1653 cbp->ci_int = 1; /* interrupt on CU idle */
1654 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1655 cbp->ext_stats_dis = 1; /* disable extended counters */
1656 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
1657 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm;
1658 cbp->disc_short_rx = !prm; /* discard short packets */
1659 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
1660 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
1661 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
1662 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1663 cbp->csma_dis = 0; /* (don't) disable link */
1664 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
1665 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
1666 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
1667 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
1668 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
1669 cbp->nsai = 1; /* (don't) disable source addr insert */
1670 cbp->preamble_length = 2; /* (7 byte) preamble */
1671 cbp->loopback = 0; /* (don't) loopback */
1672 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1673 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1674 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1675 cbp->promiscuous = prm; /* promiscuous mode */
1676 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1677 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
1678 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
1679 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
1680 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1682 cbp->stripping = !prm; /* truncate rx packet to byte count */
1683 cbp->padding = 1; /* (do) pad short tx packets */
1684 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1685 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1686 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
1687 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
1688 /* must set wake_en in PMCSR also */
1689 cbp->force_fdx = 0; /* (don't) force full duplex */
1690 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1691 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1692 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1694 if (sc->revision == FXP_REV_82557) {
1696 * The 82557 has no hardware flow control, the values
1697 * below are the defaults for the chip.
1699 cbp->fc_delay_lsb = 0;
1700 cbp->fc_delay_msb = 0x40;
1701 cbp->pri_fc_thresh = 3;
1703 cbp->rx_fc_restop = 0;
1704 cbp->rx_fc_restart = 0;
1706 cbp->pri_fc_loc = 1;
1708 cbp->fc_delay_lsb = 0x1f;
1709 cbp->fc_delay_msb = 0x01;
1710 cbp->pri_fc_thresh = 3;
1711 cbp->tx_fc_dis = 0; /* enable transmit FC */
1712 cbp->rx_fc_restop = 1; /* enable FC restop frames */
1713 cbp->rx_fc_restart = 1; /* enable FC restart frames */
1714 cbp->fc_filter = !prm; /* drop FC frames to host */
1715 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
1719 * Start the config command/DMA.
1722 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1723 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1724 /* ...and wait for it to complete. */
1725 fxp_dma_wait(&cbp->cb_status, sc);
1728 * Now initialize the station address. Temporarily use the TxCB
1729 * memory area like we did above for the config CB.
1731 cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1732 cb_ias->cb_status = 0;
1733 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
1734 cb_ias->link_addr = -1;
1735 bcopy(sc->arpcom.ac_enaddr,
1736 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr,
1737 sizeof(sc->arpcom.ac_enaddr));
1740 * Start the IAS (Individual Address Setup) command/DMA.
1743 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1744 /* ...and wait for it to complete. */
1745 fxp_dma_wait(&cb_ias->cb_status, sc);
1748 * Initialize transmit control block (TxCB) list.
1752 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1753 for (i = 0; i < FXP_NTXCB; i++) {
1754 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
1755 txp[i].cb_command = FXP_CB_COMMAND_NOP;
1757 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1758 if (sc->flags & FXP_FLAG_EXT_TXCB)
1759 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]);
1761 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1762 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1765 * Set the suspend flag on the first TxCB and start the control
1766 * unit. It will execute the NOP and then suspend.
1768 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
1769 sc->cbl_first = sc->cbl_last = txp;
1773 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1776 * Initialize receiver buffer area - RFA.
1779 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1780 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1781 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1784 * Set current media.
1786 if (sc->miibus != NULL)
1787 mii_mediachg(device_get_softc(sc->miibus));
1789 ifp->if_flags |= IFF_RUNNING;
1790 ifp->if_flags &= ~IFF_OACTIVE;
1793 * Enable interrupts.
1795 #ifdef DEVICE_POLLING
1797 * ... but only do that if we are not polling. And because (presumably)
1798 * the default is interrupts on, we need to disable them explicitly!
1800 if ( ifp->if_ipending & IFF_POLLING )
1801 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1803 #endif /* DEVICE_POLLING */
1804 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1808 * Start stats updater.
1810 sc->stat_ch = timeout(fxp_tick, sc, hz);
1814 fxp_serial_ifmedia_upd(struct ifnet *ifp)
1821 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1824 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
1828 * Change media according to request.
1831 fxp_ifmedia_upd(struct ifnet *ifp)
1833 struct fxp_softc *sc = ifp->if_softc;
1834 struct mii_data *mii;
1836 mii = device_get_softc(sc->miibus);
1842 * Notify the world which media we're using.
1845 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1847 struct fxp_softc *sc = ifp->if_softc;
1848 struct mii_data *mii;
1850 mii = device_get_softc(sc->miibus);
1852 ifmr->ifm_active = mii->mii_media_active;
1853 ifmr->ifm_status = mii->mii_media_status;
1855 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
1856 sc->cu_resume_bug = 1;
1858 sc->cu_resume_bug = 0;
1862 * Add a buffer to the end of the RFA buffer list.
1863 * Return 0 if successful, 1 for failure. A failure results in
1864 * adding the 'oldm' (if non-NULL) on to the end of the list -
1865 * tossing out its old contents and recycling it.
1866 * The RFA struct is stuck at the beginning of mbuf cluster and the
1867 * data pointer is fixed up to point just past it.
1870 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm)
1874 struct fxp_rfa *rfa, *p_rfa;
1876 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1877 if (m == NULL) { /* try to recycle the old mbuf instead */
1881 m->m_data = m->m_ext.ext_buf;
1885 * Move the data pointer up so that the incoming data packet
1886 * will be 32-bit aligned.
1888 m->m_data += RFA_ALIGNMENT_FUDGE;
1891 * Get a pointer to the base of the mbuf cluster and move
1892 * data start past it.
1894 rfa = mtod(m, struct fxp_rfa *);
1895 m->m_data += sizeof(struct fxp_rfa);
1896 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE);
1899 * Initialize the rest of the RFA. Note that since the RFA
1900 * is misaligned, we cannot store values directly. Instead,
1901 * we use an optimized, inline copy.
1904 rfa->rfa_status = 0;
1905 rfa->rfa_control = FXP_RFA_CONTROL_EL;
1906 rfa->actual_size = 0;
1909 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr);
1910 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr);
1913 * If there are other buffers already on the list, attach this
1914 * one to the end by fixing up the tail to point to this one.
1916 if (sc->rfa_headm != NULL) {
1917 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf +
1918 RFA_ALIGNMENT_FUDGE);
1919 sc->rfa_tailm->m_next = m;
1921 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr);
1922 p_rfa->rfa_control = 0;
1932 fxp_miibus_readreg(device_t dev, int phy, int reg)
1934 struct fxp_softc *sc = device_get_softc(dev);
1938 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1939 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
1941 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
1946 device_printf(dev, "fxp_miibus_readreg: timed out\n");
1948 return (value & 0xffff);
1952 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
1954 struct fxp_softc *sc = device_get_softc(dev);
1957 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1958 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
1961 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
1966 device_printf(dev, "fxp_miibus_writereg: timed out\n");
1970 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1972 struct fxp_softc *sc = ifp->if_softc;
1973 struct ifreq *ifr = (struct ifreq *)data;
1974 struct mii_data *mii;
1983 error = ether_ioctl(ifp, command, data);
1987 if (ifp->if_flags & IFF_ALLMULTI)
1988 sc->flags |= FXP_FLAG_ALL_MCAST;
1990 sc->flags &= ~FXP_FLAG_ALL_MCAST;
1993 * If interface is marked up and not running, then start it.
1994 * If it is marked down and running, stop it.
1995 * XXX If it's up then re-initialize it. This is so flags
1996 * such as IFF_PROMISC are handled.
1998 if (ifp->if_flags & IFF_UP) {
2001 if (ifp->if_flags & IFF_RUNNING)
2008 if (ifp->if_flags & IFF_ALLMULTI)
2009 sc->flags |= FXP_FLAG_ALL_MCAST;
2011 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2013 * Multicast list has changed; set the hardware filter
2016 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2019 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2020 * again rather than else {}.
2022 if (sc->flags & FXP_FLAG_ALL_MCAST)
2029 if (sc->miibus != NULL) {
2030 mii = device_get_softc(sc->miibus);
2031 error = ifmedia_ioctl(ifp, ifr,
2032 &mii->mii_media, command);
2034 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2046 * Fill in the multicast address list and return number of entries.
2049 fxp_mc_addrs(struct fxp_softc *sc)
2051 struct fxp_cb_mcs *mcsp = sc->mcsp;
2052 struct ifnet *ifp = &sc->sc_if;
2053 struct ifmultiaddr *ifma;
2057 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2058 #if __FreeBSD_version < 500000
2059 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2061 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2063 if (ifma->ifma_addr->sa_family != AF_LINK)
2065 if (nmcasts >= MAXMCADDR) {
2066 sc->flags |= FXP_FLAG_ALL_MCAST;
2070 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2071 (void *)(uintptr_t)(volatile void *)
2072 &sc->mcsp->mc_addr[nmcasts][0], 6);
2076 mcsp->mc_cnt = nmcasts * 6;
2081 * Program the multicast filter.
2083 * We have an artificial restriction that the multicast setup command
2084 * must be the first command in the chain, so we take steps to ensure
2085 * this. By requiring this, it allows us to keep up the performance of
2086 * the pre-initialized command ring (esp. link pointers) by not actually
2087 * inserting the mcsetup command in the ring - i.e. its link pointer
2088 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2089 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2090 * lead into the regular TxCB ring when it completes.
2092 * This function must be called at splimp.
2095 fxp_mc_setup(struct fxp_softc *sc)
2097 struct fxp_cb_mcs *mcsp = sc->mcsp;
2098 struct ifnet *ifp = &sc->sc_if;
2102 * If there are queued commands, we must wait until they are all
2103 * completed. If we are already waiting, then add a NOP command
2104 * with interrupt option so that we're notified when all commands
2105 * have been completed - fxp_start() ensures that no additional
2106 * TX commands will be added when need_mcsetup is true.
2108 if (sc->tx_queued) {
2109 struct fxp_cb_tx *txp;
2112 * need_mcsetup will be true if we are already waiting for the
2113 * NOP command to be completed (see below). In this case, bail.
2115 if (sc->need_mcsetup)
2117 sc->need_mcsetup = 1;
2120 * Add a NOP command with interrupt so that we are notified
2121 * when all TX commands have been processed.
2123 txp = sc->cbl_last->next;
2124 txp->mb_head = NULL;
2126 txp->cb_command = FXP_CB_COMMAND_NOP |
2127 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2129 * Advance the end of list forward.
2131 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2135 * Issue a resume in case the CU has just suspended.
2138 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2140 * Set a 5 second timer just in case we don't hear from the
2147 sc->need_mcsetup = 0;
2150 * Initialize multicast setup descriptor.
2152 mcsp->next = sc->cbl_base;
2153 mcsp->mb_head = NULL;
2154 mcsp->cb_status = 0;
2155 mcsp->cb_command = FXP_CB_COMMAND_MCAS |
2156 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2157 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2158 (void) fxp_mc_addrs(sc);
2159 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2163 * Wait until command unit is not active. This should never
2164 * be the case when nothing is queued, but make sure anyway.
2167 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2168 FXP_SCB_CUS_ACTIVE && --count)
2171 device_printf(sc->dev, "command queue timeout\n");
2176 * Start the multicast setup command.
2179 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2180 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2186 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2187 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2188 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2189 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2190 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2191 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2193 #define UCODE(x) x, sizeof(x)
2199 u_short int_delay_offset;
2200 u_short bundle_max_offset;
2202 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2203 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2204 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2205 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2206 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2207 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2208 { FXP_REV_82550, UCODE(fxp_ucode_d102),
2209 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2210 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2211 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2212 { 0, NULL, 0, 0, 0 }
2216 fxp_load_ucode(struct fxp_softc *sc)
2219 struct fxp_cb_ucode *cbp;
2221 for (uc = ucode_table; uc->ucode != NULL; uc++)
2222 if (sc->revision == uc->revision)
2224 if (uc->ucode == NULL)
2226 cbp = (struct fxp_cb_ucode *)sc->cbl_base;
2228 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL;
2229 cbp->link_addr = -1; /* (no) next command */
2230 memcpy(cbp->ucode, uc->ucode, uc->length);
2231 if (uc->int_delay_offset)
2232 *(u_short *)&cbp->ucode[uc->int_delay_offset] =
2233 sc->tunable_int_delay + sc->tunable_int_delay / 2;
2234 if (uc->bundle_max_offset)
2235 *(u_short *)&cbp->ucode[uc->bundle_max_offset] =
2236 sc->tunable_bundle_max;
2238 * Download the ucode to the chip.
2241 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
2242 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2243 /* ...and wait for it to complete. */
2244 fxp_dma_wait(&cbp->cb_status, sc);
2245 device_printf(sc->dev,
2246 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
2247 sc->tunable_int_delay,
2248 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2249 sc->flags |= FXP_FLAG_UCODE;
2253 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2257 value = *(int *)arg1;
2258 error = sysctl_handle_int(oidp, &value, 0, req);
2259 if (error || !req->newptr)
2261 if (value < low || value > high)
2263 *(int *)arg1 = value;
2268 * Interrupt delay is expressed in microseconds, a multiplier is used
2269 * to convert this to the appropriate clock ticks before using.
2272 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
2274 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
2278 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
2280 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));