2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $
33 * $DragonFly: src/sys/dev/netif/sf/if_sf.c,v 1.5 2003/11/20 22:07:30 dillon Exp $
35 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $
39 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD.
40 * Programming manual is available from:
41 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Department of Electical Engineering
45 * Columbia University, New York City
49 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet
50 * controller designed with flexibility and reducing CPU load in mind.
51 * The Starfire offers high and low priority buffer queues, a
52 * producer/consumer index mechanism and several different buffer
53 * queue and completion queue descriptor types. Any one of a number
54 * of different driver designs can be used, depending on system and
55 * OS requirements. This driver makes use of type0 transmit frame
56 * descriptors (since BSD fragments packets across an mbuf chain)
57 * and two RX buffer queues prioritized on size (one queue for small
58 * frames that will fit into a single mbuf, another with full size
59 * mbuf clusters for everything else). The producer/consumer indexes
60 * and completion queues are also used.
62 * One downside to the Starfire has to do with alignment: buffer
63 * queues must be aligned on 256-byte boundaries, and receive buffers
64 * must be aligned on longword boundaries. The receive buffer alignment
65 * causes problems on the Alpha platform, where the packet payload
66 * should be longword aligned. There is no simple way around this.
68 * For receive filtering, the Starfire offers 16 perfect filter slots
69 * and a 512-bit hash table.
71 * The Starfire has no internal transceiver, relying instead on an
72 * external MII-based transceiver. Accessing registers on external
73 * PHYs is done through a special register map rather than with the
74 * usual bitbang MDIO method.
76 * Acesssing the registers on the Starfire is a little tricky. The
77 * Starfire has a 512K internal register space. When programmed for
78 * PCI memory mapped mode, the entire register space can be accessed
79 * directly. However in I/O space mode, only 256 bytes are directly
80 * mapped into PCI I/O space. The other registers can be accessed
81 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA
82 * registers inside the 256-byte I/O window.
85 #include <sys/param.h>
86 #include <sys/systm.h>
87 #include <sys/sockio.h>
89 #include <sys/malloc.h>
90 #include <sys/kernel.h>
91 #include <sys/socket.h>
94 #include <net/if_arp.h>
95 #include <net/ethernet.h>
96 #include <net/if_dl.h>
97 #include <net/if_media.h>
101 #include <vm/vm.h> /* for vtophys */
102 #include <vm/pmap.h> /* for vtophys */
103 #include <machine/clock.h> /* for DELAY */
104 #include <machine/bus_pio.h>
105 #include <machine/bus_memio.h>
106 #include <machine/bus.h>
107 #include <machine/resource.h>
109 #include <sys/rman.h>
111 #include "../mii_layer/mii.h"
112 #include "../mii_layer/miivar.h"
114 /* "controller miibus0" required. See GENERIC if you get errors here. */
115 #include "miibus_if.h"
117 #include <bus/pci/pcireg.h>
118 #include <bus/pci/pcivar.h>
120 #define SF_USEIOSPACE
122 #include "if_sfreg.h"
124 static struct sf_type sf_devs[] = {
125 { AD_VENDORID, AD_DEVICEID_STARFIRE,
126 "Adaptec AIC-6915 10/100BaseTX" },
130 static int sf_probe (device_t);
131 static int sf_attach (device_t);
132 static int sf_detach (device_t);
133 static void sf_intr (void *);
134 static void sf_stats_update (void *);
135 static void sf_rxeof (struct sf_softc *);
136 static void sf_txeof (struct sf_softc *);
137 static int sf_encap (struct sf_softc *,
138 struct sf_tx_bufdesc_type0 *,
140 static void sf_start (struct ifnet *);
141 static int sf_ioctl (struct ifnet *, u_long, caddr_t);
142 static void sf_init (void *);
143 static void sf_stop (struct sf_softc *);
144 static void sf_watchdog (struct ifnet *);
145 static void sf_shutdown (device_t);
146 static int sf_ifmedia_upd (struct ifnet *);
147 static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *);
148 static void sf_reset (struct sf_softc *);
149 static int sf_init_rx_ring (struct sf_softc *);
150 static void sf_init_tx_ring (struct sf_softc *);
151 static int sf_newbuf (struct sf_softc *,
152 struct sf_rx_bufdesc_type0 *,
154 static void sf_setmulti (struct sf_softc *);
155 static int sf_setperf (struct sf_softc *, int, caddr_t);
156 static int sf_sethash (struct sf_softc *, caddr_t, int);
158 static int sf_setvlan (struct sf_softc *, int, u_int32_t);
161 static u_int8_t sf_read_eeprom (struct sf_softc *, int);
162 static u_int32_t sf_calchash (caddr_t);
164 static int sf_miibus_readreg (device_t, int, int);
165 static int sf_miibus_writereg (device_t, int, int, int);
166 static void sf_miibus_statchg (device_t);
168 static u_int32_t csr_read_4 (struct sf_softc *, int);
169 static void csr_write_4 (struct sf_softc *, int, u_int32_t);
170 static void sf_txthresh_adjust (struct sf_softc *);
173 #define SF_RES SYS_RES_IOPORT
174 #define SF_RID SF_PCI_LOIO
176 #define SF_RES SYS_RES_MEMORY
177 #define SF_RID SF_PCI_LOMEM
180 static device_method_t sf_methods[] = {
181 /* Device interface */
182 DEVMETHOD(device_probe, sf_probe),
183 DEVMETHOD(device_attach, sf_attach),
184 DEVMETHOD(device_detach, sf_detach),
185 DEVMETHOD(device_shutdown, sf_shutdown),
188 DEVMETHOD(bus_print_child, bus_generic_print_child),
189 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
192 DEVMETHOD(miibus_readreg, sf_miibus_readreg),
193 DEVMETHOD(miibus_writereg, sf_miibus_writereg),
194 DEVMETHOD(miibus_statchg, sf_miibus_statchg),
199 static driver_t sf_driver = {
202 sizeof(struct sf_softc),
205 static devclass_t sf_devclass;
207 DECLARE_DUMMY_MODULE(if_sf);
208 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0);
209 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0);
211 #define SF_SETBIT(sc, reg, x) \
212 csr_write_4(sc, reg, csr_read_4(sc, reg) | x)
214 #define SF_CLRBIT(sc, reg, x) \
215 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)
217 static u_int32_t csr_read_4(sc, reg)
224 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
225 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);
227 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));
233 static u_int8_t sf_read_eeprom(sc, reg)
239 val = (csr_read_4(sc, SF_EEADDR_BASE +
240 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;
245 static void csr_write_4(sc, reg, val)
251 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
252 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val);
254 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);
259 static u_int32_t sf_calchash(addr)
262 u_int32_t crc, carry;
266 /* Compute CRC for the address value. */
267 crc = 0xFFFFFFFF; /* initial value */
269 for (i = 0; i < 6; i++) {
271 for (j = 0; j < 8; j++) {
272 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
276 crc = (crc ^ 0x04c11db6) | carry;
280 /* return the filter bit position */
281 return(crc >> 23 & 0x1FF);
285 * Copy the address 'mac' into the perfect RX filter entry at
286 * offset 'idx.' The perfect filter only has 16 entries so do
289 static int sf_setperf(sc, idx, mac)
296 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT)
302 p = (u_int16_t *)mac;
304 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
305 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2]));
306 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
307 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1]));
308 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
309 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0]));
315 * Set the bit in the 512-bit hash table that corresponds to the
316 * specified mac address 'mac.' If 'prio' is nonzero, update the
317 * priority hash table instead of the filter hash table.
319 static int sf_sethash(sc, mac, prio)
329 h = sf_calchash(mac);
332 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF +
333 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
335 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF +
336 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
344 * Set a VLAN tag in the receive filter.
346 static int sf_setvlan(sc, idx, vlan)
351 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT)
354 csr_write_4(sc, SF_RXFILT_HASH_BASE +
355 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan);
361 static int sf_miibus_readreg(dev, phy, reg)
369 sc = device_get_softc(dev);
371 for (i = 0; i < SF_TIMEOUT; i++) {
372 val = csr_read_4(sc, SF_PHY_REG(phy, reg));
373 if (val & SF_MII_DATAVALID)
380 if ((val & 0x0000FFFF) == 0xFFFF)
383 return(val & 0x0000FFFF);
386 static int sf_miibus_writereg(dev, phy, reg, val)
394 sc = device_get_softc(dev);
396 csr_write_4(sc, SF_PHY_REG(phy, reg), val);
398 for (i = 0; i < SF_TIMEOUT; i++) {
399 busy = csr_read_4(sc, SF_PHY_REG(phy, reg));
400 if (!(busy & SF_MII_BUSY))
407 static void sf_miibus_statchg(dev)
411 struct mii_data *mii;
413 sc = device_get_softc(dev);
414 mii = device_get_softc(sc->sf_miibus);
416 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
417 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
418 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX);
420 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
421 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX);
427 static void sf_setmulti(sc)
432 struct ifmultiaddr *ifma;
433 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 };
435 ifp = &sc->arpcom.ac_if;
437 /* First zot all the existing filters. */
438 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++)
439 sf_setperf(sc, i, (char *)&dummy);
440 for (i = SF_RXFILT_HASH_BASE;
441 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
442 csr_write_4(sc, i, 0);
443 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
445 /* Now program new ones. */
446 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
447 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
450 /* First find the tail of the list. */
451 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
452 ifma = ifma->ifma_link.le_next) {
453 if (ifma->ifma_link.le_next == NULL)
456 /* Now traverse the list backwards. */
457 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
458 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
459 if (ifma->ifma_addr->sa_family != AF_LINK)
462 * Program the first 15 multicast groups
463 * into the perfect filter. For all others,
464 * use the hash table.
466 if (i < SF_RXFILT_PERFECT_CNT) {
468 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
474 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0);
484 static int sf_ifmedia_upd(ifp)
488 struct mii_data *mii;
491 mii = device_get_softc(sc->sf_miibus);
493 if (mii->mii_instance) {
494 struct mii_softc *miisc;
495 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
496 miisc = LIST_NEXT(miisc, mii_list))
497 mii_phy_reset(miisc);
505 * Report current media status.
507 static void sf_ifmedia_sts(ifp, ifmr)
509 struct ifmediareq *ifmr;
512 struct mii_data *mii;
515 mii = device_get_softc(sc->sf_miibus);
518 ifmr->ifm_active = mii->mii_media_active;
519 ifmr->ifm_status = mii->mii_media_status;
524 static int sf_ioctl(ifp, command, data)
529 struct sf_softc *sc = ifp->if_softc;
530 struct ifreq *ifr = (struct ifreq *) data;
531 struct mii_data *mii;
540 error = ether_ioctl(ifp, command, data);
543 if (ifp->if_flags & IFF_UP) {
544 if (ifp->if_flags & IFF_RUNNING &&
545 ifp->if_flags & IFF_PROMISC &&
546 !(sc->sf_if_flags & IFF_PROMISC)) {
547 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
548 } else if (ifp->if_flags & IFF_RUNNING &&
549 !(ifp->if_flags & IFF_PROMISC) &&
550 sc->sf_if_flags & IFF_PROMISC) {
551 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
552 } else if (!(ifp->if_flags & IFF_RUNNING))
555 if (ifp->if_flags & IFF_RUNNING)
558 sc->sf_if_flags = ifp->if_flags;
568 mii = device_get_softc(sc->sf_miibus);
569 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
581 static void sf_reset(sc)
586 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
587 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
589 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
591 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET);
593 for (i = 0; i < SF_TIMEOUT; i++) {
595 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET))
600 printf("sf%d: reset never completed!\n", sc->sf_unit);
602 /* Wait a little while for the chip to get its brains in order. */
608 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device
609 * IDs against our list and return a device name if we find a match.
610 * We also check the subsystem ID so that we can identify exactly which
611 * NIC has been found, if possible.
613 static int sf_probe(dev)
620 while(t->sf_name != NULL) {
621 if ((pci_get_vendor(dev) == t->sf_vid) &&
622 (pci_get_device(dev) == t->sf_did)) {
623 switch((pci_read_config(dev,
624 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) {
625 case AD_SUBSYSID_62011_REV0:
626 case AD_SUBSYSID_62011_REV1:
628 "Adaptec ANA-62011 10/100BaseTX");
631 case AD_SUBSYSID_62022:
633 "Adaptec ANA-62022 10/100BaseTX");
636 case AD_SUBSYSID_62044_REV0:
637 case AD_SUBSYSID_62044_REV1:
639 "Adaptec ANA-62044 10/100BaseTX");
642 case AD_SUBSYSID_62020:
644 "Adaptec ANA-62020 10/100BaseFX");
647 case AD_SUBSYSID_69011:
649 "Adaptec ANA-69011 10/100BaseTX");
653 device_set_desc(dev, t->sf_name);
665 * Attach the interface. Allocate softc structures, do ifmedia
666 * setup and ethernet/BPF attach.
668 static int sf_attach(dev)
675 int unit, rid, error = 0;
679 sc = device_get_softc(dev);
680 unit = device_get_unit(dev);
681 bzero(sc, sizeof(struct sf_softc));
684 * Handle power management nonsense.
686 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF;
687 if (command == 0x01) {
689 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4);
690 if (command & SF_PSTATE_MASK) {
691 u_int32_t iobase, membase, irq;
693 /* Save important PCI config data. */
694 iobase = pci_read_config(dev, SF_PCI_LOIO, 4);
695 membase = pci_read_config(dev, SF_PCI_LOMEM, 4);
696 irq = pci_read_config(dev, SF_PCI_INTLINE, 4);
698 /* Reset the power state. */
699 printf("sf%d: chip is in D%d power mode "
700 "-- setting to D0\n", unit, command & SF_PSTATE_MASK);
701 command &= 0xFFFFFFFC;
702 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4);
704 /* Restore PCI config data. */
705 pci_write_config(dev, SF_PCI_LOIO, iobase, 4);
706 pci_write_config(dev, SF_PCI_LOMEM, membase, 4);
707 pci_write_config(dev, SF_PCI_INTLINE, irq, 4);
712 * Map control/status registers.
714 command = pci_read_config(dev, PCIR_COMMAND, 4);
715 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
716 pci_write_config(dev, PCIR_COMMAND, command, 4);
717 command = pci_read_config(dev, PCIR_COMMAND, 4);
720 if (!(command & PCIM_CMD_PORTEN)) {
721 printf("sf%d: failed to enable I/O ports!\n", unit);
726 if (!(command & PCIM_CMD_MEMEN)) {
727 printf("sf%d: failed to enable memory mapping!\n", unit);
734 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid,
735 0, ~0, 1, RF_ACTIVE);
737 if (sc->sf_res == NULL) {
738 printf ("sf%d: couldn't map ports\n", unit);
743 sc->sf_btag = rman_get_bustag(sc->sf_res);
744 sc->sf_bhandle = rman_get_bushandle(sc->sf_res);
746 /* Allocate interrupt */
748 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
749 RF_SHAREABLE | RF_ACTIVE);
751 if (sc->sf_irq == NULL) {
752 printf("sf%d: couldn't map interrupt\n", unit);
753 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
758 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET,
759 sf_intr, sc, &sc->sf_intrhand);
762 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res);
763 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
764 printf("sf%d: couldn't set up irq\n", unit);
768 callout_handle_init(&sc->sf_stat_ch);
770 /* Reset the adapter. */
774 * Get station address from the EEPROM.
776 for (i = 0; i < ETHER_ADDR_LEN; i++)
777 sc->arpcom.ac_enaddr[i] =
778 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i);
781 * An Adaptec chip was detected. Inform the world.
783 printf("sf%d: Ethernet address: %6D\n", unit,
784 sc->arpcom.ac_enaddr, ":");
788 /* Allocate the descriptor queues. */
789 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF,
790 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
792 if (sc->sf_ldata == NULL) {
793 printf("sf%d: no memory for list buffers!\n", unit);
794 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
795 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
796 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
801 bzero(sc->sf_ldata, sizeof(struct sf_list_data));
804 if (mii_phy_probe(dev, &sc->sf_miibus,
805 sf_ifmedia_upd, sf_ifmedia_sts)) {
806 printf("sf%d: MII without any phy!\n", sc->sf_unit);
807 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF);
808 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
809 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
810 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
815 ifp = &sc->arpcom.ac_if;
819 ifp->if_mtu = ETHERMTU;
820 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
821 ifp->if_ioctl = sf_ioctl;
822 ifp->if_output = ether_output;
823 ifp->if_start = sf_start;
824 ifp->if_watchdog = sf_watchdog;
825 ifp->if_init = sf_init;
826 ifp->if_baudrate = 10000000;
827 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1;
830 * Call MI attach routine.
832 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
839 static int sf_detach(dev)
848 sc = device_get_softc(dev);
849 ifp = &sc->arpcom.ac_if;
851 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
854 bus_generic_detach(dev);
855 device_delete_child(dev, sc->sf_miibus);
857 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
858 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
859 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
861 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF);
868 static int sf_init_rx_ring(sc)
871 struct sf_list_data *ld;
876 bzero((char *)ld->sf_rx_dlist_big,
877 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT);
878 bzero((char *)ld->sf_rx_clist,
879 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT);
881 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
882 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS)
889 static void sf_init_tx_ring(sc)
892 struct sf_list_data *ld;
897 bzero((char *)ld->sf_tx_dlist,
898 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT);
899 bzero((char *)ld->sf_tx_clist,
900 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT);
902 for (i = 0; i < SF_TX_DLIST_CNT; i++)
903 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID;
904 for (i = 0; i < SF_TX_CLIST_CNT; i++)
905 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX;
907 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1;
913 static int sf_newbuf(sc, c, m)
915 struct sf_rx_bufdesc_type0 *c;
918 struct mbuf *m_new = NULL;
921 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
925 MCLGET(m_new, M_DONTWAIT);
926 if (!(m_new->m_flags & M_EXT)) {
930 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
933 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
934 m_new->m_data = m_new->m_ext.ext_buf;
937 m_adj(m_new, sizeof(u_int64_t));
940 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t)));
947 * The starfire is programmed to use 'normal' mode for packet reception,
948 * which means we use the consumer/producer model for both the buffer
949 * descriptor queue and the completion descriptor queue. The only problem
950 * with this is that it involves a lot of register accesses: we have to
951 * read the RX completion consumer and producer indexes and the RX buffer
952 * producer index, plus the RX completion consumer and RX buffer producer
953 * indexes have to be updated. It would have been easier if Adaptec had
954 * put each index in a separate register, especially given that the damn
955 * NIC has a 512K register space.
957 * In spite of all the lovely features that Adaptec crammed into the 6915,
958 * it is marred by one truly stupid design flaw, which is that receive
959 * buffer addresses must be aligned on a longword boundary. This forces
960 * the packet payload to be unaligned, which is suboptimal on the x86 and
961 * completely unuseable on the Alpha. Our only recourse is to copy received
962 * packets into properly aligned buffers before handing them off.
965 static void sf_rxeof(sc)
968 struct ether_header *eh;
971 struct sf_rx_bufdesc_type0 *desc;
972 struct sf_rx_cmpdesc_type3 *cur_rx;
973 u_int32_t rxcons, rxprod;
974 int cmpprodidx, cmpconsidx, bufprodidx;
976 ifp = &sc->arpcom.ac_if;
978 rxcons = csr_read_4(sc, SF_CQ_CONSIDX);
979 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1);
980 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX));
981 cmpconsidx = SF_IDX_LO(rxcons);
982 bufprodidx = SF_IDX_LO(rxprod);
984 while (cmpconsidx != cmpprodidx) {
987 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx];
988 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx];
990 SF_INC(cmpconsidx, SF_RX_CLIST_CNT);
991 SF_INC(bufprodidx, SF_RX_DLIST_CNT);
993 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) {
995 sf_newbuf(sc, desc, m);
999 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1000 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL);
1001 sf_newbuf(sc, desc, m);
1006 m_adj(m0, ETHER_ALIGN);
1009 eh = mtod(m, struct ether_header *);
1012 /* Remove header from mbuf and pass it on. */
1013 m_adj(m, sizeof(struct ether_header));
1014 ether_input(ifp, eh, m);
1017 csr_write_4(sc, SF_CQ_CONSIDX,
1018 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx);
1019 csr_write_4(sc, SF_RXDQ_PTR_Q1,
1020 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx);
1026 * Read the transmit status from the completion queue and release
1027 * mbufs. Note that the buffer descriptor index in the completion
1028 * descriptor is an offset from the start of the transmit buffer
1029 * descriptor list in bytes. This is important because the manual
1030 * gives the impression that it should match the producer/consumer
1031 * index, which is the offset in 8 byte blocks.
1033 static void sf_txeof(sc)
1034 struct sf_softc *sc;
1036 int txcons, cmpprodidx, cmpconsidx;
1037 struct sf_tx_cmpdesc_type1 *cur_cmp;
1038 struct sf_tx_bufdesc_type0 *cur_tx;
1041 ifp = &sc->arpcom.ac_if;
1043 txcons = csr_read_4(sc, SF_CQ_CONSIDX);
1044 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX));
1045 cmpconsidx = SF_IDX_HI(txcons);
1047 while (cmpconsidx != cmpprodidx) {
1048 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx];
1049 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7];
1051 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK)
1054 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN)
1055 sf_txthresh_adjust(sc);
1060 if (cur_tx->sf_mbuf != NULL) {
1061 m_freem(cur_tx->sf_mbuf);
1062 cur_tx->sf_mbuf = NULL;
1065 SF_INC(cmpconsidx, SF_TX_CLIST_CNT);
1069 ifp->if_flags &= ~IFF_OACTIVE;
1071 csr_write_4(sc, SF_CQ_CONSIDX,
1072 (txcons & ~SF_CQ_CONSIDX_TXQ) |
1073 ((cmpconsidx << 16) & 0xFFFF0000));
1078 static void sf_txthresh_adjust(sc)
1079 struct sf_softc *sc;
1084 txfctl = csr_read_4(sc, SF_TX_FRAMCTL);
1085 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH;
1086 if (txthresh < 0xFF) {
1088 txfctl &= ~SF_TXFRMCTL_TXTHRESH;
1091 printf("sf%d: tx underrun, increasing "
1092 "tx threshold to %d bytes\n",
1093 sc->sf_unit, txthresh * 4);
1095 csr_write_4(sc, SF_TX_FRAMCTL, txfctl);
1101 static void sf_intr(arg)
1104 struct sf_softc *sc;
1109 ifp = &sc->arpcom.ac_if;
1111 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED))
1114 /* Disable interrupts. */
1115 csr_write_4(sc, SF_IMR, 0x00000000);
1118 status = csr_read_4(sc, SF_ISR);
1120 csr_write_4(sc, SF_ISR, status);
1122 if (!(status & SF_INTRS))
1125 if (status & SF_ISR_RXDQ1_DMADONE)
1128 if (status & SF_ISR_TX_TXDONE ||
1129 status & SF_ISR_TX_DMADONE ||
1130 status & SF_ISR_TX_QUEUEDONE)
1133 if (status & SF_ISR_TX_LOFIFO)
1134 sf_txthresh_adjust(sc);
1136 if (status & SF_ISR_ABNORMALINTR) {
1137 if (status & SF_ISR_STATSOFLOW) {
1138 untimeout(sf_stats_update, sc,
1140 sf_stats_update(sc);
1146 /* Re-enable interrupts. */
1147 csr_write_4(sc, SF_IMR, SF_INTRS);
1149 if (ifp->if_snd.ifq_head != NULL)
1155 static void sf_init(xsc)
1158 struct sf_softc *sc;
1160 struct mii_data *mii;
1166 ifp = &sc->arpcom.ac_if;
1167 mii = device_get_softc(sc->sf_miibus);
1172 /* Init all the receive filter registers */
1173 for (i = SF_RXFILT_PERFECT_BASE;
1174 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
1175 csr_write_4(sc, i, 0);
1177 /* Empty stats counter registers. */
1178 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++)
1179 csr_write_4(sc, SF_STATS_BASE +
1180 (i + sizeof(u_int32_t)), 0);
1182 /* Init our MAC address */
1183 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1184 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1185 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr);
1187 if (sf_init_rx_ring(sc) == ENOBUFS) {
1188 printf("sf%d: initialization failed: no "
1189 "memory for rx buffers\n", sc->sf_unit);
1194 sf_init_tx_ring(sc);
1196 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN);
1198 /* If we want promiscuous mode, set the allframes bit. */
1199 if (ifp->if_flags & IFF_PROMISC) {
1200 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1202 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1205 if (ifp->if_flags & IFF_BROADCAST) {
1206 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1208 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1212 * Load the multicast filter.
1216 /* Init the completion queue indexes */
1217 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1218 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1220 /* Init the RX completion queue */
1221 csr_write_4(sc, SF_RXCQ_CTL_1,
1222 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR);
1223 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3);
1225 /* Init RX DMA control. */
1226 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS);
1228 /* Init the RX buffer descriptor queue. */
1229 csr_write_4(sc, SF_RXDQ_ADDR_Q1,
1230 vtophys(sc->sf_ldata->sf_rx_dlist_big));
1231 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES);
1232 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
1234 /* Init the TX completion queue */
1235 csr_write_4(sc, SF_TXCQ_CTL,
1236 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR);
1238 /* Init the TX buffer descriptor queue. */
1239 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO,
1240 vtophys(sc->sf_ldata->sf_tx_dlist));
1241 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX);
1242 csr_write_4(sc, SF_TXDQ_CTL,
1243 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES);
1244 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP);
1246 /* Enable autopadding of short TX frames. */
1247 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD);
1249 /* Enable interrupts. */
1250 csr_write_4(sc, SF_IMR, SF_INTRS);
1251 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB);
1253 /* Enable the RX and TX engines. */
1254 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB);
1255 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB);
1257 /*mii_mediachg(mii);*/
1258 sf_ifmedia_upd(ifp);
1260 ifp->if_flags |= IFF_RUNNING;
1261 ifp->if_flags &= ~IFF_OACTIVE;
1263 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz);
1270 static int sf_encap(sc, c, m_head)
1271 struct sf_softc *sc;
1272 struct sf_tx_bufdesc_type0 *c;
1273 struct mbuf *m_head;
1276 struct sf_frag *f = NULL;
1281 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1282 if (m->m_len != 0) {
1283 if (frag == SF_MAXFRAGS)
1285 f = &c->sf_frags[frag];
1287 f->sf_pktlen = m_head->m_pkthdr.len;
1288 f->sf_fraglen = m->m_len;
1289 f->sf_addr = vtophys(mtod(m, vm_offset_t));
1295 struct mbuf *m_new = NULL;
1297 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1298 if (m_new == NULL) {
1299 printf("sf%d: no memory for tx list", sc->sf_unit);
1303 if (m_head->m_pkthdr.len > MHLEN) {
1304 MCLGET(m_new, M_DONTWAIT);
1305 if (!(m_new->m_flags & M_EXT)) {
1307 printf("sf%d: no memory for tx list",
1312 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1313 mtod(m_new, caddr_t));
1314 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1317 f = &c->sf_frags[0];
1318 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len;
1319 f->sf_addr = vtophys(mtod(m_head, caddr_t));
1323 c->sf_mbuf = m_head;
1324 c->sf_id = SF_TX_BUFDESC_ID;
1325 c->sf_fragcnt = frag;
1333 static void sf_start(ifp)
1336 struct sf_softc *sc;
1337 struct sf_tx_bufdesc_type0 *cur_tx = NULL;
1338 struct mbuf *m_head = NULL;
1343 if (!sc->sf_link && ifp->if_snd.ifq_len < 10)
1346 if (ifp->if_flags & IFF_OACTIVE)
1349 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1350 i = SF_IDX_HI(txprod) >> 4;
1352 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1353 printf("sf%d: TX ring full, resetting\n", sc->sf_unit);
1355 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1356 i = SF_IDX_HI(txprod) >> 4;
1359 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) {
1360 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) {
1361 ifp->if_flags |= IFF_OACTIVE;
1365 IF_DEQUEUE(&ifp->if_snd, m_head);
1369 cur_tx = &sc->sf_ldata->sf_tx_dlist[i];
1370 if (sf_encap(sc, cur_tx, m_head)) {
1371 IF_PREPEND(&ifp->if_snd, m_head);
1372 ifp->if_flags |= IFF_OACTIVE;
1379 * If there's a BPF listener, bounce a copy of this frame
1383 bpf_mtap(ifp, m_head);
1385 SF_INC(i, SF_TX_DLIST_CNT);
1388 * Don't get the TX DMA queue get too full.
1390 if (sc->sf_tx_cnt > 64)
1398 csr_write_4(sc, SF_TXDQ_PRODIDX,
1399 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) |
1400 ((i << 20) & 0xFFFF0000));
1407 static void sf_stop(sc)
1408 struct sf_softc *sc;
1413 ifp = &sc->arpcom.ac_if;
1415 untimeout(sf_stats_update, sc, sc->sf_stat_ch);
1417 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
1418 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1419 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1420 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
1421 csr_write_4(sc, SF_RXDQ_CTL_1, 0);
1422 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
1423 csr_write_4(sc, SF_TXCQ_CTL, 0);
1424 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
1425 csr_write_4(sc, SF_TXDQ_CTL, 0);
1430 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1431 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) {
1432 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf);
1433 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL;
1437 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1438 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1439 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf);
1440 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL;
1444 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1450 * Note: it is important that this function not be interrupted. We
1451 * use a two-stage register access scheme: if we are interrupted in
1452 * between setting the indirect address register and reading from the
1453 * indirect data register, the contents of the address register could
1454 * be changed out from under us.
1456 static void sf_stats_update(xsc)
1459 struct sf_softc *sc;
1461 struct mii_data *mii;
1462 struct sf_stats stats;
1469 ifp = &sc->arpcom.ac_if;
1470 mii = device_get_softc(sc->sf_miibus);
1472 ptr = (u_int32_t *)&stats;
1473 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1474 ptr[i] = csr_read_4(sc, SF_STATS_BASE +
1475 (i + sizeof(u_int32_t)));
1477 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1478 csr_write_4(sc, SF_STATS_BASE +
1479 (i + sizeof(u_int32_t)), 0);
1481 ifp->if_collisions += stats.sf_tx_single_colls +
1482 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls;
1487 if (mii->mii_media_status & IFM_ACTIVE &&
1488 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1490 if (ifp->if_snd.ifq_head != NULL)
1494 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz);
1501 static void sf_watchdog(ifp)
1504 struct sf_softc *sc;
1509 printf("sf%d: watchdog timeout\n", sc->sf_unit);
1515 if (ifp->if_snd.ifq_head != NULL)
1521 static void sf_shutdown(dev)
1524 struct sf_softc *sc;
1526 sc = device_get_softc(dev);