sys/dev/netif/sk/if_sk.c

   1 /*      $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */
   2
   3 /*
   4  * Copyright (c) 1997, 1998, 1999, 2000
   5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Bill Paul.
  18  * 4. Neither the name of the author nor the names of any co-contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  32  * THE POSSIBILITY OF SUCH DAMAGE.
  33  *
  34  * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $
  35  * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.9 2003/11/20 22:07:30 dillon Exp $
  36  *
  37  * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $
  38  */
  39
  40 /*
  41  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
  42  *
  43  * Permission to use, copy, modify, and distribute this software for any
  44  * purpose with or without fee is hereby granted, provided that the above
  45  * copyright notice and this permission notice appear in all copies.
  46  *
  47  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  48  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  49  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  50  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  51  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  52  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  53  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  54  */
  55
  56 /*
  57  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
  58  * the SK-984x series adapters, both single port and dual port.
  59  * References:
  60  *      The XaQti XMAC II datasheet,
  61  *  http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  62  *      The SysKonnect GEnesis manual, http://www.syskonnect.com
  63  *
  64  * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the
  65  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
  66  * convenience to others until Vitesse corrects this problem:
  67  *
  68  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  69  *
  70  * Written by Bill Paul <wpaul@ee.columbia.edu>
  71  * Department of Electrical Engineering
  72  * Columbia University, New York City
  73  */
  74
  75 /*
  76  * The SysKonnect gigabit ethernet adapters consist of two main
  77  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
  78  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
  79  * components and a PHY while the GEnesis controller provides a PCI
  80  * interface with DMA support. Each card may have between 512K and
  81  * 2MB of SRAM on board depending on the configuration.
  82  *
  83  * The SysKonnect GEnesis controller can have either one or two XMAC
  84  * chips connected to it, allowing single or dual port NIC configurations.
  85  * SysKonnect has the distinction of being the only vendor on the market
  86  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
  87  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
  88  * XMAC registers. This driver takes advantage of these features to allow
  89  * both XMACs to operate as independent interfaces.
  90  */
  91
  92 #include <sys/param.h>
  93 #include <sys/systm.h>
  94 #include <sys/sockio.h>
  95 #include <sys/mbuf.h>
  96 #include <sys/malloc.h>
  97 #include <sys/kernel.h>
  98 #include <sys/socket.h>
  99 #include <sys/queue.h>
 100
 101 #include <net/if.h>
 102 #include <net/if_arp.h>
 103 #include <net/ethernet.h>
 104 #include <net/if_dl.h>
 105 #include <net/if_media.h>
 106
 107 #include <net/bpf.h>
 108
 109 #include <vm/vm.h>              /* for vtophys */
 110 #include <vm/pmap.h>            /* for vtophys */
 111 #include <machine/clock.h>      /* for DELAY */
 112 #include <machine/bus_pio.h>
 113 #include <machine/bus_memio.h>
 114 #include <machine/bus.h>
 115 #include <machine/resource.h>
 116 #include <sys/bus.h>
 117 #include <sys/rman.h>
 118
 119 #include "../mii_layer/mii.h"
 120 #include "../mii_layer/miivar.h"
 121 #include "../mii_layer/brgphyreg.h"
 122
 123 #include <bus/pci/pcireg.h>
 124 #include <bus/pci/pcivar.h>
 125
 126 #if 0
 127 #define SK_USEIOSPACE
 128 #endif
 129
 130 #include "if_skreg.h"
 131 #include "xmaciireg.h"
 132 #include "yukonreg.h"
 133
 134 /* "controller miibus0" required.  See GENERIC if you get errors here. */
 135 #include "miibus_if.h"
 136
 137 static struct sk_type sk_devs[] = {
 138         {
 139                 VENDORID_SK,
 140                 DEVICEID_SK_V1,
 141                 "SysKonnect Gigabit Ethernet (V1.0)"
 142         },
 143         {
 144                 VENDORID_SK,
 145                 DEVICEID_SK_V2,
 146                 "SysKonnect Gigabit Ethernet (V2.0)"
 147         },
 148         {
 149                 VENDORID_MARVELL,
 150                 DEVICEID_SK_V2,
 151                 "Marvell Gigabit Ethernet"
 152         },
 153         {
 154                 VENDORID_3COM,
 155                 DEVICEID_3COM_3C940,
 156                 "3Com 3C940 Gigabit Ethernet"
 157         },
 158         { 0, 0, NULL }
 159 };
 160
 161 static int skc_probe            (device_t);
 162 static int skc_attach           (device_t);
 163 static int skc_detach           (device_t);
 164 static void skc_shutdown        (device_t);
 165 static int sk_probe             (device_t);
 166 static int sk_attach            (device_t);
 167 static int sk_detach            (device_t);
 168 static void sk_tick             (void *);
 169 static void sk_intr             (void *);
 170 static void sk_intr_bcom        (struct sk_if_softc *);
 171 static void sk_intr_xmac        (struct sk_if_softc *);
 172 static void sk_intr_yukon       (struct sk_if_softc *);
 173 static void sk_rxeof            (struct sk_if_softc *);
 174 static void sk_txeof            (struct sk_if_softc *);
 175 static int sk_encap             (struct sk_if_softc *, struct mbuf *,
 176                                         u_int32_t *);
 177 static void sk_start            (struct ifnet *);
 178 static int sk_ioctl             (struct ifnet *, u_long, caddr_t);
 179 static void sk_init             (void *);
 180 static void sk_init_xmac        (struct sk_if_softc *);
 181 static void sk_init_yukon       (struct sk_if_softc *);
 182 static void sk_stop             (struct sk_if_softc *);
 183 static void sk_watchdog         (struct ifnet *);
 184 static int sk_ifmedia_upd       (struct ifnet *);
 185 static void sk_ifmedia_sts      (struct ifnet *, struct ifmediareq *);
 186 static void sk_reset            (struct sk_softc *);
 187 static int sk_newbuf            (struct sk_if_softc *,
 188                                         struct sk_chain *, struct mbuf *);
 189 static int sk_alloc_jumbo_mem   (struct sk_if_softc *);
 190 static void *sk_jalloc          (struct sk_if_softc *);
 191 static void sk_jfree            (caddr_t, u_int);
 192 static void sk_jref             (caddr_t, u_int);
 193 static int sk_init_rx_ring      (struct sk_if_softc *);
 194 static void sk_init_tx_ring     (struct sk_if_softc *);
 195 static u_int32_t sk_win_read_4  (struct sk_softc *, int);
 196 static u_int16_t sk_win_read_2  (struct sk_softc *, int);
 197 static u_int8_t sk_win_read_1   (struct sk_softc *, int);
 198 static void sk_win_write_4      (struct sk_softc *, int, u_int32_t);
 199 static void sk_win_write_2      (struct sk_softc *, int, u_int32_t);
 200 static void sk_win_write_1      (struct sk_softc *, int, u_int32_t);
 201 static u_int8_t sk_vpd_readbyte (struct sk_softc *, int);
 202 static void sk_vpd_read_res     (struct sk_softc *,
 203                                         struct vpd_res *, int);
 204 static void sk_vpd_read         (struct sk_softc *);
 205
 206 static int sk_miibus_readreg    (device_t, int, int);
 207 static int sk_miibus_writereg   (device_t, int, int, int);
 208 static void sk_miibus_statchg   (device_t);
 209
 210 static int sk_xmac_miibus_readreg     (struct sk_if_softc *, int, int);
 211 static int sk_xmac_miibus_writereg    (struct sk_if_softc *, int, int, int);
 212 static void sk_xmac_miibus_statchg    (struct sk_if_softc *);
 213
 214 static int sk_marv_miibus_readreg     (struct sk_if_softc *, int, int);
 215 static int sk_marv_miibus_writereg    (struct sk_if_softc *, int, int, int);
 216 static void sk_marv_miibus_statchg    (struct sk_if_softc *);
 217
 218 static u_int32_t sk_calchash    (caddr_t);
 219 static void sk_setfilt          (struct sk_if_softc *, caddr_t, int);
 220 static void sk_setmulti         (struct sk_if_softc *);
 221 static void sk_setpromisc       (struct sk_if_softc *);
 222
 223 #ifdef SK_USEIOSPACE
 224 #define SK_RES          SYS_RES_IOPORT
 225 #define SK_RID          SK_PCI_LOIO
 226 #else
 227 #define SK_RES          SYS_RES_MEMORY
 228 #define SK_RID          SK_PCI_LOMEM
 229 #endif
 230
 231 /*
 232  * Note that we have newbus methods for both the GEnesis controller
 233  * itself and the XMAC(s). The XMACs are children of the GEnesis, and
 234  * the miibus code is a child of the XMACs. We need to do it this way
 235  * so that the miibus drivers can access the PHY registers on the
 236  * right PHY. It's not quite what I had in mind, but it's the only
 237  * design that achieves the desired effect.
 238  */
 239 static device_method_t skc_methods[] = {
 240         /* Device interface */
 241         DEVMETHOD(device_probe,         skc_probe),
 242         DEVMETHOD(device_attach,        skc_attach),
 243         DEVMETHOD(device_detach,        skc_detach),
 244         DEVMETHOD(device_shutdown,      skc_shutdown),
 245
 246         /* bus interface */
 247         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 248         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 249
 250         { 0, 0 }
 251 };
 252
 253 static driver_t skc_driver = {
 254         "skc",
 255         skc_methods,
 256         sizeof(struct sk_softc)
 257 };
 258
 259 static devclass_t skc_devclass;
 260
 261 static device_method_t sk_methods[] = {
 262         /* Device interface */
 263         DEVMETHOD(device_probe,         sk_probe),
 264         DEVMETHOD(device_attach,        sk_attach),
 265         DEVMETHOD(device_detach,        sk_detach),
 266         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 267
 268         /* bus interface */
 269         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 270         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 271
 272         /* MII interface */
 273         DEVMETHOD(miibus_readreg,       sk_miibus_readreg),
 274         DEVMETHOD(miibus_writereg,      sk_miibus_writereg),
 275         DEVMETHOD(miibus_statchg,       sk_miibus_statchg),
 276
 277         { 0, 0 }
 278 };
 279
 280 static driver_t sk_driver = {
 281         "sk",
 282         sk_methods,
 283         sizeof(struct sk_if_softc)
 284 };
 285
 286 static devclass_t sk_devclass;
 287
 288 DECLARE_DUMMY_MODULE(if_sk);
 289 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0);
 290 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0);
 291 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
 292
 293 #define SK_SETBIT(sc, reg, x)           \
 294         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
 295
 296 #define SK_CLRBIT(sc, reg, x)           \
 297         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
 298
 299 #define SK_WIN_SETBIT_4(sc, reg, x)     \
 300         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
 301
 302 #define SK_WIN_CLRBIT_4(sc, reg, x)     \
 303         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
 304
 305 #define SK_WIN_SETBIT_2(sc, reg, x)     \
 306         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
 307
 308 #define SK_WIN_CLRBIT_2(sc, reg, x)     \
 309         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
 310
 311 static u_int32_t sk_win_read_4(sc, reg)
 312         struct sk_softc         *sc;
 313         int                     reg;
 314 {
 315 #ifdef SK_USEIOSPACE
 316         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 317         return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
 318 #else
 319         return(CSR_READ_4(sc, reg));
 320 #endif
 321 }
 322
 323 static u_int16_t sk_win_read_2(sc, reg)
 324         struct sk_softc         *sc;
 325         int                     reg;
 326 {
 327 #ifdef SK_USEIOSPACE
 328         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 329         return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
 330 #else
 331         return(CSR_READ_2(sc, reg));
 332 #endif
 333 }
 334
 335 static u_int8_t sk_win_read_1(sc, reg)
 336         struct sk_softc         *sc;
 337         int                     reg;
 338 {
 339 #ifdef SK_USEIOSPACE
 340         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 341         return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
 342 #else
 343         return(CSR_READ_1(sc, reg));
 344 #endif
 345 }
 346
 347 static void sk_win_write_4(sc, reg, val)
 348         struct sk_softc         *sc;
 349         int                     reg;
 350         u_int32_t               val;
 351 {
 352 #ifdef SK_USEIOSPACE
 353         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 354         CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
 355 #else
 356         CSR_WRITE_4(sc, reg, val);
 357 #endif
 358         return;
 359 }
 360
 361 static void sk_win_write_2(sc, reg, val)
 362         struct sk_softc         *sc;
 363         int                     reg;
 364         u_int32_t               val;
 365 {
 366 #ifdef SK_USEIOSPACE
 367         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 368         CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
 369 #else
 370         CSR_WRITE_2(sc, reg, val);
 371 #endif
 372         return;
 373 }
 374
 375 static void sk_win_write_1(sc, reg, val)
 376         struct sk_softc         *sc;
 377         int                     reg;
 378         u_int32_t               val;
 379 {
 380 #ifdef SK_USEIOSPACE
 381         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 382         CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
 383 #else
 384         CSR_WRITE_1(sc, reg, val);
 385 #endif
 386         return;
 387 }
 388
 389 /*
 390  * The VPD EEPROM contains Vital Product Data, as suggested in
 391  * the PCI 2.1 specification. The VPD data is separared into areas
 392  * denoted by resource IDs. The SysKonnect VPD contains an ID string
 393  * resource (the name of the adapter), a read-only area resource
 394  * containing various key/data fields and a read/write area which
 395  * can be used to store asset management information or log messages.
 396  * We read the ID string and read-only into buffers attached to
 397  * the controller softc structure for later use. At the moment,
 398  * we only use the ID string during sk_attach().
 399  */
 400 static u_int8_t sk_vpd_readbyte(sc, addr)
 401         struct sk_softc         *sc;
 402         int                     addr;
 403 {
 404         int                     i;
 405
 406         sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr);
 407         for (i = 0; i < SK_TIMEOUT; i++) {
 408                 DELAY(1);
 409                 if (sk_win_read_2(sc,
 410                     SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG)
 411                         break;
 412         }
 413
 414         if (i == SK_TIMEOUT)
 415                 return(0);
 416
 417         return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)));
 418 }
 419
 420 static void sk_vpd_read_res(sc, res, addr)
 421         struct sk_softc         *sc;
 422         struct vpd_res          *res;
 423         int                     addr;
 424 {
 425         int                     i;
 426         u_int8_t                *ptr;
 427
 428         ptr = (u_int8_t *)res;
 429         for (i = 0; i < sizeof(struct vpd_res); i++)
 430                 ptr[i] = sk_vpd_readbyte(sc, i + addr);
 431
 432         return;
 433 }
 434
 435 static void sk_vpd_read(sc)
 436         struct sk_softc         *sc;
 437 {
 438         int                     pos = 0, i;
 439         struct vpd_res          res;
 440
 441         if (sc->sk_vpd_prodname != NULL)
 442                 free(sc->sk_vpd_prodname, M_DEVBUF);
 443         if (sc->sk_vpd_readonly != NULL)
 444                 free(sc->sk_vpd_readonly, M_DEVBUF);
 445         sc->sk_vpd_prodname = NULL;
 446         sc->sk_vpd_readonly = NULL;
 447
 448         sk_vpd_read_res(sc, &res, pos);
 449
 450         if (res.vr_id != VPD_RES_ID) {
 451                 printf("skc%d: bad VPD resource id: expected %x got %x\n",
 452                     sc->sk_unit, VPD_RES_ID, res.vr_id);
 453                 return;
 454         }
 455
 456         pos += sizeof(res);
 457         sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
 458         for (i = 0; i < res.vr_len; i++)
 459                 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos);
 460         sc->sk_vpd_prodname[i] = '\0';
 461         pos += i;
 462
 463         sk_vpd_read_res(sc, &res, pos);
 464
 465         if (res.vr_id != VPD_RES_READ) {
 466                 printf("skc%d: bad VPD resource id: expected %x got %x\n",
 467                     sc->sk_unit, VPD_RES_READ, res.vr_id);
 468                 return;
 469         }
 470
 471         pos += sizeof(res);
 472         sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
 473         for (i = 0; i < res.vr_len + 1; i++)
 474                 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos);
 475
 476         return;
 477 }
 478
 479 static int sk_miibus_readreg(dev, phy, reg)
 480         device_t                dev;
 481         int                     phy, reg;
 482 {
 483         struct sk_if_softc      *sc_if;
 484
 485         sc_if = device_get_softc(dev);
 486
 487         switch(sc_if->sk_softc->sk_type) {
 488         case SK_GENESIS:
 489                 return(sk_xmac_miibus_readreg(sc_if, phy, reg));
 490         case SK_YUKON:
 491                 return(sk_marv_miibus_readreg(sc_if, phy, reg));
 492         }
 493
 494         return(0);
 495 }
 496
 497 static int sk_miibus_writereg(dev, phy, reg, val)
 498         device_t                dev;
 499         int                     phy, reg, val;
 500 {
 501         struct sk_if_softc      *sc_if;
 502
 503         sc_if = device_get_softc(dev);
 504
 505         switch(sc_if->sk_softc->sk_type) {
 506         case SK_GENESIS:
 507                 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val));
 508         case SK_YUKON:
 509                 return(sk_marv_miibus_writereg(sc_if, phy, reg, val));
 510         }
 511
 512         return(0);
 513 }
 514
 515 static void sk_miibus_statchg(dev)
 516         device_t                dev;
 517 {
 518         struct sk_if_softc      *sc_if;
 519
 520         sc_if = device_get_softc(dev);
 521
 522         switch(sc_if->sk_softc->sk_type) {
 523         case SK_GENESIS:
 524                 sk_xmac_miibus_statchg(sc_if);
 525                 break;
 526         case SK_YUKON:
 527                 sk_marv_miibus_statchg(sc_if);
 528                 break;
 529         }
 530
 531         return;
 532 }
 533
 534 static int sk_xmac_miibus_readreg(sc_if, phy, reg)
 535         struct sk_if_softc      *sc_if;
 536         int                     phy, reg;
 537 {
 538         int                     i;
 539
 540         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
 541                 return(0);
 542
 543         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 544         SK_XM_READ_2(sc_if, XM_PHY_DATA);
 545         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 546                 for (i = 0; i < SK_TIMEOUT; i++) {
 547                         DELAY(1);
 548                         if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
 549                             XM_MMUCMD_PHYDATARDY)
 550                                 break;
 551                 }
 552
 553                 if (i == SK_TIMEOUT) {
 554                         printf("sk%d: phy failed to come ready\n",
 555                             sc_if->sk_unit);
 556                         return(0);
 557                 }
 558         }
 559         DELAY(1);
 560         return(SK_XM_READ_2(sc_if, XM_PHY_DATA));
 561 }
 562
 563 static int sk_xmac_miibus_writereg(sc_if, phy, reg, val)
 564         struct sk_if_softc      *sc_if;
 565         int                     phy, reg, val;
 566 {
 567         int                     i;
 568
 569         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 570         for (i = 0; i < SK_TIMEOUT; i++) {
 571                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 572                         break;
 573         }
 574
 575         if (i == SK_TIMEOUT) {
 576                 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit);
 577                 return(ETIMEDOUT);
 578         }
 579
 580         SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
 581         for (i = 0; i < SK_TIMEOUT; i++) {
 582                 DELAY(1);
 583                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 584                         break;
 585         }
 586
 587         if (i == SK_TIMEOUT)
 588                 printf("sk%d: phy write timed out\n", sc_if->sk_unit);
 589
 590         return(0);
 591 }
 592
 593 static void sk_xmac_miibus_statchg(sc_if)
 594         struct sk_if_softc      *sc_if;
 595 {
 596         struct mii_data         *mii;
 597
 598         mii = device_get_softc(sc_if->sk_miibus);
 599
 600         /*
 601          * If this is a GMII PHY, manually set the XMAC's
 602          * duplex mode accordingly.
 603          */
 604         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 605                 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 606                         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 607                 } else {
 608                         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 609                 }
 610         }
 611
 612         return;
 613 }
 614
 615 static int sk_marv_miibus_readreg(sc_if, phy, reg)
 616         struct sk_if_softc      *sc_if;
 617         int                     phy, reg;
 618 {
 619         u_int16_t               val;
 620         int                     i;
 621
 622         if (phy != 0 ||
 623             (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
 624              sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
 625                 return(0);
 626         }
 627
 628         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 629                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
 630
 631         for (i = 0; i < SK_TIMEOUT; i++) {
 632                 DELAY(1);
 633                 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
 634                 if (val & YU_SMICR_READ_VALID)
 635                         break;
 636         }
 637
 638         if (i == SK_TIMEOUT) {
 639                 printf("sk%d: phy failed to come ready\n",
 640                     sc_if->sk_unit);
 641                 return(0);
 642         }
 643
 644         val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
 645
 646         return(val);
 647 }
 648
 649 static int sk_marv_miibus_writereg(sc_if, phy, reg, val)
 650         struct sk_if_softc      *sc_if;
 651         int                     phy, reg, val;
 652 {
 653         int                     i;
 654
 655         SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
 656         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 657                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
 658
 659         for (i = 0; i < SK_TIMEOUT; i++) {
 660                 DELAY(1);
 661                 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)
 662                         break;
 663         }
 664
 665         return(0);
 666 }
 667
 668 static void sk_marv_miibus_statchg(sc_if)
 669         struct sk_if_softc      *sc_if;
 670 {
 671         return;
 672 }
 673
 674 #define SK_POLY         0xEDB88320
 675 #define SK_BITS         6
 676
 677 static u_int32_t sk_calchash(addr)
 678         caddr_t                 addr;
 679 {
 680         u_int32_t               idx, bit, data, crc;
 681
 682         /* Compute CRC for the address value. */
 683         crc = 0xFFFFFFFF; /* initial value */
 684
 685         for (idx = 0; idx < 6; idx++) {
 686                 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
 687                         crc = (crc >> 1) ^ (((crc ^ data) & 1) ? SK_POLY : 0);
 688         }
 689
 690         return (~crc & ((1 << SK_BITS) - 1));
 691 }
 692
 693 static void sk_setfilt(sc_if, addr, slot)
 694         struct sk_if_softc      *sc_if;
 695         caddr_t                 addr;
 696         int                     slot;
 697 {
 698         int                     base;
 699
 700         base = XM_RXFILT_ENTRY(slot);
 701
 702         SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0]));
 703         SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2]));
 704         SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4]));
 705
 706         return;
 707 }
 708
 709 static void sk_setmulti(sc_if)
 710         struct sk_if_softc      *sc_if;
 711 {
 712         struct sk_softc         *sc = sc_if->sk_softc;
 713         struct ifnet            *ifp = &sc_if->arpcom.ac_if;
 714         u_int32_t               hashes[2] = { 0, 0 };
 715         int                     h, i;
 716         struct ifmultiaddr      *ifma;
 717         u_int8_t                dummy[] = { 0, 0, 0, 0, 0 ,0 };
 718
 719
 720         /* First, zot all the existing filters. */
 721         switch(sc->sk_type) {
 722         case SK_GENESIS:
 723                 for (i = 1; i < XM_RXFILT_MAX; i++)
 724                         sk_setfilt(sc_if, (caddr_t)&dummy, i);
 725
 726                 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
 727                 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
 728                 break;
 729         case SK_YUKON:
 730                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
 731                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
 732                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
 733                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
 734                 break;
 735         }
 736
 737         /* Now program new ones. */
 738         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 739                 hashes[0] = 0xFFFFFFFF;
 740                 hashes[1] = 0xFFFFFFFF;
 741         } else {
 742                 i = 1;
 743                 /* First find the tail of the list. */
 744                 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
 745                                         ifma = ifma->ifma_link.le_next) {
 746                         if (ifma->ifma_link.le_next == NULL)
 747                                 break;
 748                 }
 749                 /* Now traverse the list backwards. */
 750                 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
 751                         ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
 752                         if (ifma->ifma_addr->sa_family != AF_LINK)
 753                                 continue;
 754                         /*
 755                          * Program the first XM_RXFILT_MAX multicast groups
 756                          * into the perfect filter. For all others,
 757                          * use the hash table.
 758                          */
 759                         if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) {
 760                                 sk_setfilt(sc_if,
 761                         LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
 762                                 i++;
 763                                 continue;
 764                         }
 765
 766                         h = sk_calchash(
 767                                 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
 768                         if (h < 32)
 769                                 hashes[0] |= (1 << h);
 770                         else
 771                                 hashes[1] |= (1 << (h - 32));
 772                 }
 773         }
 774
 775         switch(sc->sk_type) {
 776         case SK_GENESIS:
 777                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
 778                                XM_MODE_RX_USE_PERFECT);
 779                 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
 780                 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
 781                 break;
 782         case SK_YUKON:
 783                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
 784                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
 785                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
 786                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
 787                 break;
 788         }
 789
 790         return;
 791 }
 792
 793 static void sk_setpromisc(sc_if)
 794         struct sk_if_softc      *sc_if;
 795 {
 796         struct sk_softc         *sc = sc_if->sk_softc;
 797         struct ifnet            *ifp = &sc_if->arpcom.ac_if;
 798
 799         switch(sc->sk_type) {
 800         case SK_GENESIS:
 801                 if (ifp->if_flags & IFF_PROMISC) {
 802                         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 803                 } else {
 804                         SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 805                 }
 806                 break;
 807         case SK_YUKON:
 808                 if (ifp->if_flags & IFF_PROMISC) {
 809                         SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
 810                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 811                 } else {
 812                         SK_YU_SETBIT_2(sc_if, YUKON_RCR,
 813                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 814                 }
 815                 break;
 816         }
 817
 818         return;
 819 }
 820
 821 static int sk_init_rx_ring(sc_if)
 822         struct sk_if_softc      *sc_if;
 823 {
 824         struct sk_chain_data    *cd = &sc_if->sk_cdata;
 825         struct sk_ring_data     *rd = sc_if->sk_rdata;
 826         int                     i;
 827
 828         bzero((char *)rd->sk_rx_ring,
 829             sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
 830
 831         for (i = 0; i < SK_RX_RING_CNT; i++) {
 832                 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i];
 833                 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS)
 834                         return(ENOBUFS);
 835                 if (i == (SK_RX_RING_CNT - 1)) {
 836                         cd->sk_rx_chain[i].sk_next =
 837                             &cd->sk_rx_chain[0];
 838                         rd->sk_rx_ring[i].sk_next =
 839                             vtophys(&rd->sk_rx_ring[0]);
 840                 } else {
 841                         cd->sk_rx_chain[i].sk_next =
 842                             &cd->sk_rx_chain[i + 1];
 843                         rd->sk_rx_ring[i].sk_next =
 844                             vtophys(&rd->sk_rx_ring[i + 1]);
 845                 }
 846         }
 847
 848         sc_if->sk_cdata.sk_rx_prod = 0;
 849         sc_if->sk_cdata.sk_rx_cons = 0;
 850
 851         return(0);
 852 }
 853
 854 static void sk_init_tx_ring(sc_if)
 855         struct sk_if_softc      *sc_if;
 856 {
 857         struct sk_chain_data    *cd = &sc_if->sk_cdata;
 858         struct sk_ring_data     *rd = sc_if->sk_rdata;
 859         int                     i;
 860
 861         bzero((char *)sc_if->sk_rdata->sk_tx_ring,
 862             sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
 863
 864         for (i = 0; i < SK_TX_RING_CNT; i++) {
 865                 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i];
 866                 if (i == (SK_TX_RING_CNT - 1)) {
 867                         cd->sk_tx_chain[i].sk_next =
 868                             &cd->sk_tx_chain[0];
 869                         rd->sk_tx_ring[i].sk_next =
 870                             vtophys(&rd->sk_tx_ring[0]);
 871                 } else {
 872                         cd->sk_tx_chain[i].sk_next =
 873                             &cd->sk_tx_chain[i + 1];
 874                         rd->sk_tx_ring[i].sk_next =
 875                             vtophys(&rd->sk_tx_ring[i + 1]);
 876                 }
 877         }
 878
 879         sc_if->sk_cdata.sk_tx_prod = 0;
 880         sc_if->sk_cdata.sk_tx_cons = 0;
 881         sc_if->sk_cdata.sk_tx_cnt = 0;
 882
 883         return;
 884 }
 885
 886 static int sk_newbuf(sc_if, c, m)
 887         struct sk_if_softc      *sc_if;
 888         struct sk_chain         *c;
 889         struct mbuf             *m;
 890 {
 891         struct mbuf             *m_new = NULL;
 892         struct sk_rx_desc       *r;
 893
 894         if (m == NULL) {
 895                 caddr_t                 *buf = NULL;
 896
 897                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 898                 if (m_new == NULL)
 899                         return(ENOBUFS);
 900
 901                 /* Allocate the jumbo buffer */
 902                 buf = sk_jalloc(sc_if);
 903                 if (buf == NULL) {
 904                         m_freem(m_new);
 905 #ifdef SK_VERBOSE
 906                         printf("sk%d: jumbo allocation failed "
 907                             "-- packet dropped!\n", sc_if->sk_unit);
 908 #endif
 909                         return(ENOBUFS);
 910                 }
 911
 912                 /* Attach the buffer to the mbuf */
 913                 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
 914                 m_new->m_flags |= M_EXT;
 915                 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
 916                     m_new->m_len = SK_MCLBYTES;
 917                 m_new->m_ext.ext_free = sk_jfree;
 918                 m_new->m_ext.ext_ref = sk_jref;
 919         } else {
 920                 /*
 921                  * We're re-using a previously allocated mbuf;
 922                  * be sure to re-init pointers and lengths to
 923                  * default values.
 924                  */
 925                 m_new = m;
 926                 m_new->m_len = m_new->m_pkthdr.len = SK_MCLBYTES;
 927                 m_new->m_data = m_new->m_ext.ext_buf;
 928         }
 929
 930         /*
 931          * Adjust alignment so packet payload begins on a
 932          * longword boundary. Mandatory for Alpha, useful on
 933          * x86 too.
 934          */
 935         m_adj(m_new, ETHER_ALIGN);
 936
 937         r = c->sk_desc;
 938         c->sk_mbuf = m_new;
 939         r->sk_data_lo = vtophys(mtod(m_new, caddr_t));
 940         r->sk_ctl = m_new->m_len | SK_RXSTAT;
 941
 942         return(0);
 943 }
 944
 945 /*
 946  * Allocate jumbo buffer storage. The SysKonnect adapters support
 947  * "jumbograms" (9K frames), although SysKonnect doesn't currently
 948  * use them in their drivers. In order for us to use them, we need
 949  * large 9K receive buffers, however standard mbuf clusters are only
 950  * 2048 bytes in size. Consequently, we need to allocate and manage
 951  * our own jumbo buffer pool. Fortunately, this does not require an
 952  * excessive amount of additional code.
 953  */
 954 static int sk_alloc_jumbo_mem(sc_if)
 955         struct sk_if_softc      *sc_if;
 956 {
 957         caddr_t                 ptr;
 958         int             i;
 959         struct sk_jpool_entry   *entry;
 960
 961         /* Grab a big chunk o' storage. */
 962         sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF,
 963             M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
 964
 965         if (sc_if->sk_cdata.sk_jumbo_buf == NULL) {
 966                 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit);
 967                 return(ENOBUFS);
 968         }
 969
 970         SLIST_INIT(&sc_if->sk_jfree_listhead);
 971         SLIST_INIT(&sc_if->sk_jinuse_listhead);
 972
 973         /*
 974          * Now divide it up into 9K pieces and save the addresses
 975          * in an array. Note that we play an evil trick here by using
 976          * the first few bytes in the buffer to hold the the address
 977          * of the softc structure for this interface. This is because
 978          * sk_jfree() needs it, but it is called by the mbuf management
 979          * code which will not pass it to us explicitly.
 980          */
 981         ptr = sc_if->sk_cdata.sk_jumbo_buf;
 982         for (i = 0; i < SK_JSLOTS; i++) {
 983                 u_int64_t               **aptr;
 984                 aptr = (u_int64_t **)ptr;
 985                 aptr[0] = (u_int64_t *)sc_if;
 986                 ptr += sizeof(u_int64_t);
 987                 sc_if->sk_cdata.sk_jslots[i].sk_buf = ptr;
 988                 sc_if->sk_cdata.sk_jslots[i].sk_inuse = 0;
 989                 ptr += SK_MCLBYTES;
 990                 entry = malloc(sizeof(struct sk_jpool_entry),
 991                     M_DEVBUF, M_NOWAIT);
 992                 if (entry == NULL) {
 993                         free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF);
 994                         sc_if->sk_cdata.sk_jumbo_buf = NULL;
 995                         printf("sk%d: no memory for jumbo "
 996                             "buffer queue!\n", sc_if->sk_unit);
 997                         return(ENOBUFS);
 998                 }
 999                 entry->slot = i;
1000                 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
1001                     entry, jpool_entries);
1002         }
1003
1004         return(0);
1005 }
1006
1007 /*
1008  * Allocate a jumbo buffer.
1009  */
1010 static void *sk_jalloc(sc_if)
1011         struct sk_if_softc      *sc_if;
1012 {
1013         struct sk_jpool_entry   *entry;
1014
1015         entry = SLIST_FIRST(&sc_if->sk_jfree_listhead);
1016
1017         if (entry == NULL) {
1018 #ifdef SK_VERBOSE
1019                 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit);
1020 #endif
1021                 return(NULL);
1022         }
1023
1024         SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries);
1025         SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries);
1026         sc_if->sk_cdata.sk_jslots[entry->slot].sk_inuse = 1;
1027         return(sc_if->sk_cdata.sk_jslots[entry->slot].sk_buf);
1028 }
1029
1030 /*
1031  * Adjust usage count on a jumbo buffer. In general this doesn't
1032  * get used much because our jumbo buffers don't get passed around
1033  * a lot, but it's implemented for correctness.
1034  */
1035 static void sk_jref(buf, size)
1036         caddr_t                 buf;
1037         u_int                   size;
1038 {
1039         struct sk_if_softc      *sc_if;
1040         u_int64_t               **aptr;
1041         int             i;
1042
1043         /* Extract the softc struct pointer. */
1044         aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
1045         sc_if = (struct sk_if_softc *)(aptr[0]);
1046
1047         if (sc_if == NULL)
1048                 panic("sk_jref: can't find softc pointer!");
1049
1050         if (size != SK_MCLBYTES)
1051                 panic("sk_jref: adjusting refcount of buf of wrong size!");
1052
1053         /* calculate the slot this buffer belongs to */
1054
1055         i = ((vm_offset_t)aptr
1056              - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN;
1057
1058         if ((i < 0) || (i >= SK_JSLOTS))
1059                 panic("sk_jref: asked to reference buffer "
1060                     "that we don't manage!");
1061         else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0)
1062                 panic("sk_jref: buffer already free!");
1063         else
1064                 sc_if->sk_cdata.sk_jslots[i].sk_inuse++;
1065
1066         return;
1067 }
1068
1069 /*
1070  * Release a jumbo buffer.
1071  */
1072 static void sk_jfree(buf, size)
1073         caddr_t                 buf;
1074         u_int                   size;
1075 {
1076         struct sk_if_softc      *sc_if;
1077         u_int64_t               **aptr;
1078         int                     i;
1079         struct sk_jpool_entry   *entry;
1080
1081         /* Extract the softc struct pointer. */
1082         aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
1083         sc_if = (struct sk_if_softc *)(aptr[0]);
1084
1085         if (sc_if == NULL)
1086                 panic("sk_jfree: can't find softc pointer!");
1087
1088         if (size != SK_MCLBYTES)
1089                 panic("sk_jfree: freeing buffer of wrong size!");
1090
1091         /* calculate the slot this buffer belongs to */
1092
1093         i = ((vm_offset_t)aptr
1094              - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN;
1095
1096         if ((i < 0) || (i >= SK_JSLOTS))
1097                 panic("sk_jfree: asked to free buffer that we don't manage!");
1098         else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0)
1099                 panic("sk_jfree: buffer already free!");
1100         else {
1101                 sc_if->sk_cdata.sk_jslots[i].sk_inuse--;
1102                 if(sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) {
1103                         entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead);
1104                         if (entry == NULL)
1105                                 panic("sk_jfree: buffer not in use!");
1106                         entry->slot = i;
1107                         SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead,
1108                                           jpool_entries);
1109                         SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
1110                                           entry, jpool_entries);
1111                 }
1112         }
1113
1114         return;
1115 }
1116
1117 /*
1118  * Set media options.
1119  */
1120 static int sk_ifmedia_upd(ifp)
1121         struct ifnet            *ifp;
1122 {
1123         struct sk_if_softc      *sc_if = ifp->if_softc;
1124         struct mii_data         *mii;
1125
1126         mii = device_get_softc(sc_if->sk_miibus);
1127         sk_init(sc_if);
1128         mii_mediachg(mii);
1129
1130         return(0);
1131 }
1132
1133 /*
1134  * Report current media status.
1135  */
1136 static void sk_ifmedia_sts(ifp, ifmr)
1137         struct ifnet            *ifp;
1138         struct ifmediareq       *ifmr;
1139 {
1140         struct sk_if_softc      *sc_if;
1141         struct mii_data         *mii;
1142
1143         sc_if = ifp->if_softc;
1144         mii = device_get_softc(sc_if->sk_miibus);
1145
1146         mii_pollstat(mii);
1147         ifmr->ifm_active = mii->mii_media_active;
1148         ifmr->ifm_status = mii->mii_media_status;
1149
1150         return;
1151 }
1152
1153 static int sk_ioctl(ifp, command, data)
1154         struct ifnet            *ifp;
1155         u_long                  command;
1156         caddr_t                 data;
1157 {
1158         struct sk_if_softc      *sc_if = ifp->if_softc;
1159         struct ifreq            *ifr = (struct ifreq *) data;
1160         int                     s, error = 0;
1161         struct mii_data         *mii;
1162
1163         s = splimp();
1164
1165         switch(command) {
1166         case SIOCSIFADDR:
1167         case SIOCGIFADDR:
1168                 error = ether_ioctl(ifp, command, data);
1169                 break;
1170         case SIOCSIFMTU:
1171                 if (ifr->ifr_mtu > SK_JUMBO_MTU)
1172                         error = EINVAL;
1173                 else {
1174                         ifp->if_mtu = ifr->ifr_mtu;
1175                         sk_init(sc_if);
1176                 }
1177                 break;
1178         case SIOCSIFFLAGS:
1179                 if (ifp->if_flags & IFF_UP) {
1180                         if (ifp->if_flags & IFF_RUNNING) {
1181                                 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1182                                     & IFF_PROMISC) {
1183                                         sk_setpromisc(sc_if);
1184                                         sk_setmulti(sc_if);
1185                                 }
1186                         } else
1187                                 sk_init(sc_if);
1188                 } else {
1189                         if (ifp->if_flags & IFF_RUNNING)
1190                                 sk_stop(sc_if);
1191                 }
1192                 sc_if->sk_if_flags = ifp->if_flags;
1193                 error = 0;
1194                 break;
1195         case SIOCADDMULTI:
1196         case SIOCDELMULTI:
1197                 sk_setmulti(sc_if);
1198                 error = 0;
1199                 break;
1200         case SIOCGIFMEDIA:
1201         case SIOCSIFMEDIA:
1202                 mii = device_get_softc(sc_if->sk_miibus);
1203                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1204                 break;
1205         default:
1206                 error = EINVAL;
1207                 break;
1208         }
1209
1210         (void)splx(s);
1211
1212         return(error);
1213 }
1214
1215 /*
1216  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1217  * IDs against our list and return a device name if we find a match.
1218  */
1219 static int skc_probe(dev)
1220         device_t                dev;
1221 {
1222         struct sk_softc         *sc;
1223         struct sk_type          *t = sk_devs;
1224
1225         sc = device_get_softc(dev);
1226
1227         while(t->sk_name != NULL) {
1228                 if ((pci_get_vendor(dev) == t->sk_vid) &&
1229                     (pci_get_device(dev) == t->sk_did)) {
1230                         device_set_desc(dev, t->sk_name);
1231                         return(0);
1232                 }
1233                 t++;
1234         }
1235
1236         return(ENXIO);
1237 }
1238
1239 /*
1240  * Force the GEnesis into reset, then bring it out of reset.
1241  */
1242 static void sk_reset(sc)
1243         struct sk_softc         *sc;
1244 {
1245         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1246         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1247         if (sc->sk_type == SK_YUKON)
1248                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1249
1250         DELAY(1000);
1251         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1252         DELAY(2);
1253         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1254         if (sc->sk_type == SK_YUKON)
1255                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1256
1257         if (sc->sk_type == SK_GENESIS) {
1258                 /* Configure packet arbiter */
1259                 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1260                 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1261                 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1262                 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1263                 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1264         }
1265
1266         /* Enable RAM interface */
1267         sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1268
1269         /*
1270          * Configure interrupt moderation. The moderation timer
1271          * defers interrupts specified in the interrupt moderation
1272          * timer mask based on the timeout specified in the interrupt
1273          * moderation timer init register. Each bit in the timer
1274          * register represents 18.825ns, so to specify a timeout in
1275          * microseconds, we have to multiply by 54.
1276          */
1277         sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200));
1278         sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1279             SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1280         sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1281
1282         return;
1283 }
1284
1285 static int sk_probe(dev)
1286         device_t                dev;
1287 {
1288         struct sk_softc         *sc;
1289
1290         sc = device_get_softc(device_get_parent(dev));
1291
1292         /*
1293          * Not much to do here. We always know there will be
1294          * at least one XMAC present, and if there are two,
1295          * skc_attach() will create a second device instance
1296          * for us.
1297          */
1298         switch (sc->sk_type) {
1299         case SK_GENESIS:
1300                 device_set_desc(dev, "XaQti Corp. XMAC II");
1301                 break;
1302         case SK_YUKON:
1303                 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1304                 break;
1305         }
1306
1307         return(0);
1308 }
1309
1310 /*
1311  * Each XMAC chip is attached as a separate logical IP interface.
1312  * Single port cards will have only one logical interface of course.
1313  */
1314 static int sk_attach(dev)
1315         device_t                dev;
1316 {
1317         struct sk_softc         *sc;
1318         struct sk_if_softc      *sc_if;
1319         struct ifnet            *ifp;
1320         int                     i, port;
1321
1322         if (dev == NULL)
1323                 return(EINVAL);
1324
1325         sc_if = device_get_softc(dev);
1326         sc = device_get_softc(device_get_parent(dev));
1327         port = *(int *)device_get_ivars(dev);
1328         free(device_get_ivars(dev), M_DEVBUF);
1329         device_set_ivars(dev, NULL);
1330         sc_if->sk_dev = dev;
1331
1332         bzero((char *)sc_if, sizeof(struct sk_if_softc));
1333
1334         sc_if->sk_dev = dev;
1335         sc_if->sk_unit = device_get_unit(dev);
1336         sc_if->sk_port = port;
1337         sc_if->sk_softc = sc;
1338         sc->sk_if[port] = sc_if;
1339         if (port == SK_PORT_A)
1340                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1341         if (port == SK_PORT_B)
1342                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1343
1344         /*
1345          * Get station address for this interface. Note that
1346          * dual port cards actually come with three station
1347          * addresses: one for each port, plus an extra. The
1348          * extra one is used by the SysKonnect driver software
1349          * as a 'virtual' station address for when both ports
1350          * are operating in failover mode. Currently we don't
1351          * use this extra address.
1352          */
1353         for (i = 0; i < ETHER_ADDR_LEN; i++)
1354                 sc_if->arpcom.ac_enaddr[i] =
1355                     sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1356
1357         printf("sk%d: Ethernet address: %6D\n",
1358             sc_if->sk_unit, sc_if->arpcom.ac_enaddr, ":");
1359
1360         /*
1361          * Set up RAM buffer addresses. The NIC will have a certain
1362          * amount of SRAM on it, somewhere between 512K and 2MB. We
1363          * need to divide this up a) between the transmitter and
1364          * receiver and b) between the two XMACs, if this is a
1365          * dual port NIC. Our algotithm is to divide up the memory
1366          * evenly so that everyone gets a fair share.
1367          */
1368         if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1369                 u_int32_t               chunk, val;
1370
1371                 chunk = sc->sk_ramsize / 2;
1372                 val = sc->sk_rboff / sizeof(u_int64_t);
1373                 sc_if->sk_rx_ramstart = val;
1374                 val += (chunk / sizeof(u_int64_t));
1375                 sc_if->sk_rx_ramend = val - 1;
1376                 sc_if->sk_tx_ramstart = val;
1377                 val += (chunk / sizeof(u_int64_t));
1378                 sc_if->sk_tx_ramend = val - 1;
1379         } else {
1380                 u_int32_t               chunk, val;
1381
1382                 chunk = sc->sk_ramsize / 4;
1383                 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1384                     sizeof(u_int64_t);
1385                 sc_if->sk_rx_ramstart = val;
1386                 val += (chunk / sizeof(u_int64_t));
1387                 sc_if->sk_rx_ramend = val - 1;
1388                 sc_if->sk_tx_ramstart = val;
1389                 val += (chunk / sizeof(u_int64_t));
1390                 sc_if->sk_tx_ramend = val - 1;
1391         }
1392
1393         /* Read and save PHY type and set PHY address */
1394         sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1395         switch(sc_if->sk_phytype) {
1396         case SK_PHYTYPE_XMAC:
1397                 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1398                 break;
1399         case SK_PHYTYPE_BCOM:
1400                 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1401                 break;
1402         case SK_PHYTYPE_MARV_COPPER:
1403                 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1404                 break;
1405         default:
1406                 printf("skc%d: unsupported PHY type: %d\n",
1407                     sc->sk_unit, sc_if->sk_phytype);
1408                 return(ENODEV);
1409         }
1410
1411         /* Allocate the descriptor queues. */
1412         sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF,
1413             M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1414
1415         if (sc_if->sk_rdata == NULL) {
1416                 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit);
1417                 sc->sk_if[port] = NULL;
1418                 return(ENOMEM);
1419         }
1420
1421         bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data));
1422
1423         /* Try to allocate memory for jumbo buffers. */
1424         if (sk_alloc_jumbo_mem(sc_if)) {
1425                 printf("sk%d: jumbo buffer allocation failed\n",
1426                     sc_if->sk_unit);
1427                 contigfree(sc_if->sk_rdata,
1428                     sizeof(struct sk_ring_data), M_DEVBUF);
1429                 sc->sk_if[port] = NULL;
1430                 return(ENOMEM);
1431         }
1432
1433         ifp = &sc_if->arpcom.ac_if;
1434         ifp->if_softc = sc_if;
1435         ifp->if_unit = sc_if->sk_unit;
1436         ifp->if_name = "sk";
1437         ifp->if_mtu = ETHERMTU;
1438         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1439         ifp->if_ioctl = sk_ioctl;
1440         ifp->if_output = ether_output;
1441         ifp->if_start = sk_start;
1442         ifp->if_watchdog = sk_watchdog;
1443         ifp->if_init = sk_init;
1444         ifp->if_baudrate = 1000000000;
1445         ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1;
1446
1447         /*
1448          * Do miibus setup.
1449          */
1450         switch (sc->sk_type) {
1451         case SK_GENESIS:
1452                 sk_init_xmac(sc_if);
1453                 break;
1454         case SK_YUKON:
1455                 sk_init_yukon(sc_if);
1456                 break;
1457         }
1458
1459         if (mii_phy_probe(dev, &sc_if->sk_miibus,
1460             sk_ifmedia_upd, sk_ifmedia_sts)) {
1461                 printf("skc%d: no PHY found!\n", sc_if->sk_unit);
1462                 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM,
1463                     M_DEVBUF);
1464                 contigfree(sc_if->sk_rdata,
1465                     sizeof(struct sk_ring_data), M_DEVBUF);
1466                 return(ENXIO);
1467         }
1468
1469         /*
1470          * Call MI attach routine.
1471          */
1472         ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1473         callout_handle_init(&sc_if->sk_tick_ch);
1474
1475         return(0);
1476 }
1477
1478 /*
1479  * Attach the interface. Allocate softc structures, do ifmedia
1480  * setup and ethernet/BPF attach.
1481  */
1482 static int skc_attach(dev)
1483         device_t                dev;
1484 {
1485         int                     s;
1486         u_int32_t               command;
1487         struct sk_softc         *sc;
1488         int                     unit, error = 0, rid, *port;
1489
1490         s = splimp();
1491
1492         sc = device_get_softc(dev);
1493         unit = device_get_unit(dev);
1494         bzero(sc, sizeof(struct sk_softc));
1495         switch (pci_get_device(dev)) {
1496         case DEVICEID_SK_V1:
1497                 sc->sk_type = SK_GENESIS;
1498                 break;
1499         case DEVICEID_SK_V2:
1500         case DEVICEID_3COM_3C940:
1501                 sc->sk_type = SK_YUKON;
1502                 break;
1503         }
1504
1505         /*
1506          * Handle power management nonsense.
1507          */
1508         command = pci_read_config(dev, SK_PCI_CAPID, 4) & 0x000000FF;
1509         if (command == 0x01) {
1510                 command = pci_read_config(dev, SK_PCI_PWRMGMTCTRL, 4);
1511                 if (command & SK_PSTATE_MASK) {
1512                         u_int32_t               iobase, membase, irq;
1513
1514                         /* Save important PCI config data. */
1515                         iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1516                         membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1517                         irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1518
1519                         /* Reset the power state. */
1520                         printf("skc%d: chip is in D%d power mode "
1521                         "-- setting to D0\n", unit, command & SK_PSTATE_MASK);
1522                         command &= 0xFFFFFFFC;
1523                         pci_write_config(dev, SK_PCI_PWRMGMTCTRL, command, 4);
1524
1525                         /* Restore PCI config data. */
1526                         pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1527                         pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1528                         pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
1529                 }
1530         }
1531
1532         /*
1533          * Map control/status registers.
1534          */
1535         command = pci_read_config(dev, PCIR_COMMAND, 4);
1536         command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1537         pci_write_config(dev, PCIR_COMMAND, command, 4);
1538         command = pci_read_config(dev, PCIR_COMMAND, 4);
1539
1540 #ifdef SK_USEIOSPACE
1541         if (!(command & PCIM_CMD_PORTEN)) {
1542                 printf("skc%d: failed to enable I/O ports!\n", unit);
1543                 error = ENXIO;
1544                 goto fail;
1545         }
1546 #else
1547         if (!(command & PCIM_CMD_MEMEN)) {
1548                 printf("skc%d: failed to enable memory mapping!\n", unit);
1549                 error = ENXIO;
1550                 goto fail;
1551         }
1552 #endif
1553
1554         rid = SK_RID;
1555         sc->sk_res = bus_alloc_resource(dev, SK_RES, &rid,
1556             0, ~0, 1, RF_ACTIVE);
1557
1558         if (sc->sk_res == NULL) {
1559                 printf("sk%d: couldn't map ports/memory\n", unit);
1560                 error = ENXIO;
1561                 goto fail;
1562         }
1563
1564         sc->sk_btag = rman_get_bustag(sc->sk_res);
1565         sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1566
1567         /* Allocate interrupt */
1568         rid = 0;
1569         sc->sk_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1570             RF_SHAREABLE | RF_ACTIVE);
1571
1572         if (sc->sk_irq == NULL) {
1573                 printf("skc%d: couldn't map interrupt\n", unit);
1574                 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1575                 error = ENXIO;
1576                 goto fail;
1577         }
1578
1579         error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET,
1580             sk_intr, sc, &sc->sk_intrhand);
1581
1582         if (error) {
1583                 printf("skc%d: couldn't set up irq\n", unit);
1584                 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1585                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1586                 goto fail;
1587         }
1588
1589         /* Reset the adapter. */
1590         sk_reset(sc);
1591
1592         sc->sk_unit = unit;
1593
1594         /* Read and save vital product data from EEPROM. */
1595         sk_vpd_read(sc);
1596
1597         if (sc->sk_type == SK_GENESIS) {
1598                 /* Read and save RAM size and RAMbuffer offset */
1599                 switch(sk_win_read_1(sc, SK_EPROM0)) {
1600                 case SK_RAMSIZE_512K_64:
1601                         sc->sk_ramsize = 0x80000;
1602                         sc->sk_rboff = SK_RBOFF_0;
1603                         break;
1604                 case SK_RAMSIZE_1024K_64:
1605                         sc->sk_ramsize = 0x100000;
1606                         sc->sk_rboff = SK_RBOFF_80000;
1607                         break;
1608                 case SK_RAMSIZE_1024K_128:
1609                         sc->sk_ramsize = 0x100000;
1610                         sc->sk_rboff = SK_RBOFF_0;
1611                         break;
1612                 case SK_RAMSIZE_2048K_128:
1613                         sc->sk_ramsize = 0x200000;
1614                         sc->sk_rboff = SK_RBOFF_0;
1615                         break;
1616                 default:
1617                         printf("skc%d: unknown ram size: %d\n",
1618                             sc->sk_unit, sk_win_read_1(sc, SK_EPROM0));
1619                         bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1620                         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1621                         bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1622                         error = ENXIO;
1623                         goto fail;
1624                         break;
1625                 }
1626         } else {
1627                 sc->sk_ramsize = 0x20000;
1628                 sc->sk_rboff = SK_RBOFF_0;
1629         }
1630
1631         /* Read and save physical media type */
1632         switch(sk_win_read_1(sc, SK_PMDTYPE)) {
1633         case SK_PMD_1000BASESX:
1634                 sc->sk_pmd = IFM_1000_SX;
1635                 break;
1636         case SK_PMD_1000BASELX:
1637                 sc->sk_pmd = IFM_1000_LX;
1638                 break;
1639         case SK_PMD_1000BASECX:
1640                 sc->sk_pmd = IFM_1000_CX;
1641                 break;
1642         case SK_PMD_1000BASETX:
1643                 sc->sk_pmd = IFM_1000_TX;
1644                 break;
1645         default:
1646                 printf("skc%d: unknown media type: 0x%x\n",
1647                     sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE));
1648                 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1649                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1650                 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1651                 error = ENXIO;
1652                 goto fail;
1653         }
1654
1655         /* Announce the product name. */
1656         printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname);
1657         sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1658         port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1659         *port = SK_PORT_A;
1660         device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1661
1662         if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1663                 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1664                 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1665                 *port = SK_PORT_B;
1666                 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1667         }
1668
1669         /* Turn on the 'driver is loaded' LED. */
1670         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1671
1672         bus_generic_attach(dev);
1673
1674 fail:
1675         splx(s);
1676         return(error);
1677 }
1678
1679 static int sk_detach(dev)
1680         device_t                dev;
1681 {
1682         struct sk_softc         *sc;
1683         struct sk_if_softc      *sc_if;
1684         struct ifnet            *ifp;
1685         int                     s;
1686
1687         s = splimp();
1688
1689         sc = device_get_softc(device_get_parent(dev));
1690         sc_if = device_get_softc(dev);
1691         ifp = &sc_if->arpcom.ac_if;
1692         sk_stop(sc_if);
1693         ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1694         bus_generic_detach(dev);
1695         if (sc_if->sk_miibus != NULL)
1696                 device_delete_child(dev, sc_if->sk_miibus);
1697         contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF);
1698         contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF);
1699
1700         return(0);
1701 }
1702
1703 static int skc_detach(dev)
1704         device_t                dev;
1705 {
1706         struct sk_softc         *sc;
1707         int                     s;
1708
1709         s = splimp();
1710
1711         sc = device_get_softc(dev);
1712
1713         bus_generic_detach(dev);
1714         if (sc->sk_devs[SK_PORT_A] != NULL)
1715                 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1716         if (sc->sk_devs[SK_PORT_B] != NULL)
1717                 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1718
1719         bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1720         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1721         bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1722
1723         splx(s);
1724
1725         return(0);
1726 }
1727
1728 static int sk_encap(sc_if, m_head, txidx)
1729         struct sk_if_softc      *sc_if;
1730         struct mbuf             *m_head;
1731         u_int32_t               *txidx;
1732 {
1733         struct sk_tx_desc       *f = NULL;
1734         struct mbuf             *m;
1735         u_int32_t               frag, cur, cnt = 0;
1736
1737         m = m_head;
1738         cur = frag = *txidx;
1739
1740         /*
1741          * Start packing the mbufs in this chain into
1742          * the fragment pointers. Stop when we run out
1743          * of fragments or hit the end of the mbuf chain.
1744          */
1745         for (m = m_head; m != NULL; m = m->m_next) {
1746                 if (m->m_len != 0) {
1747                         if ((SK_TX_RING_CNT -
1748                             (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2)
1749                                 return(ENOBUFS);
1750                         f = &sc_if->sk_rdata->sk_tx_ring[frag];
1751                         f->sk_data_lo = vtophys(mtod(m, vm_offset_t));
1752                         f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT;
1753                         if (cnt == 0)
1754                                 f->sk_ctl |= SK_TXCTL_FIRSTFRAG;
1755                         else
1756                                 f->sk_ctl |= SK_TXCTL_OWN;
1757                         cur = frag;
1758                         SK_INC(frag, SK_TX_RING_CNT);
1759                         cnt++;
1760                 }
1761         }
1762
1763         if (m != NULL)
1764                 return(ENOBUFS);
1765
1766         sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |=
1767                 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR;
1768         sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
1769         sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN;
1770         sc_if->sk_cdata.sk_tx_cnt += cnt;
1771
1772         *txidx = frag;
1773
1774         return(0);
1775 }
1776
1777 static void sk_start(ifp)
1778         struct ifnet            *ifp;
1779 {
1780         struct sk_softc         *sc;
1781         struct sk_if_softc      *sc_if;
1782         struct mbuf             *m_head = NULL;
1783         u_int32_t               idx;
1784
1785         sc_if = ifp->if_softc;
1786         sc = sc_if->sk_softc;
1787
1788         idx = sc_if->sk_cdata.sk_tx_prod;
1789
1790         while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
1791                 IF_DEQUEUE(&ifp->if_snd, m_head);
1792                 if (m_head == NULL)
1793                         break;
1794
1795                 /*
1796                  * Pack the data into the transmit ring. If we
1797                  * don't have room, set the OACTIVE flag and wait
1798                  * for the NIC to drain the ring.
1799                  */
1800                 if (sk_encap(sc_if, m_head, &idx)) {
1801                         IF_PREPEND(&ifp->if_snd, m_head);
1802                         ifp->if_flags |= IFF_OACTIVE;
1803                         break;
1804                 }
1805
1806                 /*
1807                  * If there's a BPF listener, bounce a copy of this frame
1808                  * to him.
1809                  */
1810                 if (ifp->if_bpf)
1811                         bpf_mtap(ifp, m_head);
1812         }
1813
1814         /* Transmit */
1815         sc_if->sk_cdata.sk_tx_prod = idx;
1816         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1817
1818         /* Set a timeout in case the chip goes out to lunch. */
1819         ifp->if_timer = 5;
1820
1821         return;
1822 }
1823
1824
1825 static void sk_watchdog(ifp)
1826         struct ifnet            *ifp;
1827 {
1828         struct sk_if_softc      *sc_if;
1829
1830         sc_if = ifp->if_softc;
1831
1832         printf("sk%d: watchdog timeout\n", sc_if->sk_unit);
1833         sk_init(sc_if);
1834
1835         return;
1836 }
1837
1838 static void skc_shutdown(dev)
1839         device_t                dev;
1840 {
1841         struct sk_softc         *sc;
1842
1843         sc = device_get_softc(dev);
1844
1845         /* Turn off the 'driver is loaded' LED. */
1846         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1847
1848         /*
1849          * Reset the GEnesis controller. Doing this should also
1850          * assert the resets on the attached XMAC(s).
1851          */
1852         sk_reset(sc);
1853
1854         return;
1855 }
1856
1857 static void sk_rxeof(sc_if)
1858         struct sk_if_softc      *sc_if;
1859 {
1860         struct ether_header     *eh;
1861         struct mbuf             *m;
1862         struct ifnet            *ifp;
1863         struct sk_chain         *cur_rx;
1864         int                     total_len = 0;
1865         int                     i;
1866         u_int32_t               rxstat;
1867
1868         ifp = &sc_if->arpcom.ac_if;
1869         i = sc_if->sk_cdata.sk_rx_prod;
1870         cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1871
1872         while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) {
1873
1874                 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1875                 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat;
1876                 m = cur_rx->sk_mbuf;
1877                 cur_rx->sk_mbuf = NULL;
1878                 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl);
1879                 SK_INC(i, SK_RX_RING_CNT);
1880
1881                 if (rxstat & XM_RXSTAT_ERRFRAME) {
1882                         ifp->if_ierrors++;
1883                         sk_newbuf(sc_if, cur_rx, m);
1884                         continue;
1885                 }
1886
1887                 /*
1888                  * Try to allocate a new jumbo buffer. If that
1889                  * fails, copy the packet to mbufs and put the
1890                  * jumbo buffer back in the ring so it can be
1891                  * re-used. If allocating mbufs fails, then we
1892                  * have to drop the packet.
1893                  */
1894                 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) {
1895                         struct mbuf             *m0;
1896                         m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1897                             total_len + ETHER_ALIGN, 0, ifp, NULL);
1898                         sk_newbuf(sc_if, cur_rx, m);
1899                         if (m0 == NULL) {
1900                                 printf("sk%d: no receive buffers "
1901                                     "available -- packet dropped!\n",
1902                                     sc_if->sk_unit);
1903                                 ifp->if_ierrors++;
1904                                 continue;
1905                         }
1906                         m_adj(m0, ETHER_ALIGN);
1907                         m = m0;
1908                 } else {
1909                         m->m_pkthdr.rcvif = ifp;
1910                         m->m_pkthdr.len = m->m_len = total_len;
1911                 }
1912
1913                 ifp->if_ipackets++;
1914                 eh = mtod(m, struct ether_header *);
1915
1916                 /* Remove header from mbuf and pass it on. */
1917                 m_adj(m, sizeof(struct ether_header));
1918                 ether_input(ifp, eh, m);
1919         }
1920
1921         sc_if->sk_cdata.sk_rx_prod = i;
1922
1923         return;
1924 }
1925
1926 static void sk_txeof(sc_if)
1927         struct sk_if_softc      *sc_if;
1928 {
1929         struct sk_tx_desc       *cur_tx = NULL;
1930         struct ifnet            *ifp;
1931         u_int32_t               idx;
1932
1933         ifp = &sc_if->arpcom.ac_if;
1934
1935         /*
1936          * Go through our tx ring and free mbufs for those
1937          * frames that have been sent.
1938          */
1939         idx = sc_if->sk_cdata.sk_tx_cons;
1940         while(idx != sc_if->sk_cdata.sk_tx_prod) {
1941                 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
1942                 if (cur_tx->sk_ctl & SK_TXCTL_OWN)
1943                         break;
1944                 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG)
1945                         ifp->if_opackets++;
1946                 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
1947                         m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf);
1948                         sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL;
1949                 }
1950                 sc_if->sk_cdata.sk_tx_cnt--;
1951                 SK_INC(idx, SK_TX_RING_CNT);
1952                 ifp->if_timer = 0;
1953         }
1954
1955         sc_if->sk_cdata.sk_tx_cons = idx;
1956
1957         if (cur_tx != NULL)
1958                 ifp->if_flags &= ~IFF_OACTIVE;
1959
1960         return;
1961 }
1962
1963 static void sk_tick(xsc_if)
1964         void                    *xsc_if;
1965 {
1966         struct sk_if_softc      *sc_if;
1967         struct mii_data         *mii;
1968         struct ifnet            *ifp;
1969         int                     i;
1970
1971         sc_if = xsc_if;
1972         ifp = &sc_if->arpcom.ac_if;
1973         mii = device_get_softc(sc_if->sk_miibus);
1974
1975         if (!(ifp->if_flags & IFF_UP))
1976                 return;
1977
1978         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
1979                 sk_intr_bcom(sc_if);
1980                 return;
1981         }
1982
1983         /*
1984          * According to SysKonnect, the correct way to verify that
1985          * the link has come back up is to poll bit 0 of the GPIO
1986          * register three times. This pin has the signal from the
1987          * link_sync pin connected to it; if we read the same link
1988          * state 3 times in a row, we know the link is up.
1989          */
1990         for (i = 0; i < 3; i++) {
1991                 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
1992                         break;
1993         }
1994
1995         if (i != 3) {
1996                 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
1997                 return;
1998         }
1999
2000         /* Turn the GP0 interrupt back on. */
2001         SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2002         SK_XM_READ_2(sc_if, XM_ISR);
2003         mii_tick(mii);
2004         mii_pollstat(mii);
2005         untimeout(sk_tick, sc_if, sc_if->sk_tick_ch);
2006
2007         return;
2008 }
2009
2010 static void sk_intr_bcom(sc_if)
2011         struct sk_if_softc      *sc_if;
2012 {
2013         struct sk_softc         *sc;
2014         struct mii_data         *mii;
2015         struct ifnet            *ifp;
2016         int                     status;
2017
2018         sc = sc_if->sk_softc;
2019         mii = device_get_softc(sc_if->sk_miibus);
2020         ifp = &sc_if->arpcom.ac_if;
2021
2022         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2023
2024         /*
2025          * Read the PHY interrupt register to make sure
2026          * we clear any pending interrupts.
2027          */
2028         status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
2029
2030         if (!(ifp->if_flags & IFF_RUNNING)) {
2031                 sk_init_xmac(sc_if);
2032                 return;
2033         }
2034
2035         if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
2036                 int                     lstat;
2037                 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
2038                     BRGPHY_MII_AUXSTS);
2039
2040                 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2041                         mii_mediachg(mii);
2042                         /* Turn off the link LED. */
2043                         SK_IF_WRITE_1(sc_if, 0,
2044                             SK_LINKLED1_CTL, SK_LINKLED_OFF);
2045                         sc_if->sk_link = 0;
2046                 } else if (status & BRGPHY_ISR_LNK_CHG) {
2047                         sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2048                             BRGPHY_MII_IMR, 0xFF00);
2049                         mii_tick(mii);
2050                         sc_if->sk_link = 1;
2051                         /* Turn on the link LED. */
2052                         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2053                             SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
2054                             SK_LINKLED_BLINK_OFF);
2055                         mii_pollstat(mii);
2056                 } else {
2057                         mii_tick(mii);
2058                         sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
2059                 }
2060         }
2061
2062         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2063
2064         return;
2065 }
2066
2067 static void sk_intr_xmac(sc_if)
2068         struct sk_if_softc      *sc_if;
2069 {
2070         struct sk_softc         *sc;
2071         u_int16_t               status;
2072         struct mii_data         *mii;
2073
2074         sc = sc_if->sk_softc;
2075         mii = device_get_softc(sc_if->sk_miibus);
2076         status = SK_XM_READ_2(sc_if, XM_ISR);
2077
2078         /*
2079          * Link has gone down. Start MII tick timeout to
2080          * watch for link resync.
2081          */
2082         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
2083                 if (status & XM_ISR_GP0_SET) {
2084                         SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2085                         sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
2086                 }
2087
2088                 if (status & XM_ISR_AUTONEG_DONE) {
2089                         sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
2090                 }
2091         }
2092
2093         if (status & XM_IMR_TX_UNDERRUN)
2094                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
2095
2096         if (status & XM_IMR_RX_OVERRUN)
2097                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
2098
2099         status = SK_XM_READ_2(sc_if, XM_ISR);
2100
2101         return;
2102 }
2103
2104 static void sk_intr_yukon(sc_if)
2105         struct sk_if_softc      *sc_if;
2106 {
2107         int status;
2108
2109         status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2110
2111         return;
2112 }
2113
2114 static void sk_intr(xsc)
2115         void                    *xsc;
2116 {
2117         struct sk_softc         *sc = xsc;
2118         struct sk_if_softc      *sc_if0 = NULL, *sc_if1 = NULL;
2119         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
2120         u_int32_t               status;
2121
2122         sc_if0 = sc->sk_if[SK_PORT_A];
2123         sc_if1 = sc->sk_if[SK_PORT_B];
2124
2125         if (sc_if0 != NULL)
2126                 ifp0 = &sc_if0->arpcom.ac_if;
2127         if (sc_if1 != NULL)
2128                 ifp1 = &sc_if1->arpcom.ac_if;
2129
2130         for (;;) {
2131                 status = CSR_READ_4(sc, SK_ISSR);
2132                 if (!(status & sc->sk_intrmask))
2133                         break;
2134
2135                 /* Handle receive interrupts first. */
2136                 if (status & SK_ISR_RX1_EOF) {
2137                         sk_rxeof(sc_if0);
2138                         CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
2139                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2140                 }
2141                 if (status & SK_ISR_RX2_EOF) {
2142                         sk_rxeof(sc_if1);
2143                         CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
2144                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2145                 }
2146
2147                 /* Then transmit interrupts. */
2148                 if (status & SK_ISR_TX1_S_EOF) {
2149                         sk_txeof(sc_if0);
2150                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
2151                             SK_TXBMU_CLR_IRQ_EOF);
2152                 }
2153                 if (status & SK_ISR_TX2_S_EOF) {
2154                         sk_txeof(sc_if1);
2155                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
2156                             SK_TXBMU_CLR_IRQ_EOF);
2157                 }
2158
2159                 /* Then MAC interrupts. */
2160                 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) {
2161                         if (sc->sk_type == SK_GENESIS)
2162                                 sk_intr_xmac(sc_if0);
2163                         else
2164                                 sk_intr_yukon(sc_if0);
2165                 }
2166
2167                 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) {
2168                         if (sc->sk_type == SK_GENESIS)
2169                                 sk_intr_xmac(sc_if1);
2170                         else
2171                                 sk_intr_yukon(sc_if0);
2172                 }
2173
2174                 if (status & SK_ISR_EXTERNAL_REG) {
2175                         if (ifp0 != NULL &&
2176                             sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
2177                                 sk_intr_bcom(sc_if0);
2178                         if (ifp1 != NULL &&
2179                             sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
2180                                 sk_intr_bcom(sc_if1);
2181                 }
2182         }
2183
2184         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2185
2186         if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL)
2187                 sk_start(ifp0);
2188         if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL)
2189                 sk_start(ifp1);
2190
2191         return;
2192 }
2193
2194 static void sk_init_xmac(sc_if)
2195         struct sk_if_softc      *sc_if;
2196 {
2197         struct sk_softc         *sc;
2198         struct ifnet            *ifp;
2199         struct sk_bcom_hack     bhack[] = {
2200         { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
2201         { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
2202         { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
2203         { 0, 0 } };
2204
2205         sc = sc_if->sk_softc;
2206         ifp = &sc_if->arpcom.ac_if;
2207
2208         /* Unreset the XMAC. */
2209         SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
2210         DELAY(1000);
2211
2212         /* Reset the XMAC's internal state. */
2213         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2214
2215         /* Save the XMAC II revision */
2216         sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
2217
2218         /*
2219          * Perform additional initialization for external PHYs,
2220          * namely for the 1000baseTX cards that use the XMAC's
2221          * GMII mode.
2222          */
2223         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2224                 int                     i = 0;
2225                 u_int32_t               val;
2226
2227                 /* Take PHY out of reset. */
2228                 val = sk_win_read_4(sc, SK_GPIO);
2229                 if (sc_if->sk_port == SK_PORT_A)
2230                         val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
2231                 else
2232                         val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
2233                 sk_win_write_4(sc, SK_GPIO, val);
2234
2235                 /* Enable GMII mode on the XMAC. */
2236                 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
2237
2238                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2239                     BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
2240                 DELAY(10000);
2241                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2242                     BRGPHY_MII_IMR, 0xFFF0);
2243
2244                 /*
2245                  * Early versions of the BCM5400 apparently have
2246                  * a bug that requires them to have their reserved
2247                  * registers initialized to some magic values. I don't
2248                  * know what the numbers do, I'm just the messenger.
2249                  */
2250                 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
2251                     == 0x6041) {
2252                         while(bhack[i].reg) {
2253                                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2254                                     bhack[i].reg, bhack[i].val);
2255                                 i++;
2256                         }
2257                 }
2258         }
2259
2260         /* Set station address */
2261         SK_XM_WRITE_2(sc_if, XM_PAR0,
2262             *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0]));
2263         SK_XM_WRITE_2(sc_if, XM_PAR1,
2264             *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2]));
2265         SK_XM_WRITE_2(sc_if, XM_PAR2,
2266             *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4]));
2267         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
2268
2269         if (ifp->if_flags & IFF_BROADCAST) {
2270                 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2271         } else {
2272                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2273         }
2274
2275         /* We don't need the FCS appended to the packet. */
2276         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2277
2278         /* We want short frames padded to 60 bytes. */
2279         SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2280
2281         /*
2282          * Enable the reception of all error frames. This is is
2283          * a necessary evil due to the design of the XMAC. The
2284          * XMAC's receive FIFO is only 8K in size, however jumbo
2285          * frames can be up to 9000 bytes in length. When bad
2286          * frame filtering is enabled, the XMAC's RX FIFO operates
2287          * in 'store and forward' mode. For this to work, the
2288          * entire frame has to fit into the FIFO, but that means
2289          * that jumbo frames larger than 8192 bytes will be
2290          * truncated. Disabling all bad frame filtering causes
2291          * the RX FIFO to operate in streaming mode, in which
2292          * case the XMAC will start transfering frames out of the
2293          * RX FIFO as soon as the FIFO threshold is reached.
2294          */
2295         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2296             XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2297             XM_MODE_RX_INRANGELEN);
2298
2299         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2300                 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2301         else
2302                 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2303
2304         /*
2305          * Bump up the transmit threshold. This helps hold off transmit
2306          * underruns when we're blasting traffic from both ports at once.
2307          */
2308         SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2309
2310         /* Set promiscuous mode */
2311         sk_setpromisc(sc_if);
2312
2313         /* Set multicast filter */
2314         sk_setmulti(sc_if);
2315
2316         /* Clear and enable interrupts */
2317         SK_XM_READ_2(sc_if, XM_ISR);
2318         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2319                 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2320         else
2321                 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2322
2323         /* Configure MAC arbiter */
2324         switch(sc_if->sk_xmac_rev) {
2325         case XM_XMAC_REV_B2:
2326                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2327                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2328                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2329                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2330                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2331                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2332                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2333                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2334                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2335                 break;
2336         case XM_XMAC_REV_C1:
2337                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2338                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2339                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2340                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2341                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2342                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2343                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2344                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2345                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2346                 break;
2347         default:
2348                 break;
2349         }
2350         sk_win_write_2(sc, SK_MACARB_CTL,
2351             SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2352
2353         sc_if->sk_link = 1;
2354
2355         return;
2356 }
2357
2358 static void sk_init_yukon(sc_if)
2359         struct sk_if_softc      *sc_if;
2360 {
2361         u_int32_t               phy;
2362         u_int16_t               reg;
2363         int                     i;
2364
2365         /* GMAC and GPHY Reset */
2366         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2367         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2368         DELAY(1000);
2369         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR);
2370         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2371         DELAY(1000);
2372
2373         phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
2374                 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
2375
2376         switch(sc_if->sk_softc->sk_pmd) {
2377         case IFM_1000_SX:
2378         case IFM_1000_LX:
2379                 phy |= SK_GPHY_FIBER;
2380                 break;
2381
2382         case IFM_1000_CX:
2383         case IFM_1000_TX:
2384                 phy |= SK_GPHY_COPPER;
2385                 break;
2386         }
2387
2388         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2389         DELAY(1000);
2390         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2391         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2392                       SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
2393
2394         /* unused read of the interrupt source register */
2395         SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2396
2397         reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2398
2399         /* MIB Counter Clear Mode set */
2400         reg |= YU_PAR_MIB_CLR;
2401         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2402
2403         /* MIB Counter Clear Mode clear */
2404         reg &= ~YU_PAR_MIB_CLR;
2405         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2406
2407         /* receive control reg */
2408         SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
2409
2410         /* transmit parameter register */
2411         SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2412                       YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
2413
2414         /* serial mode register */
2415         SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) |
2416                       YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e));
2417
2418         /* Setup Yukon's address */
2419         for (i = 0; i < 3; i++) {
2420                 /* Write Source Address 1 (unicast filter) */
2421                 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2422                               sc_if->arpcom.ac_enaddr[i * 2] |
2423                               sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
2424         }
2425
2426         for (i = 0; i < 3; i++) {
2427                 reg = sk_win_read_2(sc_if->sk_softc,
2428                                     SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2429                 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2430         }
2431
2432         /* Set promiscuous mode */
2433         sk_setpromisc(sc_if);
2434
2435         /* Set multicast filter */
2436         sk_setmulti(sc_if);
2437
2438         /* enable interrupt mask for counter overflows */
2439         SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2440         SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2441         SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2442
2443         /* Configure RX MAC FIFO */
2444         SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2445         SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON);
2446
2447         /* Configure TX MAC FIFO */
2448         SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2449         SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2450 }
2451
2452 /*
2453  * Note that to properly initialize any part of the GEnesis chip,
2454  * you first have to take it out of reset mode.
2455  */
2456 static void sk_init(xsc)
2457         void                    *xsc;
2458 {
2459         struct sk_if_softc      *sc_if = xsc;
2460         struct sk_softc         *sc;
2461         struct ifnet            *ifp;
2462         struct mii_data         *mii;
2463         int                     s;
2464         u_int16_t               reg;
2465
2466         s = splimp();
2467
2468         ifp = &sc_if->arpcom.ac_if;
2469         sc = sc_if->sk_softc;
2470         mii = device_get_softc(sc_if->sk_miibus);
2471
2472         /* Cancel pending I/O and free all RX/TX buffers. */
2473         sk_stop(sc_if);
2474
2475         if (sc->sk_type == SK_GENESIS) {
2476                 /* Configure LINK_SYNC LED */
2477                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2478                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2479                         SK_LINKLED_LINKSYNC_ON);
2480
2481                 /* Configure RX LED */
2482                 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
2483                         SK_RXLEDCTL_COUNTER_START);
2484
2485                 /* Configure TX LED */
2486                 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2487                         SK_TXLEDCTL_COUNTER_START);
2488         }
2489
2490         /* Configure I2C registers */
2491
2492         /* Configure XMAC(s) */
2493         switch (sc->sk_type) {
2494         case SK_GENESIS:
2495                 sk_init_xmac(sc_if);
2496                 break;
2497         case SK_YUKON:
2498                 sk_init_yukon(sc_if);
2499                 break;
2500         }
2501         mii_mediachg(mii);
2502
2503         if (sc->sk_type == SK_GENESIS) {
2504                 /* Configure MAC FIFOs */
2505                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2506                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2507                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2508
2509                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2510                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2511                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2512         }
2513
2514         /* Configure transmit arbiter(s) */
2515         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2516             SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
2517
2518         /* Configure RAMbuffers */
2519         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2520         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2521         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2522         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2523         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2524         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2525
2526         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2527         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2528         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2529         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2530         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2531         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2532         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2533
2534         /* Configure BMUs */
2535         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2536         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2537             vtophys(&sc_if->sk_rdata->sk_rx_ring[0]));
2538         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
2539
2540         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2541         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2542             vtophys(&sc_if->sk_rdata->sk_tx_ring[0]));
2543         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
2544
2545         /* Init descriptors */
2546         if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2547                 printf("sk%d: initialization failed: no "
2548                     "memory for rx buffers\n", sc_if->sk_unit);
2549                 sk_stop(sc_if);
2550                 (void)splx(s);
2551                 return;
2552         }
2553         sk_init_tx_ring(sc_if);
2554
2555         /* Configure interrupt handling */
2556         CSR_READ_4(sc, SK_ISSR);
2557         if (sc_if->sk_port == SK_PORT_A)
2558                 sc->sk_intrmask |= SK_INTRS1;
2559         else
2560                 sc->sk_intrmask |= SK_INTRS2;
2561
2562         sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2563
2564         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2565
2566         /* Start BMUs. */
2567         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2568
2569         switch(sc->sk_type) {
2570         case SK_GENESIS:
2571                 /* Enable XMACs TX and RX state machines */
2572                 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2573                 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2574                 break;
2575         case SK_YUKON:
2576                 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
2577                 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
2578                 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN);
2579                 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2580         }
2581
2582         ifp->if_flags |= IFF_RUNNING;
2583         ifp->if_flags &= ~IFF_OACTIVE;
2584
2585         splx(s);
2586
2587         return;
2588 }
2589
2590 static void sk_stop(sc_if)
2591         struct sk_if_softc      *sc_if;
2592 {
2593         int                     i;
2594         struct sk_softc         *sc;
2595         struct ifnet            *ifp;
2596
2597         sc = sc_if->sk_softc;
2598         ifp = &sc_if->arpcom.ac_if;
2599
2600         untimeout(sk_tick, sc_if, sc_if->sk_tick_ch);
2601
2602         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2603                 u_int32_t               val;
2604
2605                 /* Put PHY back into reset. */
2606                 val = sk_win_read_4(sc, SK_GPIO);
2607                 if (sc_if->sk_port == SK_PORT_A) {
2608                         val |= SK_GPIO_DIR0;
2609                         val &= ~SK_GPIO_DAT0;
2610                 } else {
2611                         val |= SK_GPIO_DIR2;
2612                         val &= ~SK_GPIO_DAT2;
2613                 }
2614                 sk_win_write_4(sc, SK_GPIO, val);
2615         }
2616
2617         /* Turn off various components of this interface. */
2618         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2619         switch (sc->sk_type) {
2620         case SK_GENESIS:
2621                 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2622                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2623                 break;
2624         case SK_YUKON:
2625                 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2626                 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2627                 break;
2628         }
2629         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2630         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2631         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2632         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2633         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2634         SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2635         SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2636         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2637         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2638
2639         /* Disable interrupts */
2640         if (sc_if->sk_port == SK_PORT_A)
2641                 sc->sk_intrmask &= ~SK_INTRS1;
2642         else
2643                 sc->sk_intrmask &= ~SK_INTRS2;
2644         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2645
2646         SK_XM_READ_2(sc_if, XM_ISR);
2647         SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2648
2649         /* Free RX and TX mbufs still in the queues. */
2650         for (i = 0; i < SK_RX_RING_CNT; i++) {
2651                 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) {
2652                         m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
2653                         sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
2654                 }
2655         }
2656
2657         for (i = 0; i < SK_TX_RING_CNT; i++) {
2658                 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) {
2659                         m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
2660                         sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
2661                 }
2662         }
2663
2664         ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
2665
2666         return;
2667 }