2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 * Modifications for FreeBSD-stable by Edwin Groothuis
5 * <edwin at mavetju.org
6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v
32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.9 2004/10/14 18:31:01 dillon Exp $
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/queue.h>
45 #include <net/if_arp.h>
46 #include <net/ethernet.h>
47 #include <net/if_dl.h>
48 #include <net/if_media.h>
52 #include <net/if_types.h>
53 #include <net/vlan/if_vlan_var.h>
55 #include <netinet/in_systm.h>
56 #include <netinet/in.h>
57 #include <netinet/ip.h>
59 #include <machine/bus_memio.h>
60 #include <machine/bus.h>
61 #include <machine/resource.h>
65 #include <bus/pci/pcireg.h>
66 #include <bus/pci/pcivar.h>
67 #include <bus/pci/pcidevs.h>
69 #include <dev/netif/mii_layer/mii.h>
70 #include <dev/netif/mii_layer/miivar.h>
72 #include "if_bfereg.h"
74 MODULE_DEPEND(bfe, pci, 1, 1, 1);
75 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
77 /* "controller miibus0" required. See GENERIC if you get errors here. */
78 #include "miibus_if.h"
80 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
82 static struct bfe_type bfe_devs[] = {
83 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401,
84 "Broadcom BCM4401 Fast Ethernet" },
88 static int bfe_probe(device_t);
89 static int bfe_attach(device_t);
90 static int bfe_detach(device_t);
91 static void bfe_release_resources(struct bfe_softc *);
92 static void bfe_intr(void *);
93 static void bfe_start(struct ifnet *);
94 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
95 static void bfe_init(void *);
96 static void bfe_stop(struct bfe_softc *);
97 static void bfe_watchdog(struct ifnet *);
98 static void bfe_shutdown(device_t);
99 static void bfe_tick(void *);
100 static void bfe_txeof(struct bfe_softc *);
101 static void bfe_rxeof(struct bfe_softc *);
102 static void bfe_set_rx_mode(struct bfe_softc *);
103 static int bfe_list_rx_init(struct bfe_softc *);
104 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*);
105 static void bfe_rx_ring_free(struct bfe_softc *);
107 static void bfe_pci_setup(struct bfe_softc *, uint32_t);
108 static int bfe_ifmedia_upd(struct ifnet *);
109 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
110 static int bfe_miibus_readreg(device_t, int, int);
111 static int bfe_miibus_writereg(device_t, int, int, int);
112 static void bfe_miibus_statchg(device_t);
113 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t,
115 static void bfe_get_config(struct bfe_softc *sc);
116 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *);
117 static void bfe_stats_update(struct bfe_softc *);
118 static void bfe_clear_stats (struct bfe_softc *);
119 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*);
120 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t);
121 static int bfe_resetphy(struct bfe_softc *);
122 static int bfe_setupphy(struct bfe_softc *);
123 static void bfe_chip_reset(struct bfe_softc *);
124 static void bfe_chip_halt(struct bfe_softc *);
125 static void bfe_core_reset(struct bfe_softc *);
126 static void bfe_core_disable(struct bfe_softc *);
127 static int bfe_dma_alloc(device_t);
128 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int);
129 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int);
130 static void bfe_cam_write(struct bfe_softc *, u_char *, int);
132 static device_method_t bfe_methods[] = {
133 /* Device interface */
134 DEVMETHOD(device_probe, bfe_probe),
135 DEVMETHOD(device_attach, bfe_attach),
136 DEVMETHOD(device_detach, bfe_detach),
137 DEVMETHOD(device_shutdown, bfe_shutdown),
140 DEVMETHOD(bus_print_child, bus_generic_print_child),
141 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
144 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
145 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
146 DEVMETHOD(miibus_statchg, bfe_miibus_statchg),
151 static driver_t bfe_driver = {
154 sizeof(struct bfe_softc)
157 static devclass_t bfe_devclass;
159 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
160 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
163 * Probe for a Broadcom 4401 chip.
166 bfe_probe(device_t dev)
169 struct bfe_softc *sc;
173 sc = device_get_softc(dev);
174 bzero(sc, sizeof(struct bfe_softc));
175 sc->bfe_unit = device_get_unit(dev);
178 while (t->bfe_name != NULL) {
179 if ((pci_get_vendor(dev) == t->bfe_vid) &&
180 (pci_get_device(dev) == t->bfe_did)) {
181 device_set_desc_copy(dev, t->bfe_name);
191 bfe_dma_alloc(device_t dev)
193 struct bfe_softc *sc;
196 sc = device_get_softc(dev);
199 error = bus_dma_tag_create(NULL, /* parent */
200 PAGE_SIZE, 0, /* alignment, boundary */
201 BUS_SPACE_MAXADDR, /* lowaddr */
202 BUS_SPACE_MAXADDR_32BIT, /* highaddr */
203 NULL, NULL, /* filter, filterarg */
204 MAXBSIZE, /* maxsize */
205 BUS_SPACE_UNRESTRICTED, /* num of segments */
206 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
207 BUS_DMA_ALLOCNOW, /* flags */
208 &sc->bfe_parent_tag);
211 device_printf(dev, "could not allocate dma tag\n");
216 /* tag for TX ring */
217 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_TX_LIST_SIZE,
218 BFE_TX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
219 NULL, NULL, BFE_TX_LIST_SIZE, 1,
220 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_tx_tag);
223 device_printf(dev, "could not allocate dma tag\n");
227 /* tag for RX ring */
228 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_RX_LIST_SIZE,
229 BFE_RX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
230 NULL, NULL, BFE_RX_LIST_SIZE, 1,
231 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_rx_tag);
234 device_printf(dev, "could not allocate dma tag\n");
239 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0,
240 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
241 1, BUS_SPACE_MAXSIZE_32BIT, 0,
245 device_printf(dev, "could not allocate dma tag\n");
249 /* pre allocate dmamaps for RX list */
250 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
251 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_rx_ring[i].bfe_map);
253 device_printf(dev, "cannot create DMA map for RX\n");
258 /* pre allocate dmamaps for TX list */
259 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
260 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_tx_ring[i].bfe_map);
262 device_printf(dev, "cannot create DMA map for TX\n");
267 /* Alloc dma for rx ring */
268 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
269 BUS_DMA_WAITOK, &sc->bfe_rx_map);
274 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
275 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
276 sc->bfe_rx_list, sizeof(struct bfe_desc),
277 bfe_dma_map, &sc->bfe_rx_dma, 0);
282 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
284 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
285 BUS_DMA_WAITOK, &sc->bfe_tx_map);
289 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
290 sc->bfe_tx_list, sizeof(struct bfe_desc),
291 bfe_dma_map, &sc->bfe_tx_dma, 0);
295 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
296 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
302 bfe_attach(device_t dev)
305 struct bfe_softc *sc;
306 int unit, error = 0, rid;
308 sc = device_get_softc(dev);
310 unit = device_get_unit(dev);
313 callout_init(&sc->bfe_stat_timer);
316 * Handle power management nonsense.
318 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
319 uint32_t membase, irq;
321 /* Save important PCI config data. */
322 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4);
323 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4);
325 /* Reset the power state. */
326 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n",
327 sc->bfe_unit, pci_get_powerstate(dev));
329 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
331 /* Restore PCI config data. */
332 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4);
333 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4);
337 * Map control/status registers.
339 pci_enable_busmaster(dev);
342 sc->bfe_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1,
344 if (sc->bfe_res == NULL) {
345 printf ("bfe%d: couldn't map memory\n", unit);
350 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
351 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
353 /* Allocate interrupt */
356 sc->bfe_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
357 RF_SHAREABLE | RF_ACTIVE);
358 if (sc->bfe_irq == NULL) {
359 printf("bfe%d: couldn't map interrupt\n", unit);
364 if (bfe_dma_alloc(dev)) {
365 printf("bfe%d: failed to allocate DMA resources\n", sc->bfe_unit);
366 bfe_release_resources(sc);
371 /* Set up ifnet structure */
372 ifp = &sc->arpcom.ac_if;
374 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
375 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
376 ifp->if_ioctl = bfe_ioctl;
377 ifp->if_start = bfe_start;
378 ifp->if_watchdog = bfe_watchdog;
379 ifp->if_init = bfe_init;
380 ifp->if_mtu = ETHERMTU;
381 ifp->if_baudrate = 10000000;
382 ifp->if_snd.ifq_maxlen = BFE_TX_QLEN;
386 /* Reset the chip and turn on the PHY */
389 if (mii_phy_probe(dev, &sc->bfe_miibus,
390 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
391 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit);
396 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
399 * Hook interrupt last to avoid having to lock softc
401 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET,
402 bfe_intr, sc, &sc->bfe_intrhand);
405 bfe_release_resources(sc);
406 printf("bfe%d: couldn't set up irq\n", unit);
411 bfe_release_resources(sc);
416 bfe_detach(device_t dev)
418 struct bfe_softc *sc;
422 sc = device_get_softc(dev);
426 ifp = &sc->arpcom.ac_if;
428 if (device_is_attached(dev)) {
435 bus_generic_detach(dev);
436 if (sc->bfe_miibus != NULL)
437 device_delete_child(dev, sc->bfe_miibus);
439 bfe_release_resources(sc);
446 * Stop all chip I/O so that the kernel's probe routines don't
447 * get confused by errant DMAs when rebooting.
450 bfe_shutdown(device_t dev)
452 struct bfe_softc *sc;
455 sc = device_get_softc(dev);
465 bfe_miibus_readreg(device_t dev, int phy, int reg)
467 struct bfe_softc *sc;
470 sc = device_get_softc(dev);
471 if (phy != sc->bfe_phyaddr)
473 bfe_readphy(sc, reg, &ret);
479 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
481 struct bfe_softc *sc;
483 sc = device_get_softc(dev);
484 if (phy != sc->bfe_phyaddr)
486 bfe_writephy(sc, reg, val);
492 bfe_miibus_statchg(device_t dev)
498 bfe_tx_ring_free(struct bfe_softc *sc)
502 for (i = 0; i < BFE_TX_LIST_CNT; i++)
503 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
504 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
505 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
506 bus_dmamap_unload(sc->bfe_tag,
507 sc->bfe_tx_ring[i].bfe_map);
508 bus_dmamap_destroy(sc->bfe_tag,
509 sc->bfe_tx_ring[i].bfe_map);
511 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
512 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
516 bfe_rx_ring_free(struct bfe_softc *sc)
520 for (i = 0; i < BFE_RX_LIST_CNT; i++)
521 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
522 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
523 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
524 bus_dmamap_unload(sc->bfe_tag,
525 sc->bfe_rx_ring[i].bfe_map);
526 bus_dmamap_destroy(sc->bfe_tag,
527 sc->bfe_rx_ring[i].bfe_map);
529 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
530 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
535 bfe_list_rx_init(struct bfe_softc *sc)
539 for (i = 0; i < BFE_RX_LIST_CNT; i++)
540 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS)
543 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
544 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
552 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m)
554 struct bfe_rxheader *rx_header;
559 if ((c < 0) || (c >= BFE_RX_LIST_CNT))
563 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
566 m->m_len = m->m_pkthdr.len = MCLBYTES;
569 m->m_data = m->m_ext.ext_buf;
571 rx_header = mtod(m, struct bfe_rxheader *);
573 rx_header->flags = 0;
575 /* Map the mbuf into DMA */
577 d = &sc->bfe_rx_list[c];
578 r = &sc->bfe_rx_ring[c];
579 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *),
580 MCLBYTES, bfe_dma_map_desc, d, 0);
581 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
583 ctrl = ETHER_MAX_LEN + 32;
585 if(c == BFE_RX_LIST_CNT - 1)
586 ctrl |= BFE_DESC_EOT;
590 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
595 bfe_get_config(struct bfe_softc *sc)
599 bfe_read_eeprom(sc, eeprom);
601 sc->arpcom.ac_enaddr[0] = eeprom[79];
602 sc->arpcom.ac_enaddr[1] = eeprom[78];
603 sc->arpcom.ac_enaddr[2] = eeprom[81];
604 sc->arpcom.ac_enaddr[3] = eeprom[80];
605 sc->arpcom.ac_enaddr[4] = eeprom[83];
606 sc->arpcom.ac_enaddr[5] = eeprom[82];
608 sc->bfe_phyaddr = eeprom[90] & 0x1f;
609 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
611 sc->bfe_core_unit = 0;
612 sc->bfe_dma_offset = BFE_PCI_DMA;
616 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores)
618 uint32_t bar_orig, pci_rev, val;
620 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
621 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
622 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
624 val = CSR_READ_4(sc, BFE_SBINTVEC);
626 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
628 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
629 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
630 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
632 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
636 bfe_clear_stats(struct bfe_softc *sc)
643 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
644 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
646 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
653 bfe_resetphy(struct bfe_softc *sc)
659 bfe_writephy(sc, 0, BMCR_RESET);
661 bfe_readphy(sc, 0, &val);
662 if (val & BMCR_RESET) {
663 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit);
672 bfe_chip_halt(struct bfe_softc *sc)
677 /* disable interrupts - not that it actually does..*/
678 CSR_WRITE_4(sc, BFE_IMASK, 0);
679 CSR_READ_4(sc, BFE_IMASK);
681 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
682 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
684 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
685 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
692 bfe_chip_reset(struct bfe_softc *sc)
699 /* Set the interrupt vector for the enet core */
700 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
703 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);
704 if (val == BFE_CLOCK) {
705 /* It is, so shut it down */
706 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
707 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
708 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
709 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
710 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
711 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
712 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0);
713 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
714 sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
721 * We want the phy registers to be accessible even when
722 * the driver is "downed" so initialize MDC preamble, frequency,
723 * and whether internal or external phy here.
726 /* 4402 has 62.5Mhz SB clock and internal phy */
727 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
729 /* Internal or external PHY? */
730 val = CSR_READ_4(sc, BFE_DEVCTRL);
731 if (!(val & BFE_IPP))
732 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
733 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
734 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
738 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB);
739 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
743 * We don't want lazy interrupts, so just send them at the end of a
746 BFE_OR(sc, BFE_RCV_LAZY, 0);
748 /* Set max lengths, accounting for VLAN tags */
749 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
750 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
752 /* Set watermark XXX - magic */
753 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
756 * Initialise DMA channels - not forgetting dma addresses need to be
757 * added to BFE_PCI_DMA
759 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
760 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
762 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
764 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
773 bfe_core_disable(struct bfe_softc *sc)
775 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
779 * Set reject, wait for it set, then wait for the core to stop being busy
780 * Then set reset and reject and enable the clocks
782 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
783 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
784 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
785 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
787 CSR_READ_4(sc, BFE_SBTMSLOW);
789 /* Leave reset and reject set */
790 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
795 bfe_core_reset(struct bfe_softc *sc)
799 /* Disable the core */
800 bfe_core_disable(sc);
802 /* and bring it back up */
803 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
804 CSR_READ_4(sc, BFE_SBTMSLOW);
807 /* Chip bug, clear SERR, IB and TO if they are set. */
808 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
809 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
810 val = CSR_READ_4(sc, BFE_SBIMSTATE);
811 if (val & (BFE_IBE | BFE_TO))
812 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
814 /* Clear reset and allow it to move through the core */
815 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
816 CSR_READ_4(sc, BFE_SBTMSLOW);
819 /* Leave the clock set */
820 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
821 CSR_READ_4(sc, BFE_SBTMSLOW);
826 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
830 val = ((uint32_t) data[2]) << 24;
831 val |= ((uint32_t) data[3]) << 16;
832 val |= ((uint32_t) data[4]) << 8;
833 val |= ((uint32_t) data[5]);
834 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
835 val = (BFE_CAM_HI_VALID |
836 (((uint32_t) data[0]) << 8) |
837 (((uint32_t) data[1])));
838 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
839 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
840 (index << BFE_CAM_INDEX_SHIFT)));
841 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
845 bfe_set_rx_mode(struct bfe_softc *sc)
847 struct ifnet *ifp = &sc->arpcom.ac_if;
851 val = CSR_READ_4(sc, BFE_RXCONF);
853 if (ifp->if_flags & IFF_PROMISC)
854 val |= BFE_RXCONF_PROMISC;
856 val &= ~BFE_RXCONF_PROMISC;
858 if (ifp->if_flags & IFF_BROADCAST)
859 val &= ~BFE_RXCONF_DBCAST;
861 val |= BFE_RXCONF_DBCAST;
864 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
865 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++);
867 CSR_WRITE_4(sc, BFE_RXCONF, val);
868 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
872 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
877 *ptr = segs->ds_addr;
881 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
886 /* The chip needs all addresses to be added to BFE_PCI_DMA */
887 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA;
891 bfe_release_resources(struct bfe_softc *sc)
898 if (sc->bfe_intrhand != NULL)
899 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
901 if (sc->bfe_irq != NULL)
902 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
904 if (sc->bfe_res != NULL)
905 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res);
907 if (sc->bfe_tx_tag != NULL) {
908 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
909 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, sc->bfe_tx_map);
910 bus_dma_tag_destroy(sc->bfe_tx_tag);
911 sc->bfe_tx_tag = NULL;
914 if (sc->bfe_rx_tag != NULL) {
915 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
916 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, sc->bfe_rx_map);
917 bus_dma_tag_destroy(sc->bfe_rx_tag);
918 sc->bfe_rx_tag = NULL;
921 if (sc->bfe_tag != NULL) {
922 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
923 bus_dmamap_destroy(sc->bfe_tag,
924 sc->bfe_tx_ring[i].bfe_map);
926 bus_dma_tag_destroy(sc->bfe_tag);
930 if (sc->bfe_parent_tag != NULL)
931 bus_dma_tag_destroy(sc->bfe_parent_tag);
935 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data)
938 uint16_t *ptr = (uint16_t *)data;
940 for (i = 0; i < 128; i += 2)
941 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
945 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit,
946 u_long timeout, const int clear)
950 for (i = 0; i < timeout; i++) {
951 uint32_t val = CSR_READ_4(sc, reg);
953 if (clear && !(val & bit))
955 if (!clear && (val & bit))
960 printf("bfe%d: BUG! Timeout waiting for bit %08x of register "
961 "%x to %s.\n", sc->bfe_unit, bit, reg,
962 (clear ? "clear" : "set"));
969 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val)
976 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
977 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
978 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
979 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
980 (reg << BFE_MDIO_RA_SHIFT) |
981 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
982 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
983 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
990 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val)
996 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
997 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
998 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
999 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1000 (reg << BFE_MDIO_RA_SHIFT) |
1001 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1002 (val & BFE_MDIO_DATA_DATA)));
1003 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1011 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1015 bfe_setupphy(struct bfe_softc *sc)
1022 /* Enable activity LED */
1023 bfe_readphy(sc, 26, &val);
1024 bfe_writephy(sc, 26, val & 0x7fff);
1025 bfe_readphy(sc, 26, &val);
1027 /* Enable traffic meter LED mode */
1028 bfe_readphy(sc, 27, &val);
1029 bfe_writephy(sc, 27, val | (1 << 6));
1036 bfe_stats_update(struct bfe_softc *sc)
1041 val = &sc->bfe_hwstats.tx_good_octets;
1042 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1043 *val++ += CSR_READ_4(sc, reg);
1044 val = &sc->bfe_hwstats.rx_good_octets;
1045 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1046 *val++ += CSR_READ_4(sc, reg);
1050 bfe_txeof(struct bfe_softc *sc)
1054 uint32_t i, chipidx;
1058 ifp = &sc->arpcom.ac_if;
1060 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1061 chipidx /= sizeof(struct bfe_desc);
1063 i = sc->bfe_tx_cons;
1064 /* Go through the mbufs and free those that have been transmitted */
1065 while (i != chipidx) {
1066 struct bfe_data *r = &sc->bfe_tx_ring[i];
1067 if (r->bfe_mbuf != NULL) {
1069 m_freem(r->bfe_mbuf);
1071 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1074 BFE_INC(i, BFE_TX_LIST_CNT);
1077 if (i != sc->bfe_tx_cons) {
1078 /* we freed up some mbufs */
1079 sc->bfe_tx_cons = i;
1080 ifp->if_flags &= ~IFF_OACTIVE;
1082 if (sc->bfe_tx_cnt == 0)
1090 /* Pass a received packet up the stack */
1092 bfe_rxeof(struct bfe_softc *sc)
1096 struct bfe_rxheader *rxheader;
1098 uint32_t cons, status, current, len, flags;
1102 cons = sc->bfe_rx_cons;
1103 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1104 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1106 ifp = &sc->arpcom.ac_if;
1108 while (current != cons) {
1109 r = &sc->bfe_rx_ring[cons];
1111 rxheader = mtod(m, struct bfe_rxheader*);
1112 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE);
1113 len = rxheader->len;
1116 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1117 flags = rxheader->flags;
1119 len -= ETHER_CRC_LEN;
1121 /* flag an error and try again */
1122 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1124 if (flags & BFE_RX_FLAG_SERR)
1125 ifp->if_collisions++;
1126 bfe_list_newbuf(sc, cons, m);
1127 BFE_INC(cons, BFE_RX_LIST_CNT);
1131 /* Go past the rx header */
1132 if (bfe_list_newbuf(sc, cons, NULL) != 0) {
1133 bfe_list_newbuf(sc, cons, m);
1134 BFE_INC(cons, BFE_RX_LIST_CNT);
1139 m_adj(m, BFE_RX_OFFSET);
1140 m->m_len = m->m_pkthdr.len = len;
1143 m->m_pkthdr.rcvif = ifp;
1145 (*ifp->if_input)(ifp, m);
1146 BFE_INC(cons, BFE_RX_LIST_CNT);
1148 sc->bfe_rx_cons = cons;
1155 struct bfe_softc *sc = xsc;
1157 uint32_t istat, imask, flag;
1160 ifp = &sc->arpcom.ac_if;
1164 istat = CSR_READ_4(sc, BFE_ISTAT);
1165 imask = CSR_READ_4(sc, BFE_IMASK);
1168 * Defer unsolicited interrupts - This is necessary because setting the
1169 * chips interrupt mask register to 0 doesn't actually stop the
1173 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1174 CSR_READ_4(sc, BFE_ISTAT);
1176 /* not expecting this interrupt, disregard it */
1182 if (istat & BFE_ISTAT_ERRORS) {
1183 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1184 if (flag & BFE_STAT_EMASK)
1187 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1188 if (flag & BFE_RX_FLAG_ERRORS)
1191 ifp->if_flags &= ~IFF_RUNNING;
1195 /* A packet was received */
1196 if (istat & BFE_ISTAT_RX)
1199 /* A packet was sent */
1200 if (istat & BFE_ISTAT_TX)
1203 /* We have packets pending, fire them out */
1204 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
1211 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1213 struct bfe_desc *d = NULL;
1214 struct bfe_data *r = NULL;
1216 uint32_t frag, cur, cnt = 0;
1218 if (BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2)
1222 * Start packing the mbufs in this chain into
1223 * the fragment pointers. Stop when we run out
1224 * of fragments or hit the end of the mbuf chain.
1227 cur = frag = *txidx;
1230 for (m = m_head; m != NULL; m = m->m_next) {
1231 if (m->m_len != 0) {
1232 if ((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2)
1235 d = &sc->bfe_tx_list[cur];
1236 r = &sc->bfe_tx_ring[cur];
1237 d->bfe_ctrl = BFE_DESC_LEN & m->m_len;
1238 /* always intterupt on completion */
1239 d->bfe_ctrl |= BFE_DESC_IOC;
1241 /* Set start of frame */
1242 d->bfe_ctrl |= BFE_DESC_SOF;
1243 if (cur == BFE_TX_LIST_CNT - 1)
1245 * Tell the chip to wrap to the start of the
1248 d->bfe_ctrl |= BFE_DESC_EOT;
1250 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void*),
1251 m->m_len, bfe_dma_map_desc, d, 0);
1252 bus_dmamap_sync(sc->bfe_tag, r->bfe_map,
1253 BUS_DMASYNC_PREREAD);
1256 BFE_INC(cur, BFE_TX_LIST_CNT);
1264 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF;
1265 sc->bfe_tx_ring[frag].bfe_mbuf = m_head;
1266 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
1269 sc->bfe_tx_cnt += cnt;
1274 * Set up to transmit a packet
1277 bfe_start(struct ifnet *ifp)
1279 struct bfe_softc *sc;
1280 struct mbuf *m_head = NULL;
1285 idx = sc->bfe_tx_prod;
1290 * not much point trying to send if the link is down or we have nothing to
1293 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) {
1298 if (ifp->if_flags & IFF_OACTIVE) {
1303 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) {
1304 IF_DEQUEUE(&ifp->if_snd, m_head);
1309 * Pack the data into the tx ring. If we dont have enough room, let
1310 * the chip drain the ring
1312 if (bfe_encap(sc, m_head, &idx)) {
1313 IF_PREPEND(&ifp->if_snd, m_head);
1314 ifp->if_flags |= IFF_OACTIVE;
1319 * If there's a BPF listener, bounce a copy of this frame
1322 BPF_MTAP(ifp, m_head);
1325 sc->bfe_tx_prod = idx;
1326 /* Transmit - twice due to apparent hardware bug */
1327 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1328 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1331 * Set a timeout in case the chip goes out to lunch.
1340 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1341 struct ifnet *ifp = &sc->arpcom.ac_if;
1346 if (ifp->if_flags & IFF_RUNNING) {
1354 if (bfe_list_rx_init(sc) == ENOBUFS) {
1355 printf("bfe%d: bfe_init failed. Not enough memory for list buffers\n",
1361 bfe_set_rx_mode(sc);
1363 /* Enable the chip and core */
1364 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1365 /* Enable interrupts */
1366 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1368 bfe_ifmedia_upd(ifp);
1369 ifp->if_flags |= IFF_RUNNING;
1370 ifp->if_flags &= ~IFF_OACTIVE;
1372 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1377 * Set media options.
1380 bfe_ifmedia_upd(struct ifnet *ifp)
1382 struct bfe_softc *sc;
1383 struct mii_data *mii;
1390 mii = device_get_softc(sc->bfe_miibus);
1392 if (mii->mii_instance) {
1393 struct mii_softc *miisc;
1394 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1395 miisc = LIST_NEXT(miisc, mii_list))
1396 mii_phy_reset(miisc);
1405 * Report current media status.
1408 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1410 struct bfe_softc *sc = ifp->if_softc;
1411 struct mii_data *mii;
1416 mii = device_get_softc(sc->bfe_miibus);
1418 ifmr->ifm_active = mii->mii_media_active;
1419 ifmr->ifm_status = mii->mii_media_status;
1425 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1427 struct bfe_softc *sc = ifp->if_softc;
1428 struct ifreq *ifr = (struct ifreq *) data;
1429 struct mii_data *mii;
1437 if (ifp->if_flags & IFF_UP)
1438 if (ifp->if_flags & IFF_RUNNING)
1439 bfe_set_rx_mode(sc);
1442 else if (ifp->if_flags & IFF_RUNNING)
1447 if (ifp->if_flags & IFF_RUNNING)
1448 bfe_set_rx_mode(sc);
1452 mii = device_get_softc(sc->bfe_miibus);
1453 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1459 error = ether_ioctl(ifp, command, data);
1472 bfe_watchdog(struct ifnet *ifp)
1474 struct bfe_softc *sc;
1481 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit);
1483 ifp->if_flags &= ~IFF_RUNNING;
1494 struct bfe_softc *sc = xsc;
1495 struct mii_data *mii;
1503 mii = device_get_softc(sc->bfe_miibus);
1505 bfe_stats_update(sc);
1506 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1514 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1515 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1525 * Stop the adapter and free any mbufs allocated to the
1529 bfe_stop(struct bfe_softc *sc)
1536 callout_stop(&sc->bfe_stat_timer);
1538 ifp = &sc->arpcom.ac_if;
1541 bfe_tx_ring_free(sc);
1542 bfe_rx_ring_free(sc);
1544 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);