1 /* i915_drv.c -- Intel i915 driver -*- linux-c -*-
2 * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
28 * Gareth Hughes <gareth@valinux.com>
30 * $FreeBSD: src/sys/dev/drm2/i915/i915_drv.c,v 1.1 2012/05/22 11:07:44 kib Exp $
34 #include <drm/i915_drm.h>
36 #include <drm/drm_pciids.h>
37 #include "intel_drv.h"
39 /* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
40 static drm_pci_id_list_t i915_pciidlist[] = {
44 static const struct intel_device_info intel_i830_info = {
45 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
46 .has_overlay = 1, .overlay_needs_physical = 1,
49 static const struct intel_device_info intel_845g_info = {
51 .has_overlay = 1, .overlay_needs_physical = 1,
54 static const struct intel_device_info intel_i85x_info = {
55 .gen = 2, .is_i85x = 1, .is_mobile = 1,
56 .cursor_needs_physical = 1,
57 .has_overlay = 1, .overlay_needs_physical = 1,
60 static const struct intel_device_info intel_i865g_info = {
62 .has_overlay = 1, .overlay_needs_physical = 1,
65 static const struct intel_device_info intel_i915g_info = {
66 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
67 .has_overlay = 1, .overlay_needs_physical = 1,
69 static const struct intel_device_info intel_i915gm_info = {
70 .gen = 3, .is_mobile = 1,
71 .cursor_needs_physical = 1,
72 .has_overlay = 1, .overlay_needs_physical = 1,
75 static const struct intel_device_info intel_i945g_info = {
76 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
77 .has_overlay = 1, .overlay_needs_physical = 1,
79 static const struct intel_device_info intel_i945gm_info = {
80 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
81 .has_hotplug = 1, .cursor_needs_physical = 1,
82 .has_overlay = 1, .overlay_needs_physical = 1,
86 static const struct intel_device_info intel_i965g_info = {
87 .gen = 4, .is_broadwater = 1,
92 static const struct intel_device_info intel_i965gm_info = {
93 .gen = 4, .is_crestline = 1,
94 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
99 static const struct intel_device_info intel_g33_info = {
100 .gen = 3, .is_g33 = 1,
101 .need_gfx_hws = 1, .has_hotplug = 1,
105 static const struct intel_device_info intel_g45_info = {
106 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
107 .has_pipe_cxsr = 1, .has_hotplug = 1,
111 static const struct intel_device_info intel_gm45_info = {
112 .gen = 4, .is_g4x = 1,
113 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
114 .has_pipe_cxsr = 1, .has_hotplug = 1,
119 static const struct intel_device_info intel_pineview_info = {
120 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
121 .need_gfx_hws = 1, .has_hotplug = 1,
125 static const struct intel_device_info intel_ironlake_d_info = {
127 .need_gfx_hws = 1, .has_hotplug = 1,
131 static const struct intel_device_info intel_ironlake_m_info = {
132 .gen = 5, .is_mobile = 1,
133 .need_gfx_hws = 1, .has_hotplug = 1,
134 .has_fbc = 0, /* disabled due to buggy hardware */
138 static const struct intel_device_info intel_sandybridge_d_info = {
140 .need_gfx_hws = 1, .has_hotplug = 1,
146 static const struct intel_device_info intel_sandybridge_m_info = {
147 .gen = 6, .is_mobile = 1,
148 .need_gfx_hws = 1, .has_hotplug = 1,
155 static const struct intel_device_info intel_ivybridge_d_info = {
156 .is_ivybridge = 1, .gen = 7,
157 .need_gfx_hws = 1, .has_hotplug = 1,
163 static const struct intel_device_info intel_ivybridge_m_info = {
164 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
165 .need_gfx_hws = 1, .has_hotplug = 1,
166 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
172 #define INTEL_VGA_DEVICE(id, info_) { \
177 static const struct intel_gfx_device_id {
179 const struct intel_device_info *info;
180 } pciidlist[] = { /* aka */
181 INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
182 INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
183 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
184 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
185 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
186 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
187 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
188 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
189 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
190 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
191 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
192 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
193 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
194 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
195 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
196 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
197 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
198 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
199 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
200 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
201 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
202 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
203 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
204 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
205 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
206 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
207 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),
208 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
209 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
210 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
211 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
212 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
213 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
214 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
215 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
216 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
217 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
218 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
219 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
220 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
221 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
222 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
223 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
224 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
228 static int i915_drm_freeze(struct drm_device *dev)
230 struct drm_i915_private *dev_priv;
233 dev_priv = dev->dev_private;
234 drm_kms_helper_poll_disable(dev);
237 pci_save_state(dev->pdev);
241 /* If KMS is active, we do the leavevt stuff here */
242 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
243 error = -i915_gem_idle(dev);
246 device_printf(dev->device,
247 "GEM idle failed, resume might fail\n");
250 drm_irq_uninstall(dev);
253 i915_save_state(dev);
255 intel_opregion_fini(dev);
257 /* Modeset on resume, not lid events */
258 dev_priv->modeset_on_lid = 0;
265 i915_suspend(device_t kdev)
267 struct drm_device *dev;
270 dev = device_get_softc(kdev);
271 if (dev == NULL || dev->dev_private == NULL) {
272 DRM_ERROR("DRM not initialized, aborting suspend.\n");
276 DRM_DEBUG_KMS("starting suspend\n");
277 error = i915_drm_freeze(dev);
281 error = bus_generic_suspend(kdev);
282 DRM_DEBUG_KMS("finished suspend %d\n", error);
286 static int i915_drm_thaw(struct drm_device *dev)
288 struct drm_i915_private *dev_priv = dev->dev_private;
292 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
293 i915_gem_restore_gtt_mappings(dev);
296 i915_restore_state(dev);
297 intel_opregion_setup(dev);
299 /* KMS EnterVT equivalent */
300 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
301 dev_priv->mm.suspended = 0;
303 error = i915_gem_init_hw(dev);
305 if (HAS_PCH_SPLIT(dev))
306 ironlake_init_pch_refclk(dev);
309 lockmgr(&dev->mode_config.lock, LK_EXCLUSIVE);
310 drm_mode_config_reset(dev);
311 lockmgr(&dev->mode_config.lock, LK_RELEASE);
312 drm_irq_install(dev);
314 lockmgr(&dev->mode_config.lock, LK_EXCLUSIVE);
315 /* Resume the modeset for every activated CRTC */
316 drm_helper_resume_force_mode(dev);
317 lockmgr(&dev->mode_config.lock, LK_RELEASE);
319 if (IS_IRONLAKE_M(dev))
320 ironlake_enable_rc6(dev);
324 intel_opregion_init(dev);
326 dev_priv->modeset_on_lid = 0;
334 i915_resume(device_t kdev)
336 struct drm_device *dev;
339 dev = device_get_softc(kdev);
340 DRM_DEBUG_KMS("starting resume\n");
342 if (pci_enable_device(dev->pdev))
345 pci_set_master(dev->pdev);
348 ret = -i915_drm_thaw(dev);
352 drm_kms_helper_poll_enable(dev);
353 ret = bus_generic_resume(kdev);
354 DRM_DEBUG_KMS("finished resume %d\n", ret);
359 i915_probe(device_t kdev)
362 return drm_probe(kdev, i915_pciidlist);
368 i915_attach(device_t kdev)
370 struct drm_device *dev;
372 dev = device_get_softc(kdev);
373 if (i915_modeset == 1)
374 i915_driver_info.driver_features |= DRIVER_MODESET;
375 dev->driver = &i915_driver_info;
376 return (drm_attach(kdev, i915_pciidlist));
379 const struct intel_device_info *
380 i915_get_device_id(int device)
382 const struct intel_gfx_device_id *did;
384 for (did = &pciidlist[0]; did->device != 0; did++) {
385 if (did->device != device)
392 static device_method_t i915_methods[] = {
393 /* Device interface */
394 DEVMETHOD(device_probe, i915_probe),
395 DEVMETHOD(device_attach, i915_attach),
396 DEVMETHOD(device_suspend, i915_suspend),
397 DEVMETHOD(device_resume, i915_resume),
398 DEVMETHOD(device_detach, drm_detach),
402 static driver_t i915_driver = {
405 sizeof(struct drm_device)
408 extern devclass_t drm_devclass;
409 DRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, 0, 0,
411 MODULE_DEPEND(i915kms, drm, 1, 1, 1);
412 MODULE_DEPEND(i915kms, agp, 1, 1, 1);
413 MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
414 MODULE_DEPEND(i915kms, iic, 1, 1, 1);
415 MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);
417 int intel_iommu_enabled = 0;
418 TUNABLE_INT("drm.i915.intel_iommu_enabled", &intel_iommu_enabled);
420 int i915_semaphores = -1;
421 TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
422 static int i915_try_reset = 1;
423 TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
424 unsigned int i915_lvds_downclock = 0;
425 TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
426 int i915_vbt_sdvo_panel_type = -1;
427 TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
428 unsigned int i915_powersave = 1;
429 TUNABLE_INT("drm.i915.powersave", &i915_powersave);
430 int i915_enable_fbc = 0;
431 TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
432 int i915_enable_rc6 = 0;
433 TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
434 int i915_panel_use_ssc = -1;
435 TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
436 int i915_panel_ignore_lid = 0;
437 TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
438 int i915_modeset = 1;
439 TUNABLE_INT("drm.i915.modeset", &i915_modeset);
440 int i915_enable_ppgtt = -1;
441 TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
442 int i915_enable_hangcheck = 1;
443 TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
445 #define PCI_VENDOR_INTEL 0x8086
446 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
447 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
448 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
449 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
452 intel_detect_pch(struct drm_device *dev)
454 struct drm_i915_private *dev_priv;
458 dev_priv = dev->dev_private;
459 pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
460 if (pch != NULL && pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
461 id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
462 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
463 dev_priv->pch_type = PCH_IBX;
464 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
465 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
466 dev_priv->pch_type = PCH_CPT;
467 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
468 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
469 /* PantherPoint is CPT compatible */
470 dev_priv->pch_type = PCH_CPT;
471 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
473 DRM_DEBUG_KMS("No PCH detected\n");
475 DRM_DEBUG_KMS("No Intel PCI-ISA bridge found\n");
479 __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
484 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
487 I915_WRITE_NOTRACE(FORCEWAKE, 1);
488 POSTING_READ(FORCEWAKE);
491 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
496 __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
501 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
504 I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
505 POSTING_READ(FORCEWAKE_MT);
508 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
513 gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
516 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
517 if (dev_priv->forcewake_count++ == 0)
518 dev_priv->display.force_wake_get(dev_priv);
519 lockmgr(&dev_priv->gt_lock, LK_RELEASE);
523 gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
527 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
528 if ((gtfifodbg & GT_FIFO_CPU_ERROR_MASK) != 0) {
529 kprintf("MMIO read or write has been dropped %x\n", gtfifodbg);
530 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
535 __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
538 I915_WRITE_NOTRACE(FORCEWAKE, 0);
539 /* The below doubles as a POSTING_READ */
540 gen6_gt_check_fifodbg(dev_priv);
544 __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
547 I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
548 /* The below doubles as a POSTING_READ */
549 gen6_gt_check_fifodbg(dev_priv);
553 gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
556 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
557 if (--dev_priv->forcewake_count == 0)
558 dev_priv->display.force_wake_put(dev_priv);
559 lockmgr(&dev_priv->gt_lock, LK_RELEASE);
563 __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
567 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
569 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
570 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
572 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
574 if (loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES) {
575 kprintf("%s loop\n", __func__);
578 dev_priv->gt_fifo_count = fifo;
580 dev_priv->gt_fifo_count--;
586 i8xx_do_reset(struct drm_device *dev, u8 flags)
588 struct drm_i915_private *dev_priv = dev->dev_private;
593 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
594 POSTING_READ(D_STATE);
596 if (IS_I830(dev) || IS_845G(dev)) {
597 I915_WRITE(DEBUG_RESET_I830,
598 DEBUG_RESET_DISPLAY |
601 POSTING_READ(DEBUG_RESET_I830);
604 I915_WRITE(DEBUG_RESET_I830, 0);
605 POSTING_READ(DEBUG_RESET_I830);
610 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
611 POSTING_READ(D_STATE);
617 i965_reset_complete(struct drm_device *dev)
621 gdrst = pci_read_config(dev->device, I965_GDRST, 1);
622 return (gdrst & 0x1);
626 i965_do_reset(struct drm_device *dev, u8 flags)
631 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
632 * well as the reset bit (GR/bit 0). Setting the GR bit
633 * triggers the reset; when done, the hardware will clear it.
635 gdrst = pci_read_config(dev->device, I965_GDRST, 1);
636 pci_write_config(dev->device, I965_GDRST, gdrst | flags | 0x1, 1);
638 return (_intel_wait_for(dev, i965_reset_complete(dev), 500, 1,
643 ironlake_do_reset(struct drm_device *dev, u8 flags)
645 struct drm_i915_private *dev_priv;
648 dev_priv = dev->dev_private;
649 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
650 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
651 return (_intel_wait_for(dev,
652 (I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1) != 0,
657 gen6_do_reset(struct drm_device *dev, u8 flags)
659 struct drm_i915_private *dev_priv;
662 dev_priv = dev->dev_private;
664 /* Hold gt_lock across reset to prevent any register access
665 * with forcewake not set correctly
667 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
671 /* GEN6_GDRST is not in the gt power well, no need to check
672 * for fifo space for the write or forcewake the chip for
675 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
677 /* Spin waiting for the device to ack the reset request */
678 ret = _intel_wait_for(dev,
679 (I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0,
682 /* If reset with a user forcewake, try to restore, otherwise turn it off */
683 if (dev_priv->forcewake_count)
684 dev_priv->display.force_wake_get(dev_priv);
686 dev_priv->display.force_wake_put(dev_priv);
688 /* Restore fifo count */
689 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
691 lockmgr(&dev_priv->gt_lock, LK_RELEASE);
696 i915_reset(struct drm_device *dev, u8 flags)
698 drm_i915_private_t *dev_priv = dev->dev_private;
700 * We really should only reset the display subsystem if we actually
703 bool need_display = true;
709 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT))
715 if (time_uptime - dev_priv->last_gpu_reset < 5) {
716 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
718 switch (INTEL_INFO(dev)->gen) {
721 ret = gen6_do_reset(dev, flags);
724 ret = ironlake_do_reset(dev, flags);
727 ret = i965_do_reset(dev, flags);
730 ret = i8xx_do_reset(dev, flags);
734 dev_priv->last_gpu_reset = time_uptime;
736 DRM_ERROR("Failed to reset chip.\n");
741 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
742 !dev_priv->mm.suspended) {
743 dev_priv->mm.suspended = 0;
745 i915_gem_init_swizzling(dev);
747 dev_priv->rings[RCS].init(&dev_priv->rings[RCS]);
749 dev_priv->rings[VCS].init(&dev_priv->rings[VCS]);
751 dev_priv->rings[BCS].init(&dev_priv->rings[BCS]);
753 i915_gem_init_ppgtt(dev);
755 drm_irq_uninstall(dev);
756 drm_mode_config_reset(dev);
758 drm_irq_install(dev);
764 lockmgr(&dev->mode_config.lock, LK_EXCLUSIVE);
765 drm_helper_resume_force_mode(dev);
766 lockmgr(&dev->mode_config.lock, LK_RELEASE);
772 #define __i915_read(x, y) \
773 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
775 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
776 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE); \
777 if (dev_priv->forcewake_count == 0) \
778 dev_priv->display.force_wake_get(dev_priv); \
779 val = DRM_READ##y(dev_priv->mmio_map, reg); \
780 if (dev_priv->forcewake_count == 0) \
781 dev_priv->display.force_wake_put(dev_priv); \
782 lockmgr(&dev_priv->gt_lock, LK_RELEASE); \
784 val = DRM_READ##y(dev_priv->mmio_map, reg); \
786 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
796 #define __i915_write(x, y) \
797 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
798 u32 __fifo_ret = 0; \
799 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
800 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
801 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
803 DRM_WRITE##y(dev_priv->mmio_map, reg, val); \
804 if (__predict_false(__fifo_ret)) { \
805 gen6_gt_check_fifodbg(dev_priv); \