sys/dev/drm/mach64/mach64_state.c

   1 /* mach64_state.c -- State support for mach64 (Rage Pro) driver -*- linux-c -*-
   2  * Created: Sun Dec 03 19:20:26 2000 by gareth@valinux.com
   3  */
   4 /*-
   5  * Copyright 2000 Gareth Hughes
   6  * Copyright 2002-2003 Leif Delgass
   7  * All Rights Reserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  24  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  25  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Gareth Hughes <gareth@valinux.com>
  29  *    Leif Delgass <ldelgass@retinalburn.net>
  30  *    José Fonseca <j_r_fonseca@yahoo.co.uk>
  31  */
  32
  33 #include <drm/drmP.h>
  34 #include "mach64_drm.h"
  35 #include "mach64_drv.h"
  36
  37 /* Interface history:
  38  *
  39  * 1.0 - Initial mach64 DRM
  40  *
  41  */
  42 struct drm_ioctl_desc mach64_ioctls[] = {
  43         DRM_IOCTL_DEF(DRM_MACH64_INIT, mach64_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  44         DRM_IOCTL_DEF(DRM_MACH64_CLEAR, mach64_dma_clear, DRM_AUTH),
  45         DRM_IOCTL_DEF(DRM_MACH64_SWAP, mach64_dma_swap, DRM_AUTH),
  46         DRM_IOCTL_DEF(DRM_MACH64_IDLE, mach64_dma_idle, DRM_AUTH),
  47         DRM_IOCTL_DEF(DRM_MACH64_RESET, mach64_engine_reset, DRM_AUTH),
  48         DRM_IOCTL_DEF(DRM_MACH64_VERTEX, mach64_dma_vertex, DRM_AUTH),
  49         DRM_IOCTL_DEF(DRM_MACH64_BLIT, mach64_dma_blit, DRM_AUTH),
  50         DRM_IOCTL_DEF(DRM_MACH64_FLUSH, mach64_dma_flush, DRM_AUTH),
  51         DRM_IOCTL_DEF(DRM_MACH64_GETPARAM, mach64_get_param, DRM_AUTH),
  52 };
  53
  54 int mach64_max_ioctl = DRM_ARRAY_SIZE(mach64_ioctls);
  55
  56 /* ================================================================
  57  * DMA hardware state programming functions
  58  */
  59
  60 static void mach64_print_dirty(const char *msg, unsigned int flags)
  61 {
  62         DRM_DEBUG("%s: (0x%x) %s%s%s%s%s%s%s%s%s%s%s%s\n",
  63                   msg,
  64                   flags,
  65                   (flags & MACH64_UPLOAD_DST_OFF_PITCH) ? "dst_off_pitch, " :
  66                   "",
  67                   (flags & MACH64_UPLOAD_Z_ALPHA_CNTL) ? "z_alpha_cntl, " : "",
  68                   (flags & MACH64_UPLOAD_SCALE_3D_CNTL) ? "scale_3d_cntl, " :
  69                   "", (flags & MACH64_UPLOAD_DP_FOG_CLR) ? "dp_fog_clr, " : "",
  70                   (flags & MACH64_UPLOAD_DP_WRITE_MASK) ? "dp_write_mask, " :
  71                   "",
  72                   (flags & MACH64_UPLOAD_DP_PIX_WIDTH) ? "dp_pix_width, " : "",
  73                   (flags & MACH64_UPLOAD_SETUP_CNTL) ? "setup_cntl, " : "",
  74                   (flags & MACH64_UPLOAD_MISC) ? "misc, " : "",
  75                   (flags & MACH64_UPLOAD_TEXTURE) ? "texture, " : "",
  76                   (flags & MACH64_UPLOAD_TEX0IMAGE) ? "tex0 image, " : "",
  77                   (flags & MACH64_UPLOAD_TEX1IMAGE) ? "tex1 image, " : "",
  78                   (flags & MACH64_UPLOAD_CLIPRECTS) ? "cliprects, " : "");
  79 }
  80
  81 /* Mach64 doesn't have hardware cliprects, just one hardware scissor,
  82  * so the GL scissor is intersected with each cliprect here
  83  */
  84 /* This function returns 0 on success, 1 for no intersection, and
  85  * negative for an error
  86  */
  87 static int mach64_emit_cliprect(struct drm_file *file_priv,
  88                                 drm_mach64_private_t * dev_priv,
  89                                 struct drm_clip_rect * box)
  90 {
  91         u32 sc_left_right, sc_top_bottom;
  92         struct drm_clip_rect scissor;
  93         drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
  94         drm_mach64_context_regs_t *regs = &sarea_priv->context_state;
  95         DMALOCALS;
  96
  97         DRM_DEBUG("box=%p\n", box);
  98
  99         /* Get GL scissor */
 100         /* FIXME: store scissor in SAREA as a cliprect instead of in
 101          * hardware format, or do intersection client-side
 102          */
 103         scissor.x1 = regs->sc_left_right & 0xffff;
 104         scissor.x2 = (regs->sc_left_right & 0xffff0000) >> 16;
 105         scissor.y1 = regs->sc_top_bottom & 0xffff;
 106         scissor.y2 = (regs->sc_top_bottom & 0xffff0000) >> 16;
 107
 108         /* Intersect GL scissor with cliprect */
 109         if (box->x1 > scissor.x1)
 110                 scissor.x1 = box->x1;
 111         if (box->y1 > scissor.y1)
 112                 scissor.y1 = box->y1;
 113         if (box->x2 < scissor.x2)
 114                 scissor.x2 = box->x2;
 115         if (box->y2 < scissor.y2)
 116                 scissor.y2 = box->y2;
 117         /* positive return means skip */
 118         if (scissor.x1 >= scissor.x2)
 119                 return 1;
 120         if (scissor.y1 >= scissor.y2)
 121                 return 1;
 122
 123         DMAGETPTR(file_priv, dev_priv, 2);      /* returns on failure to get buffer */
 124
 125         sc_left_right = ((scissor.x1 << 0) | (scissor.x2 << 16));
 126         sc_top_bottom = ((scissor.y1 << 0) | (scissor.y2 << 16));
 127
 128         DMAOUTREG(MACH64_SC_LEFT_RIGHT, sc_left_right);
 129         DMAOUTREG(MACH64_SC_TOP_BOTTOM, sc_top_bottom);
 130
 131         DMAADVANCE(dev_priv, 1);
 132
 133         return 0;
 134 }
 135
 136 static __inline__ int mach64_emit_state(struct drm_file *file_priv,
 137                                         drm_mach64_private_t * dev_priv)
 138 {
 139         drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
 140         drm_mach64_context_regs_t *regs = &sarea_priv->context_state;
 141         unsigned int dirty = sarea_priv->dirty;
 142         u32 offset = ((regs->tex_size_pitch & 0xf0) >> 2);
 143         DMALOCALS;
 144
 145         if (MACH64_VERBOSE) {
 146                 mach64_print_dirty(__func__, dirty);
 147         } else {
 148                 DRM_DEBUG("dirty=0x%08x\n", dirty);
 149         }
 150
 151         DMAGETPTR(file_priv, dev_priv, 17);     /* returns on failure to get buffer */
 152
 153         if (dirty & MACH64_UPLOAD_MISC) {
 154                 DMAOUTREG(MACH64_DP_MIX, regs->dp_mix);
 155                 DMAOUTREG(MACH64_DP_SRC, regs->dp_src);
 156                 DMAOUTREG(MACH64_CLR_CMP_CNTL, regs->clr_cmp_cntl);
 157                 DMAOUTREG(MACH64_GUI_TRAJ_CNTL, regs->gui_traj_cntl);
 158                 sarea_priv->dirty &= ~MACH64_UPLOAD_MISC;
 159         }
 160
 161         if (dirty & MACH64_UPLOAD_DST_OFF_PITCH) {
 162                 DMAOUTREG(MACH64_DST_OFF_PITCH, regs->dst_off_pitch);
 163                 sarea_priv->dirty &= ~MACH64_UPLOAD_DST_OFF_PITCH;
 164         }
 165         if (dirty & MACH64_UPLOAD_Z_OFF_PITCH) {
 166                 DMAOUTREG(MACH64_Z_OFF_PITCH, regs->z_off_pitch);
 167                 sarea_priv->dirty &= ~MACH64_UPLOAD_Z_OFF_PITCH;
 168         }
 169         if (dirty & MACH64_UPLOAD_Z_ALPHA_CNTL) {
 170                 DMAOUTREG(MACH64_Z_CNTL, regs->z_cntl);
 171                 DMAOUTREG(MACH64_ALPHA_TST_CNTL, regs->alpha_tst_cntl);
 172                 sarea_priv->dirty &= ~MACH64_UPLOAD_Z_ALPHA_CNTL;
 173         }
 174         if (dirty & MACH64_UPLOAD_SCALE_3D_CNTL) {
 175                 DMAOUTREG(MACH64_SCALE_3D_CNTL, regs->scale_3d_cntl);
 176                 sarea_priv->dirty &= ~MACH64_UPLOAD_SCALE_3D_CNTL;
 177         }
 178         if (dirty & MACH64_UPLOAD_DP_FOG_CLR) {
 179                 DMAOUTREG(MACH64_DP_FOG_CLR, regs->dp_fog_clr);
 180                 sarea_priv->dirty &= ~MACH64_UPLOAD_DP_FOG_CLR;
 181         }
 182         if (dirty & MACH64_UPLOAD_DP_WRITE_MASK) {
 183                 DMAOUTREG(MACH64_DP_WRITE_MASK, regs->dp_write_mask);
 184                 sarea_priv->dirty &= ~MACH64_UPLOAD_DP_WRITE_MASK;
 185         }
 186         if (dirty & MACH64_UPLOAD_DP_PIX_WIDTH) {
 187                 DMAOUTREG(MACH64_DP_PIX_WIDTH, regs->dp_pix_width);
 188                 sarea_priv->dirty &= ~MACH64_UPLOAD_DP_PIX_WIDTH;
 189         }
 190         if (dirty & MACH64_UPLOAD_SETUP_CNTL) {
 191                 DMAOUTREG(MACH64_SETUP_CNTL, regs->setup_cntl);
 192                 sarea_priv->dirty &= ~MACH64_UPLOAD_SETUP_CNTL;
 193         }
 194
 195         if (dirty & MACH64_UPLOAD_TEXTURE) {
 196                 DMAOUTREG(MACH64_TEX_SIZE_PITCH, regs->tex_size_pitch);
 197                 DMAOUTREG(MACH64_TEX_CNTL, regs->tex_cntl);
 198                 DMAOUTREG(MACH64_SECONDARY_TEX_OFF, regs->secondary_tex_off);
 199                 DMAOUTREG(MACH64_TEX_0_OFF + offset, regs->tex_offset);
 200                 sarea_priv->dirty &= ~MACH64_UPLOAD_TEXTURE;
 201         }
 202
 203         DMAADVANCE(dev_priv, 1);
 204
 205         sarea_priv->dirty &= MACH64_UPLOAD_CLIPRECTS;
 206
 207         return 0;
 208
 209 }
 210
 211 /* ================================================================
 212  * DMA command dispatch functions
 213  */
 214
 215 static int mach64_dma_dispatch_clear(struct drm_device * dev,
 216                                      struct drm_file *file_priv,
 217                                      unsigned int flags,
 218                                      int cx, int cy, int cw, int ch,
 219                                      unsigned int clear_color,
 220                                      unsigned int clear_depth)
 221 {
 222         drm_mach64_private_t *dev_priv = dev->dev_private;
 223         drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
 224         drm_mach64_context_regs_t *ctx = &sarea_priv->context_state;
 225         int nbox = sarea_priv->nbox;
 226         struct drm_clip_rect *pbox = sarea_priv->boxes;
 227         u32 fb_bpp, depth_bpp;
 228         int i;
 229         DMALOCALS;
 230
 231         DRM_DEBUG("\n");
 232
 233         switch (dev_priv->fb_bpp) {
 234         case 16:
 235                 fb_bpp = MACH64_DATATYPE_RGB565;
 236                 break;
 237         case 32:
 238                 fb_bpp = MACH64_DATATYPE_ARGB8888;
 239                 break;
 240         default:
 241                 return -EINVAL;
 242         }
 243         switch (dev_priv->depth_bpp) {
 244         case 16:
 245                 depth_bpp = MACH64_DATATYPE_RGB565;
 246                 break;
 247         case 24:
 248         case 32:
 249                 depth_bpp = MACH64_DATATYPE_ARGB8888;
 250                 break;
 251         default:
 252                 return -EINVAL;
 253         }
 254
 255         if (!nbox)
 256                 return 0;
 257
 258         DMAGETPTR(file_priv, dev_priv, nbox * 31);      /* returns on failure to get buffer */
 259
 260         for (i = 0; i < nbox; i++) {
 261                 int x = pbox[i].x1;
 262                 int y = pbox[i].y1;
 263                 int w = pbox[i].x2 - x;
 264                 int h = pbox[i].y2 - y;
 265
 266                 DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
 267                           pbox[i].x1, pbox[i].y1,
 268                           pbox[i].x2, pbox[i].y2, flags);
 269
 270                 if (flags & (MACH64_FRONT | MACH64_BACK)) {
 271                         /* Setup for color buffer clears
 272                          */
 273
 274                         DMAOUTREG(MACH64_Z_CNTL, 0);
 275                         DMAOUTREG(MACH64_SCALE_3D_CNTL, 0);
 276
 277                         DMAOUTREG(MACH64_SC_LEFT_RIGHT, ctx->sc_left_right);
 278                         DMAOUTREG(MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom);
 279
 280                         DMAOUTREG(MACH64_CLR_CMP_CNTL, 0);
 281                         DMAOUTREG(MACH64_GUI_TRAJ_CNTL,
 282                                   (MACH64_DST_X_LEFT_TO_RIGHT |
 283                                    MACH64_DST_Y_TOP_TO_BOTTOM));
 284
 285                         DMAOUTREG(MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) |
 286                                                         (fb_bpp << 4) |
 287                                                         (fb_bpp << 8) |
 288                                                         (fb_bpp << 16) |
 289                                                         (fb_bpp << 28)));
 290
 291                         DMAOUTREG(MACH64_DP_FRGD_CLR, clear_color);
 292                         DMAOUTREG(MACH64_DP_WRITE_MASK, ctx->dp_write_mask);
 293                         DMAOUTREG(MACH64_DP_MIX, (MACH64_BKGD_MIX_D |
 294                                                   MACH64_FRGD_MIX_S));
 295                         DMAOUTREG(MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR |
 296                                                   MACH64_FRGD_SRC_FRGD_CLR |
 297                                                   MACH64_MONO_SRC_ONE));
 298
 299                 }
 300
 301                 if (flags & MACH64_FRONT) {
 302
 303                         DMAOUTREG(MACH64_DST_OFF_PITCH,
 304                                   dev_priv->front_offset_pitch);
 305                         DMAOUTREG(MACH64_DST_X_Y, (y << 16) | x);
 306                         DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w);
 307
 308                 }
 309
 310                 if (flags & MACH64_BACK) {
 311
 312                         DMAOUTREG(MACH64_DST_OFF_PITCH,
 313                                   dev_priv->back_offset_pitch);
 314                         DMAOUTREG(MACH64_DST_X_Y, (y << 16) | x);
 315                         DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w);
 316
 317                 }
 318
 319                 if (flags & MACH64_DEPTH) {
 320                         /* Setup for depth buffer clear
 321                          */
 322                         DMAOUTREG(MACH64_Z_CNTL, 0);
 323                         DMAOUTREG(MACH64_SCALE_3D_CNTL, 0);
 324
 325                         DMAOUTREG(MACH64_SC_LEFT_RIGHT, ctx->sc_left_right);
 326                         DMAOUTREG(MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom);
 327
 328                         DMAOUTREG(MACH64_CLR_CMP_CNTL, 0);
 329                         DMAOUTREG(MACH64_GUI_TRAJ_CNTL,
 330                                   (MACH64_DST_X_LEFT_TO_RIGHT |
 331                                    MACH64_DST_Y_TOP_TO_BOTTOM));
 332
 333                         DMAOUTREG(MACH64_DP_PIX_WIDTH, ((depth_bpp << 0) |
 334                                                         (depth_bpp << 4) |
 335                                                         (depth_bpp << 8) |
 336                                                         (depth_bpp << 16) |
 337                                                         (depth_bpp << 28)));
 338
 339                         DMAOUTREG(MACH64_DP_FRGD_CLR, clear_depth);
 340                         DMAOUTREG(MACH64_DP_WRITE_MASK, 0xffffffff);
 341                         DMAOUTREG(MACH64_DP_MIX, (MACH64_BKGD_MIX_D |
 342                                                   MACH64_FRGD_MIX_S));
 343                         DMAOUTREG(MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR |
 344                                                   MACH64_FRGD_SRC_FRGD_CLR |
 345                                                   MACH64_MONO_SRC_ONE));
 346
 347                         DMAOUTREG(MACH64_DST_OFF_PITCH,
 348                                   dev_priv->depth_offset_pitch);
 349                         DMAOUTREG(MACH64_DST_X_Y, (y << 16) | x);
 350                         DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w);
 351                 }
 352         }
 353
 354         DMAADVANCE(dev_priv, 1);
 355
 356         return 0;
 357 }
 358
 359 static int mach64_dma_dispatch_swap(struct drm_device * dev,
 360                                     struct drm_file *file_priv)
 361 {
 362         drm_mach64_private_t *dev_priv = dev->dev_private;
 363         drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
 364         int nbox = sarea_priv->nbox;
 365         struct drm_clip_rect *pbox = sarea_priv->boxes;
 366         u32 fb_bpp;
 367         int i;
 368         DMALOCALS;
 369
 370         DRM_DEBUG("\n");
 371
 372         switch (dev_priv->fb_bpp) {
 373         case 16:
 374                 fb_bpp = MACH64_DATATYPE_RGB565;
 375                 break;
 376         case 32:
 377         default:
 378                 fb_bpp = MACH64_DATATYPE_ARGB8888;
 379                 break;
 380         }
 381
 382         if (!nbox)
 383                 return 0;
 384
 385         DMAGETPTR(file_priv, dev_priv, 13 + nbox * 4);  /* returns on failure to get buffer */
 386
 387         DMAOUTREG(MACH64_Z_CNTL, 0);
 388         DMAOUTREG(MACH64_SCALE_3D_CNTL, 0);
 389
 390         DMAOUTREG(MACH64_SC_LEFT_RIGHT, 0 | (8191 << 16));      /* no scissor */
 391         DMAOUTREG(MACH64_SC_TOP_BOTTOM, 0 | (16383 << 16));
 392
 393         DMAOUTREG(MACH64_CLR_CMP_CNTL, 0);
 394         DMAOUTREG(MACH64_GUI_TRAJ_CNTL, (MACH64_DST_X_LEFT_TO_RIGHT |
 395                                          MACH64_DST_Y_TOP_TO_BOTTOM));
 396
 397         DMAOUTREG(MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) |
 398                                         (fb_bpp << 4) |
 399                                         (fb_bpp << 8) |
 400                                         (fb_bpp << 16) | (fb_bpp << 28)));
 401
 402         DMAOUTREG(MACH64_DP_WRITE_MASK, 0xffffffff);
 403         DMAOUTREG(MACH64_DP_MIX, (MACH64_BKGD_MIX_D | MACH64_FRGD_MIX_S));
 404         DMAOUTREG(MACH64_DP_SRC, (MACH64_BKGD_SRC_BKGD_CLR |
 405                                   MACH64_FRGD_SRC_BLIT | MACH64_MONO_SRC_ONE));
 406
 407         DMAOUTREG(MACH64_SRC_OFF_PITCH, dev_priv->back_offset_pitch);
 408         DMAOUTREG(MACH64_DST_OFF_PITCH, dev_priv->front_offset_pitch);
 409
 410         for (i = 0; i < nbox; i++) {
 411                 int x = pbox[i].x1;
 412                 int y = pbox[i].y1;
 413                 int w = pbox[i].x2 - x;
 414                 int h = pbox[i].y2 - y;
 415
 416                 DRM_DEBUG("dispatch swap %d,%d-%d,%d\n",
 417                           pbox[i].x1, pbox[i].y1, pbox[i].x2, pbox[i].y2);
 418
 419                 DMAOUTREG(MACH64_SRC_WIDTH1, w);
 420                 DMAOUTREG(MACH64_SRC_Y_X, (x << 16) | y);
 421                 DMAOUTREG(MACH64_DST_Y_X, (x << 16) | y);
 422                 DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w);
 423
 424         }
 425
 426         DMAADVANCE(dev_priv, 1);
 427
 428         if (dev_priv->driver_mode == MACH64_MODE_DMA_ASYNC) {
 429                 for (i = 0; i < MACH64_MAX_QUEUED_FRAMES - 1; i++) {
 430                         dev_priv->frame_ofs[i] = dev_priv->frame_ofs[i + 1];
 431                 }
 432                 dev_priv->frame_ofs[i] = GETRINGOFFSET();
 433
 434                 dev_priv->sarea_priv->frames_queued++;
 435         }
 436
 437         return 0;
 438 }
 439
 440 static int mach64_do_get_frames_queued(drm_mach64_private_t * dev_priv)
 441 {
 442         drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
 443         drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
 444         int i, start;
 445         u32 head, tail, ofs;
 446
 447         DRM_DEBUG("\n");
 448
 449         if (sarea_priv->frames_queued == 0)
 450                 return 0;
 451
 452         tail = ring->tail;
 453         mach64_ring_tick(dev_priv, ring);
 454         head = ring->head;
 455
 456         start = (MACH64_MAX_QUEUED_FRAMES -
 457                  DRM_MIN(MACH64_MAX_QUEUED_FRAMES, sarea_priv->frames_queued));
 458
 459         if (head == tail) {
 460                 sarea_priv->frames_queued = 0;
 461                 for (i = start; i < MACH64_MAX_QUEUED_FRAMES; i++) {
 462                         dev_priv->frame_ofs[i] = ~0;
 463                 }
 464                 return 0;
 465         }
 466
 467         for (i = start; i < MACH64_MAX_QUEUED_FRAMES; i++) {
 468                 ofs = dev_priv->frame_ofs[i];
 469                 DRM_DEBUG("frame_ofs[%d] ofs: %d\n", i, ofs);
 470                 if (ofs == ~0 ||
 471                     (head < tail && (ofs < head || ofs >= tail)) ||
 472                     (head > tail && (ofs < head && ofs >= tail))) {
 473                         sarea_priv->frames_queued =
 474                             (MACH64_MAX_QUEUED_FRAMES - 1) - i;
 475                         dev_priv->frame_ofs[i] = ~0;
 476                 }
 477         }
 478
 479         return sarea_priv->frames_queued;
 480 }
 481
 482 /* Copy and verify a client submited buffer.
 483  * FIXME: Make an assembly optimized version
 484  */
 485 static __inline__ int copy_from_user_vertex(u32 *to,
 486                                             const u32 __user *ufrom,
 487                                             unsigned long bytes)
 488 {
 489         unsigned long n = bytes;        /* dwords remaining in buffer */
 490         u32 *from, *orig_from;
 491
 492         from = drm_alloc(bytes, DRM_MEM_DRIVER);
 493         if (from == NULL)
 494                 return -ENOMEM;
 495
 496         if (DRM_COPY_FROM_USER(from, ufrom, bytes)) {
 497                 drm_free(from, DRM_MEM_DRIVER);
 498                 return -EFAULT;
 499         }
 500         orig_from = from; /* we'll be modifying the "from" ptr, so save it */
 501
 502         n >>= 2;
 503
 504         while (n > 1) {
 505                 u32 data, reg, count;
 506
 507                 data = *from++;
 508
 509                 n--;
 510
 511                 reg = le32_to_cpu(data);
 512                 count = (reg >> 16) + 1;
 513                 if (count <= n) {
 514                         n -= count;
 515                         reg &= 0xffff;
 516
 517                         /* This is an exact match of Mach64's Setup Engine registers,
 518                          * excluding SETUP_CNTL (1_C1).
 519                          */
 520                         if ((reg >= 0x0190 && reg < 0x01c1) ||
 521                             (reg >= 0x01ca && reg <= 0x01cf)) {
 522                                 *to++ = data;
 523                                 memcpy(to, from, count << 2);
 524                                 from += count;
 525                                 to += count;
 526                         } else {
 527                                 DRM_ERROR("Got bad command: 0x%04x\n", reg);
 528                                 drm_free(orig_from, DRM_MEM_DRIVER);
 529                                 return -EACCES;
 530                         }
 531                 } else {
 532                         DRM_ERROR
 533                             ("Got bad command count(=%u) dwords remaining=%lu\n",
 534                              count, n);
 535                         drm_free(orig_from, DRM_MEM_DRIVER);
 536                         return -EINVAL;
 537                 }
 538         }
 539
 540         drm_free(orig_from, DRM_MEM_DRIVER);
 541         if (n == 0)
 542                 return 0;
 543         else {
 544                 DRM_ERROR("Bad buf->used(=%lu)\n", bytes);
 545                 return -EINVAL;
 546         }
 547 }
 548
 549 static int mach64_dma_dispatch_vertex(struct drm_device * dev,
 550                                       struct drm_file *file_priv,
 551                                       drm_mach64_vertex_t * vertex)
 552 {
 553         drm_mach64_private_t *dev_priv = dev->dev_private;
 554         drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
 555         struct drm_buf *copy_buf;
 556         void *buf = vertex->buf;
 557         unsigned long used = vertex->used;
 558         int ret = 0;
 559         int i = 0;
 560         int done = 0;
 561         int verify_ret = 0;
 562         DMALOCALS;
 563
 564         DRM_DEBUG("buf=%p used=%lu nbox=%d\n",
 565                   buf, used, sarea_priv->nbox);
 566
 567         if (!used)
 568                 goto _vertex_done;
 569
 570         copy_buf = mach64_freelist_get(dev_priv);
 571         if (copy_buf == NULL) {
 572                 DRM_ERROR("couldn't get buffer\n");
 573                 return -EAGAIN;
 574         }
 575
 576         /* Mach64's vertex data is actually register writes. To avoid security
 577          * compromises these register writes have to be verified and copied from
 578          * user space into a private DMA buffer.
 579          */
 580         verify_ret = copy_from_user_vertex(GETBUFPTR(copy_buf), buf, used);
 581
 582         if (verify_ret != 0) {
 583                 mach64_freelist_put(dev_priv, copy_buf);
 584                 goto _vertex_done;
 585         }
 586
 587         copy_buf->used = used;
 588
 589         DMASETPTR(copy_buf);
 590
 591         if (sarea_priv->dirty & ~MACH64_UPLOAD_CLIPRECTS) {
 592                 ret = mach64_emit_state(file_priv, dev_priv);
 593                 if (ret < 0)
 594                         return ret;
 595         }
 596
 597         do {
 598                 /* Emit the next cliprect */
 599                 if (i < sarea_priv->nbox) {
 600                         ret = mach64_emit_cliprect(file_priv, dev_priv,
 601                                                    &sarea_priv->boxes[i]);
 602                         if (ret < 0) {
 603                                 /* failed to get buffer */
 604                                 return ret;
 605                         } else if (ret != 0) {
 606                                 /* null intersection with scissor */
 607                                 continue;
 608                         }
 609                 }
 610                 if ((i >= sarea_priv->nbox - 1))
 611                         done = 1;
 612
 613                 /* Add the buffer to the DMA queue */
 614                 DMAADVANCE(dev_priv, done);
 615
 616         } while (++i < sarea_priv->nbox);
 617
 618         if (!done) {
 619                 if (copy_buf->pending) {
 620                         DMADISCARDBUF();
 621                 } else {
 622                         /* This buffer wasn't used (no cliprects), so place it
 623                          * back on the free list
 624                          */
 625                         mach64_freelist_put(dev_priv, copy_buf);
 626                 }
 627         }
 628
 629 _vertex_done:
 630         sarea_priv->dirty &= ~MACH64_UPLOAD_CLIPRECTS;
 631         sarea_priv->nbox = 0;
 632
 633         return verify_ret;
 634 }
 635
 636 static __inline__ int copy_from_user_blit(u32 *to,
 637                                           const u32 __user *ufrom,
 638                                           unsigned long bytes)
 639 {
 640         to = (u32 *)((char *)to + MACH64_HOSTDATA_BLIT_OFFSET);
 641
 642         if (DRM_COPY_FROM_USER(to, ufrom, bytes)) {
 643                 return -EFAULT;
 644         }
 645
 646         return 0;
 647 }
 648
 649 static int mach64_dma_dispatch_blit(struct drm_device * dev,
 650                                     struct drm_file *file_priv,
 651                                     drm_mach64_blit_t * blit)
 652 {
 653         drm_mach64_private_t *dev_priv = dev->dev_private;
 654         int dword_shift, dwords;
 655         unsigned long used;
 656         struct drm_buf *copy_buf;
 657         int verify_ret = 0;
 658         DMALOCALS;
 659
 660         /* The compiler won't optimize away a division by a variable,
 661          * even if the only legal values are powers of two.  Thus, we'll
 662          * use a shift instead.
 663          */
 664         switch (blit->format) {
 665         case MACH64_DATATYPE_ARGB8888:
 666                 dword_shift = 0;
 667                 break;
 668         case MACH64_DATATYPE_ARGB1555:
 669         case MACH64_DATATYPE_RGB565:
 670         case MACH64_DATATYPE_VYUY422:
 671         case MACH64_DATATYPE_YVYU422:
 672         case MACH64_DATATYPE_ARGB4444:
 673                 dword_shift = 1;
 674                 break;
 675         case MACH64_DATATYPE_CI8:
 676         case MACH64_DATATYPE_RGB8:
 677                 dword_shift = 2;
 678                 break;
 679         default:
 680                 DRM_ERROR("invalid blit format %d\n", blit->format);
 681                 return -EINVAL;
 682         }
 683
 684         /* Set buf->used to the bytes of blit data based on the blit dimensions
 685          * and verify the size.  When the setup is emitted to the buffer with
 686          * the DMA* macros below, buf->used is incremented to include the bytes
 687          * used for setup as well as the blit data.
 688          */
 689         dwords = (blit->width * blit->height) >> dword_shift;
 690         used = dwords << 2;
 691         if (used <= 0 ||
 692             used > MACH64_BUFFER_SIZE - MACH64_HOSTDATA_BLIT_OFFSET) {
 693                 DRM_ERROR("Invalid blit size: %lu bytes\n", used);
 694                 return -EINVAL;
 695         }
 696
 697         copy_buf = mach64_freelist_get(dev_priv);
 698         if (copy_buf == NULL) {
 699                 DRM_ERROR("couldn't get buffer\n");
 700                 return -EAGAIN;
 701         }
 702
 703         /* Copy the blit data from userspace.
 704          *
 705          * XXX: This is overkill. The most efficient solution would be having
 706          * two sets of buffers (one set private for vertex data, the other set
 707          * client-writable for blits). However that would bring more complexity
 708          * and would break backward compatability. The solution currently
 709          * implemented is keeping all buffers private, allowing to secure the
 710          * driver, without increasing complexity at the expense of some speed
 711          * transfering data.
 712          */
 713         verify_ret = copy_from_user_blit(GETBUFPTR(copy_buf), blit->buf, used);
 714
 715         if (verify_ret != 0) {
 716                 mach64_freelist_put(dev_priv, copy_buf);
 717                 goto _blit_done;
 718         }
 719
 720         copy_buf->used = used;
 721
 722         /* FIXME: Use a last buffer flag and reduce the state emitted for subsequent,
 723          * continuation buffers?
 724          */
 725
 726         /* Blit via BM_HOSTDATA (gui-master) - like HOST_DATA[0-15], but doesn't require
 727          * a register command every 16 dwords.  State setup is added at the start of the
 728          * buffer -- the client leaves space for this based on MACH64_HOSTDATA_BLIT_OFFSET
 729          */
 730         DMASETPTR(copy_buf);
 731
 732         DMAOUTREG(MACH64_Z_CNTL, 0);
 733         DMAOUTREG(MACH64_SCALE_3D_CNTL, 0);
 734
 735         DMAOUTREG(MACH64_SC_LEFT_RIGHT, 0 | (8191 << 16));      /* no scissor */
 736         DMAOUTREG(MACH64_SC_TOP_BOTTOM, 0 | (16383 << 16));
 737
 738         DMAOUTREG(MACH64_CLR_CMP_CNTL, 0);      /* disable */
 739         DMAOUTREG(MACH64_GUI_TRAJ_CNTL,
 740                   MACH64_DST_X_LEFT_TO_RIGHT | MACH64_DST_Y_TOP_TO_BOTTOM);
 741
 742         DMAOUTREG(MACH64_DP_PIX_WIDTH, (blit->format << 0)      /* dst pix width */
 743                   |(blit->format << 4)  /* composite pix width */
 744                   |(blit->format << 8)  /* src pix width */
 745                   |(blit->format << 16) /* host data pix width */
 746                   |(blit->format << 28) /* scaler/3D pix width */
 747             );
 748
 749         DMAOUTREG(MACH64_DP_WRITE_MASK, 0xffffffff);    /* enable all planes */
 750         DMAOUTREG(MACH64_DP_MIX, MACH64_BKGD_MIX_D | MACH64_FRGD_MIX_S);
 751         DMAOUTREG(MACH64_DP_SRC,
 752                   MACH64_BKGD_SRC_BKGD_CLR
 753                   | MACH64_FRGD_SRC_HOST | MACH64_MONO_SRC_ONE);
 754
 755         DMAOUTREG(MACH64_DST_OFF_PITCH,
 756                   (blit->pitch << 22) | (blit->offset >> 3));
 757         DMAOUTREG(MACH64_DST_X_Y, (blit->y << 16) | blit->x);
 758         DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (blit->height << 16) | blit->width);
 759
 760         DRM_DEBUG("%lu bytes\n", used);
 761
 762         /* Add the buffer to the queue */
 763         DMAADVANCEHOSTDATA(dev_priv);
 764
 765 _blit_done:
 766         return verify_ret;
 767 }
 768
 769 /* ================================================================
 770  * IOCTL functions
 771  */
 772
 773 int mach64_dma_clear(struct drm_device *dev, void *data,
 774                      struct drm_file *file_priv)
 775 {
 776         drm_mach64_private_t *dev_priv = dev->dev_private;
 777         drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
 778         drm_mach64_clear_t *clear = data;
 779         int ret;
 780
 781         DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
 782
 783         LOCK_TEST_WITH_RETURN(dev, file_priv);
 784
 785         if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS)
 786                 sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS;
 787
 788         ret = mach64_dma_dispatch_clear(dev, file_priv, clear->flags,
 789                                         clear->x, clear->y, clear->w, clear->h,
 790                                         clear->clear_color,
 791                                         clear->clear_depth);
 792
 793         /* Make sure we restore the 3D state next time.
 794          */
 795         sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT | MACH64_UPLOAD_MISC);
 796         return ret;
 797 }
 798
 799 int mach64_dma_swap(struct drm_device *dev, void *data,
 800                     struct drm_file *file_priv)
 801 {
 802         drm_mach64_private_t *dev_priv = dev->dev_private;
 803         drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
 804         int ret;
 805
 806         DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
 807
 808         LOCK_TEST_WITH_RETURN(dev, file_priv);
 809
 810         if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS)
 811                 sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS;
 812
 813         ret = mach64_dma_dispatch_swap(dev, file_priv);
 814
 815         /* Make sure we restore the 3D state next time.
 816          */
 817         sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT | MACH64_UPLOAD_MISC);
 818         return ret;
 819 }
 820
 821 int mach64_dma_vertex(struct drm_device *dev, void *data,
 822                       struct drm_file *file_priv)
 823 {
 824         drm_mach64_private_t *dev_priv = dev->dev_private;
 825         drm_mach64_sarea_t *sarea_priv;
 826         drm_mach64_vertex_t *vertex = data;
 827
 828         LOCK_TEST_WITH_RETURN(dev, file_priv);
 829
 830         if (!dev_priv) {
 831                 DRM_ERROR("called with no initialization\n");
 832                 return -EINVAL;
 833         }
 834
 835         sarea_priv = dev_priv->sarea_priv;
 836
 837         DRM_DEBUG("pid=%d buf=%p used=%lu discard=%d\n",
 838                   DRM_CURRENTPID,
 839                   vertex->buf, vertex->used, vertex->discard);
 840
 841         if (vertex->prim < 0 || vertex->prim > MACH64_PRIM_POLYGON) {
 842                 DRM_ERROR("buffer prim %d\n", vertex->prim);
 843                 return -EINVAL;
 844         }
 845
 846         if (vertex->used > MACH64_BUFFER_SIZE || (vertex->used & 3) != 0) {
 847                 DRM_ERROR("Invalid vertex buffer size: %lu bytes\n",
 848                           vertex->used);
 849                 return -EINVAL;
 850         }
 851
 852         if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS)
 853                 sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS;
 854
 855         return mach64_dma_dispatch_vertex(dev, file_priv, vertex);
 856 }
 857
 858 int mach64_dma_blit(struct drm_device *dev, void *data,
 859                     struct drm_file *file_priv)
 860 {
 861         drm_mach64_private_t *dev_priv = dev->dev_private;
 862         drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
 863         drm_mach64_blit_t *blit = data;
 864         int ret;
 865
 866         LOCK_TEST_WITH_RETURN(dev, file_priv);
 867
 868         ret = mach64_dma_dispatch_blit(dev, file_priv, blit);
 869
 870         /* Make sure we restore the 3D state next time.
 871          */
 872         sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT |
 873                               MACH64_UPLOAD_MISC | MACH64_UPLOAD_CLIPRECTS);
 874
 875         return ret;
 876 }
 877
 878 int mach64_get_param(struct drm_device *dev, void *data,
 879                      struct drm_file *file_priv)
 880 {
 881         drm_mach64_private_t *dev_priv = dev->dev_private;
 882         drm_mach64_getparam_t *param = data;
 883         int value;
 884
 885         DRM_DEBUG("\n");
 886
 887         if (!dev_priv) {
 888                 DRM_ERROR("called with no initialization\n");
 889                 return -EINVAL;
 890         }
 891
 892         switch (param->param) {
 893         case MACH64_PARAM_FRAMES_QUEUED:
 894                 /* Needs lock since it calls mach64_ring_tick() */
 895                 LOCK_TEST_WITH_RETURN(dev, file_priv);
 896                 value = mach64_do_get_frames_queued(dev_priv);
 897                 break;
 898         case MACH64_PARAM_IRQ_NR:
 899                 value = dev->irq;
 900                 break;
 901         default:
 902                 return -EINVAL;
 903         }
 904
 905         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 906                 DRM_ERROR("copy_to_user\n");
 907                 return -EFAULT;
 908         }
 909
 910         return 0;
 911 }