2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-all.h,v 1.26.2.12 2003/01/30 07:19:59 sos Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-all.h,v 1.3 2003/07/19 21:14:18 dillon Exp $
32 /* ATA register defines */
33 #define ATA_DATA 0x00 /* data register */
34 #define ATA_ERROR 0x01 /* (R) error register */
35 #define ATA_E_NM 0x02 /* no media */
36 #define ATA_E_ABORT 0x04 /* command aborted */
37 #define ATA_E_MCR 0x08 /* media change request */
38 #define ATA_E_IDNF 0x10 /* ID not found */
39 #define ATA_E_MC 0x20 /* media changed */
40 #define ATA_E_UNC 0x40 /* uncorrectable data */
41 #define ATA_E_ICRC 0x80 /* UDMA crc error */
43 #define ATA_FEATURE 0x01 /* (W) feature register */
44 #define ATA_F_DMA 0x01 /* enable DMA */
45 #define ATA_F_OVL 0x02 /* enable overlap */
47 #define ATA_COUNT 0x02 /* (W) sector count */
48 #define ATA_IREASON 0x02 /* (R) interrupt reason */
49 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
50 #define ATA_I_IN 0x02 /* read (1) | write (0) */
51 #define ATA_I_RELEASE 0x04 /* released bus (1) */
52 #define ATA_I_TAGMASK 0xf8 /* tag mask */
54 #define ATA_SECTOR 0x03 /* sector # */
55 #define ATA_CYL_LSB 0x04 /* cylinder# LSB */
56 #define ATA_CYL_MSB 0x05 /* cylinder# MSB */
57 #define ATA_DRIVE 0x06 /* Sector/Drive/Head register */
58 #define ATA_D_LBA 0x40 /* use LBA addressing */
59 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
61 #define ATA_CMD 0x07 /* command register */
62 #define ATA_C_NOP 0x00 /* NOP command */
63 #define ATA_C_F_FLUSHQUEUE 0x00 /* flush queued cmd's */
64 #define ATA_C_F_AUTOPOLL 0x01 /* start autopoll function */
65 #define ATA_C_ATAPI_RESET 0x08 /* reset ATAPI device */
66 #define ATA_C_READ 0x20 /* read command */
67 #define ATA_C_READ48 0x24 /* read command */
68 #define ATA_C_READ_DMA48 0x25 /* read w/DMA command */
69 #define ATA_C_READ_DMA_QUEUED48 0x26 /* read w/DMA QUEUED command */
70 #define ATA_C_READ_MUL48 0x29 /* read multi command */
71 #define ATA_C_WRITE 0x30 /* write command */
72 #define ATA_C_WRITE48 0x34 /* write command */
73 #define ATA_C_WRITE_DMA48 0x35 /* write w/DMA command */
74 #define ATA_C_WRITE_DMA_QUEUED48 0x36 /* write w/DMA QUEUED command */
75 #define ATA_C_WRITE_MUL48 0x39 /* write multi command */
76 #define ATA_C_PACKET_CMD 0xa0 /* packet command */
77 #define ATA_C_ATAPI_IDENTIFY 0xa1 /* get ATAPI params*/
78 #define ATA_C_SERVICE 0xa2 /* service command */
79 #define ATA_C_READ_MUL 0xc4 /* read multi command */
80 #define ATA_C_WRITE_MUL 0xc5 /* write multi command */
81 #define ATA_C_SET_MULTI 0xc6 /* set multi size command */
82 #define ATA_C_READ_DMA_QUEUED 0xc7 /* read w/DMA QUEUED command */
83 #define ATA_C_READ_DMA 0xc8 /* read w/DMA command */
84 #define ATA_C_WRITE_DMA 0xca /* write w/DMA command */
85 #define ATA_C_WRITE_DMA_QUEUED 0xcc /* write w/DMA QUEUED command */
86 #define ATA_C_SLEEP 0xe6 /* sleep command */
87 #define ATA_C_FLUSHCACHE 0xe7 /* flush cache to disk */
88 #define ATA_C_FLUSHCACHE48 0xea /* flush cache to disk */
89 #define ATA_C_ATA_IDENTIFY 0xec /* get ATA params */
90 #define ATA_C_SETFEATURES 0xef /* features command */
91 #define ATA_C_F_SETXFER 0x03 /* set transfer mode */
92 #define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
93 #define ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */
94 #define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
95 #define ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */
96 #define ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */
97 #define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */
98 #define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */
99 #define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */
101 #define ATA_STATUS 0x07 /* status register */
102 #define ATA_S_ERROR 0x01 /* error */
103 #define ATA_S_INDEX 0x02 /* index */
104 #define ATA_S_CORR 0x04 /* data corrected */
105 #define ATA_S_DRQ 0x08 /* data request */
106 #define ATA_S_DSC 0x10 /* drive seek completed */
107 #define ATA_S_SERVICE 0x10 /* drive needs service */
108 #define ATA_S_DWF 0x20 /* drive write fault */
109 #define ATA_S_DMA 0x20 /* DMA ready */
110 #define ATA_S_READY 0x40 /* drive ready */
111 #define ATA_S_BUSY 0x80 /* busy */
113 #define ATA_ALTSTAT 0x00 /* alternate status register */
114 #define ATA_ALTOFFSET 0x206 /* alternate registers offset */
115 #define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */
116 #define ATA_A_IDS 0x02 /* disable interrupts */
117 #define ATA_A_RESET 0x04 /* RESET controller */
118 #define ATA_A_4BIT 0x08 /* 4 head bits */
121 #define ATA_PRIMARY 0x1f0
122 #define ATA_SECONDARY 0x170
123 #define ATA_IOSIZE 0x08
124 #define ATA_ALTIOSIZE 0x01
125 #define ATA_BMIOSIZE 0x08
126 #define ATA_OP_FINISHED 0x00
127 #define ATA_OP_CONTINUES 0x01
128 #define ATA_IOADDR_RID 0
129 #define ATA_ALTADDR_RID 1
130 #define ATA_BMADDR_RID 2
131 #define ATA_IRQ_RID 0
132 #define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1)
134 /* busmaster DMA related defines */
135 #define ATA_DMA_ENTRIES 256
136 #define ATA_DMA_EOT 0x80000000
138 #define ATA_BMCMD_PORT 0x00
139 #define ATA_BMCMD_START_STOP 0x01
140 #define ATA_BMCMD_WRITE_READ 0x08
142 #define ATA_BMDEVSPEC_0 0x01
144 #define ATA_BMSTAT_PORT 0x02
145 #define ATA_BMSTAT_ACTIVE 0x01
146 #define ATA_BMSTAT_ERROR 0x02
147 #define ATA_BMSTAT_INTERRUPT 0x04
148 #define ATA_BMSTAT_MASK 0x07
149 #define ATA_BMSTAT_DMA_MASTER 0x20
150 #define ATA_BMSTAT_DMA_SLAVE 0x40
151 #define ATA_BMSTAT_DMA_SIMPLEX 0x80
153 #define ATA_BMDEVSPEC_1 0x03
154 #define ATA_BMDTP_PORT 0x04
156 /* structure for holding DMA address data */
157 struct ata_dmaentry {
162 /* structure describing an ATA/ATAPI device */
164 struct ata_channel *channel;
165 int unit; /* unit number */
166 #define ATA_MASTER 0x00
167 #define ATA_SLAVE 0x10
169 char *name; /* device name */
170 struct ata_params *param; /* ata param structure */
171 void *driver; /* ptr to driver for device */
173 #define ATA_D_USE_CHS 0x0001
174 #define ATA_D_DETACHING 0x0002
175 #define ATA_D_MEDIA_CHANGED 0x0004
176 #define ATA_D_ENC_PRESENT 0x0008
178 int mode; /* transfermode */
179 int cmd; /* last cmd executed */
180 void *result; /* misc data */
183 /* structure describing an ATA channel */
185 struct device *dev; /* device handle */
186 int unit; /* channel number */
187 struct resource *r_io; /* io addr resource handle */
188 struct resource *r_altio; /* altio addr resource handle */
189 struct resource *r_bmio; /* bmio addr resource handle */
190 struct resource *r_irq; /* interrupt of this channel */
191 void *ih; /* interrupt handle */
192 int (*intr_func)(struct ata_channel *); /* interrupt function */
193 u_int32_t chiptype; /* pciid of controller chip */
194 u_int32_t alignment; /* dma engine min alignment */
195 int flags; /* controller flags */
196 #define ATA_NO_SLAVE 0x01
197 #define ATA_USE_16BIT 0x02
198 #define ATA_ATAPI_DMA_RO 0x04
199 #define ATA_QUEUED 0x08
200 #define ATA_DMA_ACTIVE 0x10
202 struct ata_device device[2]; /* devices on this channel */
206 int devices; /* what is present */
207 #define ATA_ATA_MASTER 0x01
208 #define ATA_ATA_SLAVE 0x02
209 #define ATA_ATAPI_MASTER 0x04
210 #define ATA_ATAPI_SLAVE 0x08
212 u_int8_t status; /* last controller status */
213 u_int8_t error; /* last controller error */
214 int active; /* active processing request */
215 #define ATA_IDLE 0x0000
216 #define ATA_IMMEDIATE 0x0001
217 #define ATA_WAIT_INTR 0x0002
218 #define ATA_WAIT_READY 0x0004
219 #define ATA_WAIT_MASK 0x0007
220 #define ATA_ACTIVE 0x0010
221 #define ATA_ACTIVE_ATA 0x0020
222 #define ATA_ACTIVE_ATAPI 0x0040
223 #define ATA_CONTROL 0x0080
225 TAILQ_HEAD(, ad_request) ata_queue; /* head of ATA queue */
226 TAILQ_HEAD(, atapi_request) atapi_queue; /* head of ATAPI queue */
227 void *running; /* currently running request */
230 /* disk bay/enclosure related */
231 #define ATA_LED_OFF 0x00
232 #define ATA_LED_RED 0x01
233 #define ATA_LED_GREEN 0x02
234 #define ATA_LED_ORANGE 0x03
235 #define ATA_LED_MASK 0x03
238 extern devclass_t ata_devclass;
240 /* public prototypes */
241 int ata_probe(device_t);
242 int ata_attach(device_t);
243 int ata_detach(device_t);
244 int ata_resume(device_t);
246 void ata_start(struct ata_channel *);
247 void ata_reset(struct ata_channel *);
248 int ata_reinit(struct ata_channel *);
249 int ata_wait(struct ata_device *, u_int8_t);
250 int ata_command(struct ata_device *, u_int8_t, u_int64_t, u_int16_t, u_int8_t, int);
251 void ata_enclosure_leds(struct ata_device *, u_int8_t);
252 void ata_enclosure_print(struct ata_device *);
253 int ata_printf(struct ata_channel *, int, const char *, ...) __printflike(3, 4);
254 int ata_prtdev(struct ata_device *, const char *, ...) __printflike(2, 3);
255 void ata_set_name(struct ata_device *, char *, int);
256 void ata_free_name(struct ata_device *);
257 int ata_get_lun(u_int32_t *);
258 int ata_test_lun(u_int32_t *, int);
259 void ata_free_lun(u_int32_t *, int);
260 char *ata_mode2str(int);
261 int ata_pmode(struct ata_params *);
262 int ata_wmode(struct ata_params *);
263 int ata_umode(struct ata_params *);
264 int ata_find_dev(device_t, u_int32_t, u_int32_t);
266 void *ata_dmaalloc(struct ata_channel *, int);
267 void ata_dmainit(struct ata_channel *, int, int, int, int);
268 int ata_dmasetup(struct ata_channel *, int, struct ata_dmaentry *, caddr_t, int);
269 void ata_dmastart(struct ata_channel *, int, struct ata_dmaentry *, int);
270 int ata_dmastatus(struct ata_channel *);
271 int ata_dmadone(struct ata_channel *);
273 /* macros for locking a channel */
274 #define ATA_LOCK_CH(ch, value)\
275 (((ch)->active == ATA_IDLE) ? ((ch)->active = value) : 0)
277 #define ATA_SLEEPLOCK_CH(ch, value) {\
278 while ((ch)->active != ATA_IDLE)\
279 tsleep((caddr_t)&(ch), 0, "atalck", 1);\
280 (ch)->active = value; }
282 #define ATA_FORCELOCK_CH(ch, value) \
285 #define ATA_UNLOCK_CH(ch) \
286 (ch)->active = ATA_IDLE
288 /* macros to hide busspace uglyness */
289 #define ATA_INB(res, offset) \
290 bus_space_read_1(rman_get_bustag((res)), \
291 rman_get_bushandle((res)), (offset))
292 #define ATA_INW(res, offset) \
293 bus_space_read_2(rman_get_bustag((res)), \
294 rman_get_bushandle((res)), (offset))
295 #define ATA_INL(res, offset) \
296 bus_space_read_4(rman_get_bustag((res)), \
297 rman_get_bushandle((res)), (offset))
298 #define ATA_INSW(res, offset, addr, count) \
299 bus_space_read_multi_2(rman_get_bustag((res)), \
300 rman_get_bushandle((res)), \
301 (offset), (addr), (count))
302 #define ATA_INSL(res, offset, addr, count) \
303 bus_space_read_multi_4(rman_get_bustag((res)), \
304 rman_get_bushandle((res)), \
305 (offset), (addr), (count))
306 #define ATA_OUTB(res, offset, value) \
307 bus_space_write_1(rman_get_bustag((res)), \
308 rman_get_bushandle((res)), (offset), (value))
309 #define ATA_OUTW(res, offset, value) \
310 bus_space_write_2(rman_get_bustag((res)), \
311 rman_get_bushandle((res)), (offset), (value))
312 #define ATA_OUTL(res, offset, value) \
313 bus_space_write_4(rman_get_bustag((res)), \
314 rman_get_bushandle((res)), (offset), (value))
315 #define ATA_OUTSW(res, offset, addr, count) \
316 bus_space_write_multi_2(rman_get_bustag((res)), \
317 rman_get_bushandle((res)), \
318 (offset), (addr), (count))
319 #define ATA_OUTSL(res, offset, addr, count) \
320 bus_space_write_multi_4(rman_get_bustag((res)), \
321 rman_get_bushandle((res)), \
322 (offset), (addr), (count))