2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.42 2005/11/02 18:42:01 dillon Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <machine/smptests.h>
53 #include <machine/smp.h>
54 #include <arch/apic/apicreg.h>
55 #include <machine/atomic.h>
56 #include <machine/cpufunc.h>
57 #include <arch/apic/mpapic.h>
58 #include <machine/psl.h>
59 #include <machine/segments.h>
60 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
66 #include <machine/md_var.h> /* setidt() */
67 #include <i386/icu/icu.h> /* IPIs */
68 #include <i386/isa/intr_machdep.h> /* IPIs */
71 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
73 #if defined(TEST_DEFAULT_CONFIG)
74 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
76 #define MPFPS_MPFB1 mpfps->mpfb1
77 #endif /* TEST_DEFAULT_CONFIG */
79 #define WARMBOOT_TARGET 0
80 #define WARMBOOT_OFF (KERNBASE + 0x0467)
81 #define WARMBOOT_SEG (KERNBASE + 0x0469)
83 #define BIOS_BASE (0xf0000)
84 #define BIOS_SIZE (0x10000)
85 #define BIOS_COUNT (BIOS_SIZE/4)
87 #define CMOS_REG (0x70)
88 #define CMOS_DATA (0x71)
89 #define BIOS_RESET (0x0f)
90 #define BIOS_WARM (0x0a)
92 #define PROCENTRY_FLAG_EN 0x01
93 #define PROCENTRY_FLAG_BP 0x02
94 #define IOAPICENTRY_FLAG_EN 0x01
97 /* MP Floating Pointer Structure */
98 typedef struct MPFPS {
111 /* MP Configuration Table Header */
112 typedef struct MPCTH {
114 u_short base_table_length;
118 u_char product_id[12];
119 void *oem_table_pointer;
120 u_short oem_table_size;
123 u_short extended_table_length;
124 u_char extended_table_checksum;
129 typedef struct PROCENTRY {
134 u_long cpu_signature;
135 u_long feature_flags;
140 typedef struct BUSENTRY {
146 typedef struct IOAPICENTRY {
152 } *io_apic_entry_ptr;
154 typedef struct INTENTRY {
164 /* descriptions of MP basetable entries */
165 typedef struct BASETABLE_ENTRY {
172 * this code MUST be enabled here and in mpboot.s.
173 * it follows the very early stages of AP boot by placing values in CMOS ram.
174 * it NORMALLY will never be needed and thus the primitive method for enabling.
177 #if defined(CHECK_POINTS)
178 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
179 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
181 #define CHECK_INIT(D); \
182 CHECK_WRITE(0x34, (D)); \
183 CHECK_WRITE(0x35, (D)); \
184 CHECK_WRITE(0x36, (D)); \
185 CHECK_WRITE(0x37, (D)); \
186 CHECK_WRITE(0x38, (D)); \
187 CHECK_WRITE(0x39, (D));
189 #define CHECK_PRINT(S); \
190 printf("%s: %d, %d, %d, %d, %d, %d\n", \
199 #else /* CHECK_POINTS */
201 #define CHECK_INIT(D)
202 #define CHECK_PRINT(S)
204 #endif /* CHECK_POINTS */
207 * Values to send to the POST hardware.
209 #define MP_BOOTADDRESS_POST 0x10
210 #define MP_PROBE_POST 0x11
211 #define MPTABLE_PASS1_POST 0x12
213 #define MP_START_POST 0x13
214 #define MP_ENABLE_POST 0x14
215 #define MPTABLE_PASS2_POST 0x15
217 #define START_ALL_APS_POST 0x16
218 #define INSTALL_AP_TRAMP_POST 0x17
219 #define START_AP_POST 0x18
221 #define MP_ANNOUNCE_POST 0x19
223 static int need_hyperthreading_fixup;
224 static u_int logical_cpus;
225 u_int logical_cpus_mask;
227 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
228 int current_postcode;
230 /** XXX FIXME: what system files declare these??? */
231 extern struct region_descriptor r_gdt, r_idt;
233 int bsp_apic_ready = 0; /* flags useability of BSP apic */
234 int mp_naps; /* # of Applications processors */
235 int mp_nbusses; /* # of busses */
236 int mp_napics; /* # of IO APICs */
237 int boot_cpu_id; /* designated BSP */
238 vm_offset_t cpu_apic_address;
239 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
242 u_int32_t cpu_apic_versions[MAXCPU];
243 u_int32_t *io_apic_versions;
245 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
247 #ifdef APIC_INTR_REORDER
249 volatile int *location;
251 } apic_isrbit_location[32];
256 * APIC ID logical/physical mapping structures.
257 * We oversize these to simplify boot-time config.
259 int cpu_num_to_apic_id[NAPICID];
260 int io_num_to_apic_id[NAPICID];
261 int apic_id_to_logical[NAPICID];
263 /* AP uses this during bootstrap. Do not staticize. */
267 /* Hotwire a 0->4MB V==P mapping */
268 extern pt_entry_t *KPTphys;
270 /* SMP page table page */
271 extern pt_entry_t *SMPpt;
273 struct pcb stoppcbs[MAXCPU];
276 * Local data and functions.
279 static int mp_capable;
280 static u_int boot_address;
281 static u_int base_memory;
282 static int mp_finish;
284 static mpfps_t mpfps;
285 static int search_for_sig(u_int32_t target, int count);
286 static void mp_enable(u_int boot_addr);
288 static void mptable_hyperthread_fixup(u_int id_mask);
289 static void mptable_pass1(void);
290 static int mptable_pass2(void);
291 static void default_mp_table(int type);
292 static void fix_mp_table(void);
293 static void setup_apic_irq_mapping(void);
294 static int start_all_aps(u_int boot_addr);
295 static void install_ap_tramp(u_int boot_addr);
296 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
297 static int apic_int_is_bus_type(int intr, int bus_type);
299 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
300 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
301 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
304 * Calculate usable address in base memory for AP trampoline code.
307 mp_bootaddress(u_int basemem)
309 POSTCODE(MP_BOOTADDRESS_POST);
311 base_memory = basemem * 1024; /* convert to bytes */
313 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
314 if ((base_memory - boot_address) < bootMP_size)
315 boot_address -= 4096; /* not enough, lower by 4k */
322 * Look for an Intel MP spec table (ie, SMP capable hardware).
331 POSTCODE(MP_PROBE_POST);
333 /* see if EBDA exists */
334 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
335 /* search first 1K of EBDA */
336 target = (u_int32_t) (segment << 4);
337 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
340 /* last 1K of base memory, effective 'top of base' passed in */
341 target = (u_int32_t) (base_memory - 0x400);
342 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
346 /* search the BIOS */
347 target = (u_int32_t) BIOS_BASE;
348 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
357 /* calculate needed resources */
361 /* flag fact that we are running multiple processors */
368 * Startup the SMP processors.
373 POSTCODE(MP_START_POST);
375 /* look for MP capable motherboard */
377 mp_enable(boot_address);
379 panic("MP hardware not found!");
384 * Print various information about the SMP system hardware and setup.
391 POSTCODE(MP_ANNOUNCE_POST);
393 printf("DragonFly/MP: Multiprocessor motherboard\n");
394 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
395 printf(", version: 0x%08x", cpu_apic_versions[0]);
396 printf(", at 0x%08x\n", cpu_apic_address);
397 for (x = 1; x <= mp_naps; ++x) {
398 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
399 printf(", version: 0x%08x", cpu_apic_versions[x]);
400 printf(", at 0x%08x\n", cpu_apic_address);
404 for (x = 0; x < mp_napics; ++x) {
405 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
406 printf(", version: 0x%08x", io_apic_versions[x]);
407 printf(", at 0x%08x\n", io_apic_address[x]);
410 printf(" Warning: APIC I/O disabled\n");
415 * AP cpu's call this to sync up protected mode.
417 * WARNING! We must ensure that the cpu is sufficiently initialized to
418 * be able to use to the FP for our optimized bzero/bcopy code before
419 * we enter more mainstream C code.
421 * WARNING! %fs is not set up on entry. This routine sets up %fs.
427 int x, myid = bootAP;
429 struct mdglobaldata *md;
430 struct privatespace *ps;
432 ps = &CPU_prvspace[myid];
434 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
435 gdt_segs[GPROC0_SEL].ssd_base =
436 (int) &ps->mdglobaldata.gd_common_tss;
437 ps->mdglobaldata.mi.gd_prvspace = ps;
439 for (x = 0; x < NGDT; x++) {
440 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
443 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
444 r_gdt.rd_base = (int) &gdt[myid * NGDT];
445 lgdt(&r_gdt); /* does magic intra-segment return */
450 mdcpu->gd_currentldt = _default_ldt;
452 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
453 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
455 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
457 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
458 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
459 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
460 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
461 md->gd_common_tssd = *md->gd_tss_gdt;
465 * Set to a known state:
466 * Set by mpboot.s: CR0_PG, CR0_PE
467 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
470 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
472 pmap_set_opt(); /* PSE/4MB pages, etc */
474 /* set up CPU registers and state */
477 /* set up FPU state on the AP */
478 npxinit(__INITIAL_NPXCW__);
480 /* set up SSE registers */
484 /*******************************************************************
485 * local functions and data
489 * start the SMP system
492 mp_enable(u_int boot_addr)
500 POSTCODE(MP_ENABLE_POST);
502 /* turn on 4MB of V == P addressing so we can get to MP table */
503 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
506 /* examine the MP table for needed info, uses physical addresses */
512 /* can't process default configs till the CPU APIC is pmapped */
516 /* post scan cleanup */
518 setup_apic_irq_mapping();
522 /* fill the LOGICAL io_apic_versions table */
523 for (apic = 0; apic < mp_napics; ++apic) {
524 ux = io_apic_read(apic, IOAPIC_VER);
525 io_apic_versions[apic] = ux;
526 io_apic_set_id(apic, IO_TO_ID(apic));
529 /* program each IO APIC in the system */
530 for (apic = 0; apic < mp_napics; ++apic)
531 if (io_apic_setup(apic) < 0)
532 panic("IO APIC setup failure");
534 /* install a 'Spurious INTerrupt' vector */
535 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
536 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
538 /* install an inter-CPU IPI for TLB invalidation */
539 setidt(XINVLTLB_OFFSET, Xinvltlb,
540 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
542 /* install an inter-CPU IPI for IPIQ messaging */
543 setidt(XIPIQ_OFFSET, Xipiq,
544 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
546 /* install an inter-CPU IPI for CPU stop/restart */
547 setidt(XCPUSTOP_OFFSET, Xcpustop,
548 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
550 #if defined(TEST_TEST1)
551 /* install a "fake hardware INTerrupt" vector */
552 setidt(XTEST1_OFFSET, Xtest1,
553 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
554 #endif /** TEST_TEST1 */
558 /* start each Application Processor */
559 start_all_aps(boot_addr);
564 * look for the MP spec signature
567 /* string defined by the Intel MP Spec as identifying the MP table */
568 #define MP_SIG 0x5f504d5f /* _MP_ */
569 #define NEXT(X) ((X) += 4)
571 search_for_sig(u_int32_t target, int count)
574 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
576 for (x = 0; x < count; NEXT(x))
577 if (addr[x] == MP_SIG)
578 /* make array index a byte index */
579 return (target + (x * sizeof(u_int32_t)));
585 static basetable_entry basetable_entry_types[] =
587 {0, 20, "Processor"},
594 typedef struct BUSDATA {
596 enum busTypes bus_type;
599 typedef struct INTDATA {
609 typedef struct BUSTYPENAME {
614 static bus_type_name bus_type_table[] =
620 {UNKNOWN_BUSTYPE, "---"},
623 {UNKNOWN_BUSTYPE, "---"},
624 {UNKNOWN_BUSTYPE, "---"},
625 {UNKNOWN_BUSTYPE, "---"},
626 {UNKNOWN_BUSTYPE, "---"},
627 {UNKNOWN_BUSTYPE, "---"},
629 {UNKNOWN_BUSTYPE, "---"},
630 {UNKNOWN_BUSTYPE, "---"},
631 {UNKNOWN_BUSTYPE, "---"},
632 {UNKNOWN_BUSTYPE, "---"},
634 {UNKNOWN_BUSTYPE, "---"}
636 /* from MP spec v1.4, table 5-1 */
637 static int default_data[7][5] =
639 /* nbus, id0, type0, id1, type1 */
640 {1, 0, ISA, 255, 255},
641 {1, 0, EISA, 255, 255},
642 {1, 0, EISA, 255, 255},
643 {1, 0, MCA, 255, 255},
645 {2, 0, EISA, 1, PCI},
651 static bus_datum *bus_data;
653 /* the IO INT data, one entry per possible APIC INTerrupt */
654 static io_int *io_apic_ints;
658 static int processor_entry (proc_entry_ptr entry, int cpu);
659 static int bus_entry (bus_entry_ptr entry, int bus);
660 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
661 static int int_entry (int_entry_ptr entry, int intr);
662 static int lookup_bus_type (char *name);
666 * 1st pass on motherboard's Intel MP specification table.
672 * cpu_apic_address (common to all CPUs)
690 POSTCODE(MPTABLE_PASS1_POST);
692 /* clear various tables */
693 for (x = 0; x < NAPICID; ++x) {
694 io_apic_address[x] = ~0; /* IO APIC address table */
697 /* init everything to empty */
704 /* check for use of 'default' configuration */
705 if (MPFPS_MPFB1 != 0) {
706 /* use default addresses */
707 cpu_apic_address = DEFAULT_APIC_BASE;
708 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
710 /* fill in with defaults */
711 mp_naps = 2; /* includes BSP */
712 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
719 if ((cth = mpfps->pap) == 0)
720 panic("MP Configuration Table Header MISSING!");
722 cpu_apic_address = (vm_offset_t) cth->apic_address;
724 /* walk the table, recording info of interest */
725 totalSize = cth->base_table_length - sizeof(struct MPCTH);
726 position = (u_char *) cth + sizeof(struct MPCTH);
727 count = cth->entry_count;
730 switch (type = *(u_char *) position) {
731 case 0: /* processor_entry */
732 if (((proc_entry_ptr)position)->cpu_flags
733 & PROCENTRY_FLAG_EN) {
736 ((proc_entry_ptr)position)->apic_id;
739 case 1: /* bus_entry */
742 case 2: /* io_apic_entry */
743 if (((io_apic_entry_ptr)position)->apic_flags
744 & IOAPICENTRY_FLAG_EN)
745 io_apic_address[mp_napics++] =
746 (vm_offset_t)((io_apic_entry_ptr)
747 position)->apic_address;
749 case 3: /* int_entry */
752 case 4: /* int_entry */
755 panic("mpfps Base Table HOSED!");
759 totalSize -= basetable_entry_types[type].length;
760 position = (uint8_t *)position +
761 basetable_entry_types[type].length;
765 /* qualify the numbers */
766 if (mp_naps > MAXCPU) {
767 printf("Warning: only using %d of %d available CPUs!\n",
772 /* See if we need to fixup HT logical CPUs. */
773 mptable_hyperthread_fixup(id_mask);
777 * This is also used as a counter while starting the APs.
781 --mp_naps; /* subtract the BSP */
786 * 2nd pass on motherboard's Intel MP specification table.
790 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
791 * CPU_TO_ID(N), logical CPU to APIC ID table
792 * IO_TO_ID(N), logical IO to APIC ID table
799 struct PROCENTRY proc;
806 int apic, bus, cpu, intr;
811 POSTCODE(MPTABLE_PASS2_POST);
813 /* Initialize fake proc entry for use with HT fixup. */
814 bzero(&proc, sizeof(proc));
816 proc.cpu_flags = PROCENTRY_FLAG_EN;
818 pgeflag = 0; /* XXX - Not used under SMP yet. */
820 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
822 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
824 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
826 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
829 bzero(ioapic, sizeof(ioapic_t *) * mp_napics);
831 for (i = 0; i < mp_napics; i++) {
832 for (j = 0; j < mp_napics; j++) {
833 /* same page frame as a previous IO apic? */
834 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) ==
835 (io_apic_address[i] & PG_FRAME)) {
836 ioapic[i] = (ioapic_t *)((u_int)CPU_prvspace
837 + (NPTEPG-2-j) * PAGE_SIZE
838 + (io_apic_address[i] & PAGE_MASK));
841 /* use this slot if available */
842 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) {
843 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW |
844 pgeflag | (io_apic_address[i] & PG_FRAME));
845 ioapic[i] = (ioapic_t *)((u_int)CPU_prvspace
846 + (NPTEPG-2-j) * PAGE_SIZE
847 + (io_apic_address[i] & PAGE_MASK));
853 /* clear various tables */
854 for (x = 0; x < NAPICID; ++x) {
855 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
856 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
857 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
860 /* clear bus data table */
861 for (x = 0; x < mp_nbusses; ++x)
862 bus_data[x].bus_id = 0xff;
864 /* clear IO APIC INT table */
865 for (x = 0; x < (nintrs + 1); ++x) {
866 io_apic_ints[x].int_type = 0xff;
867 io_apic_ints[x].int_vector = 0xff;
870 /* setup the cpu/apic mapping arrays */
873 /* record whether PIC or virtual-wire mode */
874 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
875 machintr_setvar_simple(MACHINTR_VAR_PICMODE, picmode);
877 /* check for use of 'default' configuration */
878 if (MPFPS_MPFB1 != 0)
879 return MPFPS_MPFB1; /* return default configuration type */
881 if ((cth = mpfps->pap) == 0)
882 panic("MP Configuration Table Header MISSING!");
884 /* walk the table, recording info of interest */
885 totalSize = cth->base_table_length - sizeof(struct MPCTH);
886 position = (u_char *) cth + sizeof(struct MPCTH);
887 count = cth->entry_count;
888 apic = bus = intr = 0;
889 cpu = 1; /* pre-count the BSP */
892 switch (type = *(u_char *) position) {
894 if (processor_entry(position, cpu))
897 if (need_hyperthreading_fixup) {
899 * Create fake mptable processor entries
900 * and feed them to processor_entry() to
901 * enumerate the logical CPUs.
903 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
904 for (i = 1; i < logical_cpus; i++) {
906 (void)processor_entry(&proc, cpu);
907 logical_cpus_mask |= (1 << cpu);
913 if (bus_entry(position, bus))
917 if (io_apic_entry(position, apic))
921 if (int_entry(position, intr))
925 /* int_entry(position); */
928 panic("mpfps Base Table HOSED!");
932 totalSize -= basetable_entry_types[type].length;
933 position = (uint8_t *)position + basetable_entry_types[type].length;
936 if (boot_cpu_id == -1)
937 panic("NO BSP found!");
939 /* report fact that its NOT a default configuration */
944 * Check if we should perform a hyperthreading "fix-up" to
945 * enumerate any logical CPU's that aren't already listed
948 * XXX: We assume that all of the physical CPUs in the
949 * system have the same number of logical CPUs.
951 * XXX: We assume that APIC ID's are allocated such that
952 * the APIC ID's for a physical processor are aligned
953 * with the number of logical CPU's in the processor.
956 mptable_hyperthread_fixup(u_int id_mask)
960 /* Nothing to do if there is no HTT support. */
961 if ((cpu_feature & CPUID_HTT) == 0)
963 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
964 if (logical_cpus <= 1)
968 * For each APIC ID of a CPU that is set in the mask,
969 * scan the other candidate APIC ID's for this
970 * physical processor. If any of those ID's are
971 * already in the table, then kill the fixup.
973 for (id = 0; id <= MAXCPU; id++) {
974 if ((id_mask & 1 << id) == 0)
976 /* First, make sure we are on a logical_cpus boundary. */
977 if (id % logical_cpus != 0)
979 for (i = id + 1; i < id + logical_cpus; i++)
980 if ((id_mask & 1 << i) != 0)
985 * Ok, the ID's checked out, so enable the fixup. We have to fixup
988 need_hyperthreading_fixup = 1;
989 mp_naps *= logical_cpus;
993 assign_apic_irq(int apic, int intpin, int irq)
997 if (int_to_apicintpin[irq].ioapic != -1)
998 panic("assign_apic_irq: inconsistent table");
1000 int_to_apicintpin[irq].ioapic = apic;
1001 int_to_apicintpin[irq].int_pin = intpin;
1002 int_to_apicintpin[irq].apic_address = ioapic[apic];
1003 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1005 for (x = 0; x < nintrs; x++) {
1006 if ((io_apic_ints[x].int_type == 0 ||
1007 io_apic_ints[x].int_type == 3) &&
1008 io_apic_ints[x].int_vector == 0xff &&
1009 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1010 io_apic_ints[x].dst_apic_int == intpin)
1011 io_apic_ints[x].int_vector = irq;
1016 revoke_apic_irq(int irq)
1022 if (int_to_apicintpin[irq].ioapic == -1)
1023 panic("revoke_apic_irq: inconsistent table");
1025 oldapic = int_to_apicintpin[irq].ioapic;
1026 oldintpin = int_to_apicintpin[irq].int_pin;
1028 int_to_apicintpin[irq].ioapic = -1;
1029 int_to_apicintpin[irq].int_pin = 0;
1030 int_to_apicintpin[irq].apic_address = NULL;
1031 int_to_apicintpin[irq].redirindex = 0;
1033 for (x = 0; x < nintrs; x++) {
1034 if ((io_apic_ints[x].int_type == 0 ||
1035 io_apic_ints[x].int_type == 3) &&
1036 io_apic_ints[x].int_vector != 0xff &&
1037 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1038 io_apic_ints[x].dst_apic_int == oldintpin)
1039 io_apic_ints[x].int_vector = 0xff;
1047 allocate_apic_irq(int intr)
1053 if (io_apic_ints[intr].int_vector != 0xff)
1054 return; /* Interrupt handler already assigned */
1056 if (io_apic_ints[intr].int_type != 0 &&
1057 (io_apic_ints[intr].int_type != 3 ||
1058 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1059 io_apic_ints[intr].dst_apic_int == 0)))
1060 return; /* Not INT or ExtInt on != (0, 0) */
1063 while (irq < APIC_INTMAPSIZE &&
1064 int_to_apicintpin[irq].ioapic != -1)
1067 if (irq >= APIC_INTMAPSIZE)
1068 return; /* No free interrupt handlers */
1070 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1071 intpin = io_apic_ints[intr].dst_apic_int;
1073 assign_apic_irq(apic, intpin, irq);
1074 io_apic_setup_intpin(apic, intpin);
1079 swap_apic_id(int apic, int oldid, int newid)
1086 return; /* Nothing to do */
1088 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1089 apic, oldid, newid);
1091 /* Swap physical APIC IDs in interrupt entries */
1092 for (x = 0; x < nintrs; x++) {
1093 if (io_apic_ints[x].dst_apic_id == oldid)
1094 io_apic_ints[x].dst_apic_id = newid;
1095 else if (io_apic_ints[x].dst_apic_id == newid)
1096 io_apic_ints[x].dst_apic_id = oldid;
1099 /* Swap physical APIC IDs in IO_TO_ID mappings */
1100 for (oapic = 0; oapic < mp_napics; oapic++)
1101 if (IO_TO_ID(oapic) == newid)
1104 if (oapic < mp_napics) {
1105 printf("Changing APIC ID for IO APIC #%d from "
1106 "%d to %d in MP table\n",
1107 oapic, newid, oldid);
1108 IO_TO_ID(oapic) = oldid;
1110 IO_TO_ID(apic) = newid;
1115 fix_id_to_io_mapping(void)
1119 for (x = 0; x < NAPICID; x++)
1122 for (x = 0; x <= mp_naps; x++)
1123 if (CPU_TO_ID(x) < NAPICID)
1124 ID_TO_IO(CPU_TO_ID(x)) = x;
1126 for (x = 0; x < mp_napics; x++)
1127 if (IO_TO_ID(x) < NAPICID)
1128 ID_TO_IO(IO_TO_ID(x)) = x;
1133 first_free_apic_id(void)
1137 for (freeid = 0; freeid < NAPICID; freeid++) {
1138 for (x = 0; x <= mp_naps; x++)
1139 if (CPU_TO_ID(x) == freeid)
1143 for (x = 0; x < mp_napics; x++)
1144 if (IO_TO_ID(x) == freeid)
1155 io_apic_id_acceptable(int apic, int id)
1157 int cpu; /* Logical CPU number */
1158 int oapic; /* Logical IO APIC number for other IO APIC */
1161 return 0; /* Out of range */
1163 for (cpu = 0; cpu <= mp_naps; cpu++)
1164 if (CPU_TO_ID(cpu) == id)
1165 return 0; /* Conflict with CPU */
1167 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1168 if (IO_TO_ID(oapic) == id)
1169 return 0; /* Conflict with other APIC */
1171 return 1; /* ID is acceptable for IO APIC */
1176 io_apic_find_int_entry(int apic, int pin)
1180 /* search each of the possible INTerrupt sources */
1181 for (x = 0; x < nintrs; ++x) {
1182 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1183 (pin == io_apic_ints[x].dst_apic_int))
1184 return (&io_apic_ints[x]);
1191 * parse an Intel MP specification table
1198 int bus_0 = 0; /* Stop GCC warning */
1199 int bus_pci = 0; /* Stop GCC warning */
1201 int apic; /* IO APIC unit number */
1202 int freeid; /* Free physical APIC ID */
1203 int physid; /* Current physical IO APIC ID */
1207 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1208 * did it wrong. The MP spec says that when more than 1 PCI bus
1209 * exists the BIOS must begin with bus entries for the PCI bus and use
1210 * actual PCI bus numbering. This implies that when only 1 PCI bus
1211 * exists the BIOS can choose to ignore this ordering, and indeed many
1212 * MP motherboards do ignore it. This causes a problem when the PCI
1213 * sub-system makes requests of the MP sub-system based on PCI bus
1214 * numbers. So here we look for the situation and renumber the
1215 * busses and associated INTs in an effort to "make it right".
1218 /* find bus 0, PCI bus, count the number of PCI busses */
1219 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1220 if (bus_data[x].bus_id == 0) {
1223 if (bus_data[x].bus_type == PCI) {
1229 * bus_0 == slot of bus with ID of 0
1230 * bus_pci == slot of last PCI bus encountered
1233 /* check the 1 PCI bus case for sanity */
1234 /* if it is number 0 all is well */
1235 if (num_pci_bus == 1 &&
1236 bus_data[bus_pci].bus_id != 0) {
1238 /* mis-numbered, swap with whichever bus uses slot 0 */
1240 /* swap the bus entry types */
1241 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1242 bus_data[bus_0].bus_type = PCI;
1244 /* swap each relavant INTerrupt entry */
1245 id = bus_data[bus_pci].bus_id;
1246 for (x = 0; x < nintrs; ++x) {
1247 if (io_apic_ints[x].src_bus_id == id) {
1248 io_apic_ints[x].src_bus_id = 0;
1250 else if (io_apic_ints[x].src_bus_id == 0) {
1251 io_apic_ints[x].src_bus_id = id;
1256 /* Assign IO APIC IDs.
1258 * First try the existing ID. If a conflict is detected, try
1259 * the ID in the MP table. If a conflict is still detected, find
1262 * We cannot use the ID_TO_IO table before all conflicts has been
1263 * resolved and the table has been corrected.
1265 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1267 /* First try to use the value set by the BIOS */
1268 physid = io_apic_get_id(apic);
1269 if (io_apic_id_acceptable(apic, physid)) {
1270 if (IO_TO_ID(apic) != physid)
1271 swap_apic_id(apic, IO_TO_ID(apic), physid);
1275 /* Then check if the value in the MP table is acceptable */
1276 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1279 /* Last resort, find a free APIC ID and use it */
1280 freeid = first_free_apic_id();
1281 if (freeid >= NAPICID)
1282 panic("No free physical APIC IDs found");
1284 if (io_apic_id_acceptable(apic, freeid)) {
1285 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1288 panic("Free physical APIC ID not usable");
1290 fix_id_to_io_mapping();
1292 /* detect and fix broken Compaq MP table */
1293 if (apic_int_type(0, 0) == -1) {
1294 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1295 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1296 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1297 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1298 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1299 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1301 } else if (apic_int_type(0, 0) == 0) {
1302 printf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1303 for (x = 0; x < nintrs; ++x)
1304 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1305 (0 == io_apic_ints[x].dst_apic_int)) {
1306 io_apic_ints[x].int_type = 3;
1307 io_apic_ints[x].int_vector = 0xff;
1313 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1314 * controllers universally come in pairs. If IRQ 14 is specified
1315 * as an ISA interrupt, then IRQ 15 had better be too.
1317 * [ Shuttle XPC / AMD Athlon X2 ]
1318 * The MPTable is missing an entry for IRQ 15. Note that the
1319 * ACPI table has an entry for both 14 and 15.
1321 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1322 printf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1323 io14 = io_apic_find_int_entry(0, 14);
1324 io_apic_ints[nintrs] = *io14;
1325 io_apic_ints[nintrs].src_bus_irq = 15;
1326 io_apic_ints[nintrs].dst_apic_int = 15;
1332 /* Assign low level interrupt handlers */
1334 setup_apic_irq_mapping(void)
1340 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1341 int_to_apicintpin[x].ioapic = -1;
1342 int_to_apicintpin[x].int_pin = 0;
1343 int_to_apicintpin[x].apic_address = NULL;
1344 int_to_apicintpin[x].redirindex = 0;
1347 /* First assign ISA/EISA interrupts */
1348 for (x = 0; x < nintrs; x++) {
1349 int_vector = io_apic_ints[x].src_bus_irq;
1350 if (int_vector < APIC_INTMAPSIZE &&
1351 io_apic_ints[x].int_vector == 0xff &&
1352 int_to_apicintpin[int_vector].ioapic == -1 &&
1353 (apic_int_is_bus_type(x, ISA) ||
1354 apic_int_is_bus_type(x, EISA)) &&
1355 io_apic_ints[x].int_type == 0) {
1356 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1357 io_apic_ints[x].dst_apic_int,
1362 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1363 for (x = 0; x < nintrs; x++) {
1364 if (io_apic_ints[x].dst_apic_int == 0 &&
1365 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1366 io_apic_ints[x].int_vector == 0xff &&
1367 int_to_apicintpin[0].ioapic == -1 &&
1368 io_apic_ints[x].int_type == 3) {
1369 assign_apic_irq(0, 0, 0);
1373 /* PCI interrupt assignment is deferred */
1378 processor_entry(proc_entry_ptr entry, int cpu)
1380 /* check for usability */
1381 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1384 if(entry->apic_id >= NAPICID)
1385 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1386 /* check for BSP flag */
1387 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1388 boot_cpu_id = entry->apic_id;
1389 CPU_TO_ID(0) = entry->apic_id;
1390 ID_TO_CPU(entry->apic_id) = 0;
1391 return 0; /* its already been counted */
1394 /* add another AP to list, if less than max number of CPUs */
1395 else if (cpu < MAXCPU) {
1396 CPU_TO_ID(cpu) = entry->apic_id;
1397 ID_TO_CPU(entry->apic_id) = cpu;
1406 bus_entry(bus_entry_ptr entry, int bus)
1411 /* encode the name into an index */
1412 for (x = 0; x < 6; ++x) {
1413 if ((c = entry->bus_type[x]) == ' ')
1419 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1420 panic("unknown bus type: '%s'", name);
1422 bus_data[bus].bus_id = entry->bus_id;
1423 bus_data[bus].bus_type = x;
1430 io_apic_entry(io_apic_entry_ptr entry, int apic)
1432 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1435 IO_TO_ID(apic) = entry->apic_id;
1436 if (entry->apic_id < NAPICID)
1437 ID_TO_IO(entry->apic_id) = apic;
1444 lookup_bus_type(char *name)
1448 for (x = 0; x < MAX_BUSTYPE; ++x)
1449 if (strcmp(bus_type_table[x].name, name) == 0)
1450 return bus_type_table[x].type;
1452 return UNKNOWN_BUSTYPE;
1457 int_entry(int_entry_ptr entry, int intr)
1461 io_apic_ints[intr].int_type = entry->int_type;
1462 io_apic_ints[intr].int_flags = entry->int_flags;
1463 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1464 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1465 if (entry->dst_apic_id == 255) {
1466 /* This signal goes to all IO APICS. Select an IO APIC
1467 with sufficient number of interrupt pins */
1468 for (apic = 0; apic < mp_napics; apic++)
1469 if (((io_apic_read(apic, IOAPIC_VER) &
1470 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1471 entry->dst_apic_int)
1473 if (apic < mp_napics)
1474 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1476 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1478 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1479 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1486 apic_int_is_bus_type(int intr, int bus_type)
1490 for (bus = 0; bus < mp_nbusses; ++bus)
1491 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1492 && ((int) bus_data[bus].bus_type == bus_type))
1500 * Given a traditional ISA INT mask, return an APIC mask.
1503 isa_apic_mask(u_int isa_mask)
1508 #if defined(SKIP_IRQ15_REDIRECT)
1509 if (isa_mask == (1 << 15)) {
1510 printf("skipping ISA IRQ15 redirect\n");
1513 #endif /* SKIP_IRQ15_REDIRECT */
1515 isa_irq = ffs(isa_mask); /* find its bit position */
1516 if (isa_irq == 0) /* doesn't exist */
1518 --isa_irq; /* make it zero based */
1520 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1524 return (1 << apic_pin); /* convert pin# to a mask */
1529 * Determine which APIC pin an ISA/EISA INT is attached to.
1531 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1532 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1533 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1534 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1536 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1538 isa_apic_irq(int isa_irq)
1542 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1543 if (INTTYPE(intr) == 0) { /* standard INT */
1544 if (SRCBUSIRQ(intr) == isa_irq) {
1545 if (apic_int_is_bus_type(intr, ISA) ||
1546 apic_int_is_bus_type(intr, EISA)) {
1547 if (INTIRQ(intr) == 0xff)
1548 return -1; /* unassigned */
1549 return INTIRQ(intr); /* found */
1554 return -1; /* NOT found */
1559 * Determine which APIC pin a PCI INT is attached to.
1561 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1562 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1563 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1565 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1569 --pciInt; /* zero based */
1571 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1572 if ((INTTYPE(intr) == 0) /* standard INT */
1573 && (SRCBUSID(intr) == pciBus)
1574 && (SRCBUSDEVICE(intr) == pciDevice)
1575 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1576 if (apic_int_is_bus_type(intr, PCI)) {
1577 if (INTIRQ(intr) == 0xff)
1578 allocate_apic_irq(intr);
1579 if (INTIRQ(intr) == 0xff)
1580 return -1; /* unassigned */
1581 return INTIRQ(intr); /* exact match */
1586 return -1; /* NOT found */
1590 next_apic_irq(int irq)
1597 for (intr = 0; intr < nintrs; intr++) {
1598 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1600 bus = SRCBUSID(intr);
1601 bustype = apic_bus_type(bus);
1602 if (bustype != ISA &&
1608 if (intr >= nintrs) {
1611 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1612 if (INTTYPE(ointr) != 0)
1614 if (bus != SRCBUSID(ointr))
1616 if (bustype == PCI) {
1617 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1619 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1622 if (bustype == ISA || bustype == EISA) {
1623 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1626 if (INTPIN(intr) == INTPIN(ointr))
1630 if (ointr >= nintrs) {
1633 return INTIRQ(ointr);
1647 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1650 * Exactly what this means is unclear at this point. It is a solution
1651 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1652 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1653 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1657 undirect_isa_irq(int rirq)
1661 printf("Freeing redirected ISA irq %d.\n", rirq);
1662 /** FIXME: tickle the MB redirector chip */
1666 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1673 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1676 undirect_pci_irq(int rirq)
1680 printf("Freeing redirected PCI irq %d.\n", rirq);
1682 /** FIXME: tickle the MB redirector chip */
1686 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1694 * given a bus ID, return:
1695 * the bus type if found
1699 apic_bus_type(int id)
1703 for (x = 0; x < mp_nbusses; ++x)
1704 if (bus_data[x].bus_id == id)
1705 return bus_data[x].bus_type;
1712 * given a LOGICAL APIC# and pin#, return:
1713 * the associated src bus ID if found
1717 apic_src_bus_id(int apic, int pin)
1721 /* search each of the possible INTerrupt sources */
1722 for (x = 0; x < nintrs; ++x)
1723 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1724 (pin == io_apic_ints[x].dst_apic_int))
1725 return (io_apic_ints[x].src_bus_id);
1727 return -1; /* NOT found */
1732 * given a LOGICAL APIC# and pin#, return:
1733 * the associated src bus IRQ if found
1737 apic_src_bus_irq(int apic, int pin)
1741 for (x = 0; x < nintrs; x++)
1742 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1743 (pin == io_apic_ints[x].dst_apic_int))
1744 return (io_apic_ints[x].src_bus_irq);
1746 return -1; /* NOT found */
1751 * given a LOGICAL APIC# and pin#, return:
1752 * the associated INTerrupt type if found
1756 apic_int_type(int apic, int pin)
1760 /* search each of the possible INTerrupt sources */
1761 for (x = 0; x < nintrs; ++x) {
1762 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1763 (pin == io_apic_ints[x].dst_apic_int))
1764 return (io_apic_ints[x].int_type);
1766 return -1; /* NOT found */
1770 * Return the IRQ associated with an APIC pin
1773 apic_irq(int apic, int pin)
1778 for (x = 0; x < nintrs; ++x) {
1779 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1780 (pin == io_apic_ints[x].dst_apic_int)) {
1781 res = io_apic_ints[x].int_vector;
1784 if (apic != int_to_apicintpin[res].ioapic)
1785 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1786 if (pin != int_to_apicintpin[res].int_pin)
1787 panic("apic_irq inconsistent table (2)");
1796 * given a LOGICAL APIC# and pin#, return:
1797 * the associated trigger mode if found
1801 apic_trigger(int apic, int pin)
1805 /* search each of the possible INTerrupt sources */
1806 for (x = 0; x < nintrs; ++x)
1807 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1808 (pin == io_apic_ints[x].dst_apic_int))
1809 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1811 return -1; /* NOT found */
1816 * given a LOGICAL APIC# and pin#, return:
1817 * the associated 'active' level if found
1821 apic_polarity(int apic, int pin)
1825 /* search each of the possible INTerrupt sources */
1826 for (x = 0; x < nintrs; ++x)
1827 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1828 (pin == io_apic_ints[x].dst_apic_int))
1829 return (io_apic_ints[x].int_flags & 0x03);
1831 return -1; /* NOT found */
1836 * set data according to MP defaults
1837 * FIXME: probably not complete yet...
1840 default_mp_table(int type)
1843 #if defined(APIC_IO)
1846 #endif /* APIC_IO */
1849 printf(" MP default config type: %d\n", type);
1852 printf(" bus: ISA, APIC: 82489DX\n");
1855 printf(" bus: EISA, APIC: 82489DX\n");
1858 printf(" bus: EISA, APIC: 82489DX\n");
1861 printf(" bus: MCA, APIC: 82489DX\n");
1864 printf(" bus: ISA+PCI, APIC: Integrated\n");
1867 printf(" bus: EISA+PCI, APIC: Integrated\n");
1870 printf(" bus: MCA+PCI, APIC: Integrated\n");
1873 printf(" future type\n");
1879 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1880 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1883 CPU_TO_ID(0) = boot_cpu_id;
1884 ID_TO_CPU(boot_cpu_id) = 0;
1886 /* one and only AP */
1887 CPU_TO_ID(1) = ap_cpu_id;
1888 ID_TO_CPU(ap_cpu_id) = 1;
1890 #if defined(APIC_IO)
1891 /* one and only IO APIC */
1892 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1895 * sanity check, refer to MP spec section 3.6.6, last paragraph
1896 * necessary as some hardware isn't properly setting up the IO APIC
1898 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1899 if (io_apic_id != 2) {
1901 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1902 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1903 io_apic_set_id(0, 2);
1906 IO_TO_ID(0) = io_apic_id;
1907 ID_TO_IO(io_apic_id) = 0;
1908 #endif /* APIC_IO */
1910 /* fill out bus entries */
1919 bus_data[0].bus_id = default_data[type - 1][1];
1920 bus_data[0].bus_type = default_data[type - 1][2];
1921 bus_data[1].bus_id = default_data[type - 1][3];
1922 bus_data[1].bus_type = default_data[type - 1][4];
1925 /* case 4: case 7: MCA NOT supported */
1926 default: /* illegal/reserved */
1927 panic("BAD default MP config: %d", type);
1931 #if defined(APIC_IO)
1932 /* general cases from MP v1.4, table 5-2 */
1933 for (pin = 0; pin < 16; ++pin) {
1934 io_apic_ints[pin].int_type = 0;
1935 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1936 io_apic_ints[pin].src_bus_id = 0;
1937 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1938 io_apic_ints[pin].dst_apic_id = io_apic_id;
1939 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1942 /* special cases from MP v1.4, table 5-2 */
1944 io_apic_ints[2].int_type = 0xff; /* N/C */
1945 io_apic_ints[13].int_type = 0xff; /* N/C */
1946 #if !defined(APIC_MIXED_MODE)
1948 panic("sorry, can't support type 2 default yet");
1949 #endif /* APIC_MIXED_MODE */
1952 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1955 io_apic_ints[0].int_type = 0xff; /* N/C */
1957 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1958 #endif /* APIC_IO */
1962 * start each AP in our list
1965 start_all_aps(u_int boot_addr)
1968 u_char mpbiosreason;
1969 u_long mpbioswarmvec;
1970 struct mdglobaldata *gd;
1971 struct privatespace *ps;
1975 POSTCODE(START_ALL_APS_POST);
1977 /* initialize BSP's local APIC */
1981 /* install the AP 1st level boot code */
1982 install_ap_tramp(boot_addr);
1985 /* save the current value of the warm-start vector */
1986 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
1987 outb(CMOS_REG, BIOS_RESET);
1988 mpbiosreason = inb(CMOS_DATA);
1990 /* set up temporary P==V mapping for AP boot */
1991 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
1992 kptbase = (uintptr_t)(void *)KPTphys;
1993 for (x = 0; x < NKPT; x++) {
1994 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
1995 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2000 for (x = 1; x <= mp_naps; ++x) {
2002 /* This is a bit verbose, it will go away soon. */
2004 /* first page of AP's private space */
2005 pg = x * i386_btop(sizeof(struct privatespace));
2007 /* allocate a new private data page */
2008 gd = (struct mdglobaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
2010 /* wire it into the private page table page */
2011 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys_pte(gd));
2013 /* allocate and set up an idle stack data page */
2014 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
2015 for (i = 0; i < UPAGES; i++) {
2016 SMPpt[pg + 5 + i] = (pt_entry_t)
2017 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2020 SMPpt[pg + 1] = 0; /* *gd_CMAP1 */
2021 SMPpt[pg + 2] = 0; /* *gd_CMAP2 */
2022 SMPpt[pg + 3] = 0; /* *gd_CMAP3 */
2023 SMPpt[pg + 4] = 0; /* *gd_PMAP1 */
2025 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2026 bzero(gd, sizeof(*gd));
2027 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2029 /* prime data page for it to use */
2030 mi_gdinit(&gd->mi, x);
2032 gd->gd_CMAP1 = &SMPpt[pg + 1];
2033 gd->gd_CMAP2 = &SMPpt[pg + 2];
2034 gd->gd_CMAP3 = &SMPpt[pg + 3];
2035 gd->gd_PMAP1 = &SMPpt[pg + 4];
2036 gd->gd_CADDR1 = ps->CPAGE1;
2037 gd->gd_CADDR2 = ps->CPAGE2;
2038 gd->gd_CADDR3 = ps->CPAGE3;
2039 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2040 gd->mi.gd_ipiq = (void *)kmem_alloc(kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2041 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2043 /* setup a vector to our boot code */
2044 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2045 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2046 outb(CMOS_REG, BIOS_RESET);
2047 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2050 * Setup the AP boot stack
2052 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2055 /* attempt to start the Application Processor */
2056 CHECK_INIT(99); /* setup checkpoints */
2057 if (!start_ap(gd, boot_addr)) {
2058 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2059 CHECK_PRINT("trace"); /* show checkpoints */
2060 /* better panic as the AP may be running loose */
2061 printf("panic y/n? [y] ");
2062 if (cngetc() != 'n')
2065 CHECK_PRINT("trace"); /* show checkpoints */
2067 /* record its version info */
2068 cpu_apic_versions[x] = cpu_apic_versions[0];
2071 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2074 /* round ncpus down to power of 2 */
2078 ncpus2 = 1 << ncpus2_shift;
2079 ncpus2_mask = ncpus2 - 1;
2081 /* build our map of 'other' CPUs */
2082 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2083 mycpu->gd_ipiq = (void *)kmem_alloc(kernel_map, sizeof(lwkt_ipiq) * ncpus);
2084 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2086 /* fill in our (BSP) APIC version */
2087 cpu_apic_versions[0] = lapic.version;
2089 /* restore the warmstart vector */
2090 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2091 outb(CMOS_REG, BIOS_RESET);
2092 outb(CMOS_DATA, mpbiosreason);
2095 * NOTE! The idlestack for the BSP was setup by locore. Finish
2096 * up, clean out the P==V mapping we did earlier.
2098 for (x = 0; x < NKPT; x++)
2102 /* number of APs actually started */
2108 * load the 1st level AP boot code into base memory.
2111 /* targets for relocation */
2112 extern void bigJump(void);
2113 extern void bootCodeSeg(void);
2114 extern void bootDataSeg(void);
2115 extern void MPentry(void);
2116 extern u_int MP_GDT;
2117 extern u_int mp_gdtbase;
2120 install_ap_tramp(u_int boot_addr)
2123 int size = *(int *) ((u_long) & bootMP_size);
2124 u_char *src = (u_char *) ((u_long) bootMP);
2125 u_char *dst = (u_char *) boot_addr + KERNBASE;
2126 u_int boot_base = (u_int) bootMP;
2131 POSTCODE(INSTALL_AP_TRAMP_POST);
2133 for (x = 0; x < size; ++x)
2137 * modify addresses in code we just moved to basemem. unfortunately we
2138 * need fairly detailed info about mpboot.s for this to work. changes
2139 * to mpboot.s might require changes here.
2142 /* boot code is located in KERNEL space */
2143 dst = (u_char *) boot_addr + KERNBASE;
2145 /* modify the lgdt arg */
2146 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2147 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2149 /* modify the ljmp target for MPentry() */
2150 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2151 *dst32 = ((u_int) MPentry - KERNBASE);
2153 /* modify the target for boot code segment */
2154 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2155 dst8 = (u_int8_t *) (dst16 + 1);
2156 *dst16 = (u_int) boot_addr & 0xffff;
2157 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2159 /* modify the target for boot data segment */
2160 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2161 dst8 = (u_int8_t *) (dst16 + 1);
2162 *dst16 = (u_int) boot_addr & 0xffff;
2163 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2168 * this function starts the AP (application processor) identified
2169 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2170 * to accomplish this. This is necessary because of the nuances
2171 * of the different hardware we might encounter. It ain't pretty,
2172 * but it seems to work.
2174 * NOTE: eventually an AP gets to ap_init(), which is called just
2175 * before the AP goes into the LWKT scheduler's idle loop.
2178 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2182 u_long icr_lo, icr_hi;
2184 POSTCODE(START_AP_POST);
2186 /* get the PHYSICAL APIC ID# */
2187 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2189 /* calculate the vector */
2190 vector = (boot_addr >> 12) & 0xff;
2192 /* Make sure the target cpu sees everything */
2196 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2197 * and running the target CPU. OR this INIT IPI might be latched (P5
2198 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2202 /* setup the address for the target AP */
2203 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2204 icr_hi |= (physical_cpu << 24);
2205 lapic.icr_hi = icr_hi;
2207 /* do an INIT IPI: assert RESET */
2208 icr_lo = lapic.icr_lo & 0xfff00000;
2209 lapic.icr_lo = icr_lo | 0x0000c500;
2211 /* wait for pending status end */
2212 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2215 /* do an INIT IPI: deassert RESET */
2216 lapic.icr_lo = icr_lo | 0x00008500;
2218 /* wait for pending status end */
2219 u_sleep(10000); /* wait ~10mS */
2220 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2224 * next we do a STARTUP IPI: the previous INIT IPI might still be
2225 * latched, (P5 bug) this 1st STARTUP would then terminate
2226 * immediately, and the previously started INIT IPI would continue. OR
2227 * the previous INIT IPI has already run. and this STARTUP IPI will
2228 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2232 /* do a STARTUP IPI */
2233 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2234 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2236 u_sleep(200); /* wait ~200uS */
2239 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2240 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2241 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2242 * recognized after hardware RESET or INIT IPI.
2245 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2246 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2248 u_sleep(200); /* wait ~200uS */
2250 /* wait for it to start, see ap_init() */
2251 set_apic_timer(5000000);/* == 5 seconds */
2252 while (read_apic_timer()) {
2253 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2254 return 1; /* return SUCCESS */
2256 return 0; /* return FAILURE */
2261 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2263 * If for some reason we were unable to start all cpus we cannot safely
2264 * use broadcast IPIs.
2269 #if defined(APIC_IO)
2270 if (smp_startup_mask == smp_active_mask) {
2271 all_but_self_ipi(XINVLTLB_OFFSET);
2273 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2274 APIC_DELMODE_FIXED);
2276 #endif /* APIC_IO */
2280 * When called the executing CPU will send an IPI to all other CPUs
2281 * requesting that they halt execution.
2283 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2285 * - Signals all CPUs in map to stop.
2286 * - Waits for each to stop.
2293 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2294 * from executing at same time.
2297 stop_cpus(u_int map)
2299 map &= smp_active_mask;
2301 /* send the Xcpustop IPI to all CPUs in map */
2302 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2304 while ((stopped_cpus & map) != map)
2312 * Called by a CPU to restart stopped CPUs.
2314 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2316 * - Signals all CPUs in map to restart.
2317 * - Waits for each to restart.
2325 restart_cpus(u_int map)
2327 /* signal other cpus to restart */
2328 started_cpus = map & smp_active_mask;
2330 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2337 * This is called once the mpboot code has gotten us properly relocated
2338 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2339 * and when it returns the scheduler will call the real cpu_idle() main
2340 * loop for the idlethread. Interrupts are disabled on entry and should
2341 * remain disabled at return.
2349 * Adjust smp_startup_mask to signal the BSP that we have started
2350 * up successfully. Note that we do not yet hold the BGL. The BSP
2351 * is waiting for our signal.
2353 * We can't set our bit in smp_active_mask yet because we are holding
2354 * interrupts physically disabled and remote cpus could deadlock
2355 * trying to send us an IPI.
2357 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2361 * Interlock for finalization. Wait until mp_finish is non-zero,
2362 * then get the MP lock.
2364 * Note: We are in a critical section.
2366 * Note: We have to synchronize td_mpcount to our desired MP state
2367 * before calling cpu_try_mplock().
2369 * Note: we are the idle thread, we can only spin.
2371 * Note: The load fence is memory volatile and prevents the compiler
2372 * from improperly caching mp_finish, and the cpu from improperly
2375 while (mp_finish == 0)
2377 ++curthread->td_mpcount;
2378 while (cpu_try_mplock() == 0)
2381 /* BSP may have changed PTD while we're waiting for the lock */
2384 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2388 /* Build our map of 'other' CPUs. */
2389 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2391 printf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2393 /* A quick check from sanity claus */
2394 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2395 if (mycpu->gd_cpuid != apic_id) {
2396 printf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2397 printf("SMP: apic_id = %d\n", apic_id);
2398 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2399 panic("cpuid mismatch! boom!!");
2402 /* Init local apic for irq's */
2405 /* Set memory range attributes for this CPU to match the BSP */
2406 mem_range_AP_init();
2409 * Once we go active we must process any IPIQ messages that may
2410 * have been queued, because no actual IPI will occur until we
2411 * set our bit in the smp_active_mask. If we don't the IPI
2412 * message interlock could be left set which would also prevent
2415 * The idle loop doesn't expect the BGL to be held and while
2416 * lwkt_switch() normally cleans things up this is a special case
2417 * because we returning almost directly into the idle loop.
2419 * The idle thread is never placed on the runq, make sure
2420 * nothing we've done put it there.
2422 KKASSERT(curthread->td_mpcount == 1);
2423 smp_active_mask |= 1 << mycpu->gd_cpuid;
2424 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2425 lwkt_process_ipiq();
2427 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2431 * Get SMP fully working before we start initializing devices.
2439 printf("Finish MP startup\n");
2441 while (smp_active_mask != smp_startup_mask)
2443 while (try_mplock() == 0)
2446 printf("Active CPU Mask: %08x\n", smp_active_mask);
2449 SYSINIT(finishsmp, SI_SUB_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2451 #if defined(APIC_IO) && defined(APIC_INTR_REORDER)
2453 * Maintain mapping from softintr vector to isr bit in local apic.
2456 set_lapic_isrloc(int intr, int vector)
2458 if (intr < 0 || intr > 32)
2459 panic("set_apic_isrloc: bad intr argument: %d",intr);
2460 if (vector < ICU_OFFSET || vector > 255)
2461 panic("set_apic_isrloc: bad vector argument: %d",vector);
2462 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2463 apic_isrbit_location[intr].bit = (1<<(vector & 31));
2468 cpu_send_ipiq(int dcpu)
2470 if ((1 << dcpu) & smp_active_mask)
2471 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2474 #if 0 /* single_apic_ipi_passive() not working yet */
2476 * Returns 0 on failure, 1 on success
2479 cpu_send_ipiq_passive(int dcpu)
2482 if ((1 << dcpu) & smp_active_mask) {
2483 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2484 APIC_DELMODE_FIXED);