3 * Copyright 2008 (c) Intel Corporation
4 * Jesse Barnes <jbarnes@virtuousgeek.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include <drm/i915_drm.h>
29 #include "intel_drv.h"
32 static bool i915_pipe_enabled(struct drm_device *dev, enum i915_pipe pipe)
34 struct drm_i915_private *dev_priv = dev->dev_private;
37 /* On IVB, 3rd pipe shares PLL with another one */
41 if (HAS_PCH_SPLIT(dev))
42 dpll_reg = _PCH_DPLL(pipe);
44 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
46 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
49 static void i915_save_palette(struct drm_device *dev, enum i915_pipe pipe)
51 struct drm_i915_private *dev_priv = dev->dev_private;
52 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
56 if (!i915_pipe_enabled(dev, pipe))
59 if (HAS_PCH_SPLIT(dev))
60 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
63 array = dev_priv->regfile.save_palette_a;
65 array = dev_priv->regfile.save_palette_b;
67 for (i = 0; i < 256; i++)
68 array[i] = I915_READ(reg + (i << 2));
71 static void i915_restore_palette(struct drm_device *dev, enum i915_pipe pipe)
73 struct drm_i915_private *dev_priv = dev->dev_private;
74 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
78 if (!i915_pipe_enabled(dev, pipe))
81 if (HAS_PCH_SPLIT(dev))
82 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
85 array = dev_priv->regfile.save_palette_a;
87 array = dev_priv->regfile.save_palette_b;
89 for (i = 0; i < 256; i++)
90 I915_WRITE(reg + (i << 2), array[i]);
93 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
95 struct drm_i915_private *dev_priv = dev->dev_private;
97 I915_WRITE8(index_port, reg);
98 return I915_READ8(data_port);
101 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
103 struct drm_i915_private *dev_priv = dev->dev_private;
106 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
107 return I915_READ8(VGA_AR_DATA_READ);
110 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
112 struct drm_i915_private *dev_priv = dev->dev_private;
115 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
116 I915_WRITE8(VGA_AR_DATA_WRITE, val);
119 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
121 struct drm_i915_private *dev_priv = dev->dev_private;
123 I915_WRITE8(index_port, reg);
124 I915_WRITE8(data_port, val);
127 static void i915_save_vga(struct drm_device *dev)
129 struct drm_i915_private *dev_priv = dev->dev_private;
131 u16 cr_index, cr_data, st01;
133 /* VGA color palette registers */
134 dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
137 dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);
138 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
139 cr_index = VGA_CR_INDEX_CGA;
140 cr_data = VGA_CR_DATA_CGA;
143 cr_index = VGA_CR_INDEX_MDA;
144 cr_data = VGA_CR_DATA_MDA;
148 /* CRT controller regs */
149 i915_write_indexed(dev, cr_index, cr_data, 0x11,
150 i915_read_indexed(dev, cr_index, cr_data, 0x11) &
152 for (i = 0; i <= 0x24; i++)
153 dev_priv->regfile.saveCR[i] =
154 i915_read_indexed(dev, cr_index, cr_data, i);
155 /* Make sure we don't turn off CR group 0 writes */
156 dev_priv->regfile.saveCR[0x11] &= ~0x80;
158 /* Attribute controller registers */
160 dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
161 for (i = 0; i <= 0x14; i++)
162 dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
164 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);
167 /* Graphics controller registers */
168 for (i = 0; i < 9; i++)
169 dev_priv->regfile.saveGR[i] =
170 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
172 dev_priv->regfile.saveGR[0x10] =
173 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
174 dev_priv->regfile.saveGR[0x11] =
175 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
176 dev_priv->regfile.saveGR[0x18] =
177 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
179 /* Sequencer registers */
180 for (i = 0; i < 8; i++)
181 dev_priv->regfile.saveSR[i] =
182 i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
185 static void i915_restore_vga(struct drm_device *dev)
187 struct drm_i915_private *dev_priv = dev->dev_private;
189 u16 cr_index, cr_data, st01;
192 I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
193 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
194 cr_index = VGA_CR_INDEX_CGA;
195 cr_data = VGA_CR_DATA_CGA;
198 cr_index = VGA_CR_INDEX_MDA;
199 cr_data = VGA_CR_DATA_MDA;
203 /* Sequencer registers, don't write SR07 */
204 for (i = 0; i < 7; i++)
205 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
206 dev_priv->regfile.saveSR[i]);
208 /* CRT controller regs */
209 /* Enable CR group 0 writes */
210 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
211 for (i = 0; i <= 0x24; i++)
212 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);
214 /* Graphics controller regs */
215 for (i = 0; i < 9; i++)
216 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
217 dev_priv->regfile.saveGR[i]);
219 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
220 dev_priv->regfile.saveGR[0x10]);
221 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
222 dev_priv->regfile.saveGR[0x11]);
223 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
224 dev_priv->regfile.saveGR[0x18]);
226 /* Attribute controller registers */
227 I915_READ8(st01); /* switch back to index mode */
228 for (i = 0; i <= 0x14; i++)
229 i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
230 I915_READ8(st01); /* switch back to index mode */
231 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20);
234 /* VGA color palette registers */
235 I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
238 static void i915_save_modeset_reg(struct drm_device *dev)
240 struct drm_i915_private *dev_priv = dev->dev_private;
243 if (drm_core_check_feature(dev, DRIVER_MODESET))
247 dev_priv->regfile.saveCURACNTR = I915_READ(_CURACNTR);
248 dev_priv->regfile.saveCURAPOS = I915_READ(_CURAPOS);
249 dev_priv->regfile.saveCURABASE = I915_READ(_CURABASE);
250 dev_priv->regfile.saveCURBCNTR = I915_READ(_CURBCNTR);
251 dev_priv->regfile.saveCURBPOS = I915_READ(_CURBPOS);
252 dev_priv->regfile.saveCURBBASE = I915_READ(_CURBBASE);
254 dev_priv->regfile.saveCURSIZE = I915_READ(CURSIZE);
256 if (HAS_PCH_SPLIT(dev)) {
257 dev_priv->regfile.savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
258 dev_priv->regfile.saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
261 /* Pipe & plane A info */
262 dev_priv->regfile.savePIPEACONF = I915_READ(_PIPEACONF);
263 dev_priv->regfile.savePIPEASRC = I915_READ(_PIPEASRC);
264 if (HAS_PCH_SPLIT(dev)) {
265 dev_priv->regfile.saveFPA0 = I915_READ(_PCH_FPA0);
266 dev_priv->regfile.saveFPA1 = I915_READ(_PCH_FPA1);
267 dev_priv->regfile.saveDPLL_A = I915_READ(_PCH_DPLL_A);
269 dev_priv->regfile.saveFPA0 = I915_READ(_FPA0);
270 dev_priv->regfile.saveFPA1 = I915_READ(_FPA1);
271 dev_priv->regfile.saveDPLL_A = I915_READ(_DPLL_A);
273 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
274 dev_priv->regfile.saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
275 dev_priv->regfile.saveHTOTAL_A = I915_READ(_HTOTAL_A);
276 dev_priv->regfile.saveHBLANK_A = I915_READ(_HBLANK_A);
277 dev_priv->regfile.saveHSYNC_A = I915_READ(_HSYNC_A);
278 dev_priv->regfile.saveVTOTAL_A = I915_READ(_VTOTAL_A);
279 dev_priv->regfile.saveVBLANK_A = I915_READ(_VBLANK_A);
280 dev_priv->regfile.saveVSYNC_A = I915_READ(_VSYNC_A);
281 if (!HAS_PCH_SPLIT(dev))
282 dev_priv->regfile.saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
284 if (HAS_PCH_SPLIT(dev)) {
285 dev_priv->regfile.savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
286 dev_priv->regfile.savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
287 dev_priv->regfile.savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
288 dev_priv->regfile.savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
290 dev_priv->regfile.saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
291 dev_priv->regfile.saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
293 dev_priv->regfile.savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
294 dev_priv->regfile.savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
295 dev_priv->regfile.savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
297 dev_priv->regfile.saveTRANSACONF = I915_READ(_TRANSACONF);
298 dev_priv->regfile.saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);
299 dev_priv->regfile.saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);
300 dev_priv->regfile.saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);
301 dev_priv->regfile.saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);
302 dev_priv->regfile.saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);
303 dev_priv->regfile.saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);
306 dev_priv->regfile.saveDSPACNTR = I915_READ(_DSPACNTR);
307 dev_priv->regfile.saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
308 dev_priv->regfile.saveDSPASIZE = I915_READ(_DSPASIZE);
309 dev_priv->regfile.saveDSPAPOS = I915_READ(_DSPAPOS);
310 dev_priv->regfile.saveDSPAADDR = I915_READ(_DSPAADDR);
311 if (INTEL_INFO(dev)->gen >= 4) {
312 dev_priv->regfile.saveDSPASURF = I915_READ(_DSPASURF);
313 dev_priv->regfile.saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
315 i915_save_palette(dev, PIPE_A);
316 dev_priv->regfile.savePIPEASTAT = I915_READ(_PIPEASTAT);
318 /* Pipe & plane B info */
319 dev_priv->regfile.savePIPEBCONF = I915_READ(_PIPEBCONF);
320 dev_priv->regfile.savePIPEBSRC = I915_READ(_PIPEBSRC);
321 if (HAS_PCH_SPLIT(dev)) {
322 dev_priv->regfile.saveFPB0 = I915_READ(_PCH_FPB0);
323 dev_priv->regfile.saveFPB1 = I915_READ(_PCH_FPB1);
324 dev_priv->regfile.saveDPLL_B = I915_READ(_PCH_DPLL_B);
326 dev_priv->regfile.saveFPB0 = I915_READ(_FPB0);
327 dev_priv->regfile.saveFPB1 = I915_READ(_FPB1);
328 dev_priv->regfile.saveDPLL_B = I915_READ(_DPLL_B);
330 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
331 dev_priv->regfile.saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
332 dev_priv->regfile.saveHTOTAL_B = I915_READ(_HTOTAL_B);
333 dev_priv->regfile.saveHBLANK_B = I915_READ(_HBLANK_B);
334 dev_priv->regfile.saveHSYNC_B = I915_READ(_HSYNC_B);
335 dev_priv->regfile.saveVTOTAL_B = I915_READ(_VTOTAL_B);
336 dev_priv->regfile.saveVBLANK_B = I915_READ(_VBLANK_B);
337 dev_priv->regfile.saveVSYNC_B = I915_READ(_VSYNC_B);
338 if (!HAS_PCH_SPLIT(dev))
339 dev_priv->regfile.saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
341 if (HAS_PCH_SPLIT(dev)) {
342 dev_priv->regfile.savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
343 dev_priv->regfile.savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
344 dev_priv->regfile.savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
345 dev_priv->regfile.savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
347 dev_priv->regfile.saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
348 dev_priv->regfile.saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
350 dev_priv->regfile.savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
351 dev_priv->regfile.savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
352 dev_priv->regfile.savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
354 dev_priv->regfile.saveTRANSBCONF = I915_READ(_TRANSBCONF);
355 dev_priv->regfile.saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);
356 dev_priv->regfile.saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);
357 dev_priv->regfile.saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);
358 dev_priv->regfile.saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B);
359 dev_priv->regfile.saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B);
360 dev_priv->regfile.saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B);
363 dev_priv->regfile.saveDSPBCNTR = I915_READ(_DSPBCNTR);
364 dev_priv->regfile.saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
365 dev_priv->regfile.saveDSPBSIZE = I915_READ(_DSPBSIZE);
366 dev_priv->regfile.saveDSPBPOS = I915_READ(_DSPBPOS);
367 dev_priv->regfile.saveDSPBADDR = I915_READ(_DSPBADDR);
368 if (INTEL_INFO(dev)->gen >= 4) {
369 dev_priv->regfile.saveDSPBSURF = I915_READ(_DSPBSURF);
370 dev_priv->regfile.saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
372 i915_save_palette(dev, PIPE_B);
373 dev_priv->regfile.savePIPEBSTAT = I915_READ(_PIPEBSTAT);
376 switch (INTEL_INFO(dev)->gen) {
379 for (i = 0; i < 16; i++)
380 dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
384 for (i = 0; i < 16; i++)
385 dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
388 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
389 for (i = 0; i < 8; i++)
390 dev_priv->regfile.saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
392 for (i = 0; i < 8; i++)
393 dev_priv->regfile.saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
398 if (HAS_PCH_SPLIT(dev))
399 dev_priv->regfile.saveADPA = I915_READ(PCH_ADPA);
401 dev_priv->regfile.saveADPA = I915_READ(ADPA);
406 static void i915_restore_modeset_reg(struct drm_device *dev)
408 struct drm_i915_private *dev_priv = dev->dev_private;
409 int dpll_a_reg, fpa0_reg, fpa1_reg;
410 int dpll_b_reg, fpb0_reg, fpb1_reg;
413 if (drm_core_check_feature(dev, DRIVER_MODESET))
417 switch (INTEL_INFO(dev)->gen) {
420 for (i = 0; i < 16; i++)
421 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
425 for (i = 0; i < 16; i++)
426 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
430 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
431 for (i = 0; i < 8; i++)
432 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->regfile.saveFENCE[i+8]);
433 for (i = 0; i < 8; i++)
434 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->regfile.saveFENCE[i]);
439 if (HAS_PCH_SPLIT(dev)) {
440 dpll_a_reg = _PCH_DPLL_A;
441 dpll_b_reg = _PCH_DPLL_B;
442 fpa0_reg = _PCH_FPA0;
443 fpb0_reg = _PCH_FPB0;
444 fpa1_reg = _PCH_FPA1;
445 fpb1_reg = _PCH_FPB1;
447 dpll_a_reg = _DPLL_A;
448 dpll_b_reg = _DPLL_B;
455 if (HAS_PCH_SPLIT(dev)) {
456 I915_WRITE(PCH_DREF_CONTROL, dev_priv->regfile.savePCH_DREF_CONTROL);
457 I915_WRITE(DISP_ARB_CTL, dev_priv->regfile.saveDISP_ARB_CTL);
460 /* Pipe & plane A info */
461 /* Prime the clock */
462 if (dev_priv->regfile.saveDPLL_A & DPLL_VCO_ENABLE) {
463 I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A &
465 POSTING_READ(dpll_a_reg);
468 I915_WRITE(fpa0_reg, dev_priv->regfile.saveFPA0);
469 I915_WRITE(fpa1_reg, dev_priv->regfile.saveFPA1);
470 /* Actually enable it */
471 I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A);
472 POSTING_READ(dpll_a_reg);
474 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
475 I915_WRITE(_DPLL_A_MD, dev_priv->regfile.saveDPLL_A_MD);
476 POSTING_READ(_DPLL_A_MD);
481 I915_WRITE(_HTOTAL_A, dev_priv->regfile.saveHTOTAL_A);
482 I915_WRITE(_HBLANK_A, dev_priv->regfile.saveHBLANK_A);
483 I915_WRITE(_HSYNC_A, dev_priv->regfile.saveHSYNC_A);
484 I915_WRITE(_VTOTAL_A, dev_priv->regfile.saveVTOTAL_A);
485 I915_WRITE(_VBLANK_A, dev_priv->regfile.saveVBLANK_A);
486 I915_WRITE(_VSYNC_A, dev_priv->regfile.saveVSYNC_A);
487 if (!HAS_PCH_SPLIT(dev))
488 I915_WRITE(_BCLRPAT_A, dev_priv->regfile.saveBCLRPAT_A);
490 if (HAS_PCH_SPLIT(dev)) {
491 I915_WRITE(_PIPEA_DATA_M1, dev_priv->regfile.savePIPEA_DATA_M1);
492 I915_WRITE(_PIPEA_DATA_N1, dev_priv->regfile.savePIPEA_DATA_N1);
493 I915_WRITE(_PIPEA_LINK_M1, dev_priv->regfile.savePIPEA_LINK_M1);
494 I915_WRITE(_PIPEA_LINK_N1, dev_priv->regfile.savePIPEA_LINK_N1);
496 I915_WRITE(_FDI_RXA_CTL, dev_priv->regfile.saveFDI_RXA_CTL);
497 I915_WRITE(_FDI_TXA_CTL, dev_priv->regfile.saveFDI_TXA_CTL);
499 I915_WRITE(_PFA_CTL_1, dev_priv->regfile.savePFA_CTL_1);
500 I915_WRITE(_PFA_WIN_SZ, dev_priv->regfile.savePFA_WIN_SZ);
501 I915_WRITE(_PFA_WIN_POS, dev_priv->regfile.savePFA_WIN_POS);
503 I915_WRITE(_TRANSACONF, dev_priv->regfile.saveTRANSACONF);
504 I915_WRITE(_TRANS_HTOTAL_A, dev_priv->regfile.saveTRANS_HTOTAL_A);
505 I915_WRITE(_TRANS_HBLANK_A, dev_priv->regfile.saveTRANS_HBLANK_A);
506 I915_WRITE(_TRANS_HSYNC_A, dev_priv->regfile.saveTRANS_HSYNC_A);
507 I915_WRITE(_TRANS_VTOTAL_A, dev_priv->regfile.saveTRANS_VTOTAL_A);
508 I915_WRITE(_TRANS_VBLANK_A, dev_priv->regfile.saveTRANS_VBLANK_A);
509 I915_WRITE(_TRANS_VSYNC_A, dev_priv->regfile.saveTRANS_VSYNC_A);
512 /* Restore plane info */
513 I915_WRITE(_DSPASIZE, dev_priv->regfile.saveDSPASIZE);
514 I915_WRITE(_DSPAPOS, dev_priv->regfile.saveDSPAPOS);
515 I915_WRITE(_PIPEASRC, dev_priv->regfile.savePIPEASRC);
516 I915_WRITE(_DSPAADDR, dev_priv->regfile.saveDSPAADDR);
517 I915_WRITE(_DSPASTRIDE, dev_priv->regfile.saveDSPASTRIDE);
518 if (INTEL_INFO(dev)->gen >= 4) {
519 I915_WRITE(_DSPASURF, dev_priv->regfile.saveDSPASURF);
520 I915_WRITE(_DSPATILEOFF, dev_priv->regfile.saveDSPATILEOFF);
523 I915_WRITE(_PIPEACONF, dev_priv->regfile.savePIPEACONF);
525 i915_restore_palette(dev, PIPE_A);
526 /* Enable the plane */
527 I915_WRITE(_DSPACNTR, dev_priv->regfile.saveDSPACNTR);
528 I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
530 /* Pipe & plane B info */
531 if (dev_priv->regfile.saveDPLL_B & DPLL_VCO_ENABLE) {
532 I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B &
534 POSTING_READ(dpll_b_reg);
537 I915_WRITE(fpb0_reg, dev_priv->regfile.saveFPB0);
538 I915_WRITE(fpb1_reg, dev_priv->regfile.saveFPB1);
539 /* Actually enable it */
540 I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B);
541 POSTING_READ(dpll_b_reg);
543 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
544 I915_WRITE(_DPLL_B_MD, dev_priv->regfile.saveDPLL_B_MD);
545 POSTING_READ(_DPLL_B_MD);
550 I915_WRITE(_HTOTAL_B, dev_priv->regfile.saveHTOTAL_B);
551 I915_WRITE(_HBLANK_B, dev_priv->regfile.saveHBLANK_B);
552 I915_WRITE(_HSYNC_B, dev_priv->regfile.saveHSYNC_B);
553 I915_WRITE(_VTOTAL_B, dev_priv->regfile.saveVTOTAL_B);
554 I915_WRITE(_VBLANK_B, dev_priv->regfile.saveVBLANK_B);
555 I915_WRITE(_VSYNC_B, dev_priv->regfile.saveVSYNC_B);
556 if (!HAS_PCH_SPLIT(dev))
557 I915_WRITE(_BCLRPAT_B, dev_priv->regfile.saveBCLRPAT_B);
559 if (HAS_PCH_SPLIT(dev)) {
560 I915_WRITE(_PIPEB_DATA_M1, dev_priv->regfile.savePIPEB_DATA_M1);
561 I915_WRITE(_PIPEB_DATA_N1, dev_priv->regfile.savePIPEB_DATA_N1);
562 I915_WRITE(_PIPEB_LINK_M1, dev_priv->regfile.savePIPEB_LINK_M1);
563 I915_WRITE(_PIPEB_LINK_N1, dev_priv->regfile.savePIPEB_LINK_N1);
565 I915_WRITE(_FDI_RXB_CTL, dev_priv->regfile.saveFDI_RXB_CTL);
566 I915_WRITE(_FDI_TXB_CTL, dev_priv->regfile.saveFDI_TXB_CTL);
568 I915_WRITE(_PFB_CTL_1, dev_priv->regfile.savePFB_CTL_1);
569 I915_WRITE(_PFB_WIN_SZ, dev_priv->regfile.savePFB_WIN_SZ);
570 I915_WRITE(_PFB_WIN_POS, dev_priv->regfile.savePFB_WIN_POS);
572 I915_WRITE(_TRANSBCONF, dev_priv->regfile.saveTRANSBCONF);
573 I915_WRITE(_TRANS_HTOTAL_B, dev_priv->regfile.saveTRANS_HTOTAL_B);
574 I915_WRITE(_TRANS_HBLANK_B, dev_priv->regfile.saveTRANS_HBLANK_B);
575 I915_WRITE(_TRANS_HSYNC_B, dev_priv->regfile.saveTRANS_HSYNC_B);
576 I915_WRITE(_TRANS_VTOTAL_B, dev_priv->regfile.saveTRANS_VTOTAL_B);
577 I915_WRITE(_TRANS_VBLANK_B, dev_priv->regfile.saveTRANS_VBLANK_B);
578 I915_WRITE(_TRANS_VSYNC_B, dev_priv->regfile.saveTRANS_VSYNC_B);
581 /* Restore plane info */
582 I915_WRITE(_DSPBSIZE, dev_priv->regfile.saveDSPBSIZE);
583 I915_WRITE(_DSPBPOS, dev_priv->regfile.saveDSPBPOS);
584 I915_WRITE(_PIPEBSRC, dev_priv->regfile.savePIPEBSRC);
585 I915_WRITE(_DSPBADDR, dev_priv->regfile.saveDSPBADDR);
586 I915_WRITE(_DSPBSTRIDE, dev_priv->regfile.saveDSPBSTRIDE);
587 if (INTEL_INFO(dev)->gen >= 4) {
588 I915_WRITE(_DSPBSURF, dev_priv->regfile.saveDSPBSURF);
589 I915_WRITE(_DSPBTILEOFF, dev_priv->regfile.saveDSPBTILEOFF);
592 I915_WRITE(_PIPEBCONF, dev_priv->regfile.savePIPEBCONF);
594 i915_restore_palette(dev, PIPE_B);
595 /* Enable the plane */
596 I915_WRITE(_DSPBCNTR, dev_priv->regfile.saveDSPBCNTR);
597 I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
600 I915_WRITE(_CURAPOS, dev_priv->regfile.saveCURAPOS);
601 I915_WRITE(_CURACNTR, dev_priv->regfile.saveCURACNTR);
602 I915_WRITE(_CURABASE, dev_priv->regfile.saveCURABASE);
603 I915_WRITE(_CURBPOS, dev_priv->regfile.saveCURBPOS);
604 I915_WRITE(_CURBCNTR, dev_priv->regfile.saveCURBCNTR);
605 I915_WRITE(_CURBBASE, dev_priv->regfile.saveCURBBASE);
607 I915_WRITE(CURSIZE, dev_priv->regfile.saveCURSIZE);
610 if (HAS_PCH_SPLIT(dev))
611 I915_WRITE(PCH_ADPA, dev_priv->regfile.saveADPA);
613 I915_WRITE(ADPA, dev_priv->regfile.saveADPA);
618 static void i915_save_display(struct drm_device *dev)
620 struct drm_i915_private *dev_priv = dev->dev_private;
622 /* Display arbitration control */
623 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
625 /* This is only meaningful in non-KMS mode */
626 /* Don't regfile.save them in KMS mode */
627 i915_save_modeset_reg(dev);
630 if (HAS_PCH_SPLIT(dev)) {
631 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
632 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
633 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
634 dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
635 dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
636 dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
638 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
639 dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
640 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
641 dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
642 if (INTEL_INFO(dev)->gen >= 4)
643 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
644 if (IS_MOBILE(dev) && !IS_I830(dev))
645 dev_priv->regfile.saveLVDS = I915_READ(LVDS);
648 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
649 dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
651 if (HAS_PCH_SPLIT(dev)) {
652 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
653 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
654 dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
656 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
657 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
658 dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
661 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
662 /* Display Port state */
663 if (SUPPORTS_INTEGRATED_DP(dev)) {
664 dev_priv->regfile.saveDP_B = I915_READ(DP_B);
665 dev_priv->regfile.saveDP_C = I915_READ(DP_C);
666 dev_priv->regfile.saveDP_D = I915_READ(DP_D);
667 dev_priv->regfile.savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M);
668 dev_priv->regfile.savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M);
669 dev_priv->regfile.savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N);
670 dev_priv->regfile.savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N);
671 dev_priv->regfile.savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M);
672 dev_priv->regfile.savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M);
673 dev_priv->regfile.savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N);
674 dev_priv->regfile.savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N);
676 /* FIXME: regfile.save TV & SDVO state */
679 /* Only regfile.save FBC state on the platform that supports FBC */
680 if (I915_HAS_FBC(dev)) {
681 if (HAS_PCH_SPLIT(dev)) {
682 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
683 } else if (IS_GM45(dev)) {
684 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
686 dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
687 dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
688 dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
689 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
694 dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
695 dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
696 dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
697 if (HAS_PCH_SPLIT(dev))
698 dev_priv->regfile.saveVGACNTRL = I915_READ(CPU_VGACNTRL);
700 dev_priv->regfile.saveVGACNTRL = I915_READ(VGACNTRL);
705 static void i915_restore_display(struct drm_device *dev)
707 struct drm_i915_private *dev_priv = dev->dev_private;
709 /* Display arbitration */
710 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
712 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
713 /* Display port ratios (must be done before clock is set) */
714 if (SUPPORTS_INTEGRATED_DP(dev)) {
715 I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->regfile.savePIPEA_GMCH_DATA_M);
716 I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->regfile.savePIPEB_GMCH_DATA_M);
717 I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->regfile.savePIPEA_GMCH_DATA_N);
718 I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->regfile.savePIPEB_GMCH_DATA_N);
719 I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->regfile.savePIPEA_DP_LINK_M);
720 I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->regfile.savePIPEB_DP_LINK_M);
721 I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->regfile.savePIPEA_DP_LINK_N);
722 I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->regfile.savePIPEB_DP_LINK_N);
726 /* This is only meaningful in non-KMS mode */
727 /* Don't restore them in KMS mode */
728 i915_restore_modeset_reg(dev);
731 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
732 I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
734 if (HAS_PCH_SPLIT(dev)) {
735 I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS);
736 } else if (IS_MOBILE(dev) && !IS_I830(dev))
737 I915_WRITE(LVDS, dev_priv->regfile.saveLVDS);
739 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
740 I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
742 if (HAS_PCH_SPLIT(dev)) {
743 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
744 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
745 /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
746 * otherwise we get blank eDP screen after S3 on some machines
748 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
749 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
750 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
751 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
752 I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
753 I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
754 I915_WRITE(RSTDBYCTL,
755 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
757 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
758 I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
759 I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
760 I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
761 I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
762 I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
763 I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
766 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
767 /* Display Port state */
768 if (SUPPORTS_INTEGRATED_DP(dev)) {
769 I915_WRITE(DP_B, dev_priv->regfile.saveDP_B);
770 I915_WRITE(DP_C, dev_priv->regfile.saveDP_C);
771 I915_WRITE(DP_D, dev_priv->regfile.saveDP_D);
773 /* FIXME: restore TV & SDVO state */
776 /* only restore FBC info on the platform that supports FBC*/
777 intel_disable_fbc(dev);
778 if (I915_HAS_FBC(dev)) {
779 if (HAS_PCH_SPLIT(dev)) {
780 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
781 } else if (IS_GM45(dev)) {
782 I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
784 I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE);
785 I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE);
786 I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2);
787 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
791 if (HAS_PCH_SPLIT(dev))
792 I915_WRITE(CPU_VGACNTRL, dev_priv->regfile.saveVGACNTRL);
794 I915_WRITE(VGACNTRL, dev_priv->regfile.saveVGACNTRL);
796 I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
797 I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
798 I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
799 POSTING_READ(VGA_PD);
802 i915_restore_vga(dev);
805 int i915_save_state(struct drm_device *dev)
807 struct drm_i915_private *dev_priv = dev->dev_private;
810 dev_priv->regfile.saveLBB = pci_read_config(dev->dev, LBB, 1);
812 i915_save_display(dev);
814 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
815 /* Interrupt state */
816 if (HAS_PCH_SPLIT(dev)) {
817 dev_priv->regfile.saveDEIER = I915_READ(DEIER);
818 dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
819 dev_priv->regfile.saveGTIER = I915_READ(GTIER);
820 dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
821 dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
822 dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
823 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
824 I915_READ(RSTDBYCTL);
825 dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
827 dev_priv->regfile.saveIER = I915_READ(IER);
828 dev_priv->regfile.saveIMR = I915_READ(IMR);
832 intel_disable_gt_powersave(dev);
834 /* Cache mode state */
835 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
837 /* Memory Arbitration state */
838 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
841 for (i = 0; i < 16; i++) {
842 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
843 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
845 for (i = 0; i < 3; i++)
846 dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
851 int i915_restore_state(struct drm_device *dev)
853 struct drm_i915_private *dev_priv = dev->dev_private;
856 pci_write_config(dev->dev, LBB, dev_priv->regfile.saveLBB, 1);
858 i915_restore_display(dev);
860 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
861 /* Interrupt state */
862 if (HAS_PCH_SPLIT(dev)) {
863 I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
864 I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
865 I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
866 I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
867 I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
868 I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
869 I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
871 I915_WRITE(IER, dev_priv->regfile.saveIER);
872 I915_WRITE(IMR, dev_priv->regfile.saveIMR);
876 /* Cache mode state */
877 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000);
879 /* Memory arbitration state */
880 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
882 for (i = 0; i < 16; i++) {
883 I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
884 I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
886 for (i = 0; i < 3; i++)
887 I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
889 intel_iic_reset(dev);