1 ;; Predicate definitions for IA-32 and x86-64.
2 ;; Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; Return true if OP is either a i387 or SSE fp register.
22 (define_predicate "any_fp_register_operand"
23 (and (match_code "reg")
24 (match_test "ANY_FP_REGNO_P (REGNO (op))")))
26 ;; Return true if OP is an i387 fp register.
27 (define_predicate "fp_register_operand"
28 (and (match_code "reg")
29 (match_test "FP_REGNO_P (REGNO (op))")))
31 ;; Return true if OP is a non-fp register_operand.
32 (define_predicate "register_and_not_any_fp_reg_operand"
33 (and (match_code "reg")
34 (not (match_test "ANY_FP_REGNO_P (REGNO (op))"))))
36 ;; Return true if OP is a register operand other than an i387 fp register.
37 (define_predicate "register_and_not_fp_reg_operand"
38 (and (match_code "reg")
39 (not (match_test "FP_REGNO_P (REGNO (op))"))))
41 ;; True if the operand is an MMX register.
42 (define_predicate "mmx_reg_operand"
43 (and (match_code "reg")
44 (match_test "MMX_REGNO_P (REGNO (op))")))
46 ;; True if the operand is an SSE register.
47 (define_predicate "sse_reg_operand"
48 (and (match_code "reg")
49 (match_test "SSE_REGNO_P (REGNO (op))")))
51 ;; True if the operand is a Q_REGS class register.
52 (define_predicate "q_regs_operand"
53 (match_operand 0 "register_operand")
55 if (GET_CODE (op) == SUBREG)
57 return ANY_QI_REG_P (op);
60 ;; Match an SI or HImode register for a zero_extract.
61 (define_special_predicate "ext_register_operand"
62 (match_operand 0 "register_operand")
64 if ((!TARGET_64BIT || GET_MODE (op) != DImode)
65 && GET_MODE (op) != SImode && GET_MODE (op) != HImode)
67 if (GET_CODE (op) == SUBREG)
70 /* Be careful to accept only registers having upper parts. */
72 && (REGNO (op) > LAST_VIRTUAL_REGISTER || REGNO (op) <= BX_REG));
75 ;; Return true if op is the AX register.
76 (define_predicate "ax_reg_operand"
77 (and (match_code "reg")
78 (match_test "REGNO (op) == AX_REG")))
80 ;; Return true if op is the flags register.
81 (define_predicate "flags_reg_operand"
82 (and (match_code "reg")
83 (match_test "REGNO (op) == FLAGS_REG")))
85 ;; Return true if op is one of QImode registers: %[abcd][hl].
86 (define_predicate "QIreg_operand"
87 (match_test "QI_REG_P (op)"))
89 ;; Return true if op is a QImode register operand other than
91 (define_predicate "ext_QIreg_operand"
92 (and (match_code "reg")
93 (match_test "TARGET_64BIT")
94 (match_test "REGNO (op) > BX_REG")))
96 ;; Return true if op is not xmm0 register.
97 (define_predicate "reg_not_xmm0_operand"
98 (match_operand 0 "register_operand")
100 if (GET_CODE (op) == SUBREG)
101 op = SUBREG_REG (op);
103 return !REG_P (op) || REGNO (op) != FIRST_SSE_REG;
106 ;; As above, but also allow memory operands.
107 (define_predicate "nonimm_not_xmm0_operand"
108 (ior (match_operand 0 "memory_operand")
109 (match_operand 0 "reg_not_xmm0_operand")))
111 ;; Return true if op is not xmm0 register, but only for non-AVX targets.
112 (define_predicate "reg_not_xmm0_operand_maybe_avx"
113 (if_then_else (match_test "TARGET_AVX")
114 (match_operand 0 "register_operand")
115 (match_operand 0 "reg_not_xmm0_operand")))
117 ;; As above, but also allow memory operands.
118 (define_predicate "nonimm_not_xmm0_operand_maybe_avx"
119 (if_then_else (match_test "TARGET_AVX")
120 (match_operand 0 "nonimmediate_operand")
121 (match_operand 0 "nonimm_not_xmm0_operand")))
123 ;; Return true if VALUE can be stored in a sign extended immediate field.
124 (define_predicate "x86_64_immediate_operand"
125 (match_code "const_int,symbol_ref,label_ref,const")
128 return immediate_operand (op, mode);
130 switch (GET_CODE (op))
133 /* CONST_DOUBLES never match, since HOST_BITS_PER_WIDE_INT is known
134 to be at least 32 and this all acceptable constants are
135 represented as CONST_INT. */
136 if (HOST_BITS_PER_WIDE_INT == 32)
140 HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (op), DImode);
141 return trunc_int_for_mode (val, SImode) == val;
146 /* For certain code models, the symbolic references are known to fit.
147 in CM_SMALL_PIC model we know it fits if it is local to the shared
148 library. Don't count TLS SYMBOL_REFs here, since they should fit
149 only if inside of UNSPEC handled below. */
150 /* TLS symbols are not constant. */
151 if (SYMBOL_REF_TLS_MODEL (op))
153 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
154 || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
157 /* For certain code models, the code is near as well. */
158 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
159 || ix86_cmodel == CM_KERNEL);
162 /* We also may accept the offsetted memory references in certain
164 if (GET_CODE (XEXP (op, 0)) == UNSPEC)
165 switch (XINT (XEXP (op, 0), 1))
167 case UNSPEC_GOTPCREL:
169 case UNSPEC_GOTNTPOFF:
176 if (GET_CODE (XEXP (op, 0)) == PLUS)
178 rtx op1 = XEXP (XEXP (op, 0), 0);
179 rtx op2 = XEXP (XEXP (op, 0), 1);
180 HOST_WIDE_INT offset;
182 if (ix86_cmodel == CM_LARGE)
184 if (!CONST_INT_P (op2))
186 offset = trunc_int_for_mode (INTVAL (op2), DImode);
187 switch (GET_CODE (op1))
190 /* TLS symbols are not constant. */
191 if (SYMBOL_REF_TLS_MODEL (op1))
193 /* For CM_SMALL assume that latest object is 16MB before
194 end of 31bits boundary. We may also accept pretty
195 large negative constants knowing that all objects are
196 in the positive half of address space. */
197 if ((ix86_cmodel == CM_SMALL
198 || (ix86_cmodel == CM_MEDIUM
199 && !SYMBOL_REF_FAR_ADDR_P (op1)))
200 && offset < 16*1024*1024
201 && trunc_int_for_mode (offset, SImode) == offset)
203 /* For CM_KERNEL we know that all object resist in the
204 negative half of 32bits address space. We may not
205 accept negative offsets, since they may be just off
206 and we may accept pretty large positive ones. */
207 if (ix86_cmodel == CM_KERNEL
209 && trunc_int_for_mode (offset, SImode) == offset)
214 /* These conditions are similar to SYMBOL_REF ones, just the
215 constraints for code models differ. */
216 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
217 && offset < 16*1024*1024
218 && trunc_int_for_mode (offset, SImode) == offset)
220 if (ix86_cmodel == CM_KERNEL
222 && trunc_int_for_mode (offset, SImode) == offset)
227 switch (XINT (op1, 1))
232 && trunc_int_for_mode (offset, SImode) == offset)
250 ;; Return true if VALUE can be stored in the zero extended immediate field.
251 (define_predicate "x86_64_zext_immediate_operand"
252 (match_code "const_double,const_int,symbol_ref,label_ref,const")
254 switch (GET_CODE (op))
257 if (HOST_BITS_PER_WIDE_INT == 32)
258 return (GET_MODE (op) == VOIDmode && !CONST_DOUBLE_HIGH (op));
263 if (HOST_BITS_PER_WIDE_INT == 32)
264 return INTVAL (op) >= 0;
266 return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff);
269 /* For certain code models, the symbolic references are known to fit. */
270 /* TLS symbols are not constant. */
271 if (SYMBOL_REF_TLS_MODEL (op))
273 return (ix86_cmodel == CM_SMALL
274 || (ix86_cmodel == CM_MEDIUM
275 && !SYMBOL_REF_FAR_ADDR_P (op)));
278 /* For certain code models, the code is near as well. */
279 return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
282 /* We also may accept the offsetted memory references in certain
284 if (GET_CODE (XEXP (op, 0)) == PLUS)
286 rtx op1 = XEXP (XEXP (op, 0), 0);
287 rtx op2 = XEXP (XEXP (op, 0), 1);
289 if (ix86_cmodel == CM_LARGE)
291 switch (GET_CODE (op1))
294 /* TLS symbols are not constant. */
295 if (SYMBOL_REF_TLS_MODEL (op1))
297 /* For small code model we may accept pretty large positive
298 offsets, since one bit is available for free. Negative
299 offsets are limited by the size of NULL pointer area
300 specified by the ABI. */
301 if ((ix86_cmodel == CM_SMALL
302 || (ix86_cmodel == CM_MEDIUM
303 && !SYMBOL_REF_FAR_ADDR_P (op1)))
305 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
306 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
308 /* ??? For the kernel, we may accept adjustment of
309 -0x10000000, since we know that it will just convert
310 negative address space to positive, but perhaps this
311 is not worthwhile. */
315 /* These conditions are similar to SYMBOL_REF ones, just the
316 constraints for code models differ. */
317 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
319 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
320 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
336 ;; Return true if OP is general operand representable on x86_64.
337 (define_predicate "x86_64_general_operand"
338 (if_then_else (match_test "TARGET_64BIT")
339 (ior (match_operand 0 "nonimmediate_operand")
340 (match_operand 0 "x86_64_immediate_operand"))
341 (match_operand 0 "general_operand")))
343 ;; Return true if OP is general operand representable on x86_64
344 ;; as either sign extended or zero extended constant.
345 (define_predicate "x86_64_szext_general_operand"
346 (if_then_else (match_test "TARGET_64BIT")
347 (ior (match_operand 0 "nonimmediate_operand")
348 (match_operand 0 "x86_64_immediate_operand")
349 (match_operand 0 "x86_64_zext_immediate_operand"))
350 (match_operand 0 "general_operand")))
352 ;; Return true if OP is nonmemory operand representable on x86_64.
353 (define_predicate "x86_64_nonmemory_operand"
354 (if_then_else (match_test "TARGET_64BIT")
355 (ior (match_operand 0 "register_operand")
356 (match_operand 0 "x86_64_immediate_operand"))
357 (match_operand 0 "nonmemory_operand")))
359 ;; Return true if OP is nonmemory operand representable on x86_64.
360 (define_predicate "x86_64_szext_nonmemory_operand"
361 (if_then_else (match_test "TARGET_64BIT")
362 (ior (match_operand 0 "register_operand")
363 (match_operand 0 "x86_64_immediate_operand")
364 (match_operand 0 "x86_64_zext_immediate_operand"))
365 (match_operand 0 "nonmemory_operand")))
367 ;; Return true when operand is PIC expression that can be computed by lea
369 (define_predicate "pic_32bit_operand"
370 (match_code "const,symbol_ref,label_ref")
375 /* Rule out relocations that translate into 64bit constants. */
376 if (TARGET_64BIT && GET_CODE (op) == CONST)
379 if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
381 if (GET_CODE (op) == UNSPEC
382 && (XINT (op, 1) == UNSPEC_GOTOFF
383 || XINT (op, 1) == UNSPEC_GOT))
387 return symbolic_operand (op, mode);
390 ;; Return true if OP is nonmemory operand acceptable by movabs patterns.
391 (define_predicate "x86_64_movabs_operand"
392 (and (match_operand 0 "nonmemory_operand")
393 (not (match_operand 0 "pic_32bit_operand"))))
395 ;; Return true if OP is either a symbol reference or a sum of a symbol
396 ;; reference and a constant.
397 (define_predicate "symbolic_operand"
398 (match_code "symbol_ref,label_ref,const")
400 switch (GET_CODE (op))
408 if (GET_CODE (op) == SYMBOL_REF
409 || GET_CODE (op) == LABEL_REF
410 || (GET_CODE (op) == UNSPEC
411 && (XINT (op, 1) == UNSPEC_GOT
412 || XINT (op, 1) == UNSPEC_GOTOFF
413 || XINT (op, 1) == UNSPEC_PCREL
414 || XINT (op, 1) == UNSPEC_GOTPCREL)))
416 if (GET_CODE (op) != PLUS
417 || !CONST_INT_P (XEXP (op, 1)))
421 if (GET_CODE (op) == SYMBOL_REF
422 || GET_CODE (op) == LABEL_REF)
424 /* Only @GOTOFF gets offsets. */
425 if (GET_CODE (op) != UNSPEC
426 || XINT (op, 1) != UNSPEC_GOTOFF)
429 op = XVECEXP (op, 0, 0);
430 if (GET_CODE (op) == SYMBOL_REF
431 || GET_CODE (op) == LABEL_REF)
440 ;; Return true if OP is a symbolic operand that resolves locally.
441 (define_predicate "local_symbolic_operand"
442 (match_code "const,label_ref,symbol_ref")
444 if (GET_CODE (op) == CONST
445 && GET_CODE (XEXP (op, 0)) == PLUS
446 && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
447 op = XEXP (XEXP (op, 0), 0);
449 if (GET_CODE (op) == LABEL_REF)
452 if (GET_CODE (op) != SYMBOL_REF)
455 if (SYMBOL_REF_TLS_MODEL (op))
458 if (SYMBOL_REF_LOCAL_P (op))
461 /* There is, however, a not insubstantial body of code in the rest of
462 the compiler that assumes it can just stick the results of
463 ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
464 /* ??? This is a hack. Should update the body of the compiler to
465 always create a DECL an invoke targetm.encode_section_info. */
466 if (strncmp (XSTR (op, 0), internal_label_prefix,
467 internal_label_prefix_len) == 0)
473 ;; Test for a legitimate @GOTOFF operand.
475 ;; VxWorks does not impose a fixed gap between segments; the run-time
476 ;; gap can be different from the object-file gap. We therefore can't
477 ;; use @GOTOFF unless we are absolutely sure that the symbol is in the
478 ;; same segment as the GOT. Unfortunately, the flexibility of linker
479 ;; scripts means that we can't be sure of that in general, so assume
480 ;; that @GOTOFF is never valid on VxWorks.
481 (define_predicate "gotoff_operand"
482 (and (not (match_test "TARGET_VXWORKS_RTP"))
483 (match_operand 0 "local_symbolic_operand")))
485 ;; Test for various thread-local symbols.
486 (define_predicate "tls_symbolic_operand"
487 (and (match_code "symbol_ref")
488 (match_test "SYMBOL_REF_TLS_MODEL (op)")))
490 (define_predicate "tls_modbase_operand"
491 (and (match_code "symbol_ref")
492 (match_test "op == ix86_tls_module_base ()")))
494 ;; Test for a pc-relative call operand
495 (define_predicate "constant_call_address_operand"
496 (match_code "symbol_ref")
498 if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC)
500 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
505 ;; P6 processors will jump to the address after the decrement when %esp
506 ;; is used as a call operand, so they will execute return address as a code.
507 ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
509 (define_predicate "call_register_no_elim_operand"
510 (match_operand 0 "register_operand")
512 if (GET_CODE (op) == SUBREG)
513 op = SUBREG_REG (op);
515 if (!TARGET_64BIT && op == stack_pointer_rtx)
518 return register_no_elim_operand (op, mode);
521 ;; True for any non-virtual or eliminable register. Used in places where
522 ;; instantiation of such a register may cause the pattern to not be recognized.
523 (define_predicate "register_no_elim_operand"
524 (match_operand 0 "register_operand")
526 if (GET_CODE (op) == SUBREG)
527 op = SUBREG_REG (op);
528 return !(op == arg_pointer_rtx
529 || op == frame_pointer_rtx
530 || IN_RANGE (REGNO (op),
531 FIRST_PSEUDO_REGISTER, LAST_VIRTUAL_REGISTER));
534 ;; Similarly, but include the stack pointer. This is used to prevent esp
535 ;; from being used as an index reg.
536 (define_predicate "index_register_operand"
537 (match_operand 0 "register_operand")
539 if (GET_CODE (op) == SUBREG)
540 op = SUBREG_REG (op);
541 if (reload_in_progress || reload_completed)
542 return REG_OK_FOR_INDEX_STRICT_P (op);
544 return REG_OK_FOR_INDEX_NONSTRICT_P (op);
547 ;; Return false if this is any eliminable register. Otherwise general_operand.
548 (define_predicate "general_no_elim_operand"
549 (if_then_else (match_code "reg,subreg")
550 (match_operand 0 "register_no_elim_operand")
551 (match_operand 0 "general_operand")))
553 ;; Return false if this is any eliminable register. Otherwise
554 ;; register_operand or a constant.
555 (define_predicate "nonmemory_no_elim_operand"
556 (ior (match_operand 0 "register_no_elim_operand")
557 (match_operand 0 "immediate_operand")))
559 ;; Test for a valid operand for indirect branch.
560 (define_predicate "indirect_branch_operand"
561 (if_then_else (match_test "TARGET_X32")
562 (match_operand 0 "register_operand")
563 (match_operand 0 "nonimmediate_operand")))
565 ;; Test for a valid operand for a call instruction.
566 (define_predicate "call_insn_operand"
567 (ior (match_operand 0 "constant_call_address_operand")
568 (match_operand 0 "call_register_no_elim_operand")
569 (and (not (match_test "TARGET_X32"))
570 (match_operand 0 "memory_operand"))))
572 ;; Similarly, but for tail calls, in which we cannot allow memory references.
573 (define_predicate "sibcall_insn_operand"
574 (ior (match_operand 0 "constant_call_address_operand")
575 (match_operand 0 "register_no_elim_operand")))
577 ;; Match exactly zero.
578 (define_predicate "const0_operand"
579 (match_code "const_int,const_double,const_vector")
581 if (mode == VOIDmode)
582 mode = GET_MODE (op);
583 return op == CONST0_RTX (mode);
586 ;; Match exactly one.
587 (define_predicate "const1_operand"
588 (and (match_code "const_int")
589 (match_test "op == const1_rtx")))
591 ;; Match exactly eight.
592 (define_predicate "const8_operand"
593 (and (match_code "const_int")
594 (match_test "INTVAL (op) == 8")))
596 ;; Match exactly 128.
597 (define_predicate "const128_operand"
598 (and (match_code "const_int")
599 (match_test "INTVAL (op) == 128")))
601 ;; Match exactly 0x0FFFFFFFF in anddi as a zero-extension operation
602 (define_predicate "const_32bit_mask"
603 (and (match_code "const_int")
604 (match_test "trunc_int_for_mode (INTVAL (op), DImode)
605 == (HOST_WIDE_INT) 0xffffffff")))
607 ;; Match 2, 4, or 8. Used for leal multiplicands.
608 (define_predicate "const248_operand"
609 (match_code "const_int")
611 HOST_WIDE_INT i = INTVAL (op);
612 return i == 2 || i == 4 || i == 8;
615 ;; Match 1, 2, 4, or 8
616 (define_predicate "const1248_operand"
617 (match_code "const_int")
619 HOST_WIDE_INT i = INTVAL (op);
620 return i == 1 || i == 2 || i == 4 || i == 8;
623 ;; Match 3, 5, or 9. Used for leal multiplicands.
624 (define_predicate "const359_operand"
625 (match_code "const_int")
627 HOST_WIDE_INT i = INTVAL (op);
628 return i == 3 || i == 5 || i == 9;
632 (define_predicate "const_0_to_1_operand"
633 (and (match_code "const_int")
634 (ior (match_test "op == const0_rtx")
635 (match_test "op == const1_rtx"))))
638 (define_predicate "const_0_to_3_operand"
639 (and (match_code "const_int")
640 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
643 (define_predicate "const_0_to_7_operand"
644 (and (match_code "const_int")
645 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
648 (define_predicate "const_0_to_15_operand"
649 (and (match_code "const_int")
650 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
653 (define_predicate "const_0_to_31_operand"
654 (and (match_code "const_int")
655 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
658 (define_predicate "const_0_to_63_operand"
659 (and (match_code "const_int")
660 (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
663 (define_predicate "const_0_to_255_operand"
664 (and (match_code "const_int")
665 (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
667 ;; Match (0 to 255) * 8
668 (define_predicate "const_0_to_255_mul_8_operand"
669 (match_code "const_int")
671 unsigned HOST_WIDE_INT val = INTVAL (op);
672 return val <= 255*8 && val % 8 == 0;
675 ;; Return true if OP is CONST_INT >= 1 and <= 31 (a valid operand
676 ;; for shift & compare patterns, as shifting by 0 does not change flags).
677 (define_predicate "const_1_to_31_operand"
678 (and (match_code "const_int")
679 (match_test "IN_RANGE (INTVAL (op), 1, 31)")))
681 ;; Return true if OP is CONST_INT >= 1 and <= 63 (a valid operand
682 ;; for 64bit shift & compare patterns, as shifting by 0 does not change flags).
683 (define_predicate "const_1_to_63_operand"
684 (and (match_code "const_int")
685 (match_test "IN_RANGE (INTVAL (op), 1, 63)")))
688 (define_predicate "const_2_to_3_operand"
689 (and (match_code "const_int")
690 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
693 (define_predicate "const_4_to_5_operand"
694 (and (match_code "const_int")
695 (match_test "IN_RANGE (INTVAL (op), 4, 5)")))
698 (define_predicate "const_4_to_7_operand"
699 (and (match_code "const_int")
700 (match_test "IN_RANGE (INTVAL (op), 4, 7)")))
703 (define_predicate "const_6_to_7_operand"
704 (and (match_code "const_int")
705 (match_test "IN_RANGE (INTVAL (op), 6, 7)")))
708 (define_predicate "const_8_to_11_operand"
709 (and (match_code "const_int")
710 (match_test "IN_RANGE (INTVAL (op), 8, 11)")))
713 (define_predicate "const_12_to_15_operand"
714 (and (match_code "const_int")
715 (match_test "IN_RANGE (INTVAL (op), 12, 15)")))
717 ;; True if this is a constant appropriate for an increment or decrement.
718 (define_predicate "incdec_operand"
719 (match_code "const_int")
721 /* On Pentium4, the inc and dec operations causes extra dependency on flag
722 registers, since carry flag is not set. */
723 if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ())
725 return op == const1_rtx || op == constm1_rtx;
728 ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
729 (define_predicate "reg_or_pm1_operand"
730 (ior (match_operand 0 "register_operand")
731 (and (match_code "const_int")
732 (ior (match_test "op == const1_rtx")
733 (match_test "op == constm1_rtx")))))
735 ;; True if OP is acceptable as operand of DImode shift expander.
736 (define_predicate "shiftdi_operand"
737 (if_then_else (match_test "TARGET_64BIT")
738 (match_operand 0 "nonimmediate_operand")
739 (match_operand 0 "register_operand")))
741 (define_predicate "ashldi_input_operand"
742 (if_then_else (match_test "TARGET_64BIT")
743 (match_operand 0 "nonimmediate_operand")
744 (match_operand 0 "reg_or_pm1_operand")))
746 ;; Return true if OP is a vector load from the constant pool with just
747 ;; the first element nonzero.
748 (define_predicate "zero_extended_scalar_load_operand"
752 op = maybe_get_pool_constant (op);
754 if (!(op && GET_CODE (op) == CONST_VECTOR))
757 n_elts = CONST_VECTOR_NUNITS (op);
759 for (n_elts--; n_elts > 0; n_elts--)
761 rtx elt = CONST_VECTOR_ELT (op, n_elts);
762 if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
768 /* Return true if operand is a vector constant that is all ones. */
769 (define_predicate "vector_all_ones_operand"
770 (match_code "const_vector")
772 int nunits = GET_MODE_NUNITS (mode);
774 if (GET_CODE (op) == CONST_VECTOR
775 && CONST_VECTOR_NUNITS (op) == nunits)
778 for (i = 0; i < nunits; ++i)
780 rtx x = CONST_VECTOR_ELT (op, i);
781 if (x != constm1_rtx)
790 ; Return true when OP is operand acceptable for standard SSE move.
791 (define_predicate "vector_move_operand"
792 (ior (match_operand 0 "nonimmediate_operand")
793 (match_operand 0 "const0_operand")))
795 ;; Return true when OP is nonimmediate or standard SSE constant.
796 (define_predicate "nonimmediate_or_sse_const_operand"
797 (match_operand 0 "general_operand")
799 if (nonimmediate_operand (op, mode))
801 if (standard_sse_constant_p (op) > 0)
806 ;; Return true if OP is a register or a zero.
807 (define_predicate "reg_or_0_operand"
808 (ior (match_operand 0 "register_operand")
809 (match_operand 0 "const0_operand")))
811 ;; Return true if op if a valid address for LEA, and does not contain
812 ;; a segment override. Defined as a special predicate to allow
813 ;; mode-less const_int operands pass to address_operand.
814 (define_special_predicate "lea_address_operand"
815 (match_operand 0 "address_operand")
817 struct ix86_address parts;
820 ok = ix86_decompose_address (op, &parts);
822 return parts.seg == SEG_DEFAULT;
825 ;; Return true for RTX codes that force SImode address.
826 (define_predicate "SImode_address_operand"
827 (match_code "subreg,zero_extend,and"))
829 ;; Return true if op if a valid base register, displacement or
830 ;; sum of base register and displacement for VSIB addressing.
831 (define_predicate "vsib_address_operand"
832 (match_operand 0 "address_operand")
834 struct ix86_address parts;
838 ok = ix86_decompose_address (op, &parts);
840 if (parts.index || parts.seg != SEG_DEFAULT)
843 /* VSIB addressing doesn't support (%rip). */
847 if (GET_CODE (disp) == CONST)
849 disp = XEXP (disp, 0);
850 if (GET_CODE (disp) == PLUS)
851 disp = XEXP (disp, 0);
852 if (GET_CODE (disp) == UNSPEC)
853 switch (XINT (disp, 1))
855 case UNSPEC_GOTPCREL:
857 case UNSPEC_GOTNTPOFF:
863 && (GET_CODE (disp) == SYMBOL_REF
864 || GET_CODE (disp) == LABEL_REF))
871 (define_predicate "vsib_mem_operator"
874 ;; Return true if the rtx is known to be at least 32 bits aligned.
875 (define_predicate "aligned_operand"
876 (match_operand 0 "general_operand")
878 struct ix86_address parts;
881 /* Registers and immediate operands are always "aligned". */
885 /* All patterns using aligned_operand on memory operands ends up
886 in promoting memory operand to 64bit and thus causing memory mismatch. */
887 if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ())
890 /* Don't even try to do any aligned optimizations with volatiles. */
891 if (MEM_VOLATILE_P (op))
894 if (MEM_ALIGN (op) >= 32)
899 /* Pushes and pops are only valid on the stack pointer. */
900 if (GET_CODE (op) == PRE_DEC
901 || GET_CODE (op) == POST_INC)
904 /* Decode the address. */
905 ok = ix86_decompose_address (op, &parts);
908 if (parts.base && GET_CODE (parts.base) == SUBREG)
909 parts.base = SUBREG_REG (parts.base);
910 if (parts.index && GET_CODE (parts.index) == SUBREG)
911 parts.index = SUBREG_REG (parts.index);
913 /* Look for some component that isn't known to be aligned. */
916 if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
921 if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
926 if (!CONST_INT_P (parts.disp)
927 || (INTVAL (parts.disp) & 3))
931 /* Didn't find one -- this must be an aligned address. */
935 ;; Return true if OP is memory operand with a displacement.
936 (define_predicate "memory_displacement_operand"
937 (match_operand 0 "memory_operand")
939 struct ix86_address parts;
942 ok = ix86_decompose_address (XEXP (op, 0), &parts);
944 return parts.disp != NULL_RTX;
947 ;; Return true if OP is memory operand with a displacement only.
948 (define_predicate "memory_displacement_only_operand"
949 (match_operand 0 "memory_operand")
951 struct ix86_address parts;
957 ok = ix86_decompose_address (XEXP (op, 0), &parts);
960 if (parts.base || parts.index)
963 return parts.disp != NULL_RTX;
966 ;; Return true if OP is memory operand which will need zero or
967 ;; one register at most, not counting stack pointer or frame pointer.
968 (define_predicate "cmpxchg8b_pic_memory_operand"
969 (match_operand 0 "memory_operand")
971 struct ix86_address parts;
974 if (TARGET_64BIT || !flag_pic)
977 ok = ix86_decompose_address (XEXP (op, 0), &parts);
980 if (parts.base && GET_CODE (parts.base) == SUBREG)
981 parts.base = SUBREG_REG (parts.base);
982 if (parts.index && GET_CODE (parts.index) == SUBREG)
983 parts.index = SUBREG_REG (parts.index);
985 if (parts.base == NULL_RTX
986 || parts.base == arg_pointer_rtx
987 || parts.base == frame_pointer_rtx
988 || parts.base == hard_frame_pointer_rtx
989 || parts.base == stack_pointer_rtx)
992 if (parts.index == NULL_RTX
993 || parts.index == arg_pointer_rtx
994 || parts.index == frame_pointer_rtx
995 || parts.index == hard_frame_pointer_rtx
996 || parts.index == stack_pointer_rtx)
1003 ;; Return true if OP is memory operand that cannot be represented
1004 ;; by the modRM array.
1005 (define_predicate "long_memory_operand"
1006 (and (match_operand 0 "memory_operand")
1007 (match_test "memory_address_length (op, false)")))
1009 ;; Return true if OP is a comparison operator that can be issued by fcmov.
1010 (define_predicate "fcmov_comparison_operator"
1011 (match_operand 0 "comparison_operator")
1013 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1014 enum rtx_code code = GET_CODE (op);
1016 if (inmode == CCFPmode || inmode == CCFPUmode)
1018 if (!ix86_trivial_fp_comparison_operator (op, mode))
1020 code = ix86_fp_compare_code_to_integer (code);
1022 /* i387 supports just limited amount of conditional codes. */
1025 case LTU: case GTU: case LEU: case GEU:
1026 if (inmode == CCmode || inmode == CCFPmode || inmode == CCFPUmode
1027 || inmode == CCCmode)
1030 case ORDERED: case UNORDERED:
1038 ;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns.
1039 ;; The first set are supported directly; the second set can't be done with
1040 ;; full IEEE support, i.e. NaNs.
1042 (define_predicate "sse_comparison_operator"
1043 (ior (match_code "eq,ne,lt,le,unordered,unge,ungt,ordered")
1044 (and (match_test "TARGET_AVX")
1045 (match_code "ge,gt,uneq,unle,unlt,ltgt"))))
1047 (define_predicate "ix86_comparison_int_operator"
1048 (match_code "ne,eq,ge,gt,le,lt"))
1050 (define_predicate "ix86_comparison_uns_operator"
1051 (match_code "ne,eq,geu,gtu,leu,ltu"))
1053 (define_predicate "bt_comparison_operator"
1054 (match_code "ne,eq"))
1056 ;; Return true if OP is a valid comparison operator in valid mode.
1057 (define_predicate "ix86_comparison_operator"
1058 (match_operand 0 "comparison_operator")
1060 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1061 enum rtx_code code = GET_CODE (op);
1063 if (inmode == CCFPmode || inmode == CCFPUmode)
1064 return ix86_trivial_fp_comparison_operator (op, mode);
1071 if (inmode == CCmode || inmode == CCGCmode
1072 || inmode == CCGOCmode || inmode == CCNOmode)
1075 case LTU: case GTU: case LEU: case GEU:
1076 if (inmode == CCmode || inmode == CCCmode)
1079 case ORDERED: case UNORDERED:
1080 if (inmode == CCmode)
1084 if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
1092 ;; Return true if OP is a valid comparison operator
1093 ;; testing carry flag to be set.
1094 (define_predicate "ix86_carry_flag_operator"
1095 (match_code "ltu,lt,unlt,gtu,gt,ungt,le,unle,ge,unge,ltgt,uneq")
1097 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1098 enum rtx_code code = GET_CODE (op);
1100 if (inmode == CCFPmode || inmode == CCFPUmode)
1102 if (!ix86_trivial_fp_comparison_operator (op, mode))
1104 code = ix86_fp_compare_code_to_integer (code);
1106 else if (inmode == CCCmode)
1107 return code == LTU || code == GTU;
1108 else if (inmode != CCmode)
1114 ;; Return true if this comparison only requires testing one flag bit.
1115 (define_predicate "ix86_trivial_fp_comparison_operator"
1116 (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered"))
1118 ;; Return true if we know how to do this comparison. Others require
1119 ;; testing more than one flag bit, and we let the generic middle-end
1121 (define_predicate "ix86_fp_comparison_operator"
1122 (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1123 == IX86_FPCMP_ARITH")
1124 (match_operand 0 "comparison_operator")
1125 (match_operand 0 "ix86_trivial_fp_comparison_operator")))
1127 ;; Same as above, but for swapped comparison used in fp_jcc_4_387.
1128 (define_predicate "ix86_swapped_fp_comparison_operator"
1129 (match_operand 0 "comparison_operator")
1131 enum rtx_code code = GET_CODE (op);
1134 PUT_CODE (op, swap_condition (code));
1135 ret = ix86_fp_comparison_operator (op, mode);
1136 PUT_CODE (op, code);
1140 ;; Nearly general operand, but accept any const_double, since we wish
1141 ;; to be able to drop them into memory rather than have them get pulled
1143 (define_predicate "cmp_fp_expander_operand"
1144 (ior (match_code "const_double")
1145 (match_operand 0 "general_operand")))
1147 ;; Return true if this is a valid binary floating-point operation.
1148 (define_predicate "binary_fp_operator"
1149 (match_code "plus,minus,mult,div"))
1151 ;; Return true if this is a multiply operation.
1152 (define_predicate "mult_operator"
1153 (match_code "mult"))
1155 ;; Return true if this is a division operation.
1156 (define_predicate "div_operator"
1159 ;; Return true if this is a plus, minus, and, ior or xor operation.
1160 (define_predicate "plusminuslogic_operator"
1161 (match_code "plus,minus,and,ior,xor"))
1163 ;; Return true if this is a float extend operation.
1164 (define_predicate "float_operator"
1165 (match_code "float"))
1167 ;; Return true for ARITHMETIC_P.
1168 (define_predicate "arith_or_logical_operator"
1169 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div,
1170 mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert"))
1172 ;; Return true for COMMUTATIVE_P.
1173 (define_predicate "commutative_operator"
1174 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax"))
1176 ;; Return true if OP is a binary operator that can be promoted to wider mode.
1177 (define_predicate "promotable_binary_operator"
1178 (ior (match_code "plus,minus,and,ior,xor,ashift")
1179 (and (match_code "mult")
1180 (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL"))))
1182 (define_predicate "compare_operator"
1183 (match_code "compare"))
1185 (define_predicate "absneg_operator"
1186 (match_code "abs,neg"))
1188 ;; Return true if OP is misaligned memory operand
1189 (define_predicate "misaligned_operand"
1190 (and (match_code "mem")
1191 (match_test "MEM_ALIGN (op) < GET_MODE_ALIGNMENT (mode)")))
1193 ;; Return true if OP is a emms operation, known to be a PARALLEL.
1194 (define_predicate "emms_operation"
1195 (match_code "parallel")
1199 if (XVECLEN (op, 0) != 17)
1202 for (i = 0; i < 8; i++)
1204 rtx elt = XVECEXP (op, 0, i+1);
1206 if (GET_CODE (elt) != CLOBBER
1207 || GET_CODE (SET_DEST (elt)) != REG
1208 || GET_MODE (SET_DEST (elt)) != XFmode
1209 || REGNO (SET_DEST (elt)) != FIRST_STACK_REG + i)
1212 elt = XVECEXP (op, 0, i+9);
1214 if (GET_CODE (elt) != CLOBBER
1215 || GET_CODE (SET_DEST (elt)) != REG
1216 || GET_MODE (SET_DEST (elt)) != DImode
1217 || REGNO (SET_DEST (elt)) != FIRST_MMX_REG + i)
1223 ;; Return true if OP is a vzeroall operation, known to be a PARALLEL.
1224 (define_predicate "vzeroall_operation"
1225 (match_code "parallel")
1227 unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1229 if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1232 for (i = 0; i < nregs; i++)
1234 rtx elt = XVECEXP (op, 0, i+1);
1236 if (GET_CODE (elt) != SET
1237 || GET_CODE (SET_DEST (elt)) != REG
1238 || GET_MODE (SET_DEST (elt)) != V8SImode
1239 || REGNO (SET_DEST (elt)) != SSE_REGNO (i)
1240 || SET_SRC (elt) != CONST0_RTX (V8SImode))
1246 ;; Return true if OP is a parallel for a vbroadcast permute.
1248 (define_predicate "avx_vbroadcast_operand"
1249 (and (match_code "parallel")
1250 (match_code "const_int" "a"))
1252 rtx elt = XVECEXP (op, 0, 0);
1253 int i, nelt = XVECLEN (op, 0);
1255 /* Don't bother checking there are the right number of operands,
1256 merely that they're all identical. */
1257 for (i = 1; i < nelt; ++i)
1258 if (XVECEXP (op, 0, i) != elt)
1263 ;; Return true if OP is a proper third operand to vpblendw256.
1264 (define_predicate "avx2_pblendw_operand"
1265 (match_code "const_int")
1267 HOST_WIDE_INT val = INTVAL (op);
1268 HOST_WIDE_INT low = val & 0xff;
1269 return val == ((low << 8) | low);