1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987-2018 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* Expression definitions and descriptions for all targets are in this file.
24 Some will not be used for some targets.
26 The fields in the cpp macro call "DEF_RTL_EXPR()"
27 are used to create declarations in the C source of the compiler.
31 1. The internal name of the rtx used in the C source.
32 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
33 By convention these are in UPPER_CASE.
35 2. The name of the rtx in the external ASCII format read by
36 read_rtx(), and printed by print_rtx().
37 These names are stored in rtx_name[].
38 By convention these are the internal (field 1) names in lower_case.
40 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
41 These formats are stored in rtx_format[].
42 The meaning of the formats is documented in front of this array in rtl.c
44 4. The class of the rtx. These are stored in rtx_class and are accessed
45 via the GET_RTX_CLASS macro. They are defined as follows:
48 an rtx code that can be used to represent a constant object
51 an rtx code that can be used to represent an object (e.g, REG, MEM)
53 an rtx code for a comparison (e.g, LT, GT)
55 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
57 an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
59 an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
61 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
63 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
65 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
67 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) or
68 data that will be output as assembly pseudo-ops (DEBUG_INSN)
70 an rtx code for something that matches in insns (e.g, MATCH_DUP)
72 an rtx code for autoincrement addressing modes (e.g. POST_DEC)
76 All of the expressions that appear only in machine descriptions,
77 not in RTL used by the compiler itself, are at the end of the file. */
79 /* Unknown, or no such operation; the enumeration constant should have
81 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
83 /* Used in the cselib routines to describe a value. Objects of this
84 kind are only allocated in cselib.c, in an alloc pool instead of in
85 GC memory. The only operand of a VALUE is a cselib_val.
86 var-tracking requires this to have a distinct integral value from
87 DECL codes in trees. */
88 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
90 /* The RTL generated for a DEBUG_EXPR_DECL. It links back to the
91 DEBUG_EXPR_DECL in the first operand. */
92 DEF_RTL_EXPR(DEBUG_EXPR, "debug_expr", "0", RTX_OBJ)
94 /* ---------------------------------------------------------------------
95 Expressions used in constructing lists.
96 --------------------------------------------------------------------- */
98 /* A linked list of expressions. */
99 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
101 /* A linked list of instructions.
102 The insns are represented in print by their uids. */
103 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
105 /* A linked list of integers. */
106 DEF_RTL_EXPR(INT_LIST, "int_list", "ie", RTX_EXTRA)
108 /* SEQUENCE is used in late passes of the compiler to group insns for
109 one reason or another.
111 For example, after delay slot filling, branch instructions with filled
112 delay slots are represented as a SEQUENCE of length 1 + n_delay_slots,
113 with the branch instruction in XEXPVEC(seq, 0, 0) and the instructions
114 occupying the delay slots in the remaining XEXPVEC slots.
116 Another place where a SEQUENCE may appear, is in REG_FRAME_RELATED_EXPR
117 notes, to express complex operations that are not obvious from the insn
118 to which the REG_FRAME_RELATED_EXPR note is attached. In this usage of
119 SEQUENCE, the sequence vector slots do not hold real instructions but
120 only pseudo-instructions that can be translated to DWARF CFA expressions.
122 Some back ends also use SEQUENCE to group insns in bundles.
124 Much of the compiler infrastructure is not prepared to handle SEQUENCE
125 objects. Only passes after pass_free_cfg are expected to handle them. */
126 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
128 /* Represents a non-global base address. This is only used in alias.c. */
129 DEF_RTL_EXPR(ADDRESS, "address", "i", RTX_EXTRA)
131 /* ----------------------------------------------------------------------
132 Expression types used for things in the instruction chain.
134 All formats must start with "uu" to handle the chain.
135 Each insn expression holds an rtl instruction and its semantics
136 during back-end processing.
137 See macros in "rtl.h" for the meaning of each rtx->u.fld[].
139 ---------------------------------------------------------------------- */
141 /* An annotation for variable assignment tracking. */
142 DEF_RTL_EXPR(DEBUG_INSN, "debug_insn", "uuBeiie", RTX_INSN)
144 /* An instruction that cannot jump. */
145 DEF_RTL_EXPR(INSN, "insn", "uuBeiie", RTX_INSN)
147 /* An instruction that can possibly jump.
148 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
149 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "uuBeiie0", RTX_INSN)
151 /* An instruction that can possibly call a subroutine
152 but which will not change which instruction comes next
153 in the current function.
154 Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE.
155 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
156 DEF_RTL_EXPR(CALL_INSN, "call_insn", "uuBeiiee", RTX_INSN)
158 /* Placeholder for tablejump JUMP_INSNs. The pattern of this kind
159 of rtx is always either an ADDR_VEC or an ADDR_DIFF_VEC. These
160 placeholders do not appear as real instructions inside a basic
161 block, but are considered active_insn_p instructions for historical
162 reasons, when jump table data was represented with JUMP_INSNs. */
163 DEF_RTL_EXPR(JUMP_TABLE_DATA, "jump_table_data", "uuBe0000", RTX_INSN)
165 /* A marker that indicates that control will not flow through. */
166 DEF_RTL_EXPR(BARRIER, "barrier", "uu00000", RTX_EXTRA)
168 /* Holds a label that is followed by instructions.
170 3: is used in jump.c for the use-count of the label.
171 4: is used in the sh backend.
172 5: is a number that is unique in the entire compilation.
173 6: is the user-given name of the label, if any. */
174 DEF_RTL_EXPR(CODE_LABEL, "code_label", "uuB00is", RTX_EXTRA)
176 /* Say where in the code a source line starts, for symbol table's sake.
178 3: note-specific data
180 5: unique number if insn_note == note_insn_deleted_label. */
181 DEF_RTL_EXPR(NOTE, "note", "uuB0ni", RTX_EXTRA)
183 /* ----------------------------------------------------------------------
184 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
185 ---------------------------------------------------------------------- */
187 /* Conditionally execute code.
188 Operand 0 is the condition that if true, the code is executed.
189 Operand 1 is the code to be executed (typically a SET).
191 Semantics are that there are no side effects if the condition
192 is false. This pattern is created automatically by the if_convert
193 pass run after reload or by target-specific splitters. */
194 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
196 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
197 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
199 /* A string that is passed through to the assembler as input.
200 One can obviously pass comments through by using the
201 assembler comment syntax.
202 These occur in an insn all by themselves as the PATTERN.
203 They also appear inside an ASM_OPERANDS
204 as a convenient way to hold a string. */
205 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA)
207 /* An assembler instruction with operands.
208 1st operand is the instruction template.
209 2nd operand is the constraint for the output.
210 3rd operand is the number of the output this expression refers to.
211 When an insn stores more than one value, a separate ASM_OPERANDS
212 is made for each output; this integer distinguishes them.
213 4th is a vector of values of input operands.
214 5th is a vector of modes and constraints for the input operands.
215 Each element is an ASM_INPUT containing a constraint string
216 and whose mode indicates the mode of the input operand.
217 6th is a vector of labels that may be branched to by the asm.
218 7th is the source line number. */
219 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEEi", RTX_EXTRA)
221 /* A machine-specific operation.
222 1st operand is a vector of operands being used by the operation so that
223 any needed reloads can be done.
224 2nd operand is a unique value saying which of a number of machine-specific
225 operations is to be performed.
226 (Note that the vector must be the first operand because of the way that
227 genrecog.c record positions within an insn.)
229 UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL,
230 or inside an expression.
231 UNSPEC by itself or as a component of a PARALLEL
232 is currently considered not deletable.
234 FIXME: Replace all uses of UNSPEC that appears by itself or as a component
235 of a PARALLEL with USE.
237 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
239 /* Similar, but a volatile operation and one which may trap. */
240 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
242 /* ----------------------------------------------------------------------
243 Table jump addresses.
244 ---------------------------------------------------------------------- */
246 /* Vector of addresses, stored as full words.
247 Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
248 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
250 /* Vector of address differences X0 - BASE, X1 - BASE, ...
251 First operand is BASE; the vector contains the X's.
252 The machine mode of this rtx says how much space to leave
253 for each difference and is adjusted by branch shortening if
254 CASE_VECTOR_SHORTEN_MODE is defined.
255 The third and fourth operands store the target labels with the
256 minimum and maximum addresses respectively.
257 The fifth operand stores flags for use by branch shortening.
258 Set at the start of shorten_branches:
259 min_align: the minimum alignment for any of the target labels.
260 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
261 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
262 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
263 min_after_base: true iff minimum address target label is after BASE.
264 max_after_base: true iff maximum address target label is after BASE.
265 Set by the actual branch shortening process:
266 offset_unsigned: true iff offsets have to be treated as unsigned.
267 scale: scaling that is necessary to make offsets fit into the mode.
269 The third, fourth and fifth operands are only valid when
270 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
272 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
274 /* Memory prefetch, with attributes supported on some targets.
275 Operand 1 is the address of the memory to fetch.
276 Operand 2 is 1 for a write access, 0 otherwise.
277 Operand 3 is the level of temporal locality; 0 means there is no
278 temporal locality and 1, 2, and 3 are for increasing levels of temporal
281 The attributes specified by operands 2 and 3 are ignored for targets
282 whose prefetch instructions do not support them. */
283 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
285 /* ----------------------------------------------------------------------
286 At the top level of an instruction (perhaps under PARALLEL).
287 ---------------------------------------------------------------------- */
290 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
291 Operand 2 is the value stored there.
292 ALL assignment must use SET.
293 Instructions that do multiple assignments must use multiple SET,
295 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
297 /* Indicate something is used in a way that we don't want to explain.
298 For example, subroutine calls will use the register
299 in which the static chain is passed.
301 USE can not appear as an operand of other rtx except for PARALLEL.
302 USE is not deletable, as it indicates that the operand
303 is used in some unknown way. */
304 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
306 /* Indicate something is clobbered in a way that we don't want to explain.
307 For example, subroutine calls will clobber some physical registers
308 (the ones that are by convention not saved).
310 CLOBBER can not appear as an operand of other rtx except for PARALLEL.
311 CLOBBER of a hard register appearing by itself (not within PARALLEL)
312 is considered undeletable before reload. */
313 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
315 /* Call a subroutine.
316 Operand 1 is the address to call.
317 Operand 2 is the number of arguments. */
319 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
321 /* Return from a subroutine. */
323 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
325 /* Like RETURN, but truly represents only a function return, while
326 RETURN may represent an insn that also performs other functions
327 of the function epilogue. Like RETURN, this may also occur in
328 conditional jumps. */
329 DEF_RTL_EXPR(SIMPLE_RETURN, "simple_return", "", RTX_EXTRA)
331 /* Special for EH return from subroutine. */
333 DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA)
336 Operand 1 is the condition.
337 Operand 2 is the trap code.
338 For an unconditional trap, make the condition (const_int 1). */
339 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
341 /* ----------------------------------------------------------------------
342 Primitive values for use in expressions.
343 ---------------------------------------------------------------------- */
345 /* numeric integer constant */
346 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
348 /* numeric integer constant */
349 DEF_RTL_EXPR(CONST_WIDE_INT, "const_wide_int", "", RTX_CONST_OBJ)
351 /* An rtx representation of a poly_wide_int. */
352 DEF_RTL_EXPR(CONST_POLY_INT, "const_poly_int", "", RTX_CONST_OBJ)
354 /* fixed-point constant */
355 DEF_RTL_EXPR(CONST_FIXED, "const_fixed", "www", RTX_CONST_OBJ)
357 /* numeric floating point or integer constant. If the mode is
358 VOIDmode it is an int otherwise it has a floating point mode and a
359 floating point value. Operands hold the value. They are all 'w'
360 and there may be from 2 to 6; see real.h. */
361 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
363 /* Describes a vector constant. */
364 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
366 /* String constant. Used for attributes in machine descriptions and
367 for special cases in DWARF2 debug output. NOT used for source-
368 language string constants. */
369 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
371 /* This is used to encapsulate an expression whose value is constant
372 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
373 recognized as a constant operand rather than by arithmetic instructions. */
375 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
377 /* program counter. Ordinary jumps are represented
378 by a SET whose first operand is (PC). */
379 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
381 /* A register. The "operand" is the register number, accessed with
382 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
383 than a hardware register is being referred to. The second operand
384 points to a reg_attrs structure.
385 This rtx needs to have as many (or more) fields as a MEM, since we
386 can change REG rtx's into MEMs during reload. */
387 DEF_RTL_EXPR(REG, "reg", "r", RTX_OBJ)
389 /* A scratch register. This represents a register used only within a
390 single insn. It will be replaced by a REG during register allocation
391 or reload unless the constraint indicates that the register won't be
392 needed, in which case it can remain a SCRATCH. */
393 DEF_RTL_EXPR(SCRATCH, "scratch", "", RTX_OBJ)
395 /* A reference to a part of another value. The first operand is the
396 complete value and the second is the byte offset of the selected part. */
397 DEF_RTL_EXPR(SUBREG, "subreg", "ep", RTX_EXTRA)
399 /* This one-argument rtx is used for move instructions
400 that are guaranteed to alter only the low part of a destination.
401 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
402 has an unspecified effect on the high part of REG,
403 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
404 is guaranteed to alter only the bits of REG that are in HImode.
406 The actual instruction used is probably the same in both cases,
407 but the register constraints may be tighter when STRICT_LOW_PART
410 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
412 /* (CONCAT a b) represents the virtual concatenation of a and b
413 to make a value that has as many bits as a and b put together.
414 This is used for complex values. Normally it appears only
415 in DECL_RTLs and during RTL generation, but not in the insn chain. */
416 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
418 /* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of
419 all An to make a value. This is an extension of CONCAT to larger
420 number of components. Like CONCAT, it should not appear in the
421 insn chain. Every element of the CONCATN is the same size. */
422 DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ)
424 /* A memory location; operand is the address. The second operand is the
425 alias set to which this MEM belongs. We use `0' instead of `w' for this
426 field so that the field need not be specified in machine descriptions. */
427 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
429 /* Reference to an assembler label in the code for this function.
430 The operand is a CODE_LABEL found in the insn chain. */
431 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
433 /* Reference to a named label:
434 Operand 0: label name
435 Operand 1: tree from which this symbol is derived, or null.
436 This is either a DECL node, or some kind of constant. */
437 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s0", RTX_CONST_OBJ)
439 /* The condition code register is represented, in our imagination,
440 as a register holding a value that can be compared to zero.
441 In fact, the machine has already compared them and recorded the
442 results; but instructions that look at the condition code
443 pretend to be looking at the entire value and comparing it. */
444 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
446 /* ----------------------------------------------------------------------
447 Expressions for operators in an rtl pattern
448 ---------------------------------------------------------------------- */
450 /* if_then_else. This is used in representing ordinary
451 conditional jump instructions.
456 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
458 /* Comparison, produces a condition code result. */
459 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
462 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
464 /* Operand 0 minus operand 1. */
465 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
467 /* Minus operand 0. */
468 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
470 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
472 /* Multiplication with signed saturation */
473 DEF_RTL_EXPR(SS_MULT, "ss_mult", "ee", RTX_COMM_ARITH)
474 /* Multiplication with unsigned saturation */
475 DEF_RTL_EXPR(US_MULT, "us_mult", "ee", RTX_COMM_ARITH)
477 /* Operand 0 divided by operand 1. */
478 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
479 /* Division with signed saturation */
480 DEF_RTL_EXPR(SS_DIV, "ss_div", "ee", RTX_BIN_ARITH)
481 /* Division with unsigned saturation */
482 DEF_RTL_EXPR(US_DIV, "us_div", "ee", RTX_BIN_ARITH)
484 /* Remainder of operand 0 divided by operand 1. */
485 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
487 /* Unsigned divide and remainder. */
488 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
489 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
491 /* Bitwise operations. */
492 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
493 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
494 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
495 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
498 0: value to be shifted.
499 1: number of bits. */
500 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
501 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
502 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
503 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
504 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
506 /* Minimum and maximum values of two operands. We need both signed and
507 unsigned forms. (We cannot use MIN for SMIN because it conflicts
508 with a macro of the same name.) The signed variants should be used
509 with floating point. Further, if both operands are zeros, or if either
510 operand is NaN, then it is unspecified which of the two operands is
511 returned as the result. */
513 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
514 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
515 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
516 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
518 /* These unary operations are used to represent incrementation
519 and decrementation as they occur in memory addresses.
520 The amount of increment or decrement are not represented
521 because they can be understood from the machine-mode of the
522 containing MEM. These operations exist in only two cases:
523 1. pushes onto the stack.
524 2. created automatically by the auto-inc-dec pass. */
525 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
526 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
527 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
528 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
530 /* These binary operations are used to represent generic address
531 side-effects in memory addresses, except for simple incrementation
532 or decrementation which use the above operations. They are
533 created automatically by the life_analysis pass in flow.c.
534 The first operand is a REG which is used as the address.
535 The second operand is an expression that is assigned to the
536 register, either before (PRE_MODIFY) or after (POST_MODIFY)
537 evaluating the address.
538 Currently, the compiler can only handle second operands of the
539 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
540 the first operand of the PLUS has to be the same register as
541 the first operand of the *_MODIFY. */
542 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
543 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
545 /* Comparison operations. The ordered comparisons exist in two
546 flavors, signed and unsigned. */
547 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
548 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
549 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
550 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
551 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
552 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
553 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
554 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
555 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
556 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
558 /* Additional floating point unordered comparison flavors. */
559 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
560 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
562 /* These are equivalent to unordered or ... */
563 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
564 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
565 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
566 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
567 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
569 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
570 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
572 /* Represents the result of sign-extending the sole operand.
573 The machine modes of the operand and of the SIGN_EXTEND expression
574 determine how much sign-extension is going on. */
575 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
577 /* Similar for zero-extension (such as unsigned short to int). */
578 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
580 /* Similar but here the operand has a wider mode. */
581 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
583 /* Similar for extending floating-point values (such as SFmode to DFmode). */
584 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
585 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
587 /* Conversion of fixed point operand to floating point value. */
588 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
590 /* With fixed-point machine mode:
591 Conversion of floating point operand to fixed point value.
592 Value is defined only when the operand's value is an integer.
593 With floating-point machine mode (and operand with same mode):
594 Operand is rounded toward zero to produce an integer value
595 represented in floating point. */
596 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
598 /* Conversion of unsigned fixed point operand to floating point value. */
599 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
601 /* With fixed-point machine mode:
602 Conversion of floating point operand to *unsigned* fixed point value.
603 Value is defined only when the operand's value is an integer. */
604 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
606 /* Conversions involving fractional fixed-point types without saturation,
608 fractional to fractional (of different precision),
609 signed integer to fractional,
610 fractional to signed integer,
611 floating point to fractional,
612 fractional to floating point.
613 NOTE: fractional can be either signed or unsigned for conversions. */
614 DEF_RTL_EXPR(FRACT_CONVERT, "fract_convert", "e", RTX_UNARY)
616 /* Conversions involving fractional fixed-point types and unsigned integer
617 without saturation, including:
618 unsigned integer to fractional,
619 fractional to unsigned integer.
620 NOTE: fractional can be either signed or unsigned for conversions. */
621 DEF_RTL_EXPR(UNSIGNED_FRACT_CONVERT, "unsigned_fract_convert", "e", RTX_UNARY)
623 /* Conversions involving fractional fixed-point types with saturation,
625 fractional to fractional (of different precision),
626 signed integer to fractional,
627 floating point to fractional.
628 NOTE: fractional can be either signed or unsigned for conversions. */
629 DEF_RTL_EXPR(SAT_FRACT, "sat_fract", "e", RTX_UNARY)
631 /* Conversions involving fractional fixed-point types and unsigned integer
632 with saturation, including:
633 unsigned integer to fractional.
634 NOTE: fractional can be either signed or unsigned for conversions. */
635 DEF_RTL_EXPR(UNSIGNED_SAT_FRACT, "unsigned_sat_fract", "e", RTX_UNARY)
638 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
641 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
644 DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY)
646 /* Find first bit that is set.
647 Value is 1 + number of trailing zeros in the arg.,
649 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
651 /* Count number of leading redundant sign bits (number of leading
652 sign bits minus one). */
653 DEF_RTL_EXPR(CLRSB, "clrsb", "e", RTX_UNARY)
655 /* Count leading zeros. */
656 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
658 /* Count trailing zeros. */
659 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
661 /* Population count (number of 1 bits). */
662 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
664 /* Population parity (number of 1 bits modulo 2). */
665 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
667 /* Reference to a signed bit-field of specified size and position.
668 Operand 0 is the memory unit (usually SImode or QImode) which
669 contains the field's first bit. Operand 1 is the width, in bits.
670 Operand 2 is the number of bits in the memory unit before the
671 first bit of this field.
672 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
673 operand 2 counts from the msb of the memory unit.
674 Otherwise, the first bit is the lsb and operand 2 counts from
675 the lsb of the memory unit.
676 This kind of expression can not appear as an lvalue in RTL. */
677 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
679 /* Similar for unsigned bit-field.
680 But note! This kind of expression _can_ appear as an lvalue. */
681 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
683 /* For RISC machines. These save memory when splitting insns. */
685 /* HIGH are the high-order bits of a constant expression. */
686 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
688 /* LO_SUM is the sum of a register and the low-order bits
689 of a constant expression. */
690 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
692 /* Describes a merge operation between two vector values.
693 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
694 that specifies where the parts of the result are taken from. Set bits
695 indicate operand 0, clear bits indicate operand 1. The parts are defined
696 by the mode of the vectors. */
697 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
699 /* Describes an operation that selects parts of a vector.
700 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
701 a CONST_INT for each of the subparts of the result vector, giving the
702 number of the source subpart that should be stored into it. */
703 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
705 /* Describes a vector concat operation. Operands 0 and 1 are the source
706 vectors, the result is a vector that is as long as operands 0 and 1
707 combined and is the concatenation of the two source vectors. */
708 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
710 /* Describes an operation that converts a small vector into a larger one by
711 duplicating the input values. The output vector mode must have the same
712 submodes as the input vector mode, and the number of output parts must be
713 an integer multiple of the number of input parts. */
714 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
716 /* Creation of a vector in which element I has the value BASE + I * STEP,
717 where BASE is the first operand and STEP is the second. The result
718 must have a vector integer mode. */
719 DEF_RTL_EXPR(VEC_SERIES, "vec_series", "ee", RTX_BIN_ARITH)
721 /* Addition with signed saturation */
722 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
724 /* Addition with unsigned saturation */
725 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
727 /* Operand 0 minus operand 1, with signed saturation. */
728 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
730 /* Negation with signed saturation. */
731 DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
732 /* Negation with unsigned saturation. */
733 DEF_RTL_EXPR(US_NEG, "us_neg", "e", RTX_UNARY)
735 /* Absolute value with signed saturation. */
736 DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY)
738 /* Shift left with signed saturation. */
739 DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
741 /* Shift left with unsigned saturation. */
742 DEF_RTL_EXPR(US_ASHIFT, "us_ashift", "ee", RTX_BIN_ARITH)
744 /* Operand 0 minus operand 1, with unsigned saturation. */
745 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
747 /* Signed saturating truncate. */
748 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
750 /* Unsigned saturating truncate. */
751 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
753 /* Floating point multiply/add combined instruction. */
754 DEF_RTL_EXPR(FMA, "fma", "eee", RTX_TERNARY)
756 /* Information about the variable and its location. */
757 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA)
759 /* Used in VAR_LOCATION for a pointer to a decl that is no longer
761 DEF_RTL_EXPR(DEBUG_IMPLICIT_PTR, "debug_implicit_ptr", "t", RTX_OBJ)
763 /* Represents value that argument had on function entry. The
764 single argument is the DECL_INCOMING_RTL of the corresponding
766 DEF_RTL_EXPR(ENTRY_VALUE, "entry_value", "0", RTX_OBJ)
768 /* Used in VAR_LOCATION for a reference to a parameter that has
769 been optimized away completely. */
770 DEF_RTL_EXPR(DEBUG_PARAMETER_REF, "debug_parameter_ref", "t", RTX_OBJ)
772 /* Used in marker DEBUG_INSNs to avoid being recognized as an insn. */
773 DEF_RTL_EXPR(DEBUG_MARKER, "debug_marker", "", RTX_EXTRA)
775 /* All expressions from this point forward appear only in machine
777 #ifdef GENERATOR_FILE
779 /* Pattern-matching operators: */
781 /* Use the function named by the second arg (the string)
782 as a predicate; if matched, store the structure that was matched
783 in the operand table at index specified by the first arg (the integer).
784 If the second arg is the null string, the structure is just stored.
786 A third string argument indicates to the register allocator restrictions
787 on where the operand can be allocated.
789 If the target needs no restriction on any instruction this field should
792 The string is prepended by:
793 '=' to indicate the operand is only written to.
794 '+' to indicate the operand is both read and written to.
796 Each character in the string represents an allocable class for an operand.
797 'g' indicates the operand can be any valid class.
798 'i' indicates the operand can be immediate (in the instruction) data.
799 'r' indicates the operand can be in a register.
800 'm' indicates the operand can be in memory.
801 'o' a subset of the 'm' class. Those memory addressing modes that
802 can be offset at compile time (have a constant added to them).
804 Other characters indicate target dependent operand classes and
805 are described in each target's machine description.
807 For instructions with more than one operand, sets of classes can be
808 separated by a comma to indicate the appropriate multi-operand constraints.
809 There must be a 1 to 1 correspondence between these sets of classes in
810 all operands for an instruction.
812 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
814 /* Match a SCRATCH or a register. When used to generate rtl, a
815 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
816 the desired mode and the first argument is the operand number.
817 The second argument is the constraint. */
818 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
820 /* Apply a predicate, AND match recursively the operands of the rtx.
821 Operand 0 is the operand-number, as in match_operand.
822 Operand 1 is a predicate to apply (as a string, a function name).
823 Operand 2 is a vector of expressions, each of which must match
824 one subexpression of the rtx this construct is matching. */
825 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
827 /* Match a PARALLEL of arbitrary length. The predicate is applied
828 to the PARALLEL and the initial expressions in the PARALLEL are matched.
829 Operand 0 is the operand-number, as in match_operand.
830 Operand 1 is a predicate to apply to the PARALLEL.
831 Operand 2 is a vector of expressions, each of which must match the
832 corresponding element in the PARALLEL. */
833 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
835 /* Match only something equal to what is stored in the operand table
836 at the index specified by the argument. Use with MATCH_OPERAND. */
837 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
839 /* Match only something equal to what is stored in the operand table
840 at the index specified by the argument. Use with MATCH_OPERATOR. */
841 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
843 /* Match only something equal to what is stored in the operand table
844 at the index specified by the argument. Use with MATCH_PARALLEL. */
845 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
847 /* Appears only in define_predicate/define_special_predicate
848 expressions. Evaluates true only if the operand has an RTX code
849 from the set given by the argument (a comma-separated list). If the
850 second argument is present and nonempty, it is a sequence of digits
851 and/or letters which indicates the subexpression to test, using the
852 same syntax as genextract/genrecog's location strings: 0-9 for
853 XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
854 the result of the one before it. */
855 DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
857 /* Used to inject a C conditional expression into an .md file. It can
858 appear in a predicate definition or an attribute expression. */
859 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
861 /* Insn (and related) definitions. */
863 /* Definition of the pattern for one kind of instruction.
865 0: names this instruction.
866 If the name is the null string, the instruction is in the
867 machine description just to be recognized, and will never be emitted by
868 the tree to rtl expander.
870 2: is a string which is a C expression
871 giving an additional condition for recognizing this pattern.
872 A null string means no extra condition.
873 3: is the action to execute if this pattern is matched.
874 If this assembler code template starts with a * then it is a fragment of
875 C code to run to decide on a template to use. Otherwise, it is the
877 4: optionally, a vector of attributes for this insn.
879 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
881 /* Definition of a peephole optimization.
882 1st operand: vector of insn patterns to match
883 2nd operand: C expression that must be true
884 3rd operand: template or C code to produce assembler output.
885 4: optionally, a vector of attributes for this insn.
887 This form is deprecated; use define_peephole2 instead. */
888 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
890 /* Definition of a split operation.
891 1st operand: insn pattern to match
892 2nd operand: C expression that must be true
893 3rd operand: vector of insn patterns to place into a SEQUENCE
894 4th operand: optionally, some C code to execute before generating the
895 insns. This might, for example, create some RTX's and store them in
896 elements of `recog_data.operand' for use by the vector of
898 (`operands' is an alias here for `recog_data.operand'). */
899 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
901 /* Definition of an insn and associated split.
902 This is the concatenation, with a few modifications, of a define_insn
903 and a define_split which share the same pattern.
905 0: names this instruction.
906 If the name is the null string, the instruction is in the
907 machine description just to be recognized, and will never be emitted by
908 the tree to rtl expander.
910 2: is a string which is a C expression
911 giving an additional condition for recognizing this pattern.
912 A null string means no extra condition.
913 3: is the action to execute if this pattern is matched.
914 If this assembler code template starts with a * then it is a fragment of
915 C code to run to decide on a template to use. Otherwise, it is the
917 4: C expression that must be true for split. This may start with "&&"
918 in which case the split condition is the logical and of the insn
919 condition and what follows the "&&" of this operand.
920 5: vector of insn patterns to place into a SEQUENCE
921 6: optionally, some C code to execute before generating the
922 insns. This might, for example, create some RTX's and store them in
923 elements of `recog_data.operand' for use by the vector of
925 (`operands' is an alias here for `recog_data.operand').
926 7: optionally, a vector of attributes for this insn. */
927 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
929 /* Definition of an RTL peephole operation.
930 Follows the same arguments as define_split. */
931 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
933 /* Define how to generate multiple insns for a standard insn name.
934 1st operand: the insn name.
935 2nd operand: vector of insn-patterns.
936 Use match_operand to substitute an element of `recog_data.operand'.
937 3rd operand: C expression that must be true for this to be available.
938 This may not test any operands.
939 4th operand: Extra C code to execute before generating the insns.
940 This might, for example, create some RTX's and store them in
941 elements of `recog_data.operand' for use by the vector of
943 (`operands' is an alias here for `recog_data.operand').
944 5th: optionally, a vector of attributes for this expand. */
945 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEssV", RTX_EXTRA)
947 /* Define a requirement for delay slots.
948 1st operand: Condition involving insn attributes that, if true,
949 indicates that the insn requires the number of delay slots
951 2nd operand: Vector whose length is the three times the number of delay
953 Each entry gives three conditions, each involving attributes.
954 The first must be true for an insn to occupy that delay slot
955 location. The second is true for all insns that can be
956 annulled if the branch is true and the third is true for all
957 insns that can be annulled if the branch is false.
959 Multiple DEFINE_DELAYs may be present. They indicate differing
960 requirements for delay slots. */
961 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
963 /* Define attribute computation for `asm' instructions. */
964 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
966 /* Definition of a conditional execution meta operation. Automatically
967 generates new instances of DEFINE_INSN, selected by having attribute
968 "predicable" true. The new pattern will contain a COND_EXEC and the
969 predicate at top-level.
972 0: The predicate pattern. The top-level form should match a
973 relational operator. Operands should have only one alternative.
974 1: A C expression giving an additional condition for recognizing
975 the generated pattern.
976 2: A template or C code to produce assembler output.
977 3: A vector of attributes to append to the resulting cond_exec insn. */
978 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "EssV", RTX_EXTRA)
980 /* Definition of an operand predicate. The difference between
981 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
982 not warn about a match_operand with no mode if it has a predicate
983 defined with DEFINE_SPECIAL_PREDICATE.
986 0: The name of the predicate.
987 1: A boolean expression which computes whether or not the predicate
988 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
989 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
990 can calculate the set of RTX codes that can possibly match.
991 2: A C function body which must return true for the predicate to match.
992 Optional. Use this when the test is too complicated to fit into a
993 match_test expression. */
994 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
995 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
997 /* Definition of a register operand constraint. This simply maps the
998 constraint string to a register class.
1001 0: The name of the constraint (often, but not always, a single letter).
1002 1: A C expression which evaluates to the appropriate register class for
1003 this constraint. If this is not just a constant, it should look only
1004 at -m switches and the like.
1005 2: A docstring for this constraint, in Texinfo syntax; not currently
1006 used, in future will be incorporated into the manual's list of
1007 machine-specific operand constraints. */
1008 DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
1010 /* Definition of a non-register operand constraint. These look at the
1011 operand and decide whether it fits the constraint.
1013 DEFINE_CONSTRAINT gets no special treatment if it fails to match.
1014 It is appropriate for constant-only constraints, and most others.
1016 DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
1017 to match, if it doesn't already, by converting the operand to the form
1018 (mem (reg X)) where X is a base register. It is suitable for constraints
1019 that describe a subset of all memory references.
1021 DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
1022 to match, if it doesn't already, by converting the operand to the form
1023 (reg X) where X is a base register. It is suitable for constraints that
1024 describe a subset of all address references.
1026 When in doubt, use plain DEFINE_CONSTRAINT.
1029 0: The name of the constraint (often, but not always, a single letter).
1030 1: A docstring for this constraint, in Texinfo syntax; not currently
1031 used, in future will be incorporated into the manual's list of
1032 machine-specific operand constraints.
1033 2: A boolean expression which computes whether or not the constraint
1034 matches. It should follow the same rules as a define_predicate
1035 expression, including the bit about specifying the set of RTX codes
1036 that could possibly match. MATCH_TEST subexpressions may make use of
1038 `op' - the RTL object defining the operand.
1039 `mode' - the mode of `op'.
1040 `ival' - INTVAL(op), if op is a CONST_INT.
1041 `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
1042 `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
1043 `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
1045 Do not use ival/hval/lval/rval if op is not the appropriate kind of
1047 DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
1048 DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
1049 DEF_RTL_EXPR(DEFINE_SPECIAL_MEMORY_CONSTRAINT, "define_special_memory_constraint", "sse", RTX_EXTRA)
1050 DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
1053 /* Constructions for CPU pipeline description described by NDFAs. */
1055 /* (define_cpu_unit string [string]) describes cpu functional
1056 units (separated by comma).
1058 1st operand: Names of cpu functional units.
1059 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
1061 All define_reservations, define_cpu_units, and
1062 define_query_cpu_units should have unique names which may not be
1064 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
1066 /* (define_query_cpu_unit string [string]) describes cpu functional
1067 units analogously to define_cpu_unit. The reservation of such
1068 units can be queried for automaton state. */
1069 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
1071 /* (exclusion_set string string) means that each CPU functional unit
1072 in the first string can not be reserved simultaneously with any
1073 unit whose name is in the second string and vise versa. CPU units
1074 in the string are separated by commas. For example, it is useful
1075 for description CPU with fully pipelined floating point functional
1076 unit which can execute simultaneously only single floating point
1077 insns or only double floating point insns. All CPU functional
1078 units in a set should belong to the same automaton. */
1079 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
1081 /* (presence_set string string) means that each CPU functional unit in
1082 the first string can not be reserved unless at least one of pattern
1083 of units whose names are in the second string is reserved. This is
1084 an asymmetric relation. CPU units or unit patterns in the strings
1085 are separated by commas. Pattern is one unit name or unit names
1086 separated by white-spaces.
1088 For example, it is useful for description that slot1 is reserved
1089 after slot0 reservation for a VLIW processor. We could describe it
1090 by the following construction
1092 (presence_set "slot1" "slot0")
1094 Or slot1 is reserved only after slot0 and unit b0 reservation. In
1095 this case we could write
1097 (presence_set "slot1" "slot0 b0")
1099 All CPU functional units in a set should belong to the same
1101 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
1103 /* (final_presence_set string string) is analogous to `presence_set'.
1104 The difference between them is when checking is done. When an
1105 instruction is issued in given automaton state reflecting all
1106 current and planned unit reservations, the automaton state is
1107 changed. The first state is a source state, the second one is a
1108 result state. Checking for `presence_set' is done on the source
1109 state reservation, checking for `final_presence_set' is done on the
1110 result reservation. This construction is useful to describe a
1111 reservation which is actually two subsequent reservations. For
1114 (presence_set "slot1" "slot0")
1116 the following insn will be never issued (because slot1 requires
1117 slot0 which is absent in the source state).
1119 (define_reservation "insn_and_nop" "slot0 + slot1")
1121 but it can be issued if we use analogous `final_presence_set'. */
1122 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1124 /* (absence_set string string) means that each CPU functional unit in
1125 the first string can be reserved only if each pattern of units
1126 whose names are in the second string is not reserved. This is an
1127 asymmetric relation (actually exclusion set is analogous to this
1128 one but it is symmetric). CPU units or unit patterns in the string
1129 are separated by commas. Pattern is one unit name or unit names
1130 separated by white-spaces.
1132 For example, it is useful for description that slot0 can not be
1133 reserved after slot1 or slot2 reservation for a VLIW processor. We
1134 could describe it by the following construction
1136 (absence_set "slot2" "slot0, slot1")
1138 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1139 slot1 and unit b1 are reserved . In this case we could write
1141 (absence_set "slot2" "slot0 b0, slot1 b1")
1143 All CPU functional units in a set should to belong the same
1145 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1147 /* (final_absence_set string string) is analogous to `absence_set' but
1148 checking is done on the result (state) reservation. See comments
1149 for `final_presence_set'. */
1150 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1152 /* (define_bypass number out_insn_names in_insn_names) names bypass
1153 with given latency (the first number) from insns given by the first
1154 string (see define_insn_reservation) into insns given by the second
1155 string. Insn names in the strings are separated by commas. The
1156 third operand is optional name of function which is additional
1157 guard for the bypass. The function will get the two insns as
1158 parameters. If the function returns zero the bypass will be
1159 ignored for this case. Additional guard is necessary to recognize
1160 complicated bypasses, e.g. when consumer is load address. If there
1161 are more one bypass with the same output and input insns, the
1162 chosen bypass is the first bypass with a guard in description whose
1163 guard function returns nonzero. If there is no such bypass, then
1164 bypass without the guard function is chosen. */
1165 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1167 /* (define_automaton string) describes names of automata generated and
1168 used for pipeline hazards recognition. The names are separated by
1169 comma. Actually it is possibly to generate the single automaton
1170 but unfortunately it can be very large. If we use more one
1171 automata, the summary size of the automata usually is less than the
1172 single one. The automaton name is used in define_cpu_unit and
1173 define_query_cpu_unit. All automata should have unique names. */
1174 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1176 /* (automata_option string) describes option for generation of
1177 automata. Currently there are the following options:
1179 o "no-minimization" which makes no minimization of automata. This
1180 is only worth to do when we are debugging the description and
1181 need to look more accurately at reservations of states.
1183 o "time" which means printing additional time statistics about
1184 generation of automata.
1186 o "v" which means generation of file describing the result
1187 automata. The file has suffix `.dfa' and can be used for the
1188 description verification and debugging.
1190 o "w" which means generation of warning instead of error for
1191 non-critical errors.
1193 o "ndfa" which makes nondeterministic finite state automata.
1195 o "progress" which means output of a progress bar showing how many
1196 states were generated so far for automaton being processed. */
1197 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1199 /* (define_reservation string string) names reservation (the first
1200 string) of cpu functional units (the 2nd string). Sometimes unit
1201 reservations for different insns contain common parts. In such
1202 case, you can describe common part and use its name (the 1st
1203 parameter) in regular expression in define_insn_reservation. All
1204 define_reservations, define_cpu_units, and define_query_cpu_units
1205 should have unique names which may not be "nothing". */
1206 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1208 /* (define_insn_reservation name default_latency condition regexpr)
1209 describes reservation of cpu functional units (the 3nd operand) for
1210 instruction which is selected by the condition (the 2nd parameter).
1211 The first parameter is used for output of debugging information.
1212 The reservations are described by a regular expression according
1213 the following syntax:
1215 regexp = regexp "," oneof
1218 oneof = oneof "|" allof
1221 allof = allof "+" repeat
1224 repeat = element "*" number
1227 element = cpu_function_unit_name
1233 1. "," is used for describing start of the next cycle in
1236 2. "|" is used for describing the reservation described by the
1237 first regular expression *or* the reservation described by the
1238 second regular expression *or* etc.
1240 3. "+" is used for describing the reservation described by the
1241 first regular expression *and* the reservation described by the
1242 second regular expression *and* etc.
1244 4. "*" is used for convenience and simply means sequence in
1245 which the regular expression are repeated NUMBER times with
1246 cycle advancing (see ",").
1248 5. cpu functional unit name which means its reservation.
1250 6. reservation name -- see define_reservation.
1252 7. string "nothing" means no units reservation. */
1254 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1256 /* Expressions used for insn attributes. */
1258 /* Definition of an insn attribute.
1259 1st operand: name of the attribute
1260 2nd operand: comma-separated list of possible attribute values
1261 3rd operand: expression for the default value of the attribute. */
1262 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1264 /* Definition of an insn attribute that uses an existing enumerated type.
1265 1st operand: name of the attribute
1266 2nd operand: the name of the enumerated type
1267 3rd operand: expression for the default value of the attribute. */
1268 DEF_RTL_EXPR(DEFINE_ENUM_ATTR, "define_enum_attr", "sse", RTX_EXTRA)
1270 /* Marker for the name of an attribute. */
1271 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1273 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1274 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1277 (set_attr "name" "value") is equivalent to
1278 (set (attr "name") (const_string "value")) */
1279 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1281 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1282 specify that attribute values are to be assigned according to the
1283 alternative matched.
1285 The following three expressions are equivalent:
1287 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1288 (eq_attrq "alternative" "2") (const_string "a2")]
1289 (const_string "a3")))
1290 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1291 (const_string "a3")])
1292 (set_attr "att" "a1,a2,a3")
1294 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1296 /* A conditional expression true if the value of the specified attribute of
1297 the current insn equals the specified value. The first operand is the
1298 attribute name and the second is the comparison value. */
1299 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1301 /* A special case of the above representing a set of alternatives. The first
1302 operand is bitmap of the set, the second one is the default value. */
1303 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1305 /* A conditional expression which is true if the specified flag is
1306 true for the insn being scheduled in reorg.
1308 genattr.c defines the following flags which can be tested by
1309 (attr_flag "foo") expressions in eligible_for_delay: forward, backward. */
1311 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1313 /* General conditional. The first operand is a vector composed of pairs of
1314 expressions. The first element of each pair is evaluated, in turn.
1315 The value of the conditional is the second expression of the first pair
1316 whose first expression evaluates nonzero. If none of the expressions is
1317 true, the second operand will be used as the value of the conditional. */
1318 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1320 /* Definition of a pattern substitution meta operation on a DEFINE_EXPAND
1321 or a DEFINE_INSN. Automatically generates new instances of DEFINE_INSNs
1322 that match the substitution pattern.
1325 0: The name of the substitition template.
1326 1: Input template to match to see if a substitution is applicable.
1327 2: A C expression giving an additional condition for the generated
1328 new define_expand or define_insn.
1329 3: Output tempalate to generate via substitution.
1331 Within a DEFINE_SUBST template, the meaning of some RTL expressions is
1332 different from their usual interpretation: a MATCH_OPERAND matches any
1333 expression tree with matching machine mode or with VOIDmode. Likewise,
1334 MATCH_OP_DUP and MATCH_DUP match more liberally in a DEFINE_SUBST than
1335 in other RTL expressions. MATCH_OPERATOR matches all common operators
1336 but also UNSPEC, UNSPEC_VOLATILE, and MATCH_OPERATORS from the input
1337 DEFINE_EXPAND or DEFINE_INSN. */
1338 DEF_RTL_EXPR(DEFINE_SUBST, "define_subst", "sEsE", RTX_EXTRA)
1340 /* Substitution attribute to apply a DEFINE_SUBST to a pattern.
1343 0: The name of the subst-attribute.
1344 1: The name of the DEFINE_SUBST to be applied for this attribute.
1345 2: String to substitute for the subst-attribute name in the pattern
1346 name, for the case that the DEFINE_SUBST is not applied (i.e. the
1347 unmodified version of the pattern).
1348 3: String to substitute for the subst-attribute name in the pattern
1349 name, for the case that the DEFINE_SUBST is applied to the patten.
1351 The use of DEFINE_SUBST and DEFINE_SUBST_ATTR is explained in the
1352 GCC internals manual, under "RTL Templates Transformations". */
1353 DEF_RTL_EXPR(DEFINE_SUBST_ATTR, "define_subst_attr", "ssss", RTX_EXTRA)
1355 #endif /* GENERATOR_FILE */
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