1 /* $OpenBSD: if_uathreg.h,v 1.2 2006/09/18 16:34:23 damien Exp $ */
6 * Damien Bergamini <damien.bergamini@free.fr>
7 * Copyright (c) 2006 Sam Leffler, Errno Consulting
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #define UATH_CONFIG_INDEX 0
23 #define UATH_IFACE_INDEX 0
25 /* all fields are big endian */
28 #define UATH_WRITE_BLOCK (1 << 4)
31 #define UATH_MAX_FWBLOCK_SIZE 2048
39 #define UATH_MAX_CMDSZ 512
42 * Messages are passed in Target Endianness. All fixed-size
43 * fields of a WDS Control Message are treated as 32-bit
44 * values and Control Msgs are guaranteed to be 32-bit aligned.
46 * The format of a WDS Control Message is as follows:
47 * Message Length 32 bits
48 * Message Opcode 32 bits
54 * A variable-length parameter, or a parmeter that is larger than
55 * 32 bits is passed as <length, data> pair, where length is a
56 * 32-bit quantity and data is padded to 32 bits.
59 uint32_t len; /* msg length including header */
60 uint32_t code; /* operation code */
61 /* NB: these are defined for rev 1.5 firmware; rev 1.6 is different */
62 /* messages from Host -> Target */
63 #define WDCMSG_HOST_AVAILABLE 0x01
64 #define WDCMSG_BIND 0x02
65 #define WDCMSG_TARGET_RESET 0x03
66 #define WDCMSG_TARGET_GET_CAPABILITY 0x04
67 #define WDCMSG_TARGET_SET_CONFIG 0x05
68 #define WDCMSG_TARGET_GET_STATUS 0x06
69 #define WDCMSG_TARGET_GET_STATS 0x07
70 #define WDCMSG_TARGET_START 0x08
71 #define WDCMSG_TARGET_STOP 0x09
72 #define WDCMSG_TARGET_ENABLE 0x0a
73 #define WDCMSG_TARGET_DISABLE 0x0b
74 #define WDCMSG_CREATE_CONNECTION 0x0c
75 #define WDCMSG_UPDATE_CONNECT_ATTR 0x0d
76 #define WDCMSG_DELETE_CONNECT 0x0e
77 #define WDCMSG_SEND 0x0f
78 #define WDCMSG_FLUSH 0x10
79 /* messages from Target -> Host */
80 #define WDCMSG_STATS_UPDATE 0x11
81 #define WDCMSG_BMISS 0x12
82 #define WDCMSG_DEVICE_AVAIL 0x13
83 #define WDCMSG_SEND_COMPLETE 0x14
84 #define WDCMSG_DATA_AVAIL 0x15
85 #define WDCMSG_SET_PWR_MODE 0x16
86 #define WDCMSG_BMISS_ACK 0x17
87 #define WDCMSG_SET_LED_STEADY 0x18
88 #define WDCMSG_SET_LED_BLINK 0x19
90 #define WDCMSG_SETUP_BEACON_DESC 0x1a
91 #define WDCMSG_BEACON_INIT 0x1b
92 #define WDCMSG_RESET_KEY_CACHE 0x1c
93 #define WDCMSG_RESET_KEY_CACHE_ENTRY 0x1d
94 #define WDCMSG_SET_KEY_CACHE_ENTRY 0x1e
95 #define WDCMSG_SET_DECOMP_MASK 0x1f
96 #define WDCMSG_SET_REGULATORY_DOMAIN 0x20
97 #define WDCMSG_SET_LED_STATE 0x21
98 #define WDCMSG_WRITE_ASSOCID 0x22
99 #define WDCMSG_SET_STA_BEACON_TIMERS 0x23
100 #define WDCMSG_GET_TSF 0x24
101 #define WDCMSG_RESET_TSF 0x25
102 #define WDCMSG_SET_ADHOC_MODE 0x26
103 #define WDCMSG_SET_BASIC_RATE 0x27
104 #define WDCMSG_MIB_CONTROL 0x28
105 #define WDCMSG_GET_CHANNEL_DATA 0x29
106 #define WDCMSG_GET_CUR_RSSI 0x2a
107 #define WDCMSG_SET_ANTENNA_SWITCH 0x2b
108 #define WDCMSG_USE_SHORT_SLOT_TIME 0x2f
109 #define WDCMSG_SET_POWER_MODE 0x30
110 #define WDCMSG_SETUP_PSPOLL_DESC 0x31
111 #define WDCMSG_SET_RX_MULTICAST_FILTER 0x32
112 #define WDCMSG_RX_FILTER 0x33
113 #define WDCMSG_PER_CALIBRATION 0x34
114 #define WDCMSG_RESET 0x35
115 #define WDCMSG_DISABLE 0x36
116 #define WDCMSG_PHY_DISABLE 0x37
117 #define WDCMSG_SET_TX_POWER_LIMIT 0x38
118 #define WDCMSG_SET_TX_QUEUE_PARAMS 0x39
119 #define WDCMSG_SETUP_TX_QUEUE 0x3a
120 #define WDCMSG_RELEASE_TX_QUEUE 0x3b
121 #define WDCMSG_SET_DEFAULT_KEY 0x43
122 uint32_t msgid; /* msg id (supplied by host) */
123 uint32_t magic; /* response desired/target status */
124 uint32_t debug[4]; /* debug data area */
125 /* msg data follows */
129 uint8_t seqnum; /* sequence number for ordering */
131 #define UATH_CFLAGS_FINAL 0x01 /* final chunk of a msg */
132 #define UATH_CFLAGS_RXMSG 0x02 /* chunk contains rx completion */
133 #define UATH_CFLAGS_DEBUG 0x04 /* for debugging */
134 uint16_t length; /* chunk size in bytes */
135 /* chunk data follows */
138 #define UATH_RX_DUMMYSIZE 4
141 * Message format for a WDCMSG_DATA_AVAIL message from Target to Host.
143 struct uath_rx_desc {
144 uint32_t len; /* msg length including header */
145 uint32_t code; /* WDCMSG_DATA_AVAIL */
146 uint32_t gennum; /* generation number */
147 uint32_t status; /* start of RECEIVE_INFO */
148 #define UATH_STATUS_OK 0
149 #define UATH_STATUS_STOP_IN_PROGRESS 1
150 #define UATH_STATUS_CRC_ERR 2
151 #define UATH_STATUS_PHY_ERR 3
152 #define UATH_STATUS_DECRYPT_CRC_ERR 4
153 #define UATH_STATUS_DECRYPT_MIC_ERR 5
154 #define UATH_STATUS_DECOMP_ERR 6
155 #define UATH_STATUS_KEY_ERR 7
156 #define UATH_STATUS_ERR 8
157 uint32_t tstamp_low; /* low-order 32-bits of rx timestamp */
158 uint32_t tstamp_high; /* high-order 32-bits of rx timestamp */
159 uint32_t framelen; /* frame length */
160 uint32_t rate; /* rx rate code */
165 uint32_t connix; /* key table ix for bss traffic */
166 uint32_t decrypterror;
167 uint32_t keycachemiss;
168 uint32_t pad; /* XXX? */
171 struct uath_tx_desc {
173 uint32_t msgid; /* msg id (supplied by host) */
174 uint32_t type; /* opcode: WDMSG_SEND or WDCMSG_FLUSH */
175 uint32_t txqid; /* tx queue id and flags */
176 #define UATH_TXQID_MASK 0x0f
177 #define UATH_TXQID_MINRATE 0x10 /* use min tx rate */
178 #define UATH_TXQID_FF 0x20 /* content is fast frame */
179 uint32_t connid; /* tx connection id */
180 #define UATH_ID_INVALID 0xffffffff /* for sending prior to connection */
181 uint32_t flags; /* non-zero if response desired */
182 #define UATH_TX_NOTIFY (1 << 24) /* f/w will send a UATH_NOTIF_TX */
183 uint32_t buflen; /* payload length */
186 struct uath_cmd_host_available {
187 uint32_t sw_ver_major;
188 uint32_t sw_ver_minor;
189 uint32_t sw_ver_patch;
190 uint32_t sw_ver_build;
192 #define ATH_SW_VER_MAJOR 1
193 #define ATH_SW_VER_MINOR 5
194 #define ATH_SW_VER_PATCH 0
195 #define ATH_SW_VER_BUILD 9999
197 struct uath_cmd_bind {
198 uint32_t targethandle;
199 uint32_t hostapiversion;
202 /* structure for command WDCMSG_RESET */
203 struct uath_cmd_reset {
204 uint32_t flags; /* channel flags */
205 #define UATH_CHAN_TURBO 0x0100
206 #define UATH_CHAN_CCK 0x0200
207 #define UATH_CHAN_OFDM 0x0400
208 #define UATH_CHAN_2GHZ 0x1000
209 #define UATH_CHAN_5GHZ 0x2000
210 uint32_t freq; /* channel frequency */
213 uint32_t twiceantennareduction;
214 uint32_t channelchange;
215 uint32_t keeprccontent;
218 /* structure for commands UATH_CMD_READ_MAC and UATH_CMD_READ_EEPROM */
219 struct uath_read_mac {
224 /* structure for command UATH_CMD_WRITE_MAC */
225 struct uath_write_mac {
231 /* structure for command UATH_CMD_STA_JOIN */
232 struct uath_cmd_join_bss {
233 uint32_t bssid; /* NB: use zero */
234 uint32_t bssmac[2]; /* bssid mac address */
237 uint32_t beaconinterval;
238 uint32_t dtiminterval;
239 uint32_t cfpinterval;
241 uint32_t defaultrateix;
242 uint32_t shortslottime11g;
243 uint32_t sleepduration;
244 uint32_t bmissthreshold;
245 uint32_t tcppowerlimit;
246 uint32_t quietduration;
247 uint32_t quietoffset;
248 uint32_t quietackctsallow;
249 uint32_t bssdefaultkey; /* XXX? */
252 struct uath_cmd_assoc_bss {
257 struct uath_cmd_start_bss {
261 /* structure for command UATH_CMD_0C */
268 struct uath_cmd_ledsteady { /* WDCMSG_SET_LED_STEADY */
270 #define UATH_LED_LINK 0
271 #define UATH_LED_ACTIVITY 1
273 #define UATH_LED_OFF 0
274 #define UATH_LED_ON 1
277 struct uath_cmd_ledblink { /* WDCMSG_SET_LED_BLINK */
284 struct uath_cmd_ledstate { /* WDCMSG_SET_LED_STATE */
288 struct uath_connkey_rec {
289 uint8_t bssid[IEEE80211_ADDR_LEN];
294 uint16_t keytype; /* WEP, TKIP or AES */
295 /* As far as I know, MIPS 4Kp is 32-bit processor */
299 uint8_t aes_keyval[16];
300 uint8_t mic_txkeyval[8];
301 uint8_t mic_rxkeyval[8];
304 int32_t keyexttsc[17];
307 /* structure for command UATH_CMD_CRYPTO */
308 struct uath_cmd_crypto {
310 #define UATH_DEFAULT_KEY 6
313 struct uath_connkey_rec rec;
316 struct uath_cmd_rateset {
318 #define UATH_MAX_NRATES 32
319 uint8_t set[UATH_MAX_NRATES];
322 /* structure for command WDCMSG_SET_BASIC_RATE */
323 struct uath_cmd_rates {
325 uint32_t keeprccontent;
327 struct uath_cmd_rateset rateset;
337 WLAN_MODE_11a_TURBO_PRIME,
338 WLAN_MODE_11g_TURBO_PRIME,
343 struct uath_cmd_connection_attr {
344 uint32_t longpreambleonly;
345 struct uath_cmd_rateset rateset;
349 /* structure for command WDCMSG_CREATE_CONNECTION */
350 struct uath_cmd_create_connection {
354 struct uath_cmd_connection_attr connattr;
357 struct uath_cmd_txq_setparams { /* WDCMSG_SET_TX_QUEUE_PARAMS */
366 struct uath_cmd_txq_attr {
376 struct uath_cmd_txq_setup { /* WDCMSG_SETUP_TX_QUEUE */
379 struct uath_cmd_txq_attr attr;
382 struct uath_cmd_stoptxdma { /* WDCMSG_STOP_TX_DMA */
387 /* structure for command UATH_CMD_31 */
393 struct uath_cmd_rx_filter { /* WDCMSG_RX_FILTER */
395 #define UATH_FILTER_RX_UCAST 0x00000001
396 #define UATH_FILTER_RX_MCAST 0x00000002
397 #define UATH_FILTER_RX_BCAST 0x00000004
398 #define UATH_FILTER_RX_CONTROL 0x00000008
399 #define UATH_FILTER_RX_BEACON 0x00000010 /* beacon frames */
400 #define UATH_FILTER_RX_PROM 0x00000020 /* promiscuous mode */
401 #define UATH_FILTER_RX_PHY_ERR 0x00000040 /* phy errors */
402 #define UATH_FILTER_RX_PHY_RADAR 0x00000080 /* radar phy errors */
403 #define UATH_FILTER_RX_XR_POOL 0x00000400 /* XR group polls */
404 #define UATH_FILTER_RX_PROBE_REQ 0x00000800
406 #define UATH_FILTER_OP_INIT 0x0
407 #define UATH_FILTER_OP_SET 0x1
408 #define UATH_FILTER_OP_CLEAR 0x2
409 #define UATH_FILTER_OP_TEMP 0x3
410 #define UATH_FILTER_OP_RESTORE 0x4
413 struct uath_cmd_rx_mcast_filter { /* WDCMSG_SET_RX_MCAST_FILTER */
418 struct uath_cmd_set_associd { /* WDCMSG_WRITE_ASSOCID */
419 uint32_t defaultrateix;
426 struct uath_cmd_set_stabeacon_timers { /* WDCMSG_SET_STA_BEACON_TIMERS */
430 uint32_t beaconperiod;
433 uint32_t cfpduration;
434 uint32_t sleepduration;
435 uint32_t bsmissthreshold;
439 CFG_NONE, /* Sentinal to indicate "no config" */
440 CFG_REG_DOMAIN, /* Regulatory Domain */
441 CFG_RATE_CONTROL_ENABLE,
442 CFG_DEF_XMIT_DATA_RATE, /* NB: if rate control is not enabled */
445 CFG_SLOW_CLOCK_ENABLE,
447 CFG_USER_RTS_THRESHOLD,
448 CFG_XR2NORM_RATE_THRESHOLD,
449 CFG_XRMODE_SWITCH_COUNT,
451 CFG_BURST_SEQ_THRESHOLD,
453 CFG_IQ_LOG_COUNT_MAX,
458 /* MAC Address to use. Overrides EEPROM */
462 /* An ID for use in error & debug messages */
471 CFG_GMODE_PROTECTION,
472 CFG_GMODE_PROTECT_RATE_INDEX,
473 CFG_GMODE_NON_ERP_PREAMBLE,
474 CFG_WDC_TRANSPORT_CHUNK_SIZE,
478 /* Sentinal to indicate "no capability" */
480 CAP_ALL, /* ALL capabilities */
486 CAP_ANALOG_5GHz_REVISION,
487 CAP_ANALOG_2GHz_REVISION,
488 /* Target supports WDC message debug features */
489 CAP_DEBUG_WDCMSG_SUPPORT,
496 CAP_CHAN_SPREAD_SUPPORT,
497 CAP_SLEEP_AFTER_BEACON_BROKEN,
498 CAP_COMPRESS_SUPPORT,
500 CAP_FAST_FRAMES_SUPPORT,
501 CAP_CHAP_TUNING_SUPPORT,
503 CAP_TURBO_PRIME_SUPPORT,
508 CAP_CONNECTION_ID_MAX, /* Should absorb CAP_KEY_CACHE_SIZE */
523 CAP_TWICE_ANTENNAGAIN_5G,
524 CAP_TWICE_ANTENNAGAIN_2G,
528 ST_NONE, /* Sentinal to indicate "no status" */
535 ST_PS_FRAMES_DROPPED,
537 ST_COUNT_OTHER_RX_ANT,
538 ST_USE_FAST_DIVERSITY,
540 ST_RX_GENERATION_NUM,
543 ST_WDC_TRANSPORT_CHUNK_SIZE,
547 BSS_ATTR_BEACON_INTERVAL,
548 BSS_ATTR_DTIM_INTERVAL,
549 BSS_ATTR_CFP_INTERVAL,
550 BSS_ATTR_CFP_MAX_DURATION,
551 BSS_ATTR_ATIM_WINDOW,
552 BSS_ATTR_DEFAULT_RATE_INDEX,
553 BSS_ATTR_SHORT_SLOT_TIME_11g,
554 BSS_ATTR_SLEEP_DURATION,
555 BSS_ATTR_BMISS_THRESHOLD,
556 BSS_ATTR_TPC_POWER_LIMIT,
557 BSS_ATTR_BSS_KEY_UPDATE,
560 struct uath_cmd_update_bss_attribute {
562 uint32_t attribute; /* BSS_ATTR_BEACON_INTERVAL, et al. */
563 uint32_t cfgsize; /* should be zero 0 */
567 struct uath_cmd_update_bss_attribute_key {
569 uint32_t attribute; /* BSS_ATTR_BSS_KEY_UPDATE */
570 uint32_t cfgsize; /* size of remaining data */
572 uint32_t isdefaultkey;
573 uint32_t keyiv; /* IV generation control */
574 uint32_t extkeyiv; /* extended IV for TKIP & CCM */
577 uint32_t initvalue; /* XXX */
579 uint32_t mictxkeyval[2];
580 uint32_t micrxkeyval[2];
588 TARGET_DEVICE_PWRSAVE,
589 TARGET_DEVICE_SUSPEND,
590 TARGET_DEVICE_RESUME,
593 #define UATH_MAX_TXBUFSZ \
594 (sizeof(struct uath_chunk) + sizeof(struct uath_tx_desc) + \
598 * it's not easy to measure how the chunk is passed into the host if the target
599 * passed the multi-chunks so just we check a minimal size we can imagine.
601 #define UATH_MIN_RXBUFSZ (sizeof(struct uath_chunk))