2 * Copyright (c) 2001-2011, Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 #include "opt_ifpoll.h"
35 #include <sys/param.h>
37 #include <sys/endian.h>
38 #include <sys/interrupt.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
44 #include <sys/serialize.h>
45 #include <sys/serialize2.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
49 #include <sys/systm.h>
52 #include <net/ethernet.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/ifq_var.h>
58 #include <net/toeplitz.h>
59 #include <net/toeplitz2.h>
60 #include <net/vlan/if_vlan_var.h>
61 #include <net/vlan/if_vlan_ether.h>
62 #include <net/if_poll.h>
64 #include <netinet/in_systm.h>
65 #include <netinet/in.h>
66 #include <netinet/ip.h>
68 #include <bus/pci/pcivar.h>
69 #include <bus/pci/pcireg.h>
71 #include <dev/netif/ig_hal/e1000_api.h>
72 #include <dev/netif/ig_hal/e1000_82575.h>
73 #include <dev/netif/igb/if_igb.h>
76 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
78 if (sc->rss_debug >= lvl) \
79 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
81 #else /* !IGB_RSS_DEBUG */
82 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
83 #endif /* IGB_RSS_DEBUG */
85 #define IGB_NAME "Intel(R) PRO/1000 "
86 #define IGB_DEVICE(id) \
87 { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
88 #define IGB_DEVICE_NULL { 0, 0, NULL }
90 static struct igb_device {
95 IGB_DEVICE(82575EB_COPPER),
96 IGB_DEVICE(82575EB_FIBER_SERDES),
97 IGB_DEVICE(82575GB_QUAD_COPPER),
100 IGB_DEVICE(82576_NS_SERDES),
101 IGB_DEVICE(82576_FIBER),
102 IGB_DEVICE(82576_SERDES),
103 IGB_DEVICE(82576_SERDES_QUAD),
104 IGB_DEVICE(82576_QUAD_COPPER),
105 IGB_DEVICE(82576_QUAD_COPPER_ET2),
106 IGB_DEVICE(82576_VF),
107 IGB_DEVICE(82580_COPPER),
108 IGB_DEVICE(82580_FIBER),
109 IGB_DEVICE(82580_SERDES),
110 IGB_DEVICE(82580_SGMII),
111 IGB_DEVICE(82580_COPPER_DUAL),
112 IGB_DEVICE(82580_QUAD_FIBER),
113 IGB_DEVICE(DH89XXCC_SERDES),
114 IGB_DEVICE(DH89XXCC_SGMII),
115 IGB_DEVICE(DH89XXCC_SFP),
116 IGB_DEVICE(DH89XXCC_BACKPLANE),
117 IGB_DEVICE(I350_COPPER),
118 IGB_DEVICE(I350_FIBER),
119 IGB_DEVICE(I350_SERDES),
120 IGB_DEVICE(I350_SGMII),
122 IGB_DEVICE(I210_COPPER),
123 IGB_DEVICE(I210_COPPER_IT),
124 IGB_DEVICE(I210_COPPER_OEM1),
125 IGB_DEVICE(I210_COPPER_FLASHLESS),
126 IGB_DEVICE(I210_SERDES_FLASHLESS),
127 IGB_DEVICE(I210_FIBER),
128 IGB_DEVICE(I210_SERDES),
129 IGB_DEVICE(I210_SGMII),
130 IGB_DEVICE(I211_COPPER),
131 IGB_DEVICE(I354_BACKPLANE_1GBPS),
132 IGB_DEVICE(I354_SGMII),
134 /* required last entry */
138 static int igb_probe(device_t);
139 static int igb_attach(device_t);
140 static int igb_detach(device_t);
141 static int igb_shutdown(device_t);
142 static int igb_suspend(device_t);
143 static int igb_resume(device_t);
145 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
146 static void igb_setup_ifp(struct igb_softc *);
147 static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
148 static int igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
149 static void igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
150 static void igb_add_sysctl(struct igb_softc *);
151 static int igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
152 static int igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
153 static int igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
154 static int igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
155 static int igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
156 static void igb_set_ring_inuse(struct igb_softc *, boolean_t);
157 static int igb_get_rxring_inuse(const struct igb_softc *, boolean_t);
158 static int igb_get_txring_inuse(const struct igb_softc *, boolean_t);
159 static void igb_set_timer_cpuid(struct igb_softc *, boolean_t);
161 static int igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
162 static int igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
165 static void igb_vf_init_stats(struct igb_softc *);
166 static void igb_reset(struct igb_softc *);
167 static void igb_update_stats_counters(struct igb_softc *);
168 static void igb_update_vf_stats_counters(struct igb_softc *);
169 static void igb_update_link_status(struct igb_softc *);
170 static void igb_init_tx_unit(struct igb_softc *);
171 static void igb_init_rx_unit(struct igb_softc *);
173 static void igb_set_vlan(struct igb_softc *);
174 static void igb_set_multi(struct igb_softc *);
175 static void igb_set_promisc(struct igb_softc *);
176 static void igb_disable_promisc(struct igb_softc *);
178 static int igb_alloc_rings(struct igb_softc *);
179 static void igb_free_rings(struct igb_softc *);
180 static int igb_create_tx_ring(struct igb_tx_ring *);
181 static int igb_create_rx_ring(struct igb_rx_ring *);
182 static void igb_free_tx_ring(struct igb_tx_ring *);
183 static void igb_free_rx_ring(struct igb_rx_ring *);
184 static void igb_destroy_tx_ring(struct igb_tx_ring *, int);
185 static void igb_destroy_rx_ring(struct igb_rx_ring *, int);
186 static void igb_init_tx_ring(struct igb_tx_ring *);
187 static int igb_init_rx_ring(struct igb_rx_ring *);
188 static int igb_newbuf(struct igb_rx_ring *, int, boolean_t);
189 static int igb_encap(struct igb_tx_ring *, struct mbuf **, int *, int *);
190 static void igb_rx_refresh(struct igb_rx_ring *, int);
191 static void igb_setup_serializer(struct igb_softc *);
193 static void igb_stop(struct igb_softc *);
194 static void igb_init(void *);
195 static int igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
196 static void igb_media_status(struct ifnet *, struct ifmediareq *);
197 static int igb_media_change(struct ifnet *);
198 static void igb_timer(void *);
199 static void igb_watchdog(struct ifaltq_subque *);
200 static void igb_start(struct ifnet *, struct ifaltq_subque *);
202 static void igb_npoll(struct ifnet *, struct ifpoll_info *);
203 static void igb_npoll_rx(struct ifnet *, void *, int);
204 static void igb_npoll_tx(struct ifnet *, void *, int);
205 static void igb_npoll_status(struct ifnet *);
207 static void igb_serialize(struct ifnet *, enum ifnet_serialize);
208 static void igb_deserialize(struct ifnet *, enum ifnet_serialize);
209 static int igb_tryserialize(struct ifnet *, enum ifnet_serialize);
211 static void igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
215 static void igb_intr(void *);
216 static void igb_intr_shared(void *);
217 static void igb_rxeof(struct igb_rx_ring *, int);
218 static void igb_txeof(struct igb_tx_ring *);
219 static void igb_set_eitr(struct igb_softc *, int, int);
220 static void igb_enable_intr(struct igb_softc *);
221 static void igb_disable_intr(struct igb_softc *);
222 static void igb_init_unshared_intr(struct igb_softc *);
223 static void igb_init_intr(struct igb_softc *);
224 static int igb_setup_intr(struct igb_softc *);
225 static void igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
226 static void igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
227 static void igb_set_intr_mask(struct igb_softc *);
228 static int igb_alloc_intr(struct igb_softc *);
229 static void igb_free_intr(struct igb_softc *);
230 static void igb_teardown_intr(struct igb_softc *);
231 static void igb_msix_try_alloc(struct igb_softc *);
232 static void igb_msix_rx_conf(struct igb_softc *, int, int *, int);
233 static void igb_msix_tx_conf(struct igb_softc *, int, int *, int);
234 static void igb_msix_free(struct igb_softc *, boolean_t);
235 static int igb_msix_setup(struct igb_softc *);
236 static void igb_msix_teardown(struct igb_softc *, int);
237 static void igb_msix_rx(void *);
238 static void igb_msix_tx(void *);
239 static void igb_msix_status(void *);
240 static void igb_msix_rxtx(void *);
242 /* Management and WOL Support */
243 static void igb_get_mgmt(struct igb_softc *);
244 static void igb_rel_mgmt(struct igb_softc *);
245 static void igb_get_hw_control(struct igb_softc *);
246 static void igb_rel_hw_control(struct igb_softc *);
247 static void igb_enable_wol(device_t);
249 static device_method_t igb_methods[] = {
250 /* Device interface */
251 DEVMETHOD(device_probe, igb_probe),
252 DEVMETHOD(device_attach, igb_attach),
253 DEVMETHOD(device_detach, igb_detach),
254 DEVMETHOD(device_shutdown, igb_shutdown),
255 DEVMETHOD(device_suspend, igb_suspend),
256 DEVMETHOD(device_resume, igb_resume),
260 static driver_t igb_driver = {
263 sizeof(struct igb_softc),
266 static devclass_t igb_devclass;
268 DECLARE_DUMMY_MODULE(if_igb);
269 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
270 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
272 static int igb_rxd = IGB_DEFAULT_RXD;
273 static int igb_txd = IGB_DEFAULT_TXD;
274 static int igb_rxr = 0;
275 static int igb_txr = 0;
276 static int igb_msi_enable = 1;
277 static int igb_msix_enable = 1;
278 static int igb_eee_disabled = 1; /* Energy Efficient Ethernet */
279 static int igb_fc_setting = e1000_fc_full;
282 * DMA Coalescing, only for i350 - default to off,
283 * this feature is for power savings
285 static int igb_dma_coalesce = 0;
287 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
288 TUNABLE_INT("hw.igb.txd", &igb_txd);
289 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
290 TUNABLE_INT("hw.igb.txr", &igb_txr);
291 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
292 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
293 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
296 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
297 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
300 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
302 /* Ignore Checksum bit is set */
303 if (staterr & E1000_RXD_STAT_IXSM)
306 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
308 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
310 if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
311 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
312 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
313 CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
314 mp->m_pkthdr.csum_data = htons(0xffff);
319 static __inline struct pktinfo *
320 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
321 uint32_t hash, uint32_t hashtype, uint32_t staterr)
324 case E1000_RXDADV_RSSTYPE_IPV4_TCP:
325 pi->pi_netisr = NETISR_IP;
327 pi->pi_l3proto = IPPROTO_TCP;
330 case E1000_RXDADV_RSSTYPE_IPV4:
331 if (staterr & E1000_RXD_STAT_IXSM)
335 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
336 E1000_RXD_STAT_TCPCS) {
337 pi->pi_netisr = NETISR_IP;
339 pi->pi_l3proto = IPPROTO_UDP;
347 m->m_flags |= M_HASH;
348 m->m_pkthdr.hash = toeplitz_hash(hash);
353 igb_probe(device_t dev)
355 const struct igb_device *d;
358 vid = pci_get_vendor(dev);
359 did = pci_get_device(dev);
361 for (d = igb_devices; d->desc != NULL; ++d) {
362 if (vid == d->vid && did == d->did) {
363 device_set_desc(dev, d->desc);
371 igb_attach(device_t dev)
373 struct igb_softc *sc = device_get_softc(dev);
374 uint16_t eeprom_data;
375 int error = 0, ring_max;
377 int offset, offset_def;
382 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
383 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
384 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
385 igb_sysctl_nvm_info, "I", "NVM Information");
386 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
387 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
388 OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
389 adapter, 0, igb_set_flowcntl, "I", "Flow Control");
392 callout_init_mp(&sc->timer);
393 lwkt_serialize_init(&sc->main_serialize);
395 if_initname(&sc->arpcom.ac_if, device_get_name(dev),
396 device_get_unit(dev));
397 sc->dev = sc->osdep.dev = dev;
400 * Determine hardware and mac type
402 sc->hw.vendor_id = pci_get_vendor(dev);
403 sc->hw.device_id = pci_get_device(dev);
404 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
405 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
406 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
408 if (e1000_set_mac_type(&sc->hw))
411 /* Are we a VF device? */
412 if (sc->hw.mac.type == e1000_vfadapt ||
413 sc->hw.mac.type == e1000_vfadapt_i350)
419 * Configure total supported RX/TX ring count
421 switch (sc->hw.mac.type) {
423 ring_max = IGB_MAX_RING_82575;
427 ring_max = IGB_MAX_RING_82576;
431 ring_max = IGB_MAX_RING_82580;
435 ring_max = IGB_MAX_RING_I350;
439 ring_max = IGB_MAX_RING_I354;
443 ring_max = IGB_MAX_RING_I210;
447 ring_max = IGB_MAX_RING_I211;
451 ring_max = IGB_MIN_RING;
455 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
456 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
458 sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
460 sc->rx_ring_inuse = sc->rx_ring_cnt;
462 sc->tx_ring_cnt = device_getenv_int(dev, "txr", igb_txr);
463 sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, ring_max);
465 sc->tx_ring_cnt = device_getenv_int(dev, "txr_debug", sc->tx_ring_cnt);
467 sc->tx_ring_inuse = sc->tx_ring_cnt;
469 /* Enable bus mastering */
470 pci_enable_busmaster(dev);
475 sc->mem_rid = PCIR_BAR(0);
476 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
478 if (sc->mem_res == NULL) {
479 device_printf(dev, "Unable to allocate bus resource: memory\n");
483 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
484 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
486 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
488 /* Save PCI command register for Shared Code */
489 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
490 sc->hw.back = &sc->osdep;
492 /* Do Shared Code initialization */
493 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
494 device_printf(dev, "Setup of Shared code failed\n");
499 e1000_get_bus_info(&sc->hw);
501 sc->hw.mac.autoneg = DO_AUTO_NEG;
502 sc->hw.phy.autoneg_wait_to_complete = FALSE;
503 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
506 if (sc->hw.phy.media_type == e1000_media_type_copper) {
507 sc->hw.phy.mdix = AUTO_ALL_MODES;
508 sc->hw.phy.disable_polarity_correction = FALSE;
509 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
512 /* Set the frame limits assuming standard ethernet sized frames. */
513 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
515 /* Allocate RX/TX rings */
516 error = igb_alloc_rings(sc);
522 * NPOLLING RX CPU offset
524 if (sc->rx_ring_cnt == ncpus2) {
527 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
528 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
529 if (offset >= ncpus2 ||
530 offset % sc->rx_ring_cnt != 0) {
531 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
536 sc->rx_npoll_off = offset;
539 * NPOLLING TX CPU offset
541 if (sc->tx_ring_cnt == ncpus2) {
544 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
545 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
546 if (offset >= ncpus2 ||
547 offset % sc->tx_ring_cnt != 0) {
548 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
553 sc->tx_npoll_off = offset;
556 /* Allocate interrupt */
557 error = igb_alloc_intr(sc);
561 /* Setup serializers */
562 igb_setup_serializer(sc);
564 /* Allocate the appropriate stats memory */
566 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
568 igb_vf_init_stats(sc);
570 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
574 /* Allocate multicast array memory. */
575 sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
578 /* Some adapter-specific advanced features */
579 if (sc->hw.mac.type >= e1000_i350) {
581 igb_set_sysctl_value(adapter, "dma_coalesce",
582 "configure dma coalesce",
583 &adapter->dma_coalesce, igb_dma_coalesce);
584 igb_set_sysctl_value(adapter, "eee_disabled",
585 "enable Energy Efficient Ethernet",
586 &adapter->hw.dev_spec._82575.eee_disable,
589 sc->dma_coalesce = igb_dma_coalesce;
590 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
592 if (sc->hw.phy.media_type == e1000_media_type_copper) {
593 if (sc->hw.mac.type == e1000_i354)
594 e1000_set_eee_i354(&sc->hw);
596 e1000_set_eee_i350(&sc->hw);
601 * Start from a known state, this is important in reading the nvm and
604 e1000_reset_hw(&sc->hw);
606 /* Make sure we have a good EEPROM before we read from it */
607 if (sc->hw.mac.type != e1000_i210 && sc->hw.mac.type != e1000_i211 &&
608 e1000_validate_nvm_checksum(&sc->hw) < 0) {
610 * Some PCI-E parts fail the first check due to
611 * the link being in sleep state, call it again,
612 * if it fails a second time its a real issue.
614 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
616 "The EEPROM Checksum Is Not Valid\n");
622 /* Copy the permanent MAC address out of the EEPROM */
623 if (e1000_read_mac_addr(&sc->hw) < 0) {
624 device_printf(dev, "EEPROM read error while reading MAC"
629 if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
630 device_printf(dev, "Invalid MAC address\n");
635 /* Setup OS specific network interface */
638 /* Add sysctl tree, must after igb_setup_ifp() */
641 /* Now get a good starting state */
644 /* Initialize statistics */
645 igb_update_stats_counters(sc);
647 sc->hw.mac.get_link_status = 1;
648 igb_update_link_status(sc);
650 /* Indicate SOL/IDER usage */
651 if (e1000_check_reset_block(&sc->hw)) {
653 "PHY reset is blocked due to SOL/IDER session.\n");
656 /* Determine if we have to control management hardware */
657 if (e1000_enable_mng_pass_thru(&sc->hw))
658 sc->flags |= IGB_FLAG_HAS_MGMT;
663 /* APME bit in EEPROM is mapped to WUC.APME */
664 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
666 sc->wol = E1000_WUFC_MAG;
667 /* XXX disable WOL */
671 /* Register for VLAN events */
672 adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
673 igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
674 adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
675 igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
679 igb_add_hw_stats(adapter);
683 * Disable interrupt to prevent spurious interrupts (line based
684 * interrupt, MSI or even MSI-X), which had been observed on
685 * several types of LOMs, from being handled.
687 igb_disable_intr(sc);
689 error = igb_setup_intr(sc);
691 ether_ifdetach(&sc->arpcom.ac_if);
702 igb_detach(device_t dev)
704 struct igb_softc *sc = device_get_softc(dev);
706 if (device_is_attached(dev)) {
707 struct ifnet *ifp = &sc->arpcom.ac_if;
709 ifnet_serialize_all(ifp);
713 e1000_phy_hw_reset(&sc->hw);
715 /* Give control back to firmware */
717 igb_rel_hw_control(sc);
720 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
721 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
725 igb_teardown_intr(sc);
727 ifnet_deserialize_all(ifp);
730 } else if (sc->mem_res != NULL) {
731 igb_rel_hw_control(sc);
733 bus_generic_detach(dev);
737 if (sc->msix_mem_res != NULL) {
738 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
741 if (sc->mem_res != NULL) {
742 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
749 kfree(sc->mta, M_DEVBUF);
750 if (sc->stats != NULL)
751 kfree(sc->stats, M_DEVBUF);
752 if (sc->serializes != NULL)
753 kfree(sc->serializes, M_DEVBUF);
759 igb_shutdown(device_t dev)
761 return igb_suspend(dev);
765 igb_suspend(device_t dev)
767 struct igb_softc *sc = device_get_softc(dev);
768 struct ifnet *ifp = &sc->arpcom.ac_if;
770 ifnet_serialize_all(ifp);
775 igb_rel_hw_control(sc);
778 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
779 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
783 ifnet_deserialize_all(ifp);
785 return bus_generic_suspend(dev);
789 igb_resume(device_t dev)
791 struct igb_softc *sc = device_get_softc(dev);
792 struct ifnet *ifp = &sc->arpcom.ac_if;
795 ifnet_serialize_all(ifp);
800 for (i = 0; i < sc->tx_ring_inuse; ++i)
801 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
803 ifnet_deserialize_all(ifp);
805 return bus_generic_resume(dev);
809 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
811 struct igb_softc *sc = ifp->if_softc;
812 struct ifreq *ifr = (struct ifreq *)data;
813 int max_frame_size, mask, reinit;
816 ASSERT_IFNET_SERIALIZED_ALL(ifp);
820 max_frame_size = 9234;
821 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
827 ifp->if_mtu = ifr->ifr_mtu;
828 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
831 if (ifp->if_flags & IFF_RUNNING)
836 if (ifp->if_flags & IFF_UP) {
837 if (ifp->if_flags & IFF_RUNNING) {
838 if ((ifp->if_flags ^ sc->if_flags) &
839 (IFF_PROMISC | IFF_ALLMULTI)) {
840 igb_disable_promisc(sc);
846 } else if (ifp->if_flags & IFF_RUNNING) {
849 sc->if_flags = ifp->if_flags;
854 if (ifp->if_flags & IFF_RUNNING) {
855 igb_disable_intr(sc);
858 if (!(ifp->if_flags & IFF_NPOLLING))
865 /* Check SOL/IDER usage */
866 if (e1000_check_reset_block(&sc->hw)) {
867 if_printf(ifp, "Media change is "
868 "blocked due to SOL/IDER session.\n");
874 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
879 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
880 if (mask & IFCAP_RXCSUM) {
881 ifp->if_capenable ^= IFCAP_RXCSUM;
884 if (mask & IFCAP_VLAN_HWTAGGING) {
885 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
888 if (mask & IFCAP_TXCSUM) {
889 ifp->if_capenable ^= IFCAP_TXCSUM;
890 if (ifp->if_capenable & IFCAP_TXCSUM)
891 ifp->if_hwassist |= IGB_CSUM_FEATURES;
893 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
895 if (mask & IFCAP_TSO) {
896 ifp->if_capenable ^= IFCAP_TSO;
897 if (ifp->if_capenable & IFCAP_TSO)
898 ifp->if_hwassist |= CSUM_TSO;
900 ifp->if_hwassist &= ~CSUM_TSO;
902 if (mask & IFCAP_RSS)
903 ifp->if_capenable ^= IFCAP_RSS;
904 if (reinit && (ifp->if_flags & IFF_RUNNING))
909 error = ether_ioctl(ifp, command, data);
918 struct igb_softc *sc = xsc;
919 struct ifnet *ifp = &sc->arpcom.ac_if;
923 ASSERT_IFNET_SERIALIZED_ALL(ifp);
927 /* Get the latest mac address, User can use a LAA */
928 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
930 /* Put the address into the Receive Address Array */
931 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
934 igb_update_link_status(sc);
936 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
938 /* Configure for OS presence */
943 if (ifp->if_flags & IFF_NPOLLING)
947 /* Configured used RX/TX rings */
948 igb_set_ring_inuse(sc, polling);
949 ifq_set_subq_mask(&ifp->if_snd, sc->tx_ring_inuse - 1);
951 /* Initialize interrupt */
954 /* Prepare transmit descriptors and buffers */
955 for (i = 0; i < sc->tx_ring_inuse; ++i)
956 igb_init_tx_ring(&sc->tx_rings[i]);
957 igb_init_tx_unit(sc);
959 /* Setup Multicast table */
964 * Figure out the desired mbuf pool
965 * for doing jumbo/packetsplit
967 if (adapter->max_frame_size <= 2048)
968 adapter->rx_mbuf_sz = MCLBYTES;
969 else if (adapter->max_frame_size <= 4096)
970 adapter->rx_mbuf_sz = MJUMPAGESIZE;
972 adapter->rx_mbuf_sz = MJUM9BYTES;
975 /* Prepare receive descriptors and buffers */
976 for (i = 0; i < sc->rx_ring_inuse; ++i) {
979 error = igb_init_rx_ring(&sc->rx_rings[i]);
981 if_printf(ifp, "Could not setup receive structures\n");
986 igb_init_rx_unit(sc);
988 /* Enable VLAN support */
989 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
992 /* Don't lose promiscuous settings */
995 ifp->if_flags |= IFF_RUNNING;
996 for (i = 0; i < sc->tx_ring_inuse; ++i) {
997 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
998 ifsq_watchdog_start(&sc->tx_rings[i].tx_watchdog);
1001 igb_set_timer_cpuid(sc, polling);
1002 callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1003 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1005 /* This clears any pending interrupts */
1006 E1000_READ_REG(&sc->hw, E1000_ICR);
1009 * Only enable interrupts if we are not polling, make sure
1010 * they are off otherwise.
1013 igb_disable_intr(sc);
1015 igb_enable_intr(sc);
1016 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
1019 /* Set Energy Efficient Ethernet */
1020 if (sc->hw.phy.media_type == e1000_media_type_copper) {
1021 if (sc->hw.mac.type == e1000_i354)
1022 e1000_set_eee_i354(&sc->hw);
1024 e1000_set_eee_i350(&sc->hw);
1029 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1031 struct igb_softc *sc = ifp->if_softc;
1033 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1035 if ((ifp->if_flags & IFF_RUNNING) == 0)
1036 sc->hw.mac.get_link_status = 1;
1037 igb_update_link_status(sc);
1039 ifmr->ifm_status = IFM_AVALID;
1040 ifmr->ifm_active = IFM_ETHER;
1042 if (!sc->link_active)
1045 ifmr->ifm_status |= IFM_ACTIVE;
1047 switch (sc->link_speed) {
1049 ifmr->ifm_active |= IFM_10_T;
1054 * Support for 100Mb SFP - these are Fiber
1055 * but the media type appears as serdes
1057 if (sc->hw.phy.media_type == e1000_media_type_internal_serdes)
1058 ifmr->ifm_active |= IFM_100_FX;
1060 ifmr->ifm_active |= IFM_100_TX;
1064 ifmr->ifm_active |= IFM_1000_T;
1068 if (sc->link_duplex == FULL_DUPLEX)
1069 ifmr->ifm_active |= IFM_FDX;
1071 ifmr->ifm_active |= IFM_HDX;
1075 igb_media_change(struct ifnet *ifp)
1077 struct igb_softc *sc = ifp->if_softc;
1078 struct ifmedia *ifm = &sc->media;
1080 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1082 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1085 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1087 sc->hw.mac.autoneg = DO_AUTO_NEG;
1088 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1094 sc->hw.mac.autoneg = DO_AUTO_NEG;
1095 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1099 sc->hw.mac.autoneg = FALSE;
1100 sc->hw.phy.autoneg_advertised = 0;
1101 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1102 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1104 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1108 sc->hw.mac.autoneg = FALSE;
1109 sc->hw.phy.autoneg_advertised = 0;
1110 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1111 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1113 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1117 if_printf(ifp, "Unsupported media type\n");
1127 igb_set_promisc(struct igb_softc *sc)
1129 struct ifnet *ifp = &sc->arpcom.ac_if;
1130 struct e1000_hw *hw = &sc->hw;
1134 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1138 reg = E1000_READ_REG(hw, E1000_RCTL);
1139 if (ifp->if_flags & IFF_PROMISC) {
1140 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1141 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1142 } else if (ifp->if_flags & IFF_ALLMULTI) {
1143 reg |= E1000_RCTL_MPE;
1144 reg &= ~E1000_RCTL_UPE;
1145 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1150 igb_disable_promisc(struct igb_softc *sc)
1152 struct e1000_hw *hw = &sc->hw;
1153 struct ifnet *ifp = &sc->arpcom.ac_if;
1158 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1161 reg = E1000_READ_REG(hw, E1000_RCTL);
1162 reg &= ~E1000_RCTL_UPE;
1163 if (ifp->if_flags & IFF_ALLMULTI) {
1164 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1166 struct ifmultiaddr *ifma;
1167 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1168 if (ifma->ifma_addr->sa_family != AF_LINK)
1170 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1175 /* Don't disable if in MAX groups */
1176 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1177 reg &= ~E1000_RCTL_MPE;
1178 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1182 igb_set_multi(struct igb_softc *sc)
1184 struct ifnet *ifp = &sc->arpcom.ac_if;
1185 struct ifmultiaddr *ifma;
1186 uint32_t reg_rctl = 0;
1191 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1193 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1194 if (ifma->ifma_addr->sa_family != AF_LINK)
1197 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1200 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1201 &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1205 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1206 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1207 reg_rctl |= E1000_RCTL_MPE;
1208 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1210 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1215 igb_timer(void *xsc)
1217 struct igb_softc *sc = xsc;
1219 lwkt_serialize_enter(&sc->main_serialize);
1221 igb_update_link_status(sc);
1222 igb_update_stats_counters(sc);
1224 callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1226 lwkt_serialize_exit(&sc->main_serialize);
1230 igb_update_link_status(struct igb_softc *sc)
1232 struct ifnet *ifp = &sc->arpcom.ac_if;
1233 struct e1000_hw *hw = &sc->hw;
1234 uint32_t link_check, thstat, ctrl;
1236 link_check = thstat = ctrl = 0;
1238 /* Get the cached link value or read for real */
1239 switch (hw->phy.media_type) {
1240 case e1000_media_type_copper:
1241 if (hw->mac.get_link_status) {
1242 /* Do the work to read phy */
1243 e1000_check_for_link(hw);
1244 link_check = !hw->mac.get_link_status;
1250 case e1000_media_type_fiber:
1251 e1000_check_for_link(hw);
1252 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1255 case e1000_media_type_internal_serdes:
1256 e1000_check_for_link(hw);
1257 link_check = hw->mac.serdes_has_link;
1260 /* VF device is type_unknown */
1261 case e1000_media_type_unknown:
1262 e1000_check_for_link(hw);
1263 link_check = !hw->mac.get_link_status;
1269 /* Check for thermal downshift or shutdown */
1270 if (hw->mac.type == e1000_i350) {
1271 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1272 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1275 /* Now we check if a transition has happened */
1276 if (link_check && sc->link_active == 0) {
1277 e1000_get_speed_and_duplex(hw,
1278 &sc->link_speed, &sc->link_duplex);
1280 const char *flowctl;
1282 /* Get the flow control for display */
1283 switch (hw->fc.current_mode) {
1284 case e1000_fc_rx_pause:
1288 case e1000_fc_tx_pause:
1301 if_printf(ifp, "Link is up %d Mbps %s, "
1302 "Flow control: %s\n",
1304 sc->link_duplex == FULL_DUPLEX ?
1305 "Full Duplex" : "Half Duplex",
1308 sc->link_active = 1;
1310 ifp->if_baudrate = sc->link_speed * 1000000;
1311 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1312 (thstat & E1000_THSTAT_LINK_THROTTLE))
1313 if_printf(ifp, "Link: thermal downshift\n");
1314 /* Delay Link Up for Phy update */
1315 if ((hw->mac.type == e1000_i210 ||
1316 hw->mac.type == e1000_i211) &&
1317 hw->phy.id == I210_I_PHY_ID)
1318 msec_delay(IGB_I210_LINK_DELAY);
1319 /* This can sleep */
1320 ifp->if_link_state = LINK_STATE_UP;
1321 if_link_state_change(ifp);
1322 } else if (!link_check && sc->link_active == 1) {
1323 ifp->if_baudrate = sc->link_speed = 0;
1324 sc->link_duplex = 0;
1326 if_printf(ifp, "Link is Down\n");
1327 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1328 (thstat & E1000_THSTAT_PWR_DOWN))
1329 if_printf(ifp, "Link: thermal shutdown\n");
1330 sc->link_active = 0;
1331 /* This can sleep */
1332 ifp->if_link_state = LINK_STATE_DOWN;
1333 if_link_state_change(ifp);
1338 igb_stop(struct igb_softc *sc)
1340 struct ifnet *ifp = &sc->arpcom.ac_if;
1343 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1345 igb_disable_intr(sc);
1347 callout_stop(&sc->timer);
1349 ifp->if_flags &= ~IFF_RUNNING;
1350 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1351 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
1352 ifsq_watchdog_stop(&sc->tx_rings[i].tx_watchdog);
1353 sc->tx_rings[i].tx_flags &= ~IGB_TXFLAG_ENABLED;
1356 e1000_reset_hw(&sc->hw);
1357 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1359 e1000_led_off(&sc->hw);
1360 e1000_cleanup_led(&sc->hw);
1362 for (i = 0; i < sc->tx_ring_cnt; ++i)
1363 igb_free_tx_ring(&sc->tx_rings[i]);
1364 for (i = 0; i < sc->rx_ring_cnt; ++i)
1365 igb_free_rx_ring(&sc->rx_rings[i]);
1369 igb_reset(struct igb_softc *sc)
1371 struct ifnet *ifp = &sc->arpcom.ac_if;
1372 struct e1000_hw *hw = &sc->hw;
1373 struct e1000_fc_info *fc = &hw->fc;
1377 /* Let the firmware know the OS is in control */
1378 igb_get_hw_control(sc);
1381 * Packet Buffer Allocation (PBA)
1382 * Writing PBA sets the receive portion of the buffer
1383 * the remainder is used for the transmit buffer.
1385 switch (hw->mac.type) {
1387 pba = E1000_PBA_32K;
1392 pba = E1000_READ_REG(hw, E1000_RXPBS);
1393 pba &= E1000_RXPBS_SIZE_MASK_82576;
1399 case e1000_vfadapt_i350:
1400 pba = E1000_READ_REG(hw, E1000_RXPBS);
1401 pba = e1000_rxpbs_adjust_82580(pba);
1406 pba = E1000_PBA_34K;
1413 /* Special needs in case of Jumbo frames */
1414 if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1415 uint32_t tx_space, min_tx, min_rx;
1417 pba = E1000_READ_REG(hw, E1000_PBA);
1418 tx_space = pba >> 16;
1421 min_tx = (sc->max_frame_size +
1422 sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1423 min_tx = roundup2(min_tx, 1024);
1425 min_rx = sc->max_frame_size;
1426 min_rx = roundup2(min_rx, 1024);
1428 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1429 pba = pba - (min_tx - tx_space);
1431 * if short on rx space, rx wins
1432 * and must trump tx adjustment
1437 E1000_WRITE_REG(hw, E1000_PBA, pba);
1441 * These parameters control the automatic generation (Tx) and
1442 * response (Rx) to Ethernet PAUSE frames.
1443 * - High water mark should allow for at least two frames to be
1444 * received after sending an XOFF.
1445 * - Low water mark works best when it is very near the high water mark.
1446 * This allows the receiver to restart by sending XON when it has
1449 hwm = min(((pba << 10) * 9 / 10),
1450 ((pba << 10) - 2 * sc->max_frame_size));
1452 if (hw->mac.type < e1000_82576) {
1453 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1454 fc->low_water = fc->high_water - 8;
1456 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1457 fc->low_water = fc->high_water - 16;
1459 fc->pause_time = IGB_FC_PAUSE_TIME;
1460 fc->send_xon = TRUE;
1461 fc->requested_mode = e1000_fc_default;
1463 /* Issue a global reset */
1465 E1000_WRITE_REG(hw, E1000_WUC, 0);
1467 if (e1000_init_hw(hw) < 0)
1468 if_printf(ifp, "Hardware Initialization Failed\n");
1470 /* Setup DMA Coalescing */
1471 if (hw->mac.type > e1000_82580 && hw->mac.type != e1000_i211) {
1475 if (sc->dma_coalesce == 0) {
1479 reg = E1000_READ_REG(hw, E1000_DMACR);
1480 reg &= ~E1000_DMACR_DMAC_EN;
1481 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1485 /* Set starting thresholds */
1486 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0);
1487 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1489 hwm = 64 * pba - sc->max_frame_size / 16;
1490 if (hwm < 64 * (pba - 6))
1491 hwm = 64 * (pba - 6);
1492 reg = E1000_READ_REG(hw, E1000_FCRTC);
1493 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
1494 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
1495 & E1000_FCRTC_RTH_COAL_MASK);
1496 E1000_WRITE_REG(hw, E1000_FCRTC, reg);
1498 dmac = pba - sc->max_frame_size / 512;
1499 if (dmac < pba - 10)
1501 reg = E1000_READ_REG(hw, E1000_DMACR);
1502 reg &= ~E1000_DMACR_DMACTHR_MASK;
1503 reg = ((dmac << E1000_DMACR_DMACTHR_SHIFT)
1504 & E1000_DMACR_DMACTHR_MASK);
1505 /* Transition to L0x or L1 if available.. */
1506 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1507 /* timer = value in sc->dma_coalesce in 32usec intervals */
1508 reg |= (sc->dma_coalesce >> 5);
1509 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1511 /* Set the interval before transition */
1512 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1514 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1516 /* Free space in tx packet buffer to wake from DMA coal */
1517 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1518 (20480 - (2 * sc->max_frame_size)) >> 6);
1520 /* Make low power state decision controlled by DMA coal */
1521 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1522 reg &= ~E1000_PCIEMISC_LX_DECISION;
1523 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg);
1524 if_printf(ifp, "DMA Coalescing enabled\n");
1525 } else if (hw->mac.type == e1000_82580) {
1526 uint32_t reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1528 E1000_WRITE_REG(hw, E1000_DMACR, 0);
1529 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1530 reg & ~E1000_PCIEMISC_LX_DECISION);
1534 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1535 e1000_get_phy_info(hw);
1536 e1000_check_for_link(hw);
1540 igb_setup_ifp(struct igb_softc *sc)
1542 struct ifnet *ifp = &sc->arpcom.ac_if;
1546 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1547 ifp->if_init = igb_init;
1548 ifp->if_ioctl = igb_ioctl;
1549 ifp->if_start = igb_start;
1550 ifp->if_serialize = igb_serialize;
1551 ifp->if_deserialize = igb_deserialize;
1552 ifp->if_tryserialize = igb_tryserialize;
1554 ifp->if_serialize_assert = igb_serialize_assert;
1556 #ifdef IFPOLL_ENABLE
1557 ifp->if_npoll = igb_npoll;
1560 ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1561 ifq_set_ready(&ifp->if_snd);
1562 ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt);
1564 ifp->if_mapsubq = ifq_mapsubq_mask;
1565 ifq_set_subq_mask(&ifp->if_snd, 0);
1567 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1569 ifp->if_capabilities =
1570 IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
1571 if (IGB_ENABLE_HWRSS(sc))
1572 ifp->if_capabilities |= IFCAP_RSS;
1573 ifp->if_capenable = ifp->if_capabilities;
1574 ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1577 * Tell the upper layer(s) we support long frames
1579 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1581 /* Setup TX rings and subqueues */
1582 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1583 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
1584 struct igb_tx_ring *txr = &sc->tx_rings[i];
1586 ifsq_set_cpuid(ifsq, txr->tx_intr_cpuid);
1587 ifsq_set_priv(ifsq, txr);
1588 ifsq_set_hw_serialize(ifsq, &txr->tx_serialize);
1591 ifsq_watchdog_init(&txr->tx_watchdog, ifsq, igb_watchdog);
1595 * Specify the media types supported by this adapter and register
1596 * callbacks to update media and link information
1598 ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1599 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1600 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1601 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1603 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1605 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1606 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1608 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1609 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1611 if (sc->hw.phy.type != e1000_phy_ife) {
1612 ifmedia_add(&sc->media,
1613 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1614 ifmedia_add(&sc->media,
1615 IFM_ETHER | IFM_1000_T, 0, NULL);
1618 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1619 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1623 igb_add_sysctl(struct igb_softc *sc)
1625 struct sysctl_ctx_list *ctx;
1626 struct sysctl_oid *tree;
1630 ctx = device_get_sysctl_ctx(sc->dev);
1631 tree = device_get_sysctl_tree(sc->dev);
1632 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
1633 OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1634 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
1635 OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1636 "# of RX rings used");
1637 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
1638 OID_AUTO, "txr", CTLFLAG_RD, &sc->tx_ring_cnt, 0, "# of TX rings");
1639 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
1640 OID_AUTO, "txr_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
1641 "# of TX rings used");
1642 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
1643 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1645 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
1646 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1649 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1650 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
1651 OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1652 sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1654 for (i = 0; i < sc->msix_cnt; ++i) {
1655 struct igb_msix_data *msix = &sc->msix_data[i];
1657 ksnprintf(node, sizeof(node), "msix%d_rate", i);
1658 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
1659 OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1660 msix, 0, igb_sysctl_msix_rate, "I",
1661 msix->msix_rate_desc);
1665 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
1666 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1667 sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1668 "# of segments per TX interrupt");
1670 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
1671 OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1672 sc, 0, igb_sysctl_tx_wreg_nsegs, "I",
1673 "# of segments sent before write to hardware register");
1675 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
1676 OID_AUTO, "rx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1677 sc, 0, igb_sysctl_rx_wreg_nsegs, "I",
1678 "# of segments received before write to hardware register");
1680 #ifdef IFPOLL_ENABLE
1681 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
1682 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
1683 sc, 0, igb_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1684 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
1685 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
1686 sc, 0, igb_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1689 #ifdef IGB_RSS_DEBUG
1690 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
1691 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1693 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1694 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1695 SYSCTL_ADD_ULONG(ctx,
1696 SYSCTL_CHILDREN(tree), OID_AUTO, node,
1697 CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1700 #ifdef IGB_TSS_DEBUG
1701 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1702 ksnprintf(node, sizeof(node), "tx%d_pkt", i);
1703 SYSCTL_ADD_ULONG(ctx,
1704 SYSCTL_CHILDREN(tree), OID_AUTO, node,
1705 CTLFLAG_RW, &sc->tx_rings[i].tx_packets, "TXed packets");
1711 igb_alloc_rings(struct igb_softc *sc)
1716 * Create top level busdma tag
1718 error = bus_dma_tag_create(NULL, 1, 0,
1719 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1720 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1723 device_printf(sc->dev, "could not create top level DMA tag\n");
1728 * Allocate TX descriptor rings and buffers
1730 sc->tx_rings = kmalloc_cachealign(
1731 sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1732 M_DEVBUF, M_WAITOK | M_ZERO);
1733 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1734 struct igb_tx_ring *txr = &sc->tx_rings[i];
1736 /* Set up some basics */
1739 lwkt_serialize_init(&txr->tx_serialize);
1741 error = igb_create_tx_ring(txr);
1747 * Allocate RX descriptor rings and buffers
1749 sc->rx_rings = kmalloc_cachealign(
1750 sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1751 M_DEVBUF, M_WAITOK | M_ZERO);
1752 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1753 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1755 /* Set up some basics */
1758 lwkt_serialize_init(&rxr->rx_serialize);
1760 error = igb_create_rx_ring(rxr);
1769 igb_free_rings(struct igb_softc *sc)
1773 if (sc->tx_rings != NULL) {
1774 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1775 struct igb_tx_ring *txr = &sc->tx_rings[i];
1777 igb_destroy_tx_ring(txr, txr->num_tx_desc);
1779 kfree(sc->tx_rings, M_DEVBUF);
1782 if (sc->rx_rings != NULL) {
1783 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1784 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1786 igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1788 kfree(sc->rx_rings, M_DEVBUF);
1793 igb_create_tx_ring(struct igb_tx_ring *txr)
1795 int tsize, error, i, ntxd;
1798 * Validate number of transmit descriptors. It must not exceed
1799 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1801 ntxd = device_getenv_int(txr->sc->dev, "txd", igb_txd);
1802 if ((ntxd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN != 0 ||
1803 ntxd > IGB_MAX_TXD || ntxd < IGB_MIN_TXD) {
1804 device_printf(txr->sc->dev,
1805 "Using %d TX descriptors instead of %d!\n",
1806 IGB_DEFAULT_TXD, ntxd);
1807 txr->num_tx_desc = IGB_DEFAULT_TXD;
1809 txr->num_tx_desc = ntxd;
1813 * Allocate TX descriptor ring
1815 tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1817 txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1818 IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1819 &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1820 if (txr->txdma.dma_vaddr == NULL) {
1821 device_printf(txr->sc->dev,
1822 "Unable to allocate TX Descriptor memory\n");
1825 txr->tx_base = txr->txdma.dma_vaddr;
1826 bzero(txr->tx_base, tsize);
1828 tsize = __VM_CACHELINE_ALIGN(
1829 sizeof(struct igb_tx_buf) * txr->num_tx_desc);
1830 txr->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
1833 * Allocate TX head write-back buffer
1835 txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1836 __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1837 &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1838 if (txr->tx_hdr == NULL) {
1839 device_printf(txr->sc->dev,
1840 "Unable to allocate TX head write-back buffer\n");
1845 * Create DMA tag for TX buffers
1847 error = bus_dma_tag_create(txr->sc->parent_tag,
1848 1, 0, /* alignment, bounds */
1849 BUS_SPACE_MAXADDR, /* lowaddr */
1850 BUS_SPACE_MAXADDR, /* highaddr */
1851 NULL, NULL, /* filter, filterarg */
1852 IGB_TSO_SIZE, /* maxsize */
1853 IGB_MAX_SCATTER, /* nsegments */
1854 PAGE_SIZE, /* maxsegsize */
1855 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1856 BUS_DMA_ONEBPAGE, /* flags */
1859 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1860 kfree(txr->tx_buf, M_DEVBUF);
1866 * Create DMA maps for TX buffers
1868 for (i = 0; i < txr->num_tx_desc; ++i) {
1869 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1871 error = bus_dmamap_create(txr->tx_tag,
1872 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1874 device_printf(txr->sc->dev,
1875 "Unable to create TX DMA map\n");
1876 igb_destroy_tx_ring(txr, i);
1881 if (txr->sc->hw.mac.type == e1000_82575)
1882 txr->tx_flags |= IGB_TXFLAG_TSO_IPLEN0;
1885 * Initialize various watermark
1887 txr->spare_desc = IGB_TX_SPARE;
1888 txr->intr_nsegs = txr->num_tx_desc / 16;
1889 txr->wreg_nsegs = IGB_DEF_TXWREG_NSEGS;
1890 txr->oact_hi_desc = txr->num_tx_desc / 2;
1891 txr->oact_lo_desc = txr->num_tx_desc / 8;
1892 if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1893 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1894 if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1895 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1901 igb_free_tx_ring(struct igb_tx_ring *txr)
1905 for (i = 0; i < txr->num_tx_desc; ++i) {
1906 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1908 if (txbuf->m_head != NULL) {
1909 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1910 m_freem(txbuf->m_head);
1911 txbuf->m_head = NULL;
1917 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1921 if (txr->txdma.dma_vaddr != NULL) {
1922 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1923 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1924 txr->txdma.dma_map);
1925 bus_dma_tag_destroy(txr->txdma.dma_tag);
1926 txr->txdma.dma_vaddr = NULL;
1929 if (txr->tx_hdr != NULL) {
1930 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1931 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1933 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1937 if (txr->tx_buf == NULL)
1940 for (i = 0; i < ndesc; ++i) {
1941 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1943 KKASSERT(txbuf->m_head == NULL);
1944 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1946 bus_dma_tag_destroy(txr->tx_tag);
1948 kfree(txr->tx_buf, M_DEVBUF);
1953 igb_init_tx_ring(struct igb_tx_ring *txr)
1955 /* Clear the old descriptor contents */
1957 sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1959 /* Clear TX head write-back buffer */
1963 txr->next_avail_desc = 0;
1964 txr->next_to_clean = 0;
1967 /* Set number of descriptors available */
1968 txr->tx_avail = txr->num_tx_desc;
1970 /* Enable this TX ring */
1971 txr->tx_flags |= IGB_TXFLAG_ENABLED;
1975 igb_init_tx_unit(struct igb_softc *sc)
1977 struct e1000_hw *hw = &sc->hw;
1981 /* Setup the Tx Descriptor Rings */
1982 for (i = 0; i < sc->tx_ring_inuse; ++i) {
1983 struct igb_tx_ring *txr = &sc->tx_rings[i];
1984 uint64_t bus_addr = txr->txdma.dma_paddr;
1985 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1986 uint32_t txdctl = 0;
1987 uint32_t dca_txctrl;
1989 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1990 txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1991 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1992 (uint32_t)(bus_addr >> 32));
1993 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1994 (uint32_t)bus_addr);
1996 /* Setup the HW Tx Head and Tail descriptor pointers */
1997 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1998 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2000 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
2001 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
2002 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
2005 * Don't set WB_on_EITR:
2006 * - 82575 does not have it
2007 * - It almost has no effect on 82576, see:
2008 * 82576 specification update errata #26
2009 * - It causes unnecessary bus traffic
2011 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
2012 (uint32_t)(hdr_paddr >> 32));
2013 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
2014 ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
2017 * WTHRESH is ignored by the hardware, since header
2018 * write back mode is used.
2020 txdctl |= IGB_TX_PTHRESH;
2021 txdctl |= IGB_TX_HTHRESH << 8;
2022 txdctl |= IGB_TX_WTHRESH << 16;
2023 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2024 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2030 e1000_config_collision_dist(hw);
2032 /* Program the Transmit Control Register */
2033 tctl = E1000_READ_REG(hw, E1000_TCTL);
2034 tctl &= ~E1000_TCTL_CT;
2035 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2036 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
2038 /* This write will effectively turn on the transmit unit. */
2039 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2043 igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
2045 struct e1000_adv_tx_context_desc *TXD;
2046 uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
2047 int ehdrlen, ctxd, ip_hlen = 0;
2048 boolean_t offload = TRUE;
2050 if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
2053 vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
2055 ctxd = txr->next_avail_desc;
2056 TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
2059 * In advanced descriptors the vlan tag must
2060 * be placed into the context descriptor, thus
2061 * we need to be here just for that setup.
2063 if (mp->m_flags & M_VLANTAG) {
2066 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
2067 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
2068 } else if (!offload) {
2072 ehdrlen = mp->m_pkthdr.csum_lhlen;
2073 KASSERT(ehdrlen > 0, ("invalid ether hlen"));
2075 /* Set the ether header length */
2076 vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
2077 if (mp->m_pkthdr.csum_flags & CSUM_IP) {
2078 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
2079 ip_hlen = mp->m_pkthdr.csum_iphlen;
2080 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
2082 vlan_macip_lens |= ip_hlen;
2084 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
2085 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
2086 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
2087 else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
2088 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
2091 * 82575 needs the TX context index added; the queue
2092 * index is used as TX context index here.
2094 if (txr->sc->hw.mac.type == e1000_82575)
2095 mss_l4len_idx = txr->me << 4;
2097 /* Now copy bits into descriptor */
2098 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
2099 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
2100 TXD->seqnum_seed = htole32(0);
2101 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
2103 /* We've consumed the first desc, adjust counters */
2104 if (++ctxd == txr->num_tx_desc)
2106 txr->next_avail_desc = ctxd;
2113 igb_txeof(struct igb_tx_ring *txr)
2115 int first, hdr, avail;
2117 if (txr->tx_avail == txr->num_tx_desc)
2120 first = txr->next_to_clean;
2121 hdr = *(txr->tx_hdr);
2126 avail = txr->tx_avail;
2127 while (first != hdr) {
2128 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
2131 if (txbuf->m_head) {
2132 bus_dmamap_unload(txr->tx_tag, txbuf->map);
2133 m_freem(txbuf->m_head);
2134 txbuf->m_head = NULL;
2136 if (++first == txr->num_tx_desc)
2139 txr->next_to_clean = first;
2140 txr->tx_avail = avail;
2143 * If we have a minimum free, clear OACTIVE
2144 * to tell the stack that it is OK to send packets.
2146 if (IGB_IS_NOT_OACTIVE(txr)) {
2147 ifsq_clr_oactive(txr->ifsq);
2150 * We have enough TX descriptors, turn off
2151 * the watchdog. We allow small amount of
2152 * packets (roughly intr_nsegs) pending on
2153 * the transmit ring.
2155 txr->tx_watchdog.wd_timer = 0;
2160 igb_create_rx_ring(struct igb_rx_ring *rxr)
2162 int rsize, i, error, nrxd;
2165 * Validate number of receive descriptors. It must not exceed
2166 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
2168 nrxd = device_getenv_int(rxr->sc->dev, "rxd", igb_rxd);
2169 if ((nrxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN != 0 ||
2170 nrxd > IGB_MAX_RXD || nrxd < IGB_MIN_RXD) {
2171 device_printf(rxr->sc->dev,
2172 "Using %d RX descriptors instead of %d!\n",
2173 IGB_DEFAULT_RXD, nrxd);
2174 rxr->num_rx_desc = IGB_DEFAULT_RXD;
2176 rxr->num_rx_desc = nrxd;
2180 * Allocate RX descriptor ring
2182 rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
2184 rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
2185 IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2186 &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
2187 &rxr->rxdma.dma_paddr);
2188 if (rxr->rxdma.dma_vaddr == NULL) {
2189 device_printf(rxr->sc->dev,
2190 "Unable to allocate RxDescriptor memory\n");
2193 rxr->rx_base = rxr->rxdma.dma_vaddr;
2194 bzero(rxr->rx_base, rsize);
2196 rsize = __VM_CACHELINE_ALIGN(
2197 sizeof(struct igb_rx_buf) * rxr->num_rx_desc);
2198 rxr->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2201 * Create DMA tag for RX buffers
2203 error = bus_dma_tag_create(rxr->sc->parent_tag,
2204 1, 0, /* alignment, bounds */
2205 BUS_SPACE_MAXADDR, /* lowaddr */
2206 BUS_SPACE_MAXADDR, /* highaddr */
2207 NULL, NULL, /* filter, filterarg */
2208 MCLBYTES, /* maxsize */
2210 MCLBYTES, /* maxsegsize */
2211 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2214 device_printf(rxr->sc->dev,
2215 "Unable to create RX payload DMA tag\n");
2216 kfree(rxr->rx_buf, M_DEVBUF);
2222 * Create spare DMA map for RX buffers
2224 error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2227 device_printf(rxr->sc->dev,
2228 "Unable to create spare RX DMA maps\n");
2229 bus_dma_tag_destroy(rxr->rx_tag);
2230 kfree(rxr->rx_buf, M_DEVBUF);
2236 * Create DMA maps for RX buffers
2238 for (i = 0; i < rxr->num_rx_desc; i++) {
2239 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2241 error = bus_dmamap_create(rxr->rx_tag,
2242 BUS_DMA_WAITOK, &rxbuf->map);
2244 device_printf(rxr->sc->dev,
2245 "Unable to create RX DMA maps\n");
2246 igb_destroy_rx_ring(rxr, i);
2252 * Initialize various watermark
2254 rxr->wreg_nsegs = IGB_DEF_RXWREG_NSEGS;
2260 igb_free_rx_ring(struct igb_rx_ring *rxr)
2264 for (i = 0; i < rxr->num_rx_desc; ++i) {
2265 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2267 if (rxbuf->m_head != NULL) {
2268 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2269 m_freem(rxbuf->m_head);
2270 rxbuf->m_head = NULL;
2274 if (rxr->fmp != NULL)
2281 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2285 if (rxr->rxdma.dma_vaddr != NULL) {
2286 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2287 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2288 rxr->rxdma.dma_map);
2289 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2290 rxr->rxdma.dma_vaddr = NULL;
2293 if (rxr->rx_buf == NULL)
2296 for (i = 0; i < ndesc; ++i) {
2297 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2299 KKASSERT(rxbuf->m_head == NULL);
2300 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2302 bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2303 bus_dma_tag_destroy(rxr->rx_tag);
2305 kfree(rxr->rx_buf, M_DEVBUF);
2310 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2312 rxd->read.pkt_addr = htole64(rxbuf->paddr);
2313 rxd->wb.upper.status_error = 0;
2317 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2320 bus_dma_segment_t seg;
2322 struct igb_rx_buf *rxbuf;
2325 m = m_getcl(wait ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR);
2328 if_printf(&rxr->sc->arpcom.ac_if,
2329 "Unable to allocate RX mbuf\n");
2333 m->m_len = m->m_pkthdr.len = MCLBYTES;
2335 if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2336 m_adj(m, ETHER_ALIGN);
2338 error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2339 rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2343 if_printf(&rxr->sc->arpcom.ac_if,
2344 "Unable to load RX mbuf\n");
2349 rxbuf = &rxr->rx_buf[i];
2350 if (rxbuf->m_head != NULL)
2351 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2354 rxbuf->map = rxr->rx_sparemap;
2355 rxr->rx_sparemap = map;
2358 rxbuf->paddr = seg.ds_addr;
2360 igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2365 igb_init_rx_ring(struct igb_rx_ring *rxr)
2369 /* Clear the ring contents */
2371 rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2373 /* Now replenish the ring mbufs */
2374 for (i = 0; i < rxr->num_rx_desc; ++i) {
2377 error = igb_newbuf(rxr, i, TRUE);
2382 /* Setup our descriptor indices */
2383 rxr->next_to_check = 0;
2387 rxr->discard = FALSE;
2393 igb_init_rx_unit(struct igb_softc *sc)
2395 struct ifnet *ifp = &sc->arpcom.ac_if;
2396 struct e1000_hw *hw = &sc->hw;
2397 uint32_t rctl, rxcsum, srrctl = 0;
2401 * Make sure receives are disabled while setting
2402 * up the descriptor ring
2404 rctl = E1000_READ_REG(hw, E1000_RCTL);
2405 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2409 ** Set up for header split
2411 if (igb_header_split) {
2412 /* Use a standard mbuf for the header */
2413 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2414 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2417 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2420 ** Set up for jumbo frames
2422 if (ifp->if_mtu > ETHERMTU) {
2423 rctl |= E1000_RCTL_LPE;
2425 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2426 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2427 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2428 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2429 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2430 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2432 /* Set maximum packet len */
2433 psize = adapter->max_frame_size;
2434 /* are we on a vlan? */
2435 if (adapter->ifp->if_vlantrunk != NULL)
2436 psize += VLAN_TAG_SIZE;
2437 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2439 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2440 rctl |= E1000_RCTL_SZ_2048;
2443 rctl &= ~E1000_RCTL_LPE;
2444 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2445 rctl |= E1000_RCTL_SZ_2048;
2448 /* Setup the Base and Length of the Rx Descriptor Rings */
2449 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2450 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2451 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2454 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2455 rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2456 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2457 (uint32_t)(bus_addr >> 32));
2458 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2459 (uint32_t)bus_addr);
2460 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2461 /* Enable this Queue */
2462 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2463 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2464 rxdctl &= 0xFFF00000;
2465 rxdctl |= IGB_RX_PTHRESH;
2466 rxdctl |= IGB_RX_HTHRESH << 8;
2468 * Don't set WTHRESH to a value above 1 on 82576, see:
2469 * 82576 specification update errata #26
2471 rxdctl |= IGB_RX_WTHRESH << 16;
2472 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2475 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2476 rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2479 * Receive Checksum Offload for TCP and UDP
2481 * Checksum offloading is also enabled if multiple receive
2482 * queue is to be supported, since we need it to figure out
2485 if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2488 * PCSD must be enabled to enable multiple
2491 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2494 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2497 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2499 if (IGB_ENABLE_HWRSS(sc)) {
2500 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2501 uint32_t reta_shift;
2506 * When we reach here, RSS has already been disabled
2507 * in igb_stop(), so we could safely configure RSS key
2508 * and redirect table.
2514 toeplitz_get_key(key, sizeof(key));
2515 for (i = 0; i < IGB_NRSSRK; ++i) {
2518 rssrk = IGB_RSSRK_VAL(key, i);
2519 IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2521 E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2525 * Configure RSS redirect table in following fashion:
2526 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2528 reta_shift = IGB_RETA_SHIFT;
2529 if (hw->mac.type == e1000_82575)
2530 reta_shift = IGB_RETA_SHIFT_82575;
2533 for (j = 0; j < IGB_NRETA; ++j) {
2536 for (i = 0; i < IGB_RETA_SIZE; ++i) {
2539 q = (r % sc->rx_ring_inuse) << reta_shift;
2540 reta |= q << (8 * i);
2543 IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2544 E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2548 * Enable multiple receive queues.
2549 * Enable IPv4 RSS standard hash functions.
2550 * Disable RSS interrupt on 82575
2552 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2553 E1000_MRQC_ENABLE_RSS_4Q |
2554 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2555 E1000_MRQC_RSS_FIELD_IPV4);
2558 /* Setup the Receive Control Register */
2559 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2560 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2561 E1000_RCTL_RDMTS_HALF |
2562 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2563 /* Strip CRC bytes. */
2564 rctl |= E1000_RCTL_SECRC;
2565 /* Make sure VLAN Filters are off */
2566 rctl &= ~E1000_RCTL_VFE;
2567 /* Don't store bad packets */
2568 rctl &= ~E1000_RCTL_SBP;
2570 /* Enable Receives */
2571 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2574 * Setup the HW Rx Head and Tail Descriptor Pointers
2575 * - needs to be after enable
2577 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2578 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2580 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2581 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2586 igb_rx_refresh(struct igb_rx_ring *rxr, int i)
2589 i = rxr->num_rx_desc - 1;
2590 E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2594 igb_rxeof(struct igb_rx_ring *rxr, int count)
2596 struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2597 union e1000_adv_rx_desc *cur;
2599 int i, ncoll = 0, cpuid = mycpuid;
2601 i = rxr->next_to_check;
2602 cur = &rxr->rx_base[i];
2603 staterr = le32toh(cur->wb.upper.status_error);
2605 if ((staterr & E1000_RXD_STAT_DD) == 0)
2608 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2609 struct pktinfo *pi = NULL, pi0;
2610 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2611 struct mbuf *m = NULL;
2614 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2619 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2621 struct mbuf *mp = rxbuf->m_head;
2622 uint32_t hash, hashtype;
2626 len = le16toh(cur->wb.upper.length);
2627 if ((rxr->sc->hw.mac.type == e1000_i350 ||
2628 rxr->sc->hw.mac.type == e1000_i354) &&
2629 (staterr & E1000_RXDEXT_STATERR_LB))
2630 vlan = be16toh(cur->wb.upper.vlan);
2632 vlan = le16toh(cur->wb.upper.vlan);
2634 hash = le32toh(cur->wb.lower.hi_dword.rss);
2635 hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2636 E1000_RXDADV_RSSTYPE_MASK;
2638 IGB_RSS_DPRINTF(rxr->sc, 10,
2639 "ring%d, hash 0x%08x, hashtype %u\n",
2640 rxr->me, hash, hashtype);
2642 bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2643 BUS_DMASYNC_POSTREAD);
2645 if (igb_newbuf(rxr, i, FALSE) != 0) {
2646 IFNET_STAT_INC(ifp, iqdrops, 1);
2651 if (rxr->fmp == NULL) {
2652 mp->m_pkthdr.len = len;
2656 rxr->lmp->m_next = mp;
2657 rxr->lmp = rxr->lmp->m_next;
2658 rxr->fmp->m_pkthdr.len += len;
2666 m->m_pkthdr.rcvif = ifp;
2667 IFNET_STAT_INC(ifp, ipackets, 1);
2669 if (ifp->if_capenable & IFCAP_RXCSUM)
2670 igb_rxcsum(staterr, m);
2672 if (staterr & E1000_RXD_STAT_VP) {
2673 m->m_pkthdr.ether_vlantag = vlan;
2674 m->m_flags |= M_VLANTAG;
2677 if (ifp->if_capenable & IFCAP_RSS) {
2678 pi = igb_rssinfo(m, &pi0,
2679 hash, hashtype, staterr);
2681 #ifdef IGB_RSS_DEBUG
2686 IFNET_STAT_INC(ifp, ierrors, 1);
2688 igb_setup_rxdesc(cur, rxbuf);
2690 rxr->discard = TRUE;
2692 rxr->discard = FALSE;
2693 if (rxr->fmp != NULL) {
2702 ifp->if_input(ifp, m, pi, cpuid);
2704 /* Advance our pointers to the next descriptor. */
2705 if (++i == rxr->num_rx_desc)
2708 if (ncoll >= rxr->wreg_nsegs) {
2709 igb_rx_refresh(rxr, i);
2713 cur = &rxr->rx_base[i];
2714 staterr = le32toh(cur->wb.upper.status_error);
2716 rxr->next_to_check = i;
2719 igb_rx_refresh(rxr, i);
2724 igb_set_vlan(struct igb_softc *sc)
2726 struct e1000_hw *hw = &sc->hw;
2729 struct ifnet *ifp = sc->arpcom.ac_if;
2733 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2737 reg = E1000_READ_REG(hw, E1000_CTRL);
2738 reg |= E1000_CTRL_VME;
2739 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2742 /* Enable the Filter Table */
2743 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2744 reg = E1000_READ_REG(hw, E1000_RCTL);
2745 reg &= ~E1000_RCTL_CFIEN;
2746 reg |= E1000_RCTL_VFE;
2747 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2751 /* Update the frame size */
2752 E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2753 sc->max_frame_size + VLAN_TAG_SIZE);
2756 /* Don't bother with table if no vlans */
2757 if ((adapter->num_vlans == 0) ||
2758 ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2761 ** A soft reset zero's out the VFTA, so
2762 ** we need to repopulate it now.
2764 for (int i = 0; i < IGB_VFTA_SIZE; i++)
2765 if (adapter->shadow_vfta[i] != 0) {
2766 if (adapter->vf_ifp)
2767 e1000_vfta_set_vf(hw,
2768 adapter->shadow_vfta[i], TRUE);
2770 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2771 i, adapter->shadow_vfta[i]);
2777 igb_enable_intr(struct igb_softc *sc)
2779 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2780 lwkt_serialize_handler_enable(&sc->main_serialize);
2784 for (i = 0; i < sc->msix_cnt; ++i) {
2785 lwkt_serialize_handler_enable(
2786 sc->msix_data[i].msix_serialize);
2790 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2791 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2792 E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2794 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2795 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2796 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2797 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2799 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2801 E1000_WRITE_FLUSH(&sc->hw);
2805 igb_disable_intr(struct igb_softc *sc)
2807 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2808 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2809 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2811 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2812 E1000_WRITE_FLUSH(&sc->hw);
2814 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2815 lwkt_serialize_handler_disable(&sc->main_serialize);
2819 for (i = 0; i < sc->msix_cnt; ++i) {
2820 lwkt_serialize_handler_disable(
2821 sc->msix_data[i].msix_serialize);
2827 * Bit of a misnomer, what this really means is
2828 * to enable OS management of the system... aka
2829 * to disable special hardware management features
2832 igb_get_mgmt(struct igb_softc *sc)
2834 if (sc->flags & IGB_FLAG_HAS_MGMT) {
2835 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2836 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2838 /* disable hardware interception of ARP */
2839 manc &= ~E1000_MANC_ARP_EN;
2841 /* enable receiving management packets to the host */
2842 manc |= E1000_MANC_EN_MNG2HOST;
2843 manc2h |= 1 << 5; /* Mng Port 623 */
2844 manc2h |= 1 << 6; /* Mng Port 664 */
2845 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2846 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2851 * Give control back to hardware management controller
2855 igb_rel_mgmt(struct igb_softc *sc)
2857 if (sc->flags & IGB_FLAG_HAS_MGMT) {
2858 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2860 /* Re-enable hardware interception of ARP */
2861 manc |= E1000_MANC_ARP_EN;
2862 manc &= ~E1000_MANC_EN_MNG2HOST;
2864 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2869 * Sets CTRL_EXT:DRV_LOAD bit.
2871 * For ASF and Pass Through versions of f/w this means that
2872 * the driver is loaded.
2875 igb_get_hw_control(struct igb_softc *sc)
2882 /* Let firmware know the driver has taken over */
2883 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2884 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2885 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2889 * Resets CTRL_EXT:DRV_LOAD bit.
2891 * For ASF and Pass Through versions of f/w this means that the
2892 * driver is no longer loaded.
2895 igb_rel_hw_control(struct igb_softc *sc)
2902 /* Let firmware taken over control of h/w */
2903 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2904 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2905 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2909 igb_is_valid_ether_addr(const uint8_t *addr)
2911 uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2913 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2919 * Enable PCI Wake On Lan capability
2922 igb_enable_wol(device_t dev)
2924 uint16_t cap, status;
2927 /* First find the capabilities pointer*/
2928 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2930 /* Read the PM Capabilities */
2931 id = pci_read_config(dev, cap, 1);
2932 if (id != PCIY_PMG) /* Something wrong */
2936 * OK, we have the power capabilities,
2937 * so now get the status register
2939 cap += PCIR_POWER_STATUS;
2940 status = pci_read_config(dev, cap, 2);
2941 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2942 pci_write_config(dev, cap, status, 2);
2946 igb_update_stats_counters(struct igb_softc *sc)
2948 struct e1000_hw *hw = &sc->hw;
2949 struct e1000_hw_stats *stats;
2950 struct ifnet *ifp = &sc->arpcom.ac_if;
2953 * The virtual function adapter has only a
2954 * small controlled set of stats, do only
2958 igb_update_vf_stats_counters(sc);
2963 if (sc->hw.phy.media_type == e1000_media_type_copper ||
2964 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2966 E1000_READ_REG(hw,E1000_SYMERRS);
2967 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2970 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2971 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2972 stats->scc += E1000_READ_REG(hw, E1000_SCC);
2973 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2975 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2976 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2977 stats->colc += E1000_READ_REG(hw, E1000_COLC);
2978 stats->dc += E1000_READ_REG(hw, E1000_DC);
2979 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2980 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2981 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2984 * For watchdog management we need to know if we have been
2985 * paused during the last interval, so capture that here.
2987 sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2988 stats->xoffrxc += sc->pause_frames;
2989 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2990 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2991 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2992 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2993 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2994 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2995 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2996 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2997 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2998 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2999 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
3000 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
3002 /* For the 64-bit byte counters the low dword must be read first. */
3003 /* Both registers clear on the read of the high dword */
3005 stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
3006 ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
3007 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
3008 ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
3010 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
3011 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
3012 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
3013 stats->roc += E1000_READ_REG(hw, E1000_ROC);
3014 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
3016 stats->tor += E1000_READ_REG(hw, E1000_TORH);
3017 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
3019 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
3020 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
3021 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
3022 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
3023 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
3024 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
3025 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
3026 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
3027 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
3028 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
3030 /* Interrupt Counts */
3032 stats->iac += E1000_READ_REG(hw, E1000_IAC);
3033 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
3034 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
3035 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
3036 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
3037 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
3038 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
3039 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
3040 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
3042 /* Host to Card Statistics */
3044 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
3045 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
3046 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
3047 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
3048 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
3049 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
3050 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
3051 stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
3052 ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
3053 stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
3054 ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
3055 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
3056 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
3057 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
3059 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
3060 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
3061 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
3062 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
3063 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
3064 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
3066 IFNET_STAT_SET(ifp, collisions, stats->colc);
3069 IFNET_STAT_SET(ifp, ierrors,
3070 stats->rxerrc + stats->crcerrs + stats->algnerrc +
3071 stats->ruc + stats->roc + stats->mpc + stats->cexterr);
3074 IFNET_STAT_SET(ifp, oerrors,
3075 stats->ecol + stats->latecol + sc->watchdog_events);
3077 /* Driver specific counters */
3078 sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
3079 sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
3080 sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
3081 sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
3082 sc->packet_buf_alloc_tx =
3083 ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
3084 sc->packet_buf_alloc_rx =
3085 (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
3089 igb_vf_init_stats(struct igb_softc *sc)
3091 struct e1000_hw *hw = &sc->hw;
3092 struct e1000_vf_stats *stats;
3095 stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
3096 stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
3097 stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
3098 stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
3099 stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
3103 igb_update_vf_stats_counters(struct igb_softc *sc)
3105 struct e1000_hw *hw = &sc->hw;
3106 struct e1000_vf_stats *stats;
3108 if (sc->link_speed == 0)
3112 UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
3113 UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
3114 UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
3115 UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
3116 UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
3119 #ifdef IFPOLL_ENABLE
3122 igb_npoll_status(struct ifnet *ifp)
3124 struct igb_softc *sc = ifp->if_softc;
3127 ASSERT_SERIALIZED(&sc->main_serialize);
3129 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3130 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3131 sc->hw.mac.get_link_status = 1;
3132 igb_update_link_status(sc);
3137 igb_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
3139 struct igb_tx_ring *txr = arg;
3141 ASSERT_SERIALIZED(&txr->tx_serialize);
3144 if (!ifsq_is_empty(txr->ifsq))
3145 ifsq_devstart(txr->ifsq);
3149 igb_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
3151 struct igb_rx_ring *rxr = arg;
3153 ASSERT_SERIALIZED(&rxr->rx_serialize);
3155 igb_rxeof(rxr, cycle);
3159 igb_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3161 struct igb_softc *sc = ifp->if_softc;
3162 int i, txr_cnt, rxr_cnt;
3164 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3169 info->ifpi_status.status_func = igb_npoll_status;
3170 info->ifpi_status.serializer = &sc->main_serialize;
3172 txr_cnt = igb_get_txring_inuse(sc, TRUE);
3173 off = sc->tx_npoll_off;
3174 for (i = 0; i < txr_cnt; ++i) {
3175 struct igb_tx_ring *txr = &sc->tx_rings[i];
3178 KKASSERT(idx < ncpus2);
3179 info->ifpi_tx[idx].poll_func = igb_npoll_tx;
3180 info->ifpi_tx[idx].arg = txr;
3181 info->ifpi_tx[idx].serializer = &txr->tx_serialize;
3182 ifsq_set_cpuid(txr->ifsq, idx);
3185 rxr_cnt = igb_get_rxring_inuse(sc, TRUE);
3186 off = sc->rx_npoll_off;
3187 for (i = 0; i < rxr_cnt; ++i) {
3188 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3191 KKASSERT(idx < ncpus2);
3192 info->ifpi_rx[idx].poll_func = igb_npoll_rx;
3193 info->ifpi_rx[idx].arg = rxr;
3194 info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
3197 if (ifp->if_flags & IFF_RUNNING) {
3198 if (rxr_cnt == sc->rx_ring_inuse &&
3199 txr_cnt == sc->tx_ring_inuse) {
3200 igb_set_timer_cpuid(sc, TRUE);
3201 igb_disable_intr(sc);
3207 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3208 struct igb_tx_ring *txr = &sc->tx_rings[i];
3210 ifsq_set_cpuid(txr->ifsq, txr->tx_intr_cpuid);
3213 if (ifp->if_flags & IFF_RUNNING) {
3214 txr_cnt = igb_get_txring_inuse(sc, FALSE);
3215 rxr_cnt = igb_get_rxring_inuse(sc, FALSE);
3217 if (rxr_cnt == sc->rx_ring_inuse &&
3218 txr_cnt == sc->tx_ring_inuse) {
3219 igb_set_timer_cpuid(sc, FALSE);
3220 igb_enable_intr(sc);
3228 #endif /* IFPOLL_ENABLE */
3233 struct igb_softc *sc = xsc;
3234 struct ifnet *ifp = &sc->arpcom.ac_if;
3237 ASSERT_SERIALIZED(&sc->main_serialize);
3239 eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
3244 if (ifp->if_flags & IFF_RUNNING) {
3245 struct igb_tx_ring *txr = &sc->tx_rings[0];
3248 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3249 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3251 if (eicr & rxr->rx_intr_mask) {
3252 lwkt_serialize_enter(&rxr->rx_serialize);
3254 lwkt_serialize_exit(&rxr->rx_serialize);
3258 if (eicr & txr->tx_intr_mask) {
3259 lwkt_serialize_enter(&txr->tx_serialize);
3261 if (!ifsq_is_empty(txr->ifsq))
3262 ifsq_devstart(txr->ifsq);
3263 lwkt_serialize_exit(&txr->tx_serialize);
3267 if (eicr & E1000_EICR_OTHER) {
3268 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3270 /* Link status change */
3271 if (icr & E1000_ICR_LSC) {
3272 sc->hw.mac.get_link_status = 1;
3273 igb_update_link_status(sc);
3278 * Reading EICR has the side effect to clear interrupt mask,
3279 * so all interrupts need to be enabled here.
3281 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3285 igb_intr_shared(void *xsc)
3287 struct igb_softc *sc = xsc;
3288 struct ifnet *ifp = &sc->arpcom.ac_if;
3291 ASSERT_SERIALIZED(&sc->main_serialize);
3293 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3296 if (reg_icr == 0xffffffff)
3299 /* Definitely not our interrupt. */
3303 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3306 if (ifp->if_flags & IFF_RUNNING) {
3308 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3311 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3312 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3314 lwkt_serialize_enter(&rxr->rx_serialize);
3316 lwkt_serialize_exit(&rxr->rx_serialize);
3320 if (reg_icr & E1000_ICR_TXDW) {
3321 struct igb_tx_ring *txr = &sc->tx_rings[0];
3323 lwkt_serialize_enter(&txr->tx_serialize);
3325 if (!ifsq_is_empty(txr->ifsq))
3326 ifsq_devstart(txr->ifsq);
3327 lwkt_serialize_exit(&txr->tx_serialize);
3331 /* Link status change */
3332 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3333 sc->hw.mac.get_link_status = 1;
3334 igb_update_link_status(sc);
3337 if (reg_icr & E1000_ICR_RXO)
3342 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp,
3343 int *segs_used, int *idx)
3345 bus_dma_segment_t segs[IGB_MAX_SCATTER];
3347 struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3348 union e1000_adv_tx_desc *txd = NULL;
3349 struct mbuf *m_head = *m_headp;
3350 uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3351 int maxsegs, nsegs, i, j, error;
3352 uint32_t hdrlen = 0;
3354 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3355 error = igb_tso_pullup(txr, m_headp);
3361 /* Set basic descriptor constants */
3362 cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3363 cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3364 if (m_head->m_flags & M_VLANTAG)
3365 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3368 * Map the packet for DMA.
3370 tx_buf = &txr->tx_buf[txr->next_avail_desc];
3371 tx_buf_mapped = tx_buf;
3374 maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3375 KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3376 if (maxsegs > IGB_MAX_SCATTER)
3377 maxsegs = IGB_MAX_SCATTER;
3379 error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3380 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3382 if (error == ENOBUFS)
3383 txr->sc->mbuf_defrag_failed++;
3385 txr->sc->no_tx_dma_setup++;
3391 bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3396 * Set up the TX context descriptor, if any hardware offloading is
3397 * needed. This includes CSUM, VLAN, and TSO. It will consume one
3400 * Unlike these chips' predecessors (em/emx), TX context descriptor
3401 * will _not_ interfere TX data fetching pipelining.
3403 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3404 igb_tso_ctx(txr, m_head, &hdrlen);
3405 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3406 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3407 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3410 } else if (igb_txcsum_ctx(txr, m_head)) {
3411 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3412 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3413 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3414 olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3419 *segs_used += nsegs;
3420 txr->tx_nsegs += nsegs;
3421 if (txr->tx_nsegs >= txr->intr_nsegs) {
3423 * Report Status (RS) is turned on every intr_nsegs
3424 * descriptors (roughly).
3427 cmd_rs = E1000_ADVTXD_DCMD_RS;
3430 /* Calculate payload length */
3431 olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3432 << E1000_ADVTXD_PAYLEN_SHIFT);
3435 * 82575 needs the TX context index added; the queue
3436 * index is used as TX context index here.
3438 if (txr->sc->hw.mac.type == e1000_82575)
3439 olinfo_status |= txr->me << 4;
3441 /* Set up our transmit descriptors */
3442 i = txr->next_avail_desc;
3443 for (j = 0; j < nsegs; j++) {
3445 bus_addr_t seg_addr;
3447 tx_buf = &txr->tx_buf[i];
3448 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3449 seg_addr = segs[j].ds_addr;
3450 seg_len = segs[j].ds_len;
3452 txd->read.buffer_addr = htole64(seg_addr);
3453 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3454 txd->read.olinfo_status = htole32(olinfo_status);
3455 if (++i == txr->num_tx_desc)
3457 tx_buf->m_head = NULL;
3460 KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3461 txr->next_avail_desc = i;
3462 txr->tx_avail -= nsegs;
3464 tx_buf->m_head = m_head;
3465 tx_buf_mapped->map = tx_buf->map;
3469 * Last Descriptor of Packet needs End Of Packet (EOP)
3471 txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3474 * Defer TDT updating, until enough descrptors are setup
3477 #ifdef IGB_TSS_DEBUG
3485 igb_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3487 struct igb_softc *sc = ifp->if_softc;
3488 struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3489 struct mbuf *m_head;
3490 int idx = -1, nsegs = 0;
3492 KKASSERT(txr->ifsq == ifsq);
3493 ASSERT_SERIALIZED(&txr->tx_serialize);
3495 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
3498 if (!sc->link_active || (txr->tx_flags & IGB_TXFLAG_ENABLED) == 0) {
3503 if (!IGB_IS_NOT_OACTIVE(txr))
3506 while (!ifsq_is_empty(ifsq)) {
3507 if (IGB_IS_OACTIVE(txr)) {
3508 ifsq_set_oactive(ifsq);
3509 /* Set watchdog on */
3510 txr->tx_watchdog.wd_timer = 5;
3514 m_head = ifsq_dequeue(ifsq);
3518 if (igb_encap(txr, &m_head, &nsegs, &idx)) {
3519 IFNET_STAT_INC(ifp, oerrors, 1);
3524 * TX interrupt are aggressively aggregated, so increasing
3525 * opackets at TX interrupt time will make the opackets
3526 * statistics vastly inaccurate; we do the opackets increment
3529 IFNET_STAT_INC(ifp, opackets, 1);
3531 if (nsegs >= txr->wreg_nsegs) {
3532 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3537 /* Send a copy of the frame to the BPF listener */
3538 ETHER_BPF_MTAP(ifp, m_head);
3541 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3545 igb_watchdog(struct ifaltq_subque *ifsq)
3547 struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3548 struct ifnet *ifp = ifsq_get_ifp(ifsq);
3549 struct igb_softc *sc = ifp->if_softc;
3552 KKASSERT(txr->ifsq == ifsq);
3553 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3556 * If flow control has paused us since last checking
3557 * it invalidates the watchdog timing, so dont run it.
3559 if (sc->pause_frames) {
3560 sc->pause_frames = 0;
3561 txr->tx_watchdog.wd_timer = 5;
3565 if_printf(ifp, "Watchdog timeout -- resetting\n");
3566 if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3567 E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3568 E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3569 if_printf(ifp, "TX(%d) desc avail = %d, "
3570 "Next TX to Clean = %d\n",
3571 txr->me, txr->tx_avail, txr->next_to_clean);
3573 IFNET_STAT_INC(ifp, oerrors, 1);
3574 sc->watchdog_events++;
3577 for (i = 0; i < sc->tx_ring_inuse; ++i)
3578 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
3582 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3587 if (sc->hw.mac.type == e1000_82575) {
3588 eitr = 1000000000 / 256 / rate;
3591 * Document is wrong on the 2 bits left shift
3594 eitr = 1000000 / rate;
3595 eitr <<= IGB_EITR_INTVL_SHIFT;
3599 /* Don't disable it */
3600 eitr = 1 << IGB_EITR_INTVL_SHIFT;
3601 } else if (eitr > IGB_EITR_INTVL_MASK) {
3602 /* Don't allow it to be too large */
3603 eitr = IGB_EITR_INTVL_MASK;
3606 if (sc->hw.mac.type == e1000_82575)
3609 eitr |= E1000_EITR_CNT_IGNR;
3610 E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3614 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3616 struct igb_softc *sc = (void *)arg1;
3617 struct ifnet *ifp = &sc->arpcom.ac_if;
3618 int error, intr_rate;
3620 intr_rate = sc->intr_rate;
3621 error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3622 if (error || req->newptr == NULL)
3627 ifnet_serialize_all(ifp);
3629 sc->intr_rate = intr_rate;
3630 if (ifp->if_flags & IFF_RUNNING)
3631 igb_set_eitr(sc, 0, sc->intr_rate);
3634 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3636 ifnet_deserialize_all(ifp);
3642 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3644 struct igb_msix_data *msix = (void *)arg1;
3645 struct igb_softc *sc = msix->msix_sc;
3646 struct ifnet *ifp = &sc->arpcom.ac_if;
3647 int error, msix_rate;
3649 msix_rate = msix->msix_rate;
3650 error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3651 if (error || req->newptr == NULL)
3656 lwkt_serialize_enter(msix->msix_serialize);
3658 msix->msix_rate = msix_rate;
3659 if (ifp->if_flags & IFF_RUNNING)
3660 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3663 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3667 lwkt_serialize_exit(msix->msix_serialize);
3673 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3675 struct igb_softc *sc = (void *)arg1;
3676 struct ifnet *ifp = &sc->arpcom.ac_if;
3677 struct igb_tx_ring *txr = &sc->tx_rings[0];
3680 nsegs = txr->intr_nsegs;
3681 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3682 if (error || req->newptr == NULL)
3687 ifnet_serialize_all(ifp);
3689 if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3690 nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3696 for (i = 0; i < sc->tx_ring_cnt; ++i)
3697 sc->tx_rings[i].intr_nsegs = nsegs;
3700 ifnet_deserialize_all(ifp);
3706 igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3708 struct igb_softc *sc = (void *)arg1;
3709 struct ifnet *ifp = &sc->arpcom.ac_if;
3710 int error, nsegs, i;
3712 nsegs = sc->rx_rings[0].wreg_nsegs;
3713 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3714 if (error || req->newptr == NULL)
3717 ifnet_serialize_all(ifp);
3718 for (i = 0; i < sc->rx_ring_cnt; ++i)
3719 sc->rx_rings[i].wreg_nsegs =nsegs;
3720 ifnet_deserialize_all(ifp);
3726 igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3728 struct igb_softc *sc = (void *)arg1;
3729 struct ifnet *ifp = &sc->arpcom.ac_if;
3730 int error, nsegs, i;
3732 nsegs = sc->tx_rings[0].wreg_nsegs;
3733 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3734 if (error || req->newptr == NULL)
3737 ifnet_serialize_all(ifp);
3738 for (i = 0; i < sc->tx_ring_cnt; ++i)
3739 sc->tx_rings[i].wreg_nsegs =nsegs;
3740 ifnet_deserialize_all(ifp);
3745 #ifdef IFPOLL_ENABLE
3748 igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3750 struct igb_softc *sc = (void *)arg1;
3751 struct ifnet *ifp = &sc->arpcom.ac_if;
3754 off = sc->rx_npoll_off;
3755 error = sysctl_handle_int(oidp, &off, 0, req);
3756 if (error || req->newptr == NULL)
3761 ifnet_serialize_all(ifp);
3762 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3766 sc->rx_npoll_off = off;
3768 ifnet_deserialize_all(ifp);
3774 igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3776 struct igb_softc *sc = (void *)arg1;
3777 struct ifnet *ifp = &sc->arpcom.ac_if;
3780 off = sc->tx_npoll_off;
3781 error = sysctl_handle_int(oidp, &off, 0, req);
3782 if (error || req->newptr == NULL)
3787 ifnet_serialize_all(ifp);
3788 if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
3792 sc->tx_npoll_off = off;
3794 ifnet_deserialize_all(ifp);
3799 #endif /* IFPOLL_ENABLE */
3802 igb_init_intr(struct igb_softc *sc)
3804 igb_set_intr_mask(sc);
3806 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3807 igb_init_unshared_intr(sc);
3809 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3810 igb_set_eitr(sc, 0, sc->intr_rate);
3814 for (i = 0; i < sc->msix_cnt; ++i)
3815 igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3820 igb_init_unshared_intr(struct igb_softc *sc)
3822 struct e1000_hw *hw = &sc->hw;
3823 const struct igb_rx_ring *rxr;
3824 const struct igb_tx_ring *txr;
3825 uint32_t ivar, index;
3829 * Enable extended mode
3831 if (sc->hw.mac.type != e1000_82575) {
3835 gpie = E1000_GPIE_NSICR;
3836 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3837 gpie |= E1000_GPIE_MSIX_MODE |
3841 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3846 switch (sc->hw.mac.type) {
3848 ivar_max = IGB_MAX_IVAR_82576;
3852 ivar_max = IGB_MAX_IVAR_82580;
3856 ivar_max = IGB_MAX_IVAR_I350;
3860 ivar_max = IGB_MAX_IVAR_I354;
3864 case e1000_vfadapt_i350:
3865 ivar_max = IGB_MAX_IVAR_VF;
3869 ivar_max = IGB_MAX_IVAR_I210;
3873 ivar_max = IGB_MAX_IVAR_I211;
3877 panic("unknown mac type %d\n", sc->hw.mac.type);
3879 for (i = 0; i < ivar_max; ++i)
3880 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3881 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3885 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3886 ("82575 w/ MSI-X"));
3887 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3888 tmp |= E1000_CTRL_EXT_IRCA;
3889 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3893 * Map TX/RX interrupts to EICR
3895 switch (sc->hw.mac.type) {
3900 case e1000_vfadapt_i350:
3904 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3905 rxr = &sc->rx_rings[i];
3908 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3913 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3917 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3919 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3922 for (i = 0; i < sc->tx_ring_inuse; ++i) {
3923 txr = &sc->tx_rings[i];
3926 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3931 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3935 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3937 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3939 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3940 ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3941 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3947 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3948 rxr = &sc->rx_rings[i];
3950 index = i & 0x7; /* Each IVAR has two entries */
3951 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3956 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3960 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3962 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3965 for (i = 0; i < sc->tx_ring_inuse; ++i) {
3966 txr = &sc->tx_rings[i];
3968 index = i & 0x7; /* Each IVAR has two entries */
3969 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3974 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3978 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3980 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3982 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3983 ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3984 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3990 * Enable necessary interrupt bits.
3992 * The name of the register is confusing; in addition to
3993 * configuring the first vector of MSI-X, it also configures
3994 * which bits of EICR could be set by the hardware even when
3995 * MSI or line interrupt is used; it thus controls interrupt
3996 * generation. It MUST be configured explicitly; the default
3997 * value mentioned in the datasheet is wrong: RX queue0 and
3998 * TX queue0 are NOT enabled by default.
4000 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
4004 panic("unknown mac type %d\n", sc->hw.mac.type);
4009 igb_setup_intr(struct igb_softc *sc)
4013 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
4014 return igb_msix_setup(sc);
4016 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
4017 (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
4018 sc, &sc->intr_tag, &sc->main_serialize);
4020 device_printf(sc->dev, "Failed to register interrupt handler");
4027 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
4029 if (txr->sc->hw.mac.type == e1000_82575) {
4030 txr->tx_intr_bit = 0; /* unused */
4033 txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
4036 txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
4039 txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
4042 txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
4045 panic("unsupported # of TX ring, %d\n", txr->me);
4048 int intr_bit = *intr_bit0;
4050 txr->tx_intr_bit = intr_bit % intr_bitmax;
4051 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
4053 *intr_bit0 = intr_bit + 1;
4058 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
4060 if (rxr->sc->hw.mac.type == e1000_82575) {
4061 rxr->rx_intr_bit = 0; /* unused */
4064 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
4067 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
4070 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
4073 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
4076 panic("unsupported # of RX ring, %d\n", rxr->me);
4079 int intr_bit = *intr_bit0;
4081 rxr->rx_intr_bit = intr_bit % intr_bitmax;
4082 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
4084 *intr_bit0 = intr_bit + 1;
4089 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
4091 struct igb_softc *sc = ifp->if_softc;
4093 ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt, slz);
4097 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4099 struct igb_softc *sc = ifp->if_softc;
4101 ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt, slz);
4105 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4107 struct igb_softc *sc = ifp->if_softc;
4109 return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
4116 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
4117 boolean_t serialized)
4119 struct igb_softc *sc = ifp->if_softc;
4121 ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
4125 #endif /* INVARIANTS */
4128 igb_set_intr_mask(struct igb_softc *sc)
4132 sc->intr_mask = sc->sts_intr_mask;
4133 for (i = 0; i < sc->rx_ring_inuse; ++i)
4134 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
4135 for (i = 0; i < sc->tx_ring_inuse; ++i)
4136 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
4138 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
4144 igb_alloc_intr(struct igb_softc *sc)
4146 int i, intr_bit, intr_bitmax;
4149 igb_msix_try_alloc(sc);
4150 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
4154 * Allocate MSI/legacy interrupt resource
4156 sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
4157 &sc->intr_rid, &intr_flags);
4159 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
4162 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
4164 sc->flags |= IGB_FLAG_SHARED_INTR;
4166 device_printf(sc->dev, "IRQ shared\n");
4168 intr_flags &= ~RF_SHAREABLE;
4170 device_printf(sc->dev, "IRQ unshared\n");
4174 sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4175 &sc->intr_rid, intr_flags);
4176 if (sc->intr_res == NULL) {
4177 device_printf(sc->dev, "Unable to allocate bus resource: "
4182 for (i = 0; i < sc->tx_ring_cnt; ++i)
4183 sc->tx_rings[i].tx_intr_cpuid = rman_get_cpuid(sc->intr_res);
4186 * Setup MSI/legacy interrupt mask
4188 switch (sc->hw.mac.type) {
4190 intr_bitmax = IGB_MAX_TXRXINT_82575;
4194 intr_bitmax = IGB_MAX_TXRXINT_82576;
4198 intr_bitmax = IGB_MAX_TXRXINT_82580;
4202 intr_bitmax = IGB_MAX_TXRXINT_I350;
4206 intr_bitmax = IGB_MAX_TXRXINT_I354;
4210 intr_bitmax = IGB_MAX_TXRXINT_I210;
4214 intr_bitmax = IGB_MAX_TXRXINT_I211;
4218 intr_bitmax = IGB_MIN_TXRXINT;
4222 for (i = 0; i < sc->tx_ring_cnt; ++i)
4223 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
4224 for (i = 0; i < sc->rx_ring_cnt; ++i)
4225 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
4226 sc->sts_intr_bit = 0;
4227 sc->sts_intr_mask = E1000_EICR_OTHER;
4229 /* Initialize interrupt rate */
4230 sc->intr_rate = IGB_INTR_RATE;
4232 igb_set_ring_inuse(sc, FALSE);
4233 igb_set_intr_mask(sc);
4238 igb_free_intr(struct igb_softc *sc)
4240 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
4241 if (sc->intr_res != NULL) {
4242 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
4245 if (sc->intr_type == PCI_INTR_TYPE_MSI)
4246 pci_release_msi(sc->dev);
4248 igb_msix_free(sc, TRUE);
4253 igb_teardown_intr(struct igb_softc *sc)
4255 if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4256 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
4258 igb_msix_teardown(sc, sc->msix_cnt);
4262 igb_msix_try_alloc(struct igb_softc *sc)
4264 int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
4266 int offset, offset_def;
4267 struct igb_msix_data *msix;
4268 boolean_t aggregate, setup = FALSE;
4271 * Don't enable MSI-X on 82575, see:
4272 * 82575 specification update errata #25
4274 if (sc->hw.mac.type == e1000_82575)
4277 /* Don't enable MSI-X on VF */
4281 msix_enable = device_getenv_int(sc->dev, "msix.enable",
4286 msix_cnt = pci_msix_count(sc->dev);
4287 #ifdef IGB_MSIX_DEBUG
4288 msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
4290 if (msix_cnt <= 1) {
4291 /* One MSI-X model does not make sense */
4296 while ((1 << (i + 1)) <= msix_cnt)
4301 device_printf(sc->dev, "MSI-X count %d/%d\n",
4302 msix_cnt2, msix_cnt);
4305 KKASSERT(msix_cnt2 <= msix_cnt);
4306 if (msix_cnt == msix_cnt2) {
4307 /* We need at least one MSI-X for link status */
4309 if (msix_cnt2 <= 1) {
4310 /* One MSI-X for RX/TX does not make sense */
4311 device_printf(sc->dev, "not enough MSI-X for TX/RX, "
4312 "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
4315 KKASSERT(msix_cnt > msix_cnt2);
4318 device_printf(sc->dev, "MSI-X count fixup %d/%d\n",
4319 msix_cnt2, msix_cnt);
4323 sc->rx_ring_msix = sc->rx_ring_cnt;
4324 if (sc->rx_ring_msix > msix_cnt2)
4325 sc->rx_ring_msix = msix_cnt2;
4327 sc->tx_ring_msix = sc->tx_ring_cnt;
4328 if (sc->tx_ring_msix > msix_cnt2)
4329 sc->tx_ring_msix = msix_cnt2;
4331 if (msix_cnt >= sc->tx_ring_msix + sc->rx_ring_msix + 1) {
4333 * Independent TX/RX MSI-X
4337 device_printf(sc->dev, "independent TX/RX MSI-X\n");
4338 alloc_cnt = sc->tx_ring_msix + sc->rx_ring_msix;
4341 * Aggregate TX/RX MSI-X
4345 device_printf(sc->dev, "aggregate TX/RX MSI-X\n");
4346 alloc_cnt = msix_cnt2;
4347 if (alloc_cnt > ncpus2)
4349 if (sc->rx_ring_msix > alloc_cnt)
4350 sc->rx_ring_msix = alloc_cnt;
4351 if (sc->tx_ring_msix > alloc_cnt)
4352 sc->tx_ring_msix = alloc_cnt;
4354 ++alloc_cnt; /* For link status */
4357 device_printf(sc->dev, "MSI-X alloc %d, "
4358 "RX ring %d, TX ring %d\n", alloc_cnt,
4359 sc->rx_ring_msix, sc->tx_ring_msix);
4362 sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR);
4363 sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4364 &sc->msix_mem_rid, RF_ACTIVE);
4365 if (sc->msix_mem_res == NULL) {
4366 sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR_ALT);
4367 sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4368 &sc->msix_mem_rid, RF_ACTIVE);
4369 if (sc->msix_mem_res == NULL) {
4370 device_printf(sc->dev, "Unable to map MSI-X table\n");
4375 sc->msix_cnt = alloc_cnt;
4376 sc->msix_data = kmalloc_cachealign(
4377 sizeof(struct igb_msix_data) * sc->msix_cnt,
4378 M_DEVBUF, M_WAITOK | M_ZERO);
4379 for (x = 0; x < sc->msix_cnt; ++x) {
4380 msix = &sc->msix_data[x];
4382 lwkt_serialize_init(&msix->msix_serialize0);
4384 msix->msix_rid = -1;
4385 msix->msix_vector = x;
4386 msix->msix_mask = 1 << msix->msix_vector;
4387 msix->msix_rate = IGB_INTR_RATE;
4395 if (sc->rx_ring_msix == ncpus2) {
4398 offset_def = (sc->rx_ring_msix *
4399 device_get_unit(sc->dev)) % ncpus2;
4401 offset = device_getenv_int(sc->dev,
4402 "msix.rxoff", offset_def);
4403 if (offset >= ncpus2 ||
4404 offset % sc->rx_ring_msix != 0) {
4405 device_printf(sc->dev,
4406 "invalid msix.rxoff %d, use %d\n",
4407 offset, offset_def);
4408 offset = offset_def;
4411 igb_msix_rx_conf(sc, 0, &x, offset);
4416 if (sc->tx_ring_msix == ncpus2) {
4419 offset_def = (sc->tx_ring_msix *
4420 device_get_unit(sc->dev)) % ncpus2;
4422 offset = device_getenv_int(sc->dev,
4423 "msix.txoff", offset_def);
4424 if (offset >= ncpus2 ||
4425 offset % sc->tx_ring_msix != 0) {
4426 device_printf(sc->dev,
4427 "invalid msix.txoff %d, use %d\n",
4428 offset, offset_def);
4429 offset = offset_def;
4432 igb_msix_tx_conf(sc, 0, &x, offset);
4434 int ring_agg, ring_max;
4436 ring_agg = sc->rx_ring_msix;
4437 if (ring_agg > sc->tx_ring_msix)
4438 ring_agg = sc->tx_ring_msix;
4440 ring_max = sc->rx_ring_msix;
4441 if (ring_max < sc->tx_ring_msix)
4442 ring_max = sc->tx_ring_msix;
4444 if (ring_max == ncpus2) {
4447 offset_def = (ring_max * device_get_unit(sc->dev)) %
4450 offset = device_getenv_int(sc->dev, "msix.off",
4452 if (offset >= ncpus2 || offset % ring_max != 0) {
4453 device_printf(sc->dev,
4454 "invalid msix.off %d, use %d\n",
4455 offset, offset_def);
4456 offset = offset_def;
4460 for (i = 0; i < ring_agg; ++i) {
4461 struct igb_tx_ring *txr = &sc->tx_rings[i];
4462 struct igb_rx_ring *rxr = &sc->rx_rings[i];
4464 KKASSERT(x < sc->msix_cnt);
4465 msix = &sc->msix_data[x++];
4467 txr->tx_intr_bit = msix->msix_vector;
4468 txr->tx_intr_mask = msix->msix_mask;
4469 rxr->rx_intr_bit = msix->msix_vector;
4470 rxr->rx_intr_mask = msix->msix_mask;
4472 msix->msix_serialize = &msix->msix_serialize0;
4473 msix->msix_func = igb_msix_rxtx;
4474 msix->msix_arg = msix;
4475 msix->msix_rx = rxr;
4476 msix->msix_tx = txr;
4478 msix->msix_cpuid = i + offset;
4479 KKASSERT(msix->msix_cpuid < ncpus2);
4480 txr->tx_intr_cpuid = msix->msix_cpuid;
4482 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4483 "%s rxtx%d", device_get_nameunit(sc->dev), i);
4484 msix->msix_rate = IGB_MSIX_RX_RATE;
4485 ksnprintf(msix->msix_rate_desc,
4486 sizeof(msix->msix_rate_desc),
4487 "RXTX%d interrupt rate", i);
4490 if (ring_agg != ring_max) {
4491 if (ring_max == sc->tx_ring_msix)
4492 igb_msix_tx_conf(sc, i, &x, offset);
4494 igb_msix_rx_conf(sc, i, &x, offset);
4501 KKASSERT(x < sc->msix_cnt);
4502 msix = &sc->msix_data[x++];
4503 sc->sts_intr_bit = msix->msix_vector;
4504 sc->sts_intr_mask = msix->msix_mask;
4506 msix->msix_serialize = &sc->main_serialize;
4507 msix->msix_func = igb_msix_status;
4508 msix->msix_arg = sc;
4509 msix->msix_cpuid = 0;
4510 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s sts",
4511 device_get_nameunit(sc->dev));
4512 ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4513 "status interrupt rate");
4515 KKASSERT(x == sc->msix_cnt);
4517 error = pci_setup_msix(sc->dev);
4519 device_printf(sc->dev, "Setup MSI-X failed\n");
4524 for (i = 0; i < sc->msix_cnt; ++i) {
4525 msix = &sc->msix_data[i];
4527 error = pci_alloc_msix_vector(sc->dev, msix->msix_vector,
4528 &msix->msix_rid, msix->msix_cpuid);
4530 device_printf(sc->dev,
4531 "Unable to allocate MSI-X %d on cpu%d\n",
4532 msix->msix_vector, msix->msix_cpuid);
4536 msix->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4537 &msix->msix_rid, RF_ACTIVE);
4538 if (msix->msix_res == NULL) {
4539 device_printf(sc->dev,
4540 "Unable to allocate MSI-X %d resource\n",
4547 pci_enable_msix(sc->dev);
4548 sc->intr_type = PCI_INTR_TYPE_MSIX;
4551 igb_msix_free(sc, setup);
4555 igb_msix_free(struct igb_softc *sc, boolean_t setup)
4559 KKASSERT(sc->msix_cnt > 1);
4561 for (i = 0; i < sc->msix_cnt; ++i) {
4562 struct igb_msix_data *msix = &sc->msix_data[i];
4564 if (msix->msix_res != NULL) {
4565 bus_release_resource(sc->dev, SYS_RES_IRQ,
4566 msix->msix_rid, msix->msix_res);
4568 if (msix->msix_rid >= 0)
4569 pci_release_msix_vector(sc->dev, msix->msix_rid);
4572 pci_teardown_msix(sc->dev);
4575 kfree(sc->msix_data, M_DEVBUF);
4576 sc->msix_data = NULL;
4580 igb_msix_setup(struct igb_softc *sc)
4584 for (i = 0; i < sc->msix_cnt; ++i) {
4585 struct igb_msix_data *msix = &sc->msix_data[i];
4588 error = bus_setup_intr_descr(sc->dev, msix->msix_res,
4589 INTR_MPSAFE, msix->msix_func, msix->msix_arg,
4590 &msix->msix_handle, msix->msix_serialize, msix->msix_desc);
4592 device_printf(sc->dev, "could not set up %s "
4593 "interrupt handler.\n", msix->msix_desc);
4594 igb_msix_teardown(sc, i);
4602 igb_msix_teardown(struct igb_softc *sc, int msix_cnt)
4606 for (i = 0; i < msix_cnt; ++i) {
4607 struct igb_msix_data *msix = &sc->msix_data[i];
4609 bus_teardown_intr(sc->dev, msix->msix_res, msix->msix_handle);
4614 igb_msix_rx(void *arg)
4616 struct igb_rx_ring *rxr = arg;
4618 ASSERT_SERIALIZED(&rxr->rx_serialize);
4621 E1000_WRITE_REG(&rxr->sc->hw, E1000_EIMS, rxr->rx_intr_mask);
4625 igb_msix_tx(void *arg)
4627 struct igb_tx_ring *txr = arg;
4629 ASSERT_SERIALIZED(&txr->tx_serialize);
4632 if (!ifsq_is_empty(txr->ifsq))
4633 ifsq_devstart(txr->ifsq);
4635 E1000_WRITE_REG(&txr->sc->hw, E1000_EIMS, txr->tx_intr_mask);
4639 igb_msix_status(void *arg)
4641 struct igb_softc *sc = arg;
4644 ASSERT_SERIALIZED(&sc->main_serialize);
4646 icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4647 if (icr & E1000_ICR_LSC) {
4648 sc->hw.mac.get_link_status = 1;
4649 igb_update_link_status(sc);
4652 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->sts_intr_mask);
4656 igb_set_ring_inuse(struct igb_softc *sc, boolean_t polling)
4658 sc->rx_ring_inuse = igb_get_rxring_inuse(sc, polling);
4659 sc->tx_ring_inuse = igb_get_txring_inuse(sc, polling);
4661 if_printf(&sc->arpcom.ac_if, "RX rings %d/%d, TX rings %d/%d\n",
4662 sc->rx_ring_inuse, sc->rx_ring_cnt,
4663 sc->tx_ring_inuse, sc->tx_ring_cnt);
4668 igb_get_rxring_inuse(const struct igb_softc *sc, boolean_t polling)
4670 if (!IGB_ENABLE_HWRSS(sc))
4674 return sc->rx_ring_cnt;
4675 else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4676 return IGB_MIN_RING_RSS;
4678 return sc->rx_ring_msix;
4682 igb_get_txring_inuse(const struct igb_softc *sc, boolean_t polling)
4684 if (!IGB_ENABLE_HWTSS(sc))
4688 return sc->tx_ring_cnt;
4689 else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4690 return IGB_MIN_RING;
4692 return sc->tx_ring_msix;
4696 igb_tso_pullup(struct igb_tx_ring *txr, struct mbuf **mp)
4698 int hoff, iphlen, thoff;
4702 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4704 iphlen = m->m_pkthdr.csum_iphlen;
4705 thoff = m->m_pkthdr.csum_thlen;
4706 hoff = m->m_pkthdr.csum_lhlen;
4708 KASSERT(iphlen > 0, ("invalid ip hlen"));
4709 KASSERT(thoff > 0, ("invalid tcp hlen"));
4710 KASSERT(hoff > 0, ("invalid ether hlen"));
4712 if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4713 m = m_pullup(m, hoff + iphlen + thoff);
4720 if (txr->tx_flags & IGB_TXFLAG_TSO_IPLEN0) {
4723 ip = mtodoff(m, struct ip *, hoff);
4731 igb_tso_ctx(struct igb_tx_ring *txr, struct mbuf *m, uint32_t *hlen)
4733 struct e1000_adv_tx_context_desc *TXD;
4734 uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
4735 int hoff, ctxd, iphlen, thoff;
4737 iphlen = m->m_pkthdr.csum_iphlen;
4738 thoff = m->m_pkthdr.csum_thlen;
4739 hoff = m->m_pkthdr.csum_lhlen;
4741 vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
4743 ctxd = txr->next_avail_desc;
4744 TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
4746 if (m->m_flags & M_VLANTAG) {
4749 vlantag = htole16(m->m_pkthdr.ether_vlantag);
4750 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
4753 vlan_macip_lens |= (hoff << E1000_ADVTXD_MACLEN_SHIFT);
4754 vlan_macip_lens |= iphlen;
4756 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4757 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
4758 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
4760 mss_l4len_idx |= (m->m_pkthdr.tso_segsz << E1000_ADVTXD_MSS_SHIFT);
4761 mss_l4len_idx |= (thoff << E1000_ADVTXD_L4LEN_SHIFT);
4764 * 82575 needs the TX context index added; the queue
4765 * index is used as TX context index here.
4767 if (txr->sc->hw.mac.type == e1000_82575)
4768 mss_l4len_idx |= txr->me << 4;
4770 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
4771 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
4772 TXD->seqnum_seed = htole32(0);
4773 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
4775 /* We've consumed the first desc, adjust counters */
4776 if (++ctxd == txr->num_tx_desc)
4778 txr->next_avail_desc = ctxd;
4781 *hlen = hoff + iphlen + thoff;
4785 igb_setup_serializer(struct igb_softc *sc)
4787 const struct igb_msix_data *msix;
4791 * Allocate serializer array
4794 /* Main + TX + RX */
4795 sc->serialize_cnt = 1 + sc->tx_ring_cnt + sc->rx_ring_cnt;
4797 /* Aggregate TX/RX MSI-X */
4798 for (i = 0; i < sc->msix_cnt; ++i) {
4799 msix = &sc->msix_data[i];
4800 if (msix->msix_serialize == &msix->msix_serialize0)
4801 sc->serialize_cnt++;
4805 kmalloc(sc->serialize_cnt * sizeof(struct lwkt_serialize *),
4806 M_DEVBUF, M_WAITOK | M_ZERO);
4811 * NOTE: Order is critical
4816 KKASSERT(i < sc->serialize_cnt);
4817 sc->serializes[i++] = &sc->main_serialize;
4819 for (j = 0; j < sc->msix_cnt; ++j) {
4820 msix = &sc->msix_data[j];
4821 if (msix->msix_serialize == &msix->msix_serialize0) {
4822 KKASSERT(i < sc->serialize_cnt);
4823 sc->serializes[i++] = msix->msix_serialize;
4827 for (j = 0; j < sc->tx_ring_cnt; ++j) {
4828 KKASSERT(i < sc->serialize_cnt);
4829 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
4832 for (j = 0; j < sc->rx_ring_cnt; ++j) {
4833 KKASSERT(i < sc->serialize_cnt);
4834 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
4837 KKASSERT(i == sc->serialize_cnt);
4841 igb_msix_rx_conf(struct igb_softc *sc, int i, int *x0, int offset)
4845 for (; i < sc->rx_ring_msix; ++i) {
4846 struct igb_rx_ring *rxr = &sc->rx_rings[i];
4847 struct igb_msix_data *msix;
4849 KKASSERT(x < sc->msix_cnt);
4850 msix = &sc->msix_data[x++];
4852 rxr->rx_intr_bit = msix->msix_vector;
4853 rxr->rx_intr_mask = msix->msix_mask;
4855 msix->msix_serialize = &rxr->rx_serialize;
4856 msix->msix_func = igb_msix_rx;
4857 msix->msix_arg = rxr;
4859 msix->msix_cpuid = i + offset;
4860 KKASSERT(msix->msix_cpuid < ncpus2);
4862 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s rx%d",
4863 device_get_nameunit(sc->dev), i);
4865 msix->msix_rate = IGB_MSIX_RX_RATE;
4866 ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4867 "RX%d interrupt rate", i);
4873 igb_msix_tx_conf(struct igb_softc *sc, int i, int *x0, int offset)
4877 for (; i < sc->tx_ring_msix; ++i) {
4878 struct igb_tx_ring *txr = &sc->tx_rings[i];
4879 struct igb_msix_data *msix;
4881 KKASSERT(x < sc->msix_cnt);
4882 msix = &sc->msix_data[x++];
4884 txr->tx_intr_bit = msix->msix_vector;
4885 txr->tx_intr_mask = msix->msix_mask;
4887 msix->msix_serialize = &txr->tx_serialize;
4888 msix->msix_func = igb_msix_tx;
4889 msix->msix_arg = txr;
4891 msix->msix_cpuid = i + offset;
4892 KKASSERT(msix->msix_cpuid < ncpus2);
4893 txr->tx_intr_cpuid = msix->msix_cpuid;
4895 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s tx%d",
4896 device_get_nameunit(sc->dev), i);
4898 msix->msix_rate = IGB_MSIX_TX_RATE;
4899 ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4900 "TX%d interrupt rate", i);
4906 igb_msix_rxtx(void *arg)
4908 struct igb_msix_data *msix = arg;
4909 struct igb_rx_ring *rxr = msix->msix_rx;
4910 struct igb_tx_ring *txr = msix->msix_tx;
4912 ASSERT_SERIALIZED(&msix->msix_serialize0);
4914 lwkt_serialize_enter(&rxr->rx_serialize);
4916 lwkt_serialize_exit(&rxr->rx_serialize);
4918 lwkt_serialize_enter(&txr->tx_serialize);
4920 if (!ifsq_is_empty(txr->ifsq))
4921 ifsq_devstart(txr->ifsq);
4922 lwkt_serialize_exit(&txr->tx_serialize);
4924 E1000_WRITE_REG(&msix->msix_sc->hw, E1000_EIMS, msix->msix_mask);
4928 igb_set_timer_cpuid(struct igb_softc *sc, boolean_t polling)
4930 if (polling || sc->intr_type == PCI_INTR_TYPE_MSIX)
4931 sc->timer_cpuid = 0; /* XXX fixed */
4933 sc->timer_cpuid = rman_get_cpuid(sc->intr_res);