2 * Copyright (c) 1993 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * from: Header: timerreg.h,v 1.2 93/02/28 15:08:58 mccanne Exp
34 * $FreeBSD: src/sys/i386/isa/timerreg.h,v 1.6 1999/08/28 00:45:04 peter Exp $
35 * $DragonFly: src/sys/i386/isa/Attic/timerreg.h,v 1.2 2003/06/17 04:28:37 dillon Exp $
40 * Register definitions for the Intel 8253 Programmable Interval Timer.
42 * This chip has three independent 16-bit down counters that can be
43 * read on the fly. There are three mode registers and three countdown
44 * registers. The countdown registers are addressed directly, via the
45 * first three I/O ports. The three mode registers are accessed via
46 * the fourth I/O port, with two bits in the mode byte indicating the
47 * register. (Why are hardware interfaces always so braindead?).
49 * To write a value into the countdown register, the mode register
50 * is first programmed with a command indicating the which byte of
51 * the two byte register is to be modified. The three possibilities
52 * are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then
55 * To read the current value ("on the fly") from the countdown register,
56 * you write a "latch" command into the mode register, then read the stable
57 * value from the corresponding I/O port. For example, you write
58 * TMR_MR_LATCH into the corresponding mode register. Presumably,
59 * after doing this, a write operation to the I/O port would result
60 * in undefined behavior (but hopefully not fry the chip).
61 * Reading in this manner has no side effects.
64 * The outputs of the three timers are connected as follows:
67 * timer 1 -> dma chan 0 (for dram refresh)
68 * timer 2 -> speaker (via keyboard controller)
70 * Timer 0 is used to call hardclock.
71 * Timer 2 is used to generate console beeps.
74 * The outputs of the three timers are connected as follows:
77 * timer 1 -> speaker (via keyboard controller)
80 * Timer 0 is used to call hardclock.
81 * Timer 1 is used to generate console beeps.
85 * Macros for specifying values to be written into a mode register.
87 #define TIMER_CNTR0 (IO_TIMER1 + 0) /* timer 0 counter port */
89 #define TIMER_CNTR1 0x3fdb /* timer 1 counter port */
90 #define TIMER_CNTR2 (IO_TIMER1 + 4) /* timer 2 counter port */
91 #define TIMER_MODE (IO_TIMER1 + 6) /* timer mode port */
93 #define TIMER_CNTR1 (IO_TIMER1 + 1) /* timer 1 counter port */
94 #define TIMER_CNTR2 (IO_TIMER1 + 2) /* timer 2 counter port */
95 #define TIMER_MODE (IO_TIMER1 + 3) /* timer mode port */
97 #define TIMER_SEL0 0x00 /* select counter 0 */
98 #define TIMER_SEL1 0x40 /* select counter 1 */
99 #define TIMER_SEL2 0x80 /* select counter 2 */
100 #define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */
101 #define TIMER_ONESHOT 0x02 /* mode 1, one shot */
102 #define TIMER_RATEGEN 0x04 /* mode 2, rate generator */
103 #define TIMER_SQWAVE 0x06 /* mode 3, square wave */
104 #define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */
105 #define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */
106 #define TIMER_LATCH 0x00 /* latch counter for reading */
107 #define TIMER_LSB 0x10 /* r/w counter LSB */
108 #define TIMER_MSB 0x20 /* r/w counter MSB */
109 #define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */
110 #define TIMER_BCD 0x01 /* count in BCD */