2 * Copyright (c) 1997, 2001 Hellmuth Michaelis. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 *---------------------------------------------------------------------------
27 * i4b_itjc_isac.c - i4b NetJet-S ISAC handler
28 * --------------------------------------------
30 * $FreeBSD: src/sys/i4b/layer1/itjc/i4b_itjc_isac.c,v 1.1.2.1 2001/08/10 14:08:39 obrien Exp $
31 * $DragonFly: src/sys/net/i4b/layer1/itjc/i4b_itjc_isac.c,v 1.5 2006/01/14 11:05:18 swildner Exp $
33 * last edit-date: [Wed Jan 10 17:15:54 2001]
35 *---------------------------------------------------------------------------*/
44 #include <sys/param.h>
45 #include <sys/kernel.h>
46 #include <sys/systm.h>
48 #include <sys/socket.h>
50 #include <machine/stdarg.h>
51 #include <machine/clock.h>
55 #include <net/i4b/include/machine/i4b_debug.h>
56 #include <net/i4b/include/machine/i4b_ioctl.h>
57 #include <net/i4b/include/machine/i4b_trace.h>
59 #include "../i4b_l1.h"
61 #include "../isic/i4b_isic.h"
62 #include "../isic/i4b_isac.h"
64 #include "i4b_itjc_ext.h"
66 #include "../../include/i4b_global.h"
67 #include "../../include/i4b_mbuf.h"
69 static u_char itjc_isac_exir_hdlr(struct l1_softc *sc, u_char exir);
70 static void itjc_isac_ind_hdlr(struct l1_softc *sc, int ind);
72 /*---------------------------------------------------------------------------*
73 * ISAC interrupt service routine
74 *---------------------------------------------------------------------------*/
76 itjc_isac_irq(struct l1_softc *sc, int ista)
79 NDBGL1(L1_F_MSG, "unit %d: ista = 0x%02x", sc->sc_unit, ista);
81 if(ista & ISAC_ISTA_EXI) /* extended interrupt */
83 c |= itjc_isac_exir_hdlr(sc, ISAC_READ(I_EXIR));
86 if(ista & ISAC_ISTA_RME) /* receive message end */
91 /* get rx status register */
93 rsta = ISAC_READ(I_RSTA);
95 if((rsta & ISAC_RSTA_MASK) != 0x20)
99 if(!(rsta & ISAC_RSTA_CRC)) /* CRC error */
102 NDBGL1(L1_I_ERR, "unit %d: CRC error", sc->sc_unit);
105 if(rsta & ISAC_RSTA_RDO) /* ReceiveDataOverflow */
108 NDBGL1(L1_I_ERR, "unit %d: Data Overrun error", sc->sc_unit);
111 if(rsta & ISAC_RSTA_RAB) /* ReceiveABorted */
114 NDBGL1(L1_I_ERR, "unit %d: Receive Aborted error", sc->sc_unit);
118 NDBGL1(L1_I_ERR, "unit %d: RME unknown error, RSTA = 0x%02x!", sc->sc_unit, rsta);
120 i4b_Dfreembuf(sc->sc_ibuf);
122 c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
128 ISAC_WRITE(I_CMDR, ISAC_CMDR_RMC|ISAC_CMDR_RRES);
134 rest = (ISAC_READ(I_RBCL) & (ISAC_FIFO_LEN-1));
137 rest = ISAC_FIFO_LEN;
139 if(sc->sc_ibuf == NULL)
141 if((sc->sc_ibuf = i4b_Dgetmbuf(rest)) != NULL)
142 sc->sc_ib = sc->sc_ibuf->m_data;
144 panic("itjc_isac_irq: RME, i4b_Dgetmbuf returns NULL!\n");
148 if(sc->sc_ilen <= (MAX_DFRAME_LEN - rest))
150 ISAC_RDFIFO(sc->sc_ib, rest);
153 sc->sc_ibuf->m_pkthdr.len =
154 sc->sc_ibuf->m_len = sc->sc_ilen;
156 if(sc->sc_trace & TRACE_D_RX)
159 hdr.unit = L0ITJCUNIT(sc->sc_unit);
162 hdr.count = ++sc->sc_trace_dcount;
164 i4b_l1_trace_ind(&hdr, sc->sc_ibuf->m_len, sc->sc_ibuf->m_data);
170 (ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S))
172 i4b_l1_ph_data_ind(L0ITJCUNIT(sc->sc_unit), sc->sc_ibuf);
176 i4b_Dfreembuf(sc->sc_ibuf);
181 NDBGL1(L1_I_ERR, "RME, input buffer overflow!");
182 i4b_Dfreembuf(sc->sc_ibuf);
183 c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
191 if(ista & ISAC_ISTA_RPF) /* receive fifo full */
193 if(sc->sc_ibuf == NULL)
195 if((sc->sc_ibuf = i4b_Dgetmbuf(MAX_DFRAME_LEN)) != NULL)
196 sc->sc_ib= sc->sc_ibuf->m_data;
198 panic("itjc_isac_irq: RPF, i4b_Dgetmbuf returns NULL!\n");
202 if(sc->sc_ilen <= (MAX_DFRAME_LEN - ISAC_FIFO_LEN))
204 ISAC_RDFIFO(sc->sc_ib, ISAC_FIFO_LEN);
205 sc->sc_ilen += ISAC_FIFO_LEN;
206 sc->sc_ib += ISAC_FIFO_LEN;
211 NDBGL1(L1_I_ERR, "RPF, input buffer overflow!");
212 i4b_Dfreembuf(sc->sc_ibuf);
216 c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
220 if(ista & ISAC_ISTA_XPR) /* transmit fifo empty (XPR bit set) */
222 if((sc->sc_obuf2 != NULL) && (sc->sc_obuf == NULL))
224 sc->sc_freeflag = sc->sc_freeflag2;
225 sc->sc_obuf = sc->sc_obuf2;
226 sc->sc_op = sc->sc_obuf->m_data;
227 sc->sc_ol = sc->sc_obuf->m_len;
233 ISAC_WRFIFO(sc->sc_op, min(sc->sc_ol, ISAC_FIFO_LEN));
235 if(sc->sc_ol > ISAC_FIFO_LEN) /* length > 32 ? */
237 sc->sc_op += ISAC_FIFO_LEN; /* bufferptr+32 */
238 sc->sc_ol -= ISAC_FIFO_LEN; /* length - 32 */
239 c |= ISAC_CMDR_XTF; /* set XTF bit */
245 i4b_Dfreembuf(sc->sc_obuf);
252 c |= ISAC_CMDR_XTF | ISAC_CMDR_XME;
257 sc->sc_state &= ~ISAC_TX_ACTIVE;
261 if(ista & ISAC_ISTA_CISQ) /* channel status change CISQ */
265 /* get command/indication rx register*/
267 ci = ISAC_READ(I_CIRR);
269 /* if S/Q IRQ, read SQC reg to clr SQC IRQ */
271 if(ci & ISAC_CIRR_SQC)
274 /* C/I code change IRQ (flag already cleared by CIRR read) */
276 if(ci & ISAC_CIRR_CIC0)
277 itjc_isac_ind_hdlr(sc, (ci >> 2) & 0xf);
282 ISAC_WRITE(I_CMDR, c);
287 /*---------------------------------------------------------------------------*
288 * ISAC L1 Extended IRQ handler
289 *---------------------------------------------------------------------------*/
291 itjc_isac_exir_hdlr(struct l1_softc *sc, u_char exir)
295 if(exir & ISAC_EXIR_XMR)
297 NDBGL1(L1_I_ERR, "EXIRQ Tx Message Repeat");
302 if(exir & ISAC_EXIR_XDU)
304 NDBGL1(L1_I_ERR, "EXIRQ Tx Data Underrun");
309 if(exir & ISAC_EXIR_PCE)
311 NDBGL1(L1_I_ERR, "EXIRQ Protocol Error");
314 if(exir & ISAC_EXIR_RFO)
316 NDBGL1(L1_I_ERR, "EXIRQ Rx Frame Overflow");
318 c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
321 if(exir & ISAC_EXIR_SOV)
323 NDBGL1(L1_I_ERR, "EXIRQ Sync Xfer Overflow");
326 if(exir & ISAC_EXIR_MOS)
328 NDBGL1(L1_I_ERR, "EXIRQ Monitor Status");
331 if(exir & ISAC_EXIR_SAW)
333 /* cannot happen, STCR:TSF is set to 0 */
335 NDBGL1(L1_I_ERR, "EXIRQ Subscriber Awake");
338 if(exir & ISAC_EXIR_WOV)
340 /* cannot happen, STCR:TSF is set to 0 */
342 NDBGL1(L1_I_ERR, "EXIRQ Watchdog Timer Overflow");
348 /*---------------------------------------------------------------------------*
349 * ISAC L1 Indication handler
350 *---------------------------------------------------------------------------*/
352 itjc_isac_ind_hdlr(struct l1_softc *sc, int ind)
359 NDBGL1(L1_I_CICO, "rx AI8 in state %s", itjc_printstate(sc));
360 itjc_isac_l1_cmd(sc, CMD_AR8);
362 i4b_l1_mph_status_ind(L0ITJCUNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
365 case ISAC_CIRR_IAI10:
366 NDBGL1(L1_I_CICO, "rx AI10 in state %s", itjc_printstate(sc));
367 itjc_isac_l1_cmd(sc, CMD_AR10);
369 i4b_l1_mph_status_ind(L0ITJCUNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
373 NDBGL1(L1_I_CICO, "rx RSY in state %s", itjc_printstate(sc));
378 NDBGL1(L1_I_CICO, "rx PU in state %s", itjc_printstate(sc));
383 NDBGL1(L1_I_CICO, "rx DR in state %s", itjc_printstate(sc));
384 itjc_isac_l1_cmd(sc, CMD_DIU);
389 NDBGL1(L1_I_CICO, "rx DID in state %s", itjc_printstate(sc));
391 i4b_l1_mph_status_ind(L0ITJCUNIT(sc->sc_unit), STI_L1STAT, LAYER_IDLE, NULL);
395 NDBGL1(L1_I_CICO, "rx DIS in state %s", itjc_printstate(sc));
400 NDBGL1(L1_I_CICO, "rx EI in state %s", itjc_printstate(sc));
401 itjc_isac_l1_cmd(sc, CMD_DIU);
406 NDBGL1(L1_I_CICO, "rx ARD in state %s", itjc_printstate(sc));
411 NDBGL1(L1_I_CICO, "rx TI in state %s", itjc_printstate(sc));
416 NDBGL1(L1_I_CICO, "rx ATI in state %s", itjc_printstate(sc));
421 NDBGL1(L1_I_CICO, "rx SD in state %s", itjc_printstate(sc));
426 NDBGL1(L1_I_ERR, "UNKNOWN Indication 0x%x in state %s", ind, itjc_printstate(sc));
430 itjc_next_state(sc, event);
433 /*---------------------------------------------------------------------------*
434 * execute a layer 1 command
435 *---------------------------------------------------------------------------*/
437 itjc_isac_l1_cmd(struct l1_softc *sc, int command)
441 if(command < 0 || command > CMD_ILL)
443 NDBGL1(L1_I_ERR, "illegal cmd 0x%x in state %s", command, itjc_printstate(sc));
452 NDBGL1(L1_I_CICO, "tx TIM in state %s", itjc_printstate(sc));
453 cmd |= (ISAC_CIXR_CTIM << 2);
457 NDBGL1(L1_I_CICO, "tx RS in state %s", itjc_printstate(sc));
458 cmd |= (ISAC_CIXR_CRS << 2);
462 NDBGL1(L1_I_CICO, "tx AR8 in state %s", itjc_printstate(sc));
463 cmd |= (ISAC_CIXR_CAR8 << 2);
467 NDBGL1(L1_I_CICO, "tx AR10 in state %s", itjc_printstate(sc));
468 cmd |= (ISAC_CIXR_CAR10 << 2);
472 NDBGL1(L1_I_CICO, "tx DIU in state %s", itjc_printstate(sc));
473 cmd |= (ISAC_CIXR_CDIU << 2);
476 ISAC_WRITE(I_CIXR, cmd);
479 /*---------------------------------------------------------------------------*
480 * L1 ISAC initialization
481 *---------------------------------------------------------------------------*/
483 itjc_isac_init(struct l1_softc *sc)
485 ISAC_IMASK = 0xff; /* disable all irqs */
487 ISAC_WRITE(I_MASK, ISAC_IMASK);
489 NDBGL1(L1_I_SETUP, "configuring for IOM-2 mode");
491 /* ADF2: Select mode IOM-2 */
492 ISAC_WRITE(I_ADF2, ISAC_ADF2_IMS);
494 /* SPCR: serial port control register:
495 * SPU - software power up = 0
496 * SPM - timing mode 0
497 * TLP - test loop = 0
498 * C1C, C2C - B1 + C1 and B2 + IC2 monitoring
500 ISAC_WRITE(I_SPCR, 0x00);
502 /* SQXR: S/Q channel xmit register:
503 * IDC - IOM direction = 0 (master)
504 * CFS - Config Select = 0 (clock always active)
505 * CI1E - C/I channel 1 IRQ enable = 0
506 * SQIE - S/Q IRQ enable = 0
507 * SQX1-4 - Fa bits = 1
509 ISAC_WRITE(I_SQXR, ISAC_SQXR_SQX1|ISAC_SQXR_SQX2|ISAC_SQXR_SQX3|ISAC_SQXR_SQX4);
511 /* ADF1: additional feature reg 1:
513 * TEM - test mode = 0
514 * PFS - pre-filter = 0
515 * IOF - IOM i/f off = 0
516 * ITF - interframe fill = idle
518 ISAC_WRITE(I_ADF1, 0x00);
520 /* STCR: sync transfer control reg:
521 * TSF - terminal secific functions = 0
522 * TBA - TIC bus address = 7
525 ISAC_WRITE(I_STCR, ISAC_STCR_TBA2|ISAC_STCR_TBA1|ISAC_STCR_TBA0);
527 /* MODE: Mode Register:
528 * MDSx - transparent mode 2
529 * TMD - timer mode = external
530 * RAC - Receiver enabled
531 * DIMx - digital i/f mode
533 ISAC_WRITE(I_MODE, ISAC_MODE_MDS2|ISAC_MODE_MDS1|ISAC_MODE_RAC|ISAC_MODE_DIM0);
535 /* enabled interrupts:
536 * ===================
537 * RME - receive message end
538 * RPF - receive pool full
539 * XPR - transmit pool ready
540 * CISQ - CI or S/Q channel change
541 * EXI - extended interrupt
544 ISAC_IMASK = ISAC_MASK_RSC | /* auto mode only */
545 ISAC_MASK_TIN | /* timer irq */
546 ISAC_MASK_SIN; /* sync xfer irq */
548 ISAC_WRITE(I_MASK, ISAC_IMASK);
553 #endif /* NITJC > 0 */