1 /******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ******************************************************************************/
35 /* 82562G 10/100 Network Connection
36 * 82562G-2 10/100 Network Connection
37 * 82562GT 10/100 Network Connection
38 * 82562GT-2 10/100 Network Connection
39 * 82562V 10/100 Network Connection
40 * 82562V-2 10/100 Network Connection
41 * 82566DC-2 Gigabit Network Connection
42 * 82566DC Gigabit Network Connection
43 * 82566DM-2 Gigabit Network Connection
44 * 82566DM Gigabit Network Connection
45 * 82566MC Gigabit Network Connection
46 * 82566MM Gigabit Network Connection
47 * 82567LM Gigabit Network Connection
48 * 82567LF Gigabit Network Connection
49 * 82567V Gigabit Network Connection
50 * 82567LM-2 Gigabit Network Connection
51 * 82567LF-2 Gigabit Network Connection
52 * 82567V-2 Gigabit Network Connection
53 * 82567LF-3 Gigabit Network Connection
54 * 82567LM-3 Gigabit Network Connection
55 * 82567LM-4 Gigabit Network Connection
56 * 82577LM Gigabit Network Connection
57 * 82577LC Gigabit Network Connection
58 * 82578DM Gigabit Network Connection
59 * 82578DC Gigabit Network Connection
60 * 82579LM Gigabit Network Connection
61 * 82579V Gigabit Network Connection
62 * Ethernet Connection I217-LM
63 * Ethernet Connection I217-V
64 * Ethernet Connection I218-V
65 * Ethernet Connection I218-LM
66 * Ethernet Connection (2) I218-LM
67 * Ethernet Connection (2) I218-V
68 * Ethernet Connection (3) I218-LM
69 * Ethernet Connection (3) I218-V
72 #include "e1000_api.h"
74 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
75 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
76 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
77 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
78 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
79 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
80 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
81 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
82 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
83 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
86 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
87 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
88 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
89 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
91 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
93 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
94 u16 words, u16 *data);
95 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
96 u16 words, u16 *data);
97 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
98 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
99 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
101 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
102 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
103 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
104 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
105 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
106 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
107 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
108 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
109 u16 *speed, u16 *duplex);
110 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
111 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
112 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
113 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
114 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
115 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
116 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
117 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
118 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
119 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
120 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
121 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
122 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
123 u32 offset, u8 *data);
124 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
126 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
127 u32 offset, u16 *data);
128 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
129 u32 offset, u8 byte);
130 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
131 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
132 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
133 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
134 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
135 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
136 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
138 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
139 /* Offset 04h HSFSTS */
140 union ich8_hws_flash_status {
142 u16 flcdone:1; /* bit 0 Flash Cycle Done */
143 u16 flcerr:1; /* bit 1 Flash Cycle Error */
144 u16 dael:1; /* bit 2 Direct Access error Log */
145 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
146 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
147 u16 reserved1:2; /* bit 13:6 Reserved */
148 u16 reserved2:6; /* bit 13:6 Reserved */
149 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
150 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
155 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
156 /* Offset 06h FLCTL */
157 union ich8_hws_flash_ctrl {
158 struct ich8_hsflctl {
159 u16 flcgo:1; /* 0 Flash Cycle Go */
160 u16 flcycle:2; /* 2:1 Flash Cycle */
161 u16 reserved:5; /* 7:3 Reserved */
162 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
163 u16 flockdn:6; /* 15:10 Reserved */
168 /* ICH Flash Region Access Permissions */
169 union ich8_hws_flash_regacc {
171 u32 grra:8; /* 0:7 GbE region Read Access */
172 u32 grwa:8; /* 8:15 GbE region Write Access */
173 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
174 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
180 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
181 * @hw: pointer to the HW structure
183 * Test access to the PHY registers by reading the PHY ID registers. If
184 * the PHY ID is already known (e.g. resume path) compare it with known ID,
185 * otherwise assume the read PHY ID is correct if it is valid.
187 * Assumes the sw/fw/hw semaphore is already acquired.
189 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
197 for (retry_count = 0; retry_count < 2; retry_count++) {
198 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
199 if (ret_val || (phy_reg == 0xFFFF))
201 phy_id = (u32)(phy_reg << 16);
203 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
204 if (ret_val || (phy_reg == 0xFFFF)) {
208 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
213 if (hw->phy.id == phy_id)
217 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
221 /* In case the PHY needs to be in mdio slow mode,
222 * set slow mode and try to get the PHY id again.
224 if (hw->mac.type < e1000_pch_lpt) {
225 hw->phy.ops.release(hw);
226 ret_val = e1000_set_mdio_slow_mode_hv(hw);
228 ret_val = e1000_get_phy_id(hw);
229 hw->phy.ops.acquire(hw);
235 if (hw->mac.type == e1000_pch_lpt) {
236 /* Unforce SMBus mode in PHY */
237 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
238 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
239 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
241 /* Unforce SMBus mode in MAC */
242 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
243 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
244 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
251 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
252 * @hw: pointer to the HW structure
254 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
255 * used to reset the PHY to a quiescent state when necessary.
257 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
261 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
263 /* Set Phy Config Counter to 50msec */
264 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
265 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
266 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
267 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
269 /* Toggle LANPHYPC Value bit */
270 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
271 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
272 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
273 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
274 E1000_WRITE_FLUSH(hw);
276 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
277 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
278 E1000_WRITE_FLUSH(hw);
280 if (hw->mac.type < e1000_pch_lpt) {
287 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
288 E1000_CTRL_EXT_LPCD) && count--);
295 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
296 * @hw: pointer to the HW structure
298 * Workarounds/flow necessary for PHY initialization during driver load
301 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
303 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
306 DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
308 /* Gate automatic PHY configuration by hardware on managed and
309 * non-managed 82579 and newer adapters.
311 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
313 /* It is not possible to be certain of the current state of ULP
314 * so forcibly disable it.
316 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
317 e1000_disable_ulp_lpt_lp(hw, TRUE);
319 ret_val = hw->phy.ops.acquire(hw);
321 DEBUGOUT("Failed to initialize PHY flow\n");
325 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
326 * inaccessible and resetting the PHY is not blocked, toggle the
327 * LANPHYPC Value bit to force the interconnect to PCIe mode.
329 switch (hw->mac.type) {
331 if (e1000_phy_is_accessible_pchlan(hw))
334 /* Before toggling LANPHYPC, see if PHY is accessible by
335 * forcing MAC to SMBus mode first.
337 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
338 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
339 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
341 /* Wait 50 milliseconds for MAC to finish any retries
342 * that it might be trying to perform from previous
343 * attempts to acknowledge any phy read requests.
349 if (e1000_phy_is_accessible_pchlan(hw))
354 if ((hw->mac.type == e1000_pchlan) &&
355 (fwsm & E1000_ICH_FWSM_FW_VALID))
358 if (hw->phy.ops.check_reset_block(hw)) {
359 DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
360 ret_val = -E1000_ERR_PHY;
364 /* Toggle LANPHYPC Value bit */
365 e1000_toggle_lanphypc_pch_lpt(hw);
366 if (hw->mac.type >= e1000_pch_lpt) {
367 if (e1000_phy_is_accessible_pchlan(hw))
370 /* Toggling LANPHYPC brings the PHY out of SMBus mode
371 * so ensure that the MAC is also out of SMBus mode
373 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
374 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
375 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
377 if (e1000_phy_is_accessible_pchlan(hw))
380 ret_val = -E1000_ERR_PHY;
387 hw->phy.ops.release(hw);
390 /* Check to see if able to reset PHY. Print error if not */
391 if (hw->phy.ops.check_reset_block(hw)) {
392 ERROR_REPORT("Reset blocked by ME\n");
396 /* Reset the PHY before any access to it. Doing so, ensures
397 * that the PHY is in a known good state before we read/write
398 * PHY registers. The generic reset is sufficient here,
399 * because we haven't determined the PHY type yet.
401 ret_val = e1000_phy_hw_reset_generic(hw);
405 /* On a successful reset, possibly need to wait for the PHY
406 * to quiesce to an accessible state before returning control
407 * to the calling function. If the PHY does not quiesce, then
408 * return E1000E_BLK_PHY_RESET, as this is the condition that
411 ret_val = hw->phy.ops.check_reset_block(hw);
413 ERROR_REPORT("ME blocked access to PHY after reset\n");
417 /* Ungate automatic PHY configuration on non-managed 82579 */
418 if ((hw->mac.type == e1000_pch2lan) &&
419 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
421 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
428 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
429 * @hw: pointer to the HW structure
431 * Initialize family-specific PHY parameters and function pointers.
433 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
435 struct e1000_phy_info *phy = &hw->phy;
438 DEBUGFUNC("e1000_init_phy_params_pchlan");
441 phy->reset_delay_us = 100;
443 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
444 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
445 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
446 phy->ops.set_page = e1000_set_page_igp;
447 phy->ops.read_reg = e1000_read_phy_reg_hv;
448 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
449 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
450 phy->ops.release = e1000_release_swflag_ich8lan;
451 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
452 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
453 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
454 phy->ops.write_reg = e1000_write_phy_reg_hv;
455 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
456 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
457 phy->ops.power_up = e1000_power_up_phy_copper;
458 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
459 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
461 phy->id = e1000_phy_unknown;
463 ret_val = e1000_init_phy_workarounds_pchlan(hw);
467 if (phy->id == e1000_phy_unknown)
468 switch (hw->mac.type) {
470 ret_val = e1000_get_phy_id(hw);
473 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
478 /* In case the PHY needs to be in mdio slow mode,
479 * set slow mode and try to get the PHY id again.
481 ret_val = e1000_set_mdio_slow_mode_hv(hw);
484 ret_val = e1000_get_phy_id(hw);
489 phy->type = e1000_get_phy_type_from_id(phy->id);
492 case e1000_phy_82577:
493 case e1000_phy_82579:
495 phy->ops.check_polarity = e1000_check_polarity_82577;
496 phy->ops.force_speed_duplex =
497 e1000_phy_force_speed_duplex_82577;
498 phy->ops.get_cable_length = e1000_get_cable_length_82577;
499 phy->ops.get_info = e1000_get_phy_info_82577;
500 phy->ops.commit = e1000_phy_sw_reset_generic;
502 case e1000_phy_82578:
503 phy->ops.check_polarity = e1000_check_polarity_m88;
504 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
505 phy->ops.get_cable_length = e1000_get_cable_length_m88;
506 phy->ops.get_info = e1000_get_phy_info_m88;
509 ret_val = -E1000_ERR_PHY;
517 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
518 * @hw: pointer to the HW structure
520 * Initialize family-specific PHY parameters and function pointers.
522 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
524 struct e1000_phy_info *phy = &hw->phy;
528 DEBUGFUNC("e1000_init_phy_params_ich8lan");
531 phy->reset_delay_us = 100;
533 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
534 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
535 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
536 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
537 phy->ops.read_reg = e1000_read_phy_reg_igp;
538 phy->ops.release = e1000_release_swflag_ich8lan;
539 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
540 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
541 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
542 phy->ops.write_reg = e1000_write_phy_reg_igp;
543 phy->ops.power_up = e1000_power_up_phy_copper;
544 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
546 /* We may need to do this twice - once for IGP and if that fails,
547 * we'll set BM func pointers and try again
549 ret_val = e1000_determine_phy_address(hw);
551 phy->ops.write_reg = e1000_write_phy_reg_bm;
552 phy->ops.read_reg = e1000_read_phy_reg_bm;
553 ret_val = e1000_determine_phy_address(hw);
555 DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
561 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
564 ret_val = e1000_get_phy_id(hw);
571 case IGP03E1000_E_PHY_ID:
572 phy->type = e1000_phy_igp_3;
573 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
574 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
575 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
576 phy->ops.get_info = e1000_get_phy_info_igp;
577 phy->ops.check_polarity = e1000_check_polarity_igp;
578 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
581 case IFE_PLUS_E_PHY_ID:
583 phy->type = e1000_phy_ife;
584 phy->autoneg_mask = E1000_ALL_NOT_GIG;
585 phy->ops.get_info = e1000_get_phy_info_ife;
586 phy->ops.check_polarity = e1000_check_polarity_ife;
587 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
589 case BME1000_E_PHY_ID:
590 phy->type = e1000_phy_bm;
591 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
592 phy->ops.read_reg = e1000_read_phy_reg_bm;
593 phy->ops.write_reg = e1000_write_phy_reg_bm;
594 phy->ops.commit = e1000_phy_sw_reset_generic;
595 phy->ops.get_info = e1000_get_phy_info_m88;
596 phy->ops.check_polarity = e1000_check_polarity_m88;
597 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
600 return -E1000_ERR_PHY;
604 return E1000_SUCCESS;
608 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
609 * @hw: pointer to the HW structure
611 * Initialize family-specific NVM parameters and function
614 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
616 struct e1000_nvm_info *nvm = &hw->nvm;
617 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
618 u32 gfpreg, sector_base_addr, sector_end_addr;
621 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
623 /* Can't read flash registers if the register set isn't mapped. */
624 nvm->type = e1000_nvm_flash_sw;
625 if (!hw->flash_address) {
626 DEBUGOUT("ERROR: Flash registers not mapped\n");
627 return -E1000_ERR_CONFIG;
630 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
632 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
633 * Add 1 to sector_end_addr since this sector is included in
636 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
637 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
639 /* flash_base_addr is byte-aligned */
640 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
642 /* find total size of the NVM, then cut in half since the total
643 * size represents two separate NVM banks.
645 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
646 << FLASH_SECTOR_ADDR_SHIFT);
647 nvm->flash_bank_size /= 2;
648 /* Adjust to word count */
649 nvm->flash_bank_size /= sizeof(u16);
651 nvm->word_size = E1000_SHADOW_RAM_WORDS;
653 /* Clear shadow ram */
654 for (i = 0; i < nvm->word_size; i++) {
655 dev_spec->shadow_ram[i].modified = FALSE;
656 dev_spec->shadow_ram[i].value = 0xFFFF;
659 /* Function Pointers */
660 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
661 nvm->ops.release = e1000_release_nvm_ich8lan;
662 nvm->ops.read = e1000_read_nvm_ich8lan;
663 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
664 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
665 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
666 nvm->ops.write = e1000_write_nvm_ich8lan;
668 return E1000_SUCCESS;
672 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
673 * @hw: pointer to the HW structure
675 * Initialize family-specific MAC parameters and function
678 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
680 struct e1000_mac_info *mac = &hw->mac;
683 DEBUGFUNC("e1000_init_mac_params_ich8lan");
685 /* Set media type function pointer */
686 hw->phy.media_type = e1000_media_type_copper;
688 /* Set mta register count */
689 mac->mta_reg_count = 32;
690 /* Set rar entry count */
691 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
692 if (mac->type == e1000_ich8lan)
693 mac->rar_entry_count--;
694 /* Set if part includes ASF firmware */
695 mac->asf_firmware_present = TRUE;
697 mac->has_fwsm = TRUE;
698 /* ARC subsystem not supported */
699 mac->arc_subsystem_valid = FALSE;
700 /* Adaptive IFS supported */
701 mac->adaptive_ifs = TRUE;
703 /* Function pointers */
705 /* bus type/speed/width */
706 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
708 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
710 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
711 /* hw initialization */
712 mac->ops.init_hw = e1000_init_hw_ich8lan;
714 mac->ops.setup_link = e1000_setup_link_ich8lan;
715 /* physical interface setup */
716 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
718 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
720 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
721 /* multicast address update */
722 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
723 /* clear hardware counters */
724 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
726 /* LED and other operations */
731 /* check management mode */
732 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
734 mac->ops.id_led_init = e1000_id_led_init_generic;
736 mac->ops.blink_led = e1000_blink_led_generic;
738 mac->ops.setup_led = e1000_setup_led_generic;
740 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
741 /* turn on/off LED */
742 mac->ops.led_on = e1000_led_on_ich8lan;
743 mac->ops.led_off = e1000_led_off_ich8lan;
746 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
747 mac->ops.rar_set = e1000_rar_set_pch2lan;
750 /* multicast address update for pch2 */
751 mac->ops.update_mc_addr_list =
752 e1000_update_mc_addr_list_pch2lan;
754 /* save PCH revision_id */
755 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
756 hw->revision_id = (u8)(pci_cfg &= 0x000F);
757 /* check management mode */
758 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
760 mac->ops.id_led_init = e1000_id_led_init_pchlan;
762 mac->ops.setup_led = e1000_setup_led_pchlan;
764 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
765 /* turn on/off LED */
766 mac->ops.led_on = e1000_led_on_pchlan;
767 mac->ops.led_off = e1000_led_off_pchlan;
773 if (mac->type == e1000_pch_lpt) {
774 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
775 mac->ops.rar_set = e1000_rar_set_pch_lpt;
776 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
777 mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt;
780 /* Enable PCS Lock-loss workaround for ICH8 */
781 if (mac->type == e1000_ich8lan)
782 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
784 return E1000_SUCCESS;
788 * __e1000_access_emi_reg_locked - Read/write EMI register
789 * @hw: pointer to the HW structure
790 * @addr: EMI address to program
791 * @data: pointer to value to read/write from/to the EMI address
792 * @read: boolean flag to indicate read or write
794 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
796 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
797 u16 *data, bool read)
801 DEBUGFUNC("__e1000_access_emi_reg_locked");
803 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
808 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
811 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
818 * e1000_read_emi_reg_locked - Read Extended Management Interface register
819 * @hw: pointer to the HW structure
820 * @addr: EMI address to program
821 * @data: value to be read from the EMI address
823 * Assumes the SW/FW/HW Semaphore is already acquired.
825 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
827 DEBUGFUNC("e1000_read_emi_reg_locked");
829 return __e1000_access_emi_reg_locked(hw, addr, data, TRUE);
833 * e1000_write_emi_reg_locked - Write Extended Management Interface register
834 * @hw: pointer to the HW structure
835 * @addr: EMI address to program
836 * @data: value to be written to the EMI address
838 * Assumes the SW/FW/HW Semaphore is already acquired.
840 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
842 DEBUGFUNC("e1000_read_emi_reg_locked");
844 return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE);
848 * e1000_set_eee_pchlan - Enable/disable EEE support
849 * @hw: pointer to the HW structure
851 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
852 * the link and the EEE capabilities of the link partner. The LPI Control
853 * register bits will remain set only if/when link is up.
855 * EEE LPI must not be asserted earlier than one second after link is up.
856 * On 82579, EEE LPI should not be enabled until such time otherwise there
857 * can be link issues with some switches. Other devices can have EEE LPI
858 * enabled immediately upon link up since they have a timer in hardware which
859 * prevents LPI from being asserted too early.
861 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
863 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
865 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
867 DEBUGFUNC("e1000_set_eee_pchlan");
869 switch (hw->phy.type) {
870 case e1000_phy_82579:
871 lpa = I82579_EEE_LP_ABILITY;
872 pcs_status = I82579_EEE_PCS_STATUS;
873 adv_addr = I82579_EEE_ADVERTISEMENT;
876 lpa = I217_EEE_LP_ABILITY;
877 pcs_status = I217_EEE_PCS_STATUS;
878 adv_addr = I217_EEE_ADVERTISEMENT;
881 return E1000_SUCCESS;
884 ret_val = hw->phy.ops.acquire(hw);
888 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
892 /* Clear bits that enable EEE in various speeds */
893 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
895 /* Enable EEE if not disabled by user */
896 if (!dev_spec->eee_disable) {
897 /* Save off link partner's EEE ability */
898 ret_val = e1000_read_emi_reg_locked(hw, lpa,
899 &dev_spec->eee_lp_ability);
903 /* Read EEE advertisement */
904 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
908 /* Enable EEE only for speeds in which the link partner is
909 * EEE capable and for which we advertise EEE.
911 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
912 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
914 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
915 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
916 if (data & NWAY_LPAR_100TX_FD_CAPS)
917 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
919 /* EEE is not supported in 100Half, so ignore
920 * partner's EEE in 100 ability if full-duplex
923 dev_spec->eee_lp_ability &=
924 ~I82579_EEE_100_SUPPORTED;
928 if (hw->phy.type == e1000_phy_82579) {
929 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
934 data &= ~I82579_LPI_100_PLL_SHUT;
935 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
939 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
940 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
944 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
946 hw->phy.ops.release(hw);
952 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
953 * @hw: pointer to the HW structure
954 * @link: link up bool flag
956 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
957 * preventing further DMA write requests. Workaround the issue by disabling
958 * the de-assertion of the clock request when in 1Gpbs mode.
959 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
960 * speeds in order to avoid Tx hangs.
962 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
964 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
965 u32 status = E1000_READ_REG(hw, E1000_STATUS);
966 s32 ret_val = E1000_SUCCESS;
969 if (link && (status & E1000_STATUS_SPEED_1000)) {
970 ret_val = hw->phy.ops.acquire(hw);
975 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
981 e1000_write_kmrn_reg_locked(hw,
982 E1000_KMRNCTRLSTA_K1_CONFIG,
984 ~E1000_KMRNCTRLSTA_K1_ENABLE);
990 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
991 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
994 e1000_write_kmrn_reg_locked(hw,
995 E1000_KMRNCTRLSTA_K1_CONFIG,
998 hw->phy.ops.release(hw);
1000 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1001 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1003 if (!link || ((status & E1000_STATUS_SPEED_100) &&
1004 (status & E1000_STATUS_FD)))
1005 goto update_fextnvm6;
1007 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1011 /* Clear link status transmit timeout */
1012 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1014 if (status & E1000_STATUS_SPEED_100) {
1015 /* Set inband Tx timeout to 5x10us for 100Half */
1016 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1018 /* Do not extend the K1 entry latency for 100Half */
1019 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1021 /* Set inband Tx timeout to 50x10us for 10Full/Half */
1023 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1025 /* Extend the K1 entry latency for 10 Mbps */
1026 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1029 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1034 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1040 static u64 e1000_ltr2ns(u16 ltr)
1044 /* Determine the latency in nsec based on the LTR value & scale */
1045 value = ltr & E1000_LTRV_VALUE_MASK;
1046 scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT;
1048 return value * (1 << (scale * E1000_LTRV_SCALE_FACTOR));
1052 * e1000_platform_pm_pch_lpt - Set platform power management values
1053 * @hw: pointer to the HW structure
1054 * @link: bool indicating link status
1056 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1057 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1058 * when link is up (which must not exceed the maximum latency supported
1059 * by the platform), otherwise specify there is no LTR requirement.
1060 * Unlike TRUE-PCIe devices which set the LTR maximum snoop/no-snoop
1061 * latencies in the LTR Extended Capability Structure in the PCIe Extended
1062 * Capability register set, on this device LTR is set by writing the
1063 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1064 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1065 * message to the PMC.
1067 * Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF)
1070 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1072 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1073 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1074 u16 lat_enc = 0; /* latency encoded */
1077 DEBUGFUNC("e1000_platform_pm_pch_lpt");
1080 u16 speed, duplex, scale = 0;
1081 u16 max_snoop, max_nosnoop;
1082 u16 max_ltr_enc; /* max LTR latency encoded */
1083 s64 lat_ns; /* latency (ns) */
1087 if (!hw->mac.max_frame_size) {
1088 DEBUGOUT("max_frame_size not set.\n");
1089 return -E1000_ERR_CONFIG;
1092 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1094 DEBUGOUT("Speed not set.\n");
1095 return -E1000_ERR_CONFIG;
1098 /* Rx Packet Buffer Allocation size (KB) */
1099 rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK;
1101 /* Determine the maximum latency tolerated by the device.
1103 * Per the PCIe spec, the tolerated latencies are encoded as
1104 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1105 * a 10-bit value (0-1023) to provide a range from 1 ns to
1106 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1107 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1109 lat_ns = ((s64)rxa * 1024 -
1110 (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000;
1117 while (value > E1000_LTRV_VALUE_MASK) {
1119 value = E1000_DIVIDE_ROUND_UP(value, (1 << 5));
1121 if (scale > E1000_LTRV_SCALE_MAX) {
1122 DEBUGOUT1("Invalid LTR latency scale %d\n", scale);
1123 return -E1000_ERR_CONFIG;
1125 lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value);
1127 /* Determine the maximum latency tolerated by the platform */
1128 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop);
1129 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1130 max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop);
1132 if (lat_enc > max_ltr_enc) {
1133 lat_enc = max_ltr_enc;
1134 lat_ns = e1000_ltr2ns(max_ltr_enc);
1138 lat_ns *= speed * 1000;
1140 lat_ns /= 1000000000;
1141 obff_hwm = (s32)(rxa - lat_ns);
1143 if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) {
1144 DEBUGOUT1("Invalid high water mark %d\n", obff_hwm);
1145 return -E1000_ERR_CONFIG;
1149 /* Set Snoop and No-Snoop latencies the same */
1150 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1151 E1000_WRITE_REG(hw, E1000_LTRV, reg);
1153 /* Set OBFF high water mark */
1154 reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;
1156 E1000_WRITE_REG(hw, E1000_SVT, reg);
1159 reg = E1000_READ_REG(hw, E1000_SVCR);
1160 reg |= E1000_SVCR_OFF_EN;
1161 /* Always unblock interrupts to the CPU even when the system is
1162 * in OBFF mode. This ensures that small round-robin traffic
1163 * (like ping) does not get dropped or experience long latency.
1165 reg |= E1000_SVCR_OFF_MASKINT;
1166 E1000_WRITE_REG(hw, E1000_SVCR, reg);
1168 return E1000_SUCCESS;
1172 * e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer
1173 * @hw: pointer to the HW structure
1174 * @itr: interrupt throttling rate
1176 * Configure OBFF with the updated interrupt rate.
1178 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr)
1183 DEBUGFUNC("e1000_set_obff_timer_pch_lpt");
1185 /* Convert ITR value into microseconds for OBFF timer */
1186 timer = itr & E1000_ITR_MASK;
1187 timer = (timer * E1000_ITR_MULT) / 1000;
1189 if ((timer < 0) || (timer > E1000_ITR_MASK)) {
1190 DEBUGOUT1("Invalid OBFF timer %d\n", timer);
1191 return -E1000_ERR_CONFIG;
1194 svcr = E1000_READ_REG(hw, E1000_SVCR);
1195 svcr &= ~E1000_SVCR_OFF_TIMER_MASK;
1196 svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT;
1197 E1000_WRITE_REG(hw, E1000_SVCR, svcr);
1199 return E1000_SUCCESS;
1203 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1204 * @hw: pointer to the HW structure
1205 * @to_sx: boolean indicating a system power state transition to Sx
1207 * When link is down, configure ULP mode to significantly reduce the power
1208 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1209 * ME firmware to start the ULP configuration. If not on an ME enabled
1210 * system, configure the ULP mode by software.
1212 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1215 s32 ret_val = E1000_SUCCESS;
1218 if ((hw->mac.type < e1000_pch_lpt) ||
1219 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1220 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1221 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1222 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1223 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1226 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1227 /* Request ME configure ULP mode in the PHY */
1228 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1229 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1230 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1238 /* Poll up to 5 seconds for Cable Disconnected indication */
1239 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1240 E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1241 /* Bail if link is re-acquired */
1242 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1243 return -E1000_ERR_PHY;
1250 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1251 (E1000_READ_REG(hw, E1000_FEXT) &
1252 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1256 ret_val = hw->phy.ops.acquire(hw);
1260 /* Force SMBus mode in PHY */
1261 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1264 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1265 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1267 /* Force SMBus mode in MAC */
1268 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1269 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1270 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1272 /* Set Inband ULP Exit, Reset to SMBus mode and
1273 * Disable SMBus Release on PERST# in PHY
1275 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1278 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1279 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1281 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1282 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1284 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1286 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1288 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1290 /* Set Disable SMBus Release on PERST# in MAC */
1291 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1292 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1293 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1295 /* Commit ULP changes in PHY by starting auto ULP configuration */
1296 phy_reg |= I218_ULP_CONFIG1_START;
1297 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1299 hw->phy.ops.release(hw);
1302 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1304 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1310 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1311 * @hw: pointer to the HW structure
1312 * @force: boolean indicating whether or not to force disabling ULP
1314 * Un-configure ULP mode when link is up, the system is transitioned from
1315 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1316 * system, poll for an indication from ME that ULP has been un-configured.
1317 * If not on an ME enabled system, un-configure the ULP mode by software.
1319 * During nominal operation, this function is called when link is acquired
1320 * to disable ULP mode (force=FALSE); otherwise, for example when unloading
1321 * the driver or during Sx->S0 transitions, this is called with force=TRUE
1322 * to forcibly disable ULP.
1324 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1326 s32 ret_val = E1000_SUCCESS;
1331 if ((hw->mac.type < e1000_pch_lpt) ||
1332 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1333 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1334 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1335 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1336 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1339 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1341 /* Request ME un-configure ULP mode in the PHY */
1342 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1343 mac_reg &= ~E1000_H2ME_ULP;
1344 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1345 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1348 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1349 while (E1000_READ_REG(hw, E1000_FWSM) &
1350 E1000_FWSM_ULP_CFG_DONE) {
1352 ret_val = -E1000_ERR_PHY;
1358 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1361 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1362 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1363 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1365 /* Clear H2ME.ULP after ME ULP configuration */
1366 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1367 mac_reg &= ~E1000_H2ME_ULP;
1368 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1374 ret_val = hw->phy.ops.acquire(hw);
1379 /* Toggle LANPHYPC Value bit */
1380 e1000_toggle_lanphypc_pch_lpt(hw);
1382 /* Unforce SMBus mode in PHY */
1383 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1385 /* The MAC might be in PCIe mode, so temporarily force to
1386 * SMBus mode in order to access the PHY.
1388 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1389 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1390 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1394 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1399 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1400 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1402 /* Unforce SMBus mode in MAC */
1403 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1404 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1405 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1407 /* When ULP mode was previously entered, K1 was disabled by the
1408 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1410 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1413 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1414 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1416 /* Clear ULP enabled configuration */
1417 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1420 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1421 I218_ULP_CONFIG1_STICKY_ULP |
1422 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1423 I218_ULP_CONFIG1_WOL_HOST |
1424 I218_ULP_CONFIG1_INBAND_EXIT |
1425 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1426 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1428 /* Commit ULP changes by starting auto ULP configuration */
1429 phy_reg |= I218_ULP_CONFIG1_START;
1430 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1432 /* Clear Disable SMBus Release on PERST# in MAC */
1433 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1434 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1435 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1438 hw->phy.ops.release(hw);
1440 hw->phy.ops.reset(hw);
1445 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1447 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1453 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1454 * @hw: pointer to the HW structure
1456 * Checks to see of the link status of the hardware has changed. If a
1457 * change in link status has been detected, then we read the PHY registers
1458 * to get the current speed/duplex if link exists.
1460 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1462 struct e1000_mac_info *mac = &hw->mac;
1467 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1469 /* We only want to go out to the PHY registers to see if Auto-Neg
1470 * has completed and/or if our link status has changed. The
1471 * get_link_status flag is set upon receiving a Link Status
1472 * Change or Rx Sequence Error interrupt.
1474 if (!mac->get_link_status)
1475 return E1000_SUCCESS;
1477 /* First we want to see if the MII Status Register reports
1478 * link. If so, then we want to get the current speed/duplex
1481 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1485 if (hw->mac.type == e1000_pchlan) {
1486 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1491 /* When connected at 10Mbps half-duplex, some parts are excessively
1492 * aggressive resulting in many collisions. To avoid this, increase
1493 * the IPG and reduce Rx latency in the PHY.
1495 if (((hw->mac.type == e1000_pch2lan) ||
1496 (hw->mac.type == e1000_pch_lpt)) && link) {
1498 reg = E1000_READ_REG(hw, E1000_STATUS);
1499 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1502 reg = E1000_READ_REG(hw, E1000_TIPG);
1503 reg &= ~E1000_TIPG_IPGT_MASK;
1505 E1000_WRITE_REG(hw, E1000_TIPG, reg);
1507 /* Reduce Rx latency in analog PHY */
1508 ret_val = hw->phy.ops.acquire(hw);
1512 if (hw->mac.type == e1000_pch2lan)
1513 emi_addr = I82579_RX_CONFIG;
1515 emi_addr = I217_RX_CONFIG;
1516 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, 0);
1518 hw->phy.ops.release(hw);
1525 /* Work-around I218 hang issue */
1526 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1527 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1528 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1529 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1530 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1534 if (hw->mac.type == e1000_pch_lpt) {
1535 /* Set platform power management values for
1536 * Latency Tolerance Reporting (LTR)
1537 * Optimized Buffer Flush/Fill (OBFF)
1539 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1544 /* Clear link partner's EEE ability */
1545 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1548 return E1000_SUCCESS; /* No link detected */
1550 mac->get_link_status = FALSE;
1552 switch (hw->mac.type) {
1554 ret_val = e1000_k1_workaround_lv(hw);
1559 if (hw->phy.type == e1000_phy_82578) {
1560 ret_val = e1000_link_stall_workaround_hv(hw);
1565 /* Workaround for PCHx parts in half-duplex:
1566 * Set the number of preambles removed from the packet
1567 * when it is passed from the PHY to the MAC to prevent
1568 * the MAC from misinterpreting the packet type.
1570 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1571 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1573 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1575 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1577 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1583 /* Check if there was DownShift, must be checked
1584 * immediately after link-up
1586 e1000_check_downshift_generic(hw);
1588 /* Enable/Disable EEE after link up */
1589 if (hw->phy.type > e1000_phy_82579) {
1590 ret_val = e1000_set_eee_pchlan(hw);
1595 /* If we are forcing speed/duplex, then we simply return since
1596 * we have already determined whether we have link or not.
1599 return -E1000_ERR_CONFIG;
1601 /* Auto-Neg is enabled. Auto Speed Detection takes care
1602 * of MAC speed/duplex configuration. So we only need to
1603 * configure Collision Distance in the MAC.
1605 mac->ops.config_collision_dist(hw);
1607 /* Configure Flow Control now that Auto-Neg has completed.
1608 * First, we need to restore the desired flow control
1609 * settings because we may have had to re-autoneg with a
1610 * different link partner.
1612 ret_val = e1000_config_fc_after_link_up_generic(hw);
1614 DEBUGOUT("Error configuring flow control\n");
1620 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1621 * @hw: pointer to the HW structure
1623 * Initialize family-specific function pointers for PHY, MAC, and NVM.
1625 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1627 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1629 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1630 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1631 switch (hw->mac.type) {
1634 case e1000_ich10lan:
1635 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1640 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1648 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1649 * @hw: pointer to the HW structure
1651 * Acquires the mutex for performing NVM operations.
1653 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1655 DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1656 return E1000_SUCCESS;
1660 * e1000_release_nvm_ich8lan - Release NVM mutex
1661 * @hw: pointer to the HW structure
1663 * Releases the mutex used while performing NVM operations.
1665 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1667 DEBUGFUNC("e1000_release_nvm_ich8lan");
1672 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1673 * @hw: pointer to the HW structure
1675 * Acquires the software control flag for performing PHY and select
1678 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1680 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1681 s32 ret_val = E1000_SUCCESS;
1683 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1686 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1687 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1695 DEBUGOUT("SW has already locked the resource.\n");
1696 ret_val = -E1000_ERR_CONFIG;
1700 timeout = SW_FLAG_TIMEOUT;
1702 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1703 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1706 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1707 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1715 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1716 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1717 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1718 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1719 ret_val = -E1000_ERR_CONFIG;
1728 * e1000_release_swflag_ich8lan - Release software control flag
1729 * @hw: pointer to the HW structure
1731 * Releases the software control flag for performing PHY and select
1734 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1738 DEBUGFUNC("e1000_release_swflag_ich8lan");
1740 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1742 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1743 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1744 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1746 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1752 * e1000_check_mng_mode_ich8lan - Checks management mode
1753 * @hw: pointer to the HW structure
1755 * This checks if the adapter has any manageability enabled.
1756 * This is a function pointer entry point only called by read/write
1757 * routines for the PHY and NVM parts.
1759 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1763 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1765 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1767 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1768 ((fwsm & E1000_FWSM_MODE_MASK) ==
1769 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1773 * e1000_check_mng_mode_pchlan - Checks management mode
1774 * @hw: pointer to the HW structure
1776 * This checks if the adapter has iAMT enabled.
1777 * This is a function pointer entry point only called by read/write
1778 * routines for the PHY and NVM parts.
1780 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1784 DEBUGFUNC("e1000_check_mng_mode_pchlan");
1786 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1788 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1789 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1793 * e1000_rar_set_pch2lan - Set receive address register
1794 * @hw: pointer to the HW structure
1795 * @addr: pointer to the receive address
1796 * @index: receive address array register
1798 * Sets the receive address array register at index to the address passed
1799 * in by addr. For 82579, RAR[0] is the base address register that is to
1800 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1801 * Use SHRA[0-3] in place of those reserved for ME.
1803 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1805 u32 rar_low, rar_high;
1807 DEBUGFUNC("e1000_rar_set_pch2lan");
1809 /* HW expects these in little endian so we reverse the byte order
1810 * from network order (big endian) to little endian
1812 rar_low = ((u32) addr[0] |
1813 ((u32) addr[1] << 8) |
1814 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1816 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1818 /* If MAC address zero, no need to set the AV bit */
1819 if (rar_low || rar_high)
1820 rar_high |= E1000_RAH_AV;
1823 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1824 E1000_WRITE_FLUSH(hw);
1825 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1826 E1000_WRITE_FLUSH(hw);
1827 return E1000_SUCCESS;
1830 /* RAR[1-6] are owned by manageability. Skip those and program the
1831 * next address into the SHRA register array.
1833 if (index < (u32) (hw->mac.rar_entry_count)) {
1836 ret_val = e1000_acquire_swflag_ich8lan(hw);
1840 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1841 E1000_WRITE_FLUSH(hw);
1842 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1843 E1000_WRITE_FLUSH(hw);
1845 e1000_release_swflag_ich8lan(hw);
1847 /* verify the register updates */
1848 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1849 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1850 return E1000_SUCCESS;
1852 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1853 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1857 DEBUGOUT1("Failed to write receive address at index %d\n", index);
1858 return -E1000_ERR_CONFIG;
1862 * e1000_rar_set_pch_lpt - Set receive address registers
1863 * @hw: pointer to the HW structure
1864 * @addr: pointer to the receive address
1865 * @index: receive address array register
1867 * Sets the receive address register array at index to the address passed
1868 * in by addr. For LPT, RAR[0] is the base address register that is to
1869 * contain the MAC address. SHRA[0-10] are the shared receive address
1870 * registers that are shared between the Host and manageability engine (ME).
1872 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1874 u32 rar_low, rar_high;
1877 DEBUGFUNC("e1000_rar_set_pch_lpt");
1879 /* HW expects these in little endian so we reverse the byte order
1880 * from network order (big endian) to little endian
1882 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
1883 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1885 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1887 /* If MAC address zero, no need to set the AV bit */
1888 if (rar_low || rar_high)
1889 rar_high |= E1000_RAH_AV;
1892 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1893 E1000_WRITE_FLUSH(hw);
1894 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1895 E1000_WRITE_FLUSH(hw);
1896 return E1000_SUCCESS;
1899 /* The manageability engine (ME) can lock certain SHRAR registers that
1900 * it is using - those registers are unavailable for use.
1902 if (index < hw->mac.rar_entry_count) {
1903 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
1904 E1000_FWSM_WLOCK_MAC_MASK;
1905 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1907 /* Check if all SHRAR registers are locked */
1911 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1914 ret_val = e1000_acquire_swflag_ich8lan(hw);
1919 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
1921 E1000_WRITE_FLUSH(hw);
1922 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
1924 E1000_WRITE_FLUSH(hw);
1926 e1000_release_swflag_ich8lan(hw);
1928 /* verify the register updates */
1929 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1930 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
1931 return E1000_SUCCESS;
1936 DEBUGOUT1("Failed to write receive address at index %d\n", index);
1937 return -E1000_ERR_CONFIG;
1941 * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
1942 * @hw: pointer to the HW structure
1943 * @mc_addr_list: array of multicast addresses to program
1944 * @mc_addr_count: number of multicast addresses to program
1946 * Updates entire Multicast Table Array of the PCH2 MAC and PHY.
1947 * The caller must have a packed mc_addr_list of multicast addresses.
1949 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
1957 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
1959 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
1961 ret_val = hw->phy.ops.acquire(hw);
1965 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1969 for (i = 0; i < hw->mac.mta_reg_count; i++) {
1970 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
1971 (u16)(hw->mac.mta_shadow[i] &
1973 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
1974 (u16)((hw->mac.mta_shadow[i] >> 16) &
1978 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1981 hw->phy.ops.release(hw);
1985 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1986 * @hw: pointer to the HW structure
1988 * Checks if firmware is blocking the reset of the PHY.
1989 * This is a function pointer entry point only called by
1992 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1995 bool blocked = FALSE;
1998 DEBUGFUNC("e1000_check_reset_block_ich8lan");
2001 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2002 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2008 } while (blocked && (i++ < 10));
2009 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2013 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2014 * @hw: pointer to the HW structure
2016 * Assumes semaphore already acquired.
2019 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2022 u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2023 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2024 E1000_STRAP_SMT_FREQ_SHIFT;
2027 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2029 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2033 phy_data &= ~HV_SMB_ADDR_MASK;
2034 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2035 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2037 if (hw->phy.type == e1000_phy_i217) {
2038 /* Restore SMBus frequency */
2040 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2041 phy_data |= (freq & (1 << 0)) <<
2042 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2043 phy_data |= (freq & (1 << 1)) <<
2044 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2046 DEBUGOUT("Unsupported SMB frequency in PHY\n");
2050 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2054 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2055 * @hw: pointer to the HW structure
2057 * SW should configure the LCD from the NVM extended configuration region
2058 * as a workaround for certain parts.
2060 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2062 struct e1000_phy_info *phy = &hw->phy;
2063 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2064 s32 ret_val = E1000_SUCCESS;
2065 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2067 DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2069 /* Initialize the PHY from the NVM on ICH platforms. This
2070 * is needed due to an issue where the NVM configuration is
2071 * not properly autoloaded after power transitions.
2072 * Therefore, after each PHY reset, we will load the
2073 * configuration data out of the NVM manually.
2075 switch (hw->mac.type) {
2077 if (phy->type != e1000_phy_igp_3)
2080 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2081 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2082 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2089 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2095 ret_val = hw->phy.ops.acquire(hw);
2099 data = E1000_READ_REG(hw, E1000_FEXTNVM);
2100 if (!(data & sw_cfg_mask))
2103 /* Make sure HW does not configure LCD from PHY
2104 * extended configuration before SW configuration
2106 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2107 if ((hw->mac.type < e1000_pch2lan) &&
2108 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2111 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2112 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2113 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2117 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2118 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2120 if (((hw->mac.type == e1000_pchlan) &&
2121 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2122 (hw->mac.type > e1000_pchlan)) {
2123 /* HW configures the SMBus address and LEDs when the
2124 * OEM and LCD Write Enable bits are set in the NVM.
2125 * When both NVM bits are cleared, SW will configure
2128 ret_val = e1000_write_smbus_addr(hw);
2132 data = E1000_READ_REG(hw, E1000_LEDCTL);
2133 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2139 /* Configure LCD from extended configuration region. */
2141 /* cnf_base_addr is in DWORD */
2142 word_addr = (u16)(cnf_base_addr << 1);
2144 for (i = 0; i < cnf_size; i++) {
2145 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2150 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2155 /* Save off the PHY page for future writes. */
2156 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2157 phy_page = reg_data;
2161 reg_addr &= PHY_REG_MASK;
2162 reg_addr |= phy_page;
2164 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2171 hw->phy.ops.release(hw);
2176 * e1000_k1_gig_workaround_hv - K1 Si workaround
2177 * @hw: pointer to the HW structure
2178 * @link: link up bool flag
2180 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2181 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2182 * If link is down, the function will restore the default K1 setting located
2185 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2187 s32 ret_val = E1000_SUCCESS;
2189 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2191 DEBUGFUNC("e1000_k1_gig_workaround_hv");
2193 if (hw->mac.type != e1000_pchlan)
2194 return E1000_SUCCESS;
2196 /* Wrap the whole flow with the sw flag */
2197 ret_val = hw->phy.ops.acquire(hw);
2201 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2203 if (hw->phy.type == e1000_phy_82578) {
2204 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2209 status_reg &= (BM_CS_STATUS_LINK_UP |
2210 BM_CS_STATUS_RESOLVED |
2211 BM_CS_STATUS_SPEED_MASK);
2213 if (status_reg == (BM_CS_STATUS_LINK_UP |
2214 BM_CS_STATUS_RESOLVED |
2215 BM_CS_STATUS_SPEED_1000))
2219 if (hw->phy.type == e1000_phy_82577) {
2220 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2225 status_reg &= (HV_M_STATUS_LINK_UP |
2226 HV_M_STATUS_AUTONEG_COMPLETE |
2227 HV_M_STATUS_SPEED_MASK);
2229 if (status_reg == (HV_M_STATUS_LINK_UP |
2230 HV_M_STATUS_AUTONEG_COMPLETE |
2231 HV_M_STATUS_SPEED_1000))
2235 /* Link stall fix for link up */
2236 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2242 /* Link stall fix for link down */
2243 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2249 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2252 hw->phy.ops.release(hw);
2258 * e1000_configure_k1_ich8lan - Configure K1 power state
2259 * @hw: pointer to the HW structure
2260 * @enable: K1 state to configure
2262 * Configure the K1 power state based on the provided parameter.
2263 * Assumes semaphore already acquired.
2265 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2267 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2275 DEBUGFUNC("e1000_configure_k1_ich8lan");
2277 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2283 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2285 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2287 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2293 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2294 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2296 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2297 reg |= E1000_CTRL_FRCSPD;
2298 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2300 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2301 E1000_WRITE_FLUSH(hw);
2303 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2304 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2305 E1000_WRITE_FLUSH(hw);
2308 return E1000_SUCCESS;
2312 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2313 * @hw: pointer to the HW structure
2314 * @d0_state: boolean if entering d0 or d3 device state
2316 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2317 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2318 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2320 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2326 DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2328 if (hw->mac.type < e1000_pchlan)
2331 ret_val = hw->phy.ops.acquire(hw);
2335 if (hw->mac.type == e1000_pchlan) {
2336 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2337 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2341 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2342 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2345 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2347 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2351 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2354 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2355 oem_reg |= HV_OEM_BITS_GBE_DIS;
2357 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2358 oem_reg |= HV_OEM_BITS_LPLU;
2360 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2361 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2362 oem_reg |= HV_OEM_BITS_GBE_DIS;
2364 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2365 E1000_PHY_CTRL_NOND0A_LPLU))
2366 oem_reg |= HV_OEM_BITS_LPLU;
2369 /* Set Restart auto-neg to activate the bits */
2370 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2371 !hw->phy.ops.check_reset_block(hw))
2372 oem_reg |= HV_OEM_BITS_RESTART_AN;
2374 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2377 hw->phy.ops.release(hw);
2384 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2385 * @hw: pointer to the HW structure
2387 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2392 DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2394 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2398 data |= HV_KMRN_MDIO_SLOW;
2400 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2406 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2407 * done after every PHY reset.
2409 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2411 s32 ret_val = E1000_SUCCESS;
2414 DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2416 if (hw->mac.type != e1000_pchlan)
2417 return E1000_SUCCESS;
2419 /* Set MDIO slow mode before any other MDIO access */
2420 if (hw->phy.type == e1000_phy_82577) {
2421 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2426 if (((hw->phy.type == e1000_phy_82577) &&
2427 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2428 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2429 /* Disable generation of early preamble */
2430 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2434 /* Preamble tuning for SSC */
2435 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2441 if (hw->phy.type == e1000_phy_82578) {
2442 /* Return registers to default by doing a soft reset then
2443 * writing 0x3140 to the control register.
2445 if (hw->phy.revision < 2) {
2446 e1000_phy_sw_reset_generic(hw);
2447 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2453 ret_val = hw->phy.ops.acquire(hw);
2458 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2459 hw->phy.ops.release(hw);
2463 /* Configure the K1 Si workaround during phy reset assuming there is
2464 * link so that it disables K1 if link is in 1Gbps.
2466 ret_val = e1000_k1_gig_workaround_hv(hw, TRUE);
2470 /* Workaround for link disconnects on a busy hub in half duplex */
2471 ret_val = hw->phy.ops.acquire(hw);
2474 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2477 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2482 /* set MSE higher to enable link to stay up when noise is high */
2483 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2485 hw->phy.ops.release(hw);
2491 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2492 * @hw: pointer to the HW structure
2494 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2500 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2502 ret_val = hw->phy.ops.acquire(hw);
2505 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2509 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2510 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2511 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2512 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2513 (u16)(mac_reg & 0xFFFF));
2514 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2515 (u16)((mac_reg >> 16) & 0xFFFF));
2517 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2518 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2519 (u16)(mac_reg & 0xFFFF));
2520 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2521 (u16)((mac_reg & E1000_RAH_AV)
2525 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2528 hw->phy.ops.release(hw);
2531 static u32 e1000_calc_rx_da_crc(u8 mac[])
2533 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
2534 u32 i, j, mask, crc;
2536 DEBUGFUNC("e1000_calc_rx_da_crc");
2539 for (i = 0; i < 6; i++) {
2541 for (j = 8; j > 0; j--) {
2542 mask = (crc & 1) * (-1);
2543 crc = (crc >> 1) ^ (poly & mask);
2550 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2552 * @hw: pointer to the HW structure
2553 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2555 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2557 s32 ret_val = E1000_SUCCESS;
2562 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2564 if (hw->mac.type < e1000_pch2lan)
2565 return E1000_SUCCESS;
2567 /* disable Rx path while enabling/disabling workaround */
2568 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2569 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2570 phy_reg | (1 << 14));
2575 /* Write Rx addresses (rar_entry_count for RAL/H, and
2576 * SHRAL/H) and initial CRC values to the MAC
2578 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2579 u8 mac_addr[ETH_ADDR_LEN] = {0};
2580 u32 addr_high, addr_low;
2582 addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2583 if (!(addr_high & E1000_RAH_AV))
2585 addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2586 mac_addr[0] = (addr_low & 0xFF);
2587 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2588 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2589 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2590 mac_addr[4] = (addr_high & 0xFF);
2591 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2593 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2594 e1000_calc_rx_da_crc(mac_addr));
2597 /* Write Rx addresses to the PHY */
2598 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2600 /* Enable jumbo frame workaround in the MAC */
2601 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2602 mac_reg &= ~(1 << 14);
2603 mac_reg |= (7 << 15);
2604 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2606 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2607 mac_reg |= E1000_RCTL_SECRC;
2608 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2610 ret_val = e1000_read_kmrn_reg_generic(hw,
2611 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2615 ret_val = e1000_write_kmrn_reg_generic(hw,
2616 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2620 ret_val = e1000_read_kmrn_reg_generic(hw,
2621 E1000_KMRNCTRLSTA_HD_CTRL,
2625 data &= ~(0xF << 8);
2627 ret_val = e1000_write_kmrn_reg_generic(hw,
2628 E1000_KMRNCTRLSTA_HD_CTRL,
2633 /* Enable jumbo frame workaround in the PHY */
2634 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2635 data &= ~(0x7F << 5);
2636 data |= (0x37 << 5);
2637 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2640 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2642 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2645 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2646 data &= ~(0x3FF << 2);
2647 data |= (E1000_TX_PTR_GAP << 2);
2648 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2651 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2654 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2655 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2660 /* Write MAC register values back to h/w defaults */
2661 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2662 mac_reg &= ~(0xF << 14);
2663 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2665 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2666 mac_reg &= ~E1000_RCTL_SECRC;
2667 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2669 ret_val = e1000_read_kmrn_reg_generic(hw,
2670 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2674 ret_val = e1000_write_kmrn_reg_generic(hw,
2675 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2679 ret_val = e1000_read_kmrn_reg_generic(hw,
2680 E1000_KMRNCTRLSTA_HD_CTRL,
2684 data &= ~(0xF << 8);
2686 ret_val = e1000_write_kmrn_reg_generic(hw,
2687 E1000_KMRNCTRLSTA_HD_CTRL,
2692 /* Write PHY register values back to h/w defaults */
2693 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2694 data &= ~(0x7F << 5);
2695 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2698 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2700 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2703 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2704 data &= ~(0x3FF << 2);
2706 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2709 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2712 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2713 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2719 /* re-enable Rx path after enabling/disabling workaround */
2720 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2725 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2726 * done after every PHY reset.
2728 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2730 s32 ret_val = E1000_SUCCESS;
2732 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2734 if (hw->mac.type != e1000_pch2lan)
2735 return E1000_SUCCESS;
2737 /* Set MDIO slow mode before any other MDIO access */
2738 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2742 ret_val = hw->phy.ops.acquire(hw);
2745 /* set MSE higher to enable link to stay up when noise is high */
2746 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2749 /* drop link after 5 times MSE threshold was reached */
2750 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2752 hw->phy.ops.release(hw);
2758 * e1000_k1_gig_workaround_lv - K1 Si workaround
2759 * @hw: pointer to the HW structure
2761 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2762 * Disable K1 for 1000 and 100 speeds
2764 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2766 s32 ret_val = E1000_SUCCESS;
2769 DEBUGFUNC("e1000_k1_workaround_lv");
2771 if (hw->mac.type != e1000_pch2lan)
2772 return E1000_SUCCESS;
2774 /* Set K1 beacon duration based on 10Mbs speed */
2775 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2779 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2780 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2782 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2785 /* LV 1G/100 Packet drop issue wa */
2786 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2790 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2791 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2797 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2798 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2799 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2800 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2808 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2809 * @hw: pointer to the HW structure
2810 * @gate: boolean set to TRUE to gate, FALSE to ungate
2812 * Gate/ungate the automatic PHY configuration via hardware; perform
2813 * the configuration via software instead.
2815 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2819 DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2821 if (hw->mac.type < e1000_pch2lan)
2824 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2827 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2829 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2831 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2835 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2836 * @hw: pointer to the HW structure
2838 * Check the appropriate indication the MAC has finished configuring the
2839 * PHY after a software reset.
2841 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2843 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2845 DEBUGFUNC("e1000_lan_init_done_ich8lan");
2847 /* Wait for basic configuration completes before proceeding */
2849 data = E1000_READ_REG(hw, E1000_STATUS);
2850 data &= E1000_STATUS_LAN_INIT_DONE;
2852 } while ((!data) && --loop);
2854 /* If basic configuration is incomplete before the above loop
2855 * count reaches 0, loading the configuration from NVM will
2856 * leave the PHY in a bad state possibly resulting in no link.
2859 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
2861 /* Clear the Init Done bit for the next init event */
2862 data = E1000_READ_REG(hw, E1000_STATUS);
2863 data &= ~E1000_STATUS_LAN_INIT_DONE;
2864 E1000_WRITE_REG(hw, E1000_STATUS, data);
2868 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2869 * @hw: pointer to the HW structure
2871 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2873 s32 ret_val = E1000_SUCCESS;
2876 DEBUGFUNC("e1000_post_phy_reset_ich8lan");
2878 if (hw->phy.ops.check_reset_block(hw))
2879 return E1000_SUCCESS;
2881 /* Allow time for h/w to get to quiescent state after reset */
2884 /* Perform any necessary post-reset workarounds */
2885 switch (hw->mac.type) {
2887 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2892 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2900 /* Clear the host wakeup bit after lcd reset */
2901 if (hw->mac.type >= e1000_pchlan) {
2902 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);
2903 reg &= ~BM_WUC_HOST_WU_BIT;
2904 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
2907 /* Configure the LCD with the extended configuration region in NVM */
2908 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2912 /* Configure the LCD with the OEM bits in NVM */
2913 ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE);
2915 if (hw->mac.type == e1000_pch2lan) {
2916 /* Ungate automatic PHY configuration on non-managed 82579 */
2917 if (!(E1000_READ_REG(hw, E1000_FWSM) &
2918 E1000_ICH_FWSM_FW_VALID)) {
2920 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
2923 /* Set EEE LPI Update Timer to 200usec */
2924 ret_val = hw->phy.ops.acquire(hw);
2927 ret_val = e1000_write_emi_reg_locked(hw,
2928 I82579_LPI_UPDATE_TIMER,
2930 hw->phy.ops.release(hw);
2937 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2938 * @hw: pointer to the HW structure
2941 * This is a function pointer entry point called by drivers
2942 * or other shared routines.
2944 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2946 s32 ret_val = E1000_SUCCESS;
2948 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
2950 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2951 if ((hw->mac.type == e1000_pch2lan) &&
2952 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
2953 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
2955 ret_val = e1000_phy_hw_reset_generic(hw);
2959 return e1000_post_phy_reset_ich8lan(hw);
2963 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2964 * @hw: pointer to the HW structure
2965 * @active: TRUE to enable LPLU, FALSE to disable
2967 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2968 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2969 * the phy speed. This function will manually set the LPLU bit and restart
2970 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2971 * since it configures the same bit.
2973 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2978 DEBUGFUNC("e1000_set_lplu_state_pchlan");
2980 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
2985 oem_reg |= HV_OEM_BITS_LPLU;
2987 oem_reg &= ~HV_OEM_BITS_LPLU;
2989 if (!hw->phy.ops.check_reset_block(hw))
2990 oem_reg |= HV_OEM_BITS_RESTART_AN;
2992 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
2996 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2997 * @hw: pointer to the HW structure
2998 * @active: TRUE to enable LPLU, FALSE to disable
3000 * Sets the LPLU D0 state according to the active flag. When
3001 * activating LPLU this function also disables smart speed
3002 * and vice versa. LPLU will not be activated unless the
3003 * device autonegotiation advertisement meets standards of
3004 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3005 * This is a function pointer entry point only called by
3006 * PHY setup routines.
3008 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3010 struct e1000_phy_info *phy = &hw->phy;
3012 s32 ret_val = E1000_SUCCESS;
3015 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3017 if (phy->type == e1000_phy_ife)
3018 return E1000_SUCCESS;
3020 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3023 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3024 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3026 if (phy->type != e1000_phy_igp_3)
3027 return E1000_SUCCESS;
3029 /* Call gig speed drop workaround on LPLU before accessing
3032 if (hw->mac.type == e1000_ich8lan)
3033 e1000_gig_downshift_workaround_ich8lan(hw);
3035 /* When LPLU is enabled, we should disable SmartSpeed */
3036 ret_val = phy->ops.read_reg(hw,
3037 IGP01E1000_PHY_PORT_CONFIG,
3041 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3042 ret_val = phy->ops.write_reg(hw,
3043 IGP01E1000_PHY_PORT_CONFIG,
3048 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3049 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3051 if (phy->type != e1000_phy_igp_3)
3052 return E1000_SUCCESS;
3054 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3055 * during Dx states where the power conservation is most
3056 * important. During driver activity we should enable
3057 * SmartSpeed, so performance is maintained.
3059 if (phy->smart_speed == e1000_smart_speed_on) {
3060 ret_val = phy->ops.read_reg(hw,
3061 IGP01E1000_PHY_PORT_CONFIG,
3066 data |= IGP01E1000_PSCFR_SMART_SPEED;
3067 ret_val = phy->ops.write_reg(hw,
3068 IGP01E1000_PHY_PORT_CONFIG,
3072 } else if (phy->smart_speed == e1000_smart_speed_off) {
3073 ret_val = phy->ops.read_reg(hw,
3074 IGP01E1000_PHY_PORT_CONFIG,
3079 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3080 ret_val = phy->ops.write_reg(hw,
3081 IGP01E1000_PHY_PORT_CONFIG,
3088 return E1000_SUCCESS;
3092 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3093 * @hw: pointer to the HW structure
3094 * @active: TRUE to enable LPLU, FALSE to disable
3096 * Sets the LPLU D3 state according to the active flag. When
3097 * activating LPLU this function also disables smart speed
3098 * and vice versa. LPLU will not be activated unless the
3099 * device autonegotiation advertisement meets standards of
3100 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3101 * This is a function pointer entry point only called by
3102 * PHY setup routines.
3104 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3106 struct e1000_phy_info *phy = &hw->phy;
3108 s32 ret_val = E1000_SUCCESS;
3111 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3113 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3116 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3117 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3119 if (phy->type != e1000_phy_igp_3)
3120 return E1000_SUCCESS;
3122 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3123 * during Dx states where the power conservation is most
3124 * important. During driver activity we should enable
3125 * SmartSpeed, so performance is maintained.
3127 if (phy->smart_speed == e1000_smart_speed_on) {
3128 ret_val = phy->ops.read_reg(hw,
3129 IGP01E1000_PHY_PORT_CONFIG,
3134 data |= IGP01E1000_PSCFR_SMART_SPEED;
3135 ret_val = phy->ops.write_reg(hw,
3136 IGP01E1000_PHY_PORT_CONFIG,
3140 } else if (phy->smart_speed == e1000_smart_speed_off) {
3141 ret_val = phy->ops.read_reg(hw,
3142 IGP01E1000_PHY_PORT_CONFIG,
3147 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3148 ret_val = phy->ops.write_reg(hw,
3149 IGP01E1000_PHY_PORT_CONFIG,
3154 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3155 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3156 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3157 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3158 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3160 if (phy->type != e1000_phy_igp_3)
3161 return E1000_SUCCESS;
3163 /* Call gig speed drop workaround on LPLU before accessing
3166 if (hw->mac.type == e1000_ich8lan)
3167 e1000_gig_downshift_workaround_ich8lan(hw);
3169 /* When LPLU is enabled, we should disable SmartSpeed */
3170 ret_val = phy->ops.read_reg(hw,
3171 IGP01E1000_PHY_PORT_CONFIG,
3176 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3177 ret_val = phy->ops.write_reg(hw,
3178 IGP01E1000_PHY_PORT_CONFIG,
3186 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3187 * @hw: pointer to the HW structure
3188 * @bank: pointer to the variable that returns the active bank
3190 * Reads signature byte from the NVM using the flash access registers.
3191 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3193 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3196 struct e1000_nvm_info *nvm = &hw->nvm;
3197 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3198 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3202 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3204 switch (hw->mac.type) {
3207 eecd = E1000_READ_REG(hw, E1000_EECD);
3208 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3209 E1000_EECD_SEC1VAL_VALID_MASK) {
3210 if (eecd & E1000_EECD_SEC1VAL)
3215 return E1000_SUCCESS;
3217 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3220 /* set bank to 0 in case flash read fails */
3224 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3228 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3229 E1000_ICH_NVM_SIG_VALUE) {
3231 return E1000_SUCCESS;
3235 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3240 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3241 E1000_ICH_NVM_SIG_VALUE) {
3243 return E1000_SUCCESS;
3246 DEBUGOUT("ERROR: No valid NVM bank present\n");
3247 return -E1000_ERR_NVM;
3252 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3253 * @hw: pointer to the HW structure
3254 * @offset: The offset (in bytes) of the word(s) to read.
3255 * @words: Size of data to read in words
3256 * @data: Pointer to the word(s) to read at offset.
3258 * Reads a word(s) from the NVM using the flash access registers.
3260 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3263 struct e1000_nvm_info *nvm = &hw->nvm;
3264 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3266 s32 ret_val = E1000_SUCCESS;
3270 DEBUGFUNC("e1000_read_nvm_ich8lan");
3272 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3274 DEBUGOUT("nvm parameter(s) out of bounds\n");
3275 ret_val = -E1000_ERR_NVM;
3279 nvm->ops.acquire(hw);
3281 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3282 if (ret_val != E1000_SUCCESS) {
3283 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3287 act_offset = (bank) ? nvm->flash_bank_size : 0;
3288 act_offset += offset;
3290 ret_val = E1000_SUCCESS;
3291 for (i = 0; i < words; i++) {
3292 if (dev_spec->shadow_ram[offset+i].modified) {
3293 data[i] = dev_spec->shadow_ram[offset+i].value;
3295 ret_val = e1000_read_flash_word_ich8lan(hw,
3304 nvm->ops.release(hw);
3308 DEBUGOUT1("NVM read error: %d\n", ret_val);
3314 * e1000_flash_cycle_init_ich8lan - Initialize flash
3315 * @hw: pointer to the HW structure
3317 * This function does initial flash setup so that a new read/write/erase cycle
3320 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3322 union ich8_hws_flash_status hsfsts;
3323 s32 ret_val = -E1000_ERR_NVM;
3325 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3327 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3329 /* Check if the flash descriptor is valid */
3330 if (!hsfsts.hsf_status.fldesvalid) {
3331 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3332 return -E1000_ERR_NVM;
3335 /* Clear FCERR and DAEL in hw status by writing 1 */
3336 hsfsts.hsf_status.flcerr = 1;
3337 hsfsts.hsf_status.dael = 1;
3338 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3340 /* Either we should have a hardware SPI cycle in progress
3341 * bit to check against, in order to start a new cycle or
3342 * FDONE bit should be changed in the hardware so that it
3343 * is 1 after hardware reset, which can then be used as an
3344 * indication whether a cycle is in progress or has been
3348 if (!hsfsts.hsf_status.flcinprog) {
3349 /* There is no cycle running at present,
3350 * so we can start a cycle.
3351 * Begin by setting Flash Cycle Done.
3353 hsfsts.hsf_status.flcdone = 1;
3354 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3355 ret_val = E1000_SUCCESS;
3359 /* Otherwise poll for sometime so the current
3360 * cycle has a chance to end before giving up.
3362 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3363 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3365 if (!hsfsts.hsf_status.flcinprog) {
3366 ret_val = E1000_SUCCESS;
3371 if (ret_val == E1000_SUCCESS) {
3372 /* Successful in waiting for previous cycle to timeout,
3373 * now set the Flash Cycle Done.
3375 hsfsts.hsf_status.flcdone = 1;
3376 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3379 DEBUGOUT("Flash controller busy, cannot get access\n");
3387 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3388 * @hw: pointer to the HW structure
3389 * @timeout: maximum time to wait for completion
3391 * This function starts a flash cycle and waits for its completion.
3393 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3395 union ich8_hws_flash_ctrl hsflctl;
3396 union ich8_hws_flash_status hsfsts;
3399 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3401 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3402 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3403 hsflctl.hsf_ctrl.flcgo = 1;
3405 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3407 /* wait till FDONE bit is set to 1 */
3409 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3410 if (hsfsts.hsf_status.flcdone)
3413 } while (i++ < timeout);
3415 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3416 return E1000_SUCCESS;
3418 return -E1000_ERR_NVM;
3422 * e1000_read_flash_word_ich8lan - Read word from flash
3423 * @hw: pointer to the HW structure
3424 * @offset: offset to data location
3425 * @data: pointer to the location for storing the data
3427 * Reads the flash word at offset into data. Offset is converted
3428 * to bytes before read.
3430 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3433 DEBUGFUNC("e1000_read_flash_word_ich8lan");
3436 return -E1000_ERR_NVM;
3438 /* Must convert offset into bytes. */
3441 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3445 * e1000_read_flash_byte_ich8lan - Read byte from flash
3446 * @hw: pointer to the HW structure
3447 * @offset: The offset of the byte to read.
3448 * @data: Pointer to a byte to store the value read.
3450 * Reads a single byte from the NVM using the flash access registers.
3452 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3458 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3465 return E1000_SUCCESS;
3469 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3470 * @hw: pointer to the HW structure
3471 * @offset: The offset (in bytes) of the byte or word to read.
3472 * @size: Size of data to read, 1=byte 2=word
3473 * @data: Pointer to the word to store the value read.
3475 * Reads a byte or word from the NVM using the flash access registers.
3477 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3480 union ich8_hws_flash_status hsfsts;
3481 union ich8_hws_flash_ctrl hsflctl;
3482 u32 flash_linear_addr;
3484 s32 ret_val = -E1000_ERR_NVM;
3487 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3489 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3490 return -E1000_ERR_NVM;
3491 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3492 hw->nvm.flash_base_addr);
3497 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3498 if (ret_val != E1000_SUCCESS)
3500 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3502 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3503 hsflctl.hsf_ctrl.fldbcount = size - 1;
3504 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3505 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3506 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3508 ret_val = e1000_flash_cycle_ich8lan(hw,
3509 ICH_FLASH_READ_COMMAND_TIMEOUT);
3511 /* Check if FCERR is set to 1, if set to 1, clear it
3512 * and try the whole sequence a few more times, else
3513 * read in (shift in) the Flash Data0, the order is
3514 * least significant byte first msb to lsb
3516 if (ret_val == E1000_SUCCESS) {
3517 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3519 *data = (u8)(flash_data & 0x000000FF);
3521 *data = (u16)(flash_data & 0x0000FFFF);
3524 /* If we've gotten here, then things are probably
3525 * completely hosed, but if the error condition is
3526 * detected, it won't hurt to give it another try...
3527 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3529 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3531 if (hsfsts.hsf_status.flcerr) {
3532 /* Repeat for some time before giving up. */
3534 } else if (!hsfsts.hsf_status.flcdone) {
3535 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3539 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3546 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3547 * @hw: pointer to the HW structure
3548 * @offset: The offset (in bytes) of the word(s) to write.
3549 * @words: Size of data to write in words
3550 * @data: Pointer to the word(s) to write at offset.
3552 * Writes a byte or word to the NVM using the flash access registers.
3554 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3557 struct e1000_nvm_info *nvm = &hw->nvm;
3558 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3561 DEBUGFUNC("e1000_write_nvm_ich8lan");
3563 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3565 DEBUGOUT("nvm parameter(s) out of bounds\n");
3566 return -E1000_ERR_NVM;
3569 nvm->ops.acquire(hw);
3571 for (i = 0; i < words; i++) {
3572 dev_spec->shadow_ram[offset+i].modified = TRUE;
3573 dev_spec->shadow_ram[offset+i].value = data[i];
3576 nvm->ops.release(hw);
3578 return E1000_SUCCESS;
3582 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3583 * @hw: pointer to the HW structure
3585 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3586 * which writes the checksum to the shadow ram. The changes in the shadow
3587 * ram are then committed to the EEPROM by processing each bank at a time
3588 * checking for the modified bit and writing only the pending changes.
3589 * After a successful commit, the shadow ram is cleared and is ready for
3592 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3594 struct e1000_nvm_info *nvm = &hw->nvm;
3595 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3596 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3600 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
3602 ret_val = e1000_update_nvm_checksum_generic(hw);
3606 if (nvm->type != e1000_nvm_flash_sw)
3609 nvm->ops.acquire(hw);
3611 /* We're writing to the opposite bank so if we're on bank 1,
3612 * write to bank 0 etc. We also need to erase the segment that
3613 * is going to be written
3615 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3616 if (ret_val != E1000_SUCCESS) {
3617 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3622 new_bank_offset = nvm->flash_bank_size;
3623 old_bank_offset = 0;
3624 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3628 old_bank_offset = nvm->flash_bank_size;
3629 new_bank_offset = 0;
3630 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3634 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3635 if (dev_spec->shadow_ram[i].modified) {
3636 data = dev_spec->shadow_ram[i].value;
3638 ret_val = e1000_read_flash_word_ich8lan(hw, i +
3644 /* If the word is 0x13, then make sure the signature bits
3645 * (15:14) are 11b until the commit has completed.
3646 * This will allow us to write 10b which indicates the
3647 * signature is valid. We want to do this after the write
3648 * has completed so that we don't mark the segment valid
3649 * while the write is still in progress
3651 if (i == E1000_ICH_NVM_SIG_WORD)
3652 data |= E1000_ICH_NVM_SIG_MASK;
3654 /* Convert offset to bytes. */
3655 act_offset = (i + new_bank_offset) << 1;
3659 /* Write the bytes to the new bank. */
3660 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3667 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3674 /* Don't bother writing the segment valid bits if sector
3675 * programming failed.
3678 DEBUGOUT("Flash commit failed.\n");
3682 /* Finally validate the new segment by setting bit 15:14
3683 * to 10b in word 0x13 , this can be done without an
3684 * erase as well since these bits are 11 to start with
3685 * and we need to change bit 14 to 0b
3687 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3688 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3693 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
3698 /* And invalidate the previously valid segment by setting
3699 * its signature word (0x13) high_byte to 0b. This can be
3700 * done without an erase because flash erase sets all bits
3701 * to 1's. We can write 1's to 0's without an erase
3703 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3705 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3710 /* Great! Everything worked, we can now clear the cached entries. */
3711 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3712 dev_spec->shadow_ram[i].modified = FALSE;
3713 dev_spec->shadow_ram[i].value = 0xFFFF;
3717 nvm->ops.release(hw);
3719 /* Reload the EEPROM, or else modifications will not appear
3720 * until after the next adapter reset.
3723 nvm->ops.reload(hw);
3729 DEBUGOUT1("NVM update error: %d\n", ret_val);
3735 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3736 * @hw: pointer to the HW structure
3738 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3739 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
3740 * calculated, in which case we need to calculate the checksum and set bit 6.
3742 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3747 u16 valid_csum_mask;
3749 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
3751 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
3752 * the checksum needs to be fixed. This bit is an indication that
3753 * the NVM was prepared by OEM software and did not calculate
3754 * the checksum...a likely scenario.
3756 switch (hw->mac.type) {
3759 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3762 word = NVM_FUTURE_INIT_WORD1;
3763 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3767 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
3771 if (!(data & valid_csum_mask)) {
3772 data |= valid_csum_mask;
3773 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
3776 ret_val = hw->nvm.ops.update(hw);
3781 return e1000_validate_nvm_checksum_generic(hw);
3785 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3786 * @hw: pointer to the HW structure
3787 * @offset: The offset (in bytes) of the byte/word to read.
3788 * @size: Size of data to read, 1=byte 2=word
3789 * @data: The byte(s) to write to the NVM.
3791 * Writes one/two bytes to the NVM using the flash access registers.
3793 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3796 union ich8_hws_flash_status hsfsts;
3797 union ich8_hws_flash_ctrl hsflctl;
3798 u32 flash_linear_addr;
3803 DEBUGFUNC("e1000_write_ich8_data");
3805 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3806 return -E1000_ERR_NVM;
3808 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3809 hw->nvm.flash_base_addr);
3814 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3815 if (ret_val != E1000_SUCCESS)
3817 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3819 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3820 hsflctl.hsf_ctrl.fldbcount = size - 1;
3821 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3822 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3824 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3827 flash_data = (u32)data & 0x00FF;
3829 flash_data = (u32)data;
3831 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
3833 /* check if FCERR is set to 1 , if set to 1, clear it
3834 * and try the whole sequence a few more times else done
3837 e1000_flash_cycle_ich8lan(hw,
3838 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3839 if (ret_val == E1000_SUCCESS)
3842 /* If we're here, then things are most likely
3843 * completely hosed, but if the error condition
3844 * is detected, it won't hurt to give it another
3845 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3847 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3848 if (hsfsts.hsf_status.flcerr)
3849 /* Repeat for some time before giving up. */
3851 if (!hsfsts.hsf_status.flcdone) {
3852 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3855 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3862 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3863 * @hw: pointer to the HW structure
3864 * @offset: The index of the byte to read.
3865 * @data: The byte to write to the NVM.
3867 * Writes a single byte to the NVM using the flash access registers.
3869 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3872 u16 word = (u16)data;
3874 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
3876 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3882 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3883 * @hw: pointer to the HW structure
3884 * @offset: The offset of the byte to write.
3885 * @byte: The byte to write to the NVM.
3887 * Writes a single byte to the NVM using the flash access registers.
3888 * Goes through a retry algorithm before giving up.
3890 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3891 u32 offset, u8 byte)
3894 u16 program_retries;
3896 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
3898 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3902 for (program_retries = 0; program_retries < 100; program_retries++) {
3903 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
3905 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3906 if (ret_val == E1000_SUCCESS)
3909 if (program_retries == 100)
3910 return -E1000_ERR_NVM;
3912 return E1000_SUCCESS;
3916 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3917 * @hw: pointer to the HW structure
3918 * @bank: 0 for first bank, 1 for second bank, etc.
3920 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3921 * bank N is 4096 * N + flash_reg_addr.
3923 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3925 struct e1000_nvm_info *nvm = &hw->nvm;
3926 union ich8_hws_flash_status hsfsts;
3927 union ich8_hws_flash_ctrl hsflctl;
3928 u32 flash_linear_addr;
3929 /* bank size is in 16bit words - adjust to bytes */
3930 u32 flash_bank_size = nvm->flash_bank_size * 2;
3933 s32 j, iteration, sector_size;
3935 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
3937 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3939 /* Determine HW Sector size: Read BERASE bits of hw flash status
3941 * 00: The Hw sector is 256 bytes, hence we need to erase 16
3942 * consecutive sectors. The start index for the nth Hw sector
3943 * can be calculated as = bank * 4096 + n * 256
3944 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3945 * The start index for the nth Hw sector can be calculated
3947 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3948 * (ich9 only, otherwise error condition)
3949 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3951 switch (hsfsts.hsf_status.berasesz) {
3953 /* Hw sector size 256 */
3954 sector_size = ICH_FLASH_SEG_SIZE_256;
3955 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3958 sector_size = ICH_FLASH_SEG_SIZE_4K;
3962 sector_size = ICH_FLASH_SEG_SIZE_8K;
3966 sector_size = ICH_FLASH_SEG_SIZE_64K;
3970 return -E1000_ERR_NVM;
3973 /* Start with the base address, then add the sector offset. */
3974 flash_linear_addr = hw->nvm.flash_base_addr;
3975 flash_linear_addr += (bank) ? flash_bank_size : 0;
3977 for (j = 0; j < iteration; j++) {
3979 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3982 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3986 /* Write a value 11 (block Erase) in Flash
3987 * Cycle field in hw flash control
3990 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3992 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3993 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
3996 /* Write the last 24 bits of an index within the
3997 * block into Flash Linear address field in Flash
4000 flash_linear_addr += (j * sector_size);
4001 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4004 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4005 if (ret_val == E1000_SUCCESS)
4008 /* Check if FCERR is set to 1. If 1,
4009 * clear it and try the whole sequence
4010 * a few more times else Done
4012 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4014 if (hsfsts.hsf_status.flcerr)
4015 /* repeat for some time before giving up */
4017 else if (!hsfsts.hsf_status.flcdone)
4019 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4022 return E1000_SUCCESS;
4026 * e1000_valid_led_default_ich8lan - Set the default LED settings
4027 * @hw: pointer to the HW structure
4028 * @data: Pointer to the LED settings
4030 * Reads the LED default settings from the NVM to data. If the NVM LED
4031 * settings is all 0's or F's, set the LED default to a valid LED default
4034 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4038 DEBUGFUNC("e1000_valid_led_default_ich8lan");
4040 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4042 DEBUGOUT("NVM Read Error\n");
4046 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4047 *data = ID_LED_DEFAULT_ICH8LAN;
4049 return E1000_SUCCESS;
4053 * e1000_id_led_init_pchlan - store LED configurations
4054 * @hw: pointer to the HW structure
4056 * PCH does not control LEDs via the LEDCTL register, rather it uses
4057 * the PHY LED configuration register.
4059 * PCH also does not have an "always on" or "always off" mode which
4060 * complicates the ID feature. Instead of using the "on" mode to indicate
4061 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4062 * use "link_up" mode. The LEDs will still ID on request if there is no
4063 * link based on logic in e1000_led_[on|off]_pchlan().
4065 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4067 struct e1000_mac_info *mac = &hw->mac;
4069 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4070 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4071 u16 data, i, temp, shift;
4073 DEBUGFUNC("e1000_id_led_init_pchlan");
4075 /* Get default ID LED modes */
4076 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4080 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4081 mac->ledctl_mode1 = mac->ledctl_default;
4082 mac->ledctl_mode2 = mac->ledctl_default;
4084 for (i = 0; i < 4; i++) {
4085 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4088 case ID_LED_ON1_DEF2:
4089 case ID_LED_ON1_ON2:
4090 case ID_LED_ON1_OFF2:
4091 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4092 mac->ledctl_mode1 |= (ledctl_on << shift);
4094 case ID_LED_OFF1_DEF2:
4095 case ID_LED_OFF1_ON2:
4096 case ID_LED_OFF1_OFF2:
4097 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4098 mac->ledctl_mode1 |= (ledctl_off << shift);
4105 case ID_LED_DEF1_ON2:
4106 case ID_LED_ON1_ON2:
4107 case ID_LED_OFF1_ON2:
4108 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4109 mac->ledctl_mode2 |= (ledctl_on << shift);
4111 case ID_LED_DEF1_OFF2:
4112 case ID_LED_ON1_OFF2:
4113 case ID_LED_OFF1_OFF2:
4114 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4115 mac->ledctl_mode2 |= (ledctl_off << shift);
4123 return E1000_SUCCESS;
4127 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4128 * @hw: pointer to the HW structure
4130 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4131 * register, so the the bus width is hard coded.
4133 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4135 struct e1000_bus_info *bus = &hw->bus;
4138 DEBUGFUNC("e1000_get_bus_info_ich8lan");
4140 ret_val = e1000_get_bus_info_pcie_generic(hw);
4142 /* ICH devices are "PCI Express"-ish. They have
4143 * a configuration space, but do not contain
4144 * PCI Express Capability registers, so bus width
4145 * must be hardcoded.
4147 if (bus->width == e1000_bus_width_unknown)
4148 bus->width = e1000_bus_width_pcie_x1;
4154 * e1000_reset_hw_ich8lan - Reset the hardware
4155 * @hw: pointer to the HW structure
4157 * Does a full reset of the hardware which includes a reset of the PHY and
4160 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4162 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4167 DEBUGFUNC("e1000_reset_hw_ich8lan");
4169 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4170 * on the last TLP read/write transaction when MAC is reset.
4172 ret_val = e1000_disable_pcie_master_generic(hw);
4174 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4176 DEBUGOUT("Masking off all interrupts\n");
4177 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4179 /* Disable the Transmit and Receive units. Then delay to allow
4180 * any pending transactions to complete before we hit the MAC
4181 * with the global reset.
4183 E1000_WRITE_REG(hw, E1000_RCTL, 0);
4184 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4185 E1000_WRITE_FLUSH(hw);
4189 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4190 if (hw->mac.type == e1000_ich8lan) {
4191 /* Set Tx and Rx buffer allocation to 8k apiece. */
4192 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4193 /* Set Packet Buffer Size to 16k. */
4194 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4197 if (hw->mac.type == e1000_pchlan) {
4198 /* Save the NVM K1 bit setting*/
4199 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4203 if (kum_cfg & E1000_NVM_K1_ENABLE)
4204 dev_spec->nvm_k1_enabled = TRUE;
4206 dev_spec->nvm_k1_enabled = FALSE;
4209 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4211 if (!hw->phy.ops.check_reset_block(hw)) {
4212 /* Full-chip reset requires MAC and PHY reset at the same
4213 * time to make sure the interface between MAC and the
4214 * external PHY is reset.
4216 ctrl |= E1000_CTRL_PHY_RST;
4218 /* Gate automatic PHY configuration by hardware on
4221 if ((hw->mac.type == e1000_pch2lan) &&
4222 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4223 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
4225 ret_val = e1000_acquire_swflag_ich8lan(hw);
4226 DEBUGOUT("Issuing a global reset to ich8lan\n");
4227 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4228 /* cannot issue a flush here because it hangs the hardware */
4231 /* Set Phy Config Counter to 50msec */
4232 if (hw->mac.type == e1000_pch2lan) {
4233 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4234 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4235 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4236 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4239 if (ctrl & E1000_CTRL_PHY_RST) {
4240 ret_val = hw->phy.ops.get_cfg_done(hw);
4244 ret_val = e1000_post_phy_reset_ich8lan(hw);
4249 /* For PCH, this write will make sure that any noise
4250 * will be detected as a CRC error and be dropped rather than show up
4251 * as a bad packet to the DMA engine.
4253 if (hw->mac.type == e1000_pchlan)
4254 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
4256 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4257 E1000_READ_REG(hw, E1000_ICR);
4259 reg = E1000_READ_REG(hw, E1000_KABGTXD);
4260 reg |= E1000_KABGTXD_BGSQLBIAS;
4261 E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
4263 return E1000_SUCCESS;
4267 * e1000_init_hw_ich8lan - Initialize the hardware
4268 * @hw: pointer to the HW structure
4270 * Prepares the hardware for transmit and receive by doing the following:
4271 * - initialize hardware bits
4272 * - initialize LED identification
4273 * - setup receive address registers
4274 * - setup flow control
4275 * - setup transmit descriptors
4276 * - clear statistics
4278 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4280 struct e1000_mac_info *mac = &hw->mac;
4281 u32 ctrl_ext, txdctl, snoop;
4285 DEBUGFUNC("e1000_init_hw_ich8lan");
4287 e1000_initialize_hw_bits_ich8lan(hw);
4289 /* Initialize identification LED */
4290 ret_val = mac->ops.id_led_init(hw);
4291 /* An error is not fatal and we should not stop init due to this */
4293 DEBUGOUT("Error initializing identification LED\n");
4295 /* Setup the receive address. */
4296 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
4298 /* Zero out the Multicast HASH table */
4299 DEBUGOUT("Zeroing the MTA\n");
4300 for (i = 0; i < mac->mta_reg_count; i++)
4301 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4303 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4304 * the ME. Disable wakeup by clearing the host wakeup bit.
4305 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4307 if (hw->phy.type == e1000_phy_82578) {
4308 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
4309 i &= ~BM_WUC_HOST_WU_BIT;
4310 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
4311 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4316 /* Setup link and flow control */
4317 ret_val = mac->ops.setup_link(hw);
4319 /* Set the transmit descriptor write-back policy for both queues */
4320 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
4321 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4322 E1000_TXDCTL_FULL_TX_DESC_WB);
4323 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4324 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4325 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
4326 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
4327 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4328 E1000_TXDCTL_FULL_TX_DESC_WB);
4329 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4330 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4331 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
4333 /* ICH8 has opposite polarity of no_snoop bits.
4334 * By default, we should use snoop behavior.
4336 if (mac->type == e1000_ich8lan)
4337 snoop = PCIE_ICH8_SNOOP_ALL;
4339 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
4340 e1000_set_pcie_no_snoop_generic(hw, snoop);
4342 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
4343 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4344 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
4346 /* Clear all of the statistics registers (clear on read). It is
4347 * important that we do this after we have tried to establish link
4348 * because the symbol error count will increment wildly if there
4351 e1000_clear_hw_cntrs_ich8lan(hw);
4357 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4358 * @hw: pointer to the HW structure
4360 * Sets/Clears required hardware bits necessary for correctly setting up the
4361 * hardware for transmit and receive.
4363 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4367 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
4369 /* Extended Device Control */
4370 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
4372 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4373 if (hw->mac.type >= e1000_pchlan)
4374 reg |= E1000_CTRL_EXT_PHYPDEN;
4375 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
4377 /* Transmit Descriptor Control 0 */
4378 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
4380 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
4382 /* Transmit Descriptor Control 1 */
4383 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
4385 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
4387 /* Transmit Arbitration Control 0 */
4388 reg = E1000_READ_REG(hw, E1000_TARC(0));
4389 if (hw->mac.type == e1000_ich8lan)
4390 reg |= (1 << 28) | (1 << 29);
4391 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
4392 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
4394 /* Transmit Arbitration Control 1 */
4395 reg = E1000_READ_REG(hw, E1000_TARC(1));
4396 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
4400 reg |= (1 << 24) | (1 << 26) | (1 << 30);
4401 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
4404 if (hw->mac.type == e1000_ich8lan) {
4405 reg = E1000_READ_REG(hw, E1000_STATUS);
4407 E1000_WRITE_REG(hw, E1000_STATUS, reg);
4410 /* work-around descriptor data corruption issue during nfs v2 udp
4411 * traffic, just disable the nfs filtering capability
4413 reg = E1000_READ_REG(hw, E1000_RFCTL);
4414 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4416 /* Disable IPv6 extension header parsing because some malformed
4417 * IPv6 headers can hang the Rx.
4419 if (hw->mac.type == e1000_ich8lan)
4420 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4421 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
4423 /* Enable ECC on Lynxpoint */
4424 if (hw->mac.type == e1000_pch_lpt) {
4425 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
4426 reg |= E1000_PBECCSTS_ECC_ENABLE;
4427 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
4429 reg = E1000_READ_REG(hw, E1000_CTRL);
4430 reg |= E1000_CTRL_MEHE;
4431 E1000_WRITE_REG(hw, E1000_CTRL, reg);
4438 * e1000_setup_link_ich8lan - Setup flow control and link settings
4439 * @hw: pointer to the HW structure
4441 * Determines which flow control settings to use, then configures flow
4442 * control. Calls the appropriate media-specific link configuration
4443 * function. Assuming the adapter has a valid link partner, a valid link
4444 * should be established. Assumes the hardware has previously been reset
4445 * and the transmitter and receiver are not enabled.
4447 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4451 DEBUGFUNC("e1000_setup_link_ich8lan");
4453 if (hw->phy.ops.check_reset_block(hw))
4454 return E1000_SUCCESS;
4456 /* ICH parts do not have a word in the NVM to determine
4457 * the default flow control setting, so we explicitly
4460 if (hw->fc.requested_mode == e1000_fc_default)
4461 hw->fc.requested_mode = e1000_fc_full;
4463 /* Save off the requested flow control mode for use later. Depending
4464 * on the link partner's capabilities, we may or may not use this mode.
4466 hw->fc.current_mode = hw->fc.requested_mode;
4468 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
4469 hw->fc.current_mode);
4471 /* Continue to configure the copper link. */
4472 ret_val = hw->mac.ops.setup_physical_interface(hw);
4476 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
4477 if ((hw->phy.type == e1000_phy_82578) ||
4478 (hw->phy.type == e1000_phy_82579) ||
4479 (hw->phy.type == e1000_phy_i217) ||
4480 (hw->phy.type == e1000_phy_82577)) {
4481 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
4483 ret_val = hw->phy.ops.write_reg(hw,
4484 PHY_REG(BM_PORT_CTRL_PAGE, 27),
4490 return e1000_set_fc_watermarks_generic(hw);
4494 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4495 * @hw: pointer to the HW structure
4497 * Configures the kumeran interface to the PHY to wait the appropriate time
4498 * when polling the PHY, then call the generic setup_copper_link to finish
4499 * configuring the copper link.
4501 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4507 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
4509 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4510 ctrl |= E1000_CTRL_SLU;
4511 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4512 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4514 /* Set the mac to wait the maximum time between each iteration
4515 * and increase the max iterations when polling the phy;
4516 * this fixes erroneous timeouts at 10Mbps.
4518 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
4522 ret_val = e1000_read_kmrn_reg_generic(hw,
4523 E1000_KMRNCTRLSTA_INBAND_PARAM,
4528 ret_val = e1000_write_kmrn_reg_generic(hw,
4529 E1000_KMRNCTRLSTA_INBAND_PARAM,
4534 switch (hw->phy.type) {
4535 case e1000_phy_igp_3:
4536 ret_val = e1000_copper_link_setup_igp(hw);
4541 case e1000_phy_82578:
4542 ret_val = e1000_copper_link_setup_m88(hw);
4546 case e1000_phy_82577:
4547 case e1000_phy_82579:
4548 ret_val = e1000_copper_link_setup_82577(hw);
4553 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
4558 reg_data &= ~IFE_PMC_AUTO_MDIX;
4560 switch (hw->phy.mdix) {
4562 reg_data &= ~IFE_PMC_FORCE_MDIX;
4565 reg_data |= IFE_PMC_FORCE_MDIX;
4569 reg_data |= IFE_PMC_AUTO_MDIX;
4572 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
4581 return e1000_setup_copper_link_generic(hw);
4585 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
4586 * @hw: pointer to the HW structure
4588 * Calls the PHY specific link setup function and then calls the
4589 * generic setup_copper_link to finish configuring the link for
4590 * Lynxpoint PCH devices
4592 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4597 DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
4599 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4600 ctrl |= E1000_CTRL_SLU;
4601 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4602 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4604 ret_val = e1000_copper_link_setup_82577(hw);
4608 return e1000_setup_copper_link_generic(hw);
4612 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4613 * @hw: pointer to the HW structure
4614 * @speed: pointer to store current link speed
4615 * @duplex: pointer to store the current link duplex
4617 * Calls the generic get_speed_and_duplex to retrieve the current link
4618 * information and then calls the Kumeran lock loss workaround for links at
4621 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4626 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
4628 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
4632 if ((hw->mac.type == e1000_ich8lan) &&
4633 (hw->phy.type == e1000_phy_igp_3) &&
4634 (*speed == SPEED_1000)) {
4635 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4642 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4643 * @hw: pointer to the HW structure
4645 * Work-around for 82566 Kumeran PCS lock loss:
4646 * On link status change (i.e. PCI reset, speed change) and link is up and
4648 * 0) if workaround is optionally disabled do nothing
4649 * 1) wait 1ms for Kumeran link to come up
4650 * 2) check Kumeran Diagnostic register PCS lock loss bit
4651 * 3) if not set the link is locked (all is good), otherwise...
4653 * 5) repeat up to 10 times
4654 * Note: this is only called for IGP3 copper when speed is 1gb.
4656 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4658 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4664 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
4666 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4667 return E1000_SUCCESS;
4669 /* Make sure link is up before proceeding. If not just return.
4670 * Attempting this while link is negotiating fouled up link
4673 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
4675 return E1000_SUCCESS;
4677 for (i = 0; i < 10; i++) {
4678 /* read once to clear */
4679 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4682 /* and again to get new status */
4683 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4687 /* check for PCS lock */
4688 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4689 return E1000_SUCCESS;
4691 /* Issue PHY reset */
4692 hw->phy.ops.reset(hw);
4695 /* Disable GigE link negotiation */
4696 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4697 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4698 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4699 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4701 /* Call gig speed drop workaround on Gig disable before accessing
4704 e1000_gig_downshift_workaround_ich8lan(hw);
4706 /* unable to acquire PCS lock */
4707 return -E1000_ERR_PHY;
4711 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4712 * @hw: pointer to the HW structure
4713 * @state: boolean value used to set the current Kumeran workaround state
4715 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
4716 * /disabled - FALSE).
4718 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4721 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4723 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
4725 if (hw->mac.type != e1000_ich8lan) {
4726 DEBUGOUT("Workaround applies to ICH8 only.\n");
4730 dev_spec->kmrn_lock_loss_workaround_enabled = state;
4736 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4737 * @hw: pointer to the HW structure
4739 * Workaround for 82566 power-down on D3 entry:
4740 * 1) disable gigabit link
4741 * 2) write VR power-down enable
4743 * Continue if successful, else issue LCD reset and repeat
4745 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4751 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
4753 if (hw->phy.type != e1000_phy_igp_3)
4756 /* Try the workaround twice (if needed) */
4759 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
4760 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4761 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4762 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
4764 /* Call gig speed drop workaround on Gig disable before
4765 * accessing any PHY registers
4767 if (hw->mac.type == e1000_ich8lan)
4768 e1000_gig_downshift_workaround_ich8lan(hw);
4770 /* Write VR power-down enable */
4771 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4772 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4773 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
4774 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4776 /* Read it back and test */
4777 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4778 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4779 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4782 /* Issue PHY reset and repeat at most one more time */
4783 reg = E1000_READ_REG(hw, E1000_CTRL);
4784 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
4790 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4791 * @hw: pointer to the HW structure
4793 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4794 * LPLU, Gig disable, MDIC PHY reset):
4795 * 1) Set Kumeran Near-end loopback
4796 * 2) Clear Kumeran Near-end loopback
4797 * Should only be called for ICH8[m] devices with any 1G Phy.
4799 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4804 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
4806 if ((hw->mac.type != e1000_ich8lan) ||
4807 (hw->phy.type == e1000_phy_ife))
4810 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4814 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4815 ret_val = e1000_write_kmrn_reg_generic(hw,
4816 E1000_KMRNCTRLSTA_DIAG_OFFSET,
4820 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4821 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4826 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4827 * @hw: pointer to the HW structure
4829 * During S0 to Sx transition, it is possible the link remains at gig
4830 * instead of negotiating to a lower speed. Before going to Sx, set
4831 * 'Gig Disable' to force link speed negotiation to a lower speed based on
4832 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
4833 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4834 * needs to be written.
4835 * Parts that support (and are linked to a partner which support) EEE in
4836 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4837 * than 10Mbps w/o EEE.
4839 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4841 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4845 DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
4847 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4848 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4850 if (hw->phy.type == e1000_phy_i217) {
4851 u16 phy_reg, device_id = hw->device_id;
4853 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4854 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4855 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4856 (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4857 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
4859 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
4860 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4863 ret_val = hw->phy.ops.acquire(hw);
4867 if (!dev_spec->eee_disable) {
4871 e1000_read_emi_reg_locked(hw,
4872 I217_EEE_ADVERTISEMENT,
4877 /* Disable LPLU if both link partners support 100BaseT
4878 * EEE and 100Full is advertised on both ends of the
4879 * link, and enable Auto Enable LPI since there will
4880 * be no driver to enable LPI while in Sx.
4882 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4883 (dev_spec->eee_lp_ability &
4884 I82579_EEE_100_SUPPORTED) &&
4885 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
4886 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4887 E1000_PHY_CTRL_NOND0A_LPLU);
4889 /* Set Auto Enable LPI after link up */
4890 hw->phy.ops.read_reg_locked(hw,
4893 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4894 hw->phy.ops.write_reg_locked(hw,
4900 /* For i217 Intel Rapid Start Technology support,
4901 * when the system is going into Sx and no manageability engine
4902 * is present, the driver must configure proxy to reset only on
4903 * power good. LPI (Low Power Idle) state must also reset only
4904 * on power good, as well as the MTA (Multicast table array).
4905 * The SMBus release must also be disabled on LCD reset.
4907 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4908 E1000_ICH_FWSM_FW_VALID)) {
4909 /* Enable proxy to reset only on power good. */
4910 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
4912 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4913 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
4916 /* Set bit enable LPI (EEE) to reset only on
4919 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
4920 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4921 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
4923 /* Disable the SMB release on LCD reset. */
4924 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
4925 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4926 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4929 /* Enable MTA to reset for Intel Rapid Start Technology
4932 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
4933 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4934 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4937 hw->phy.ops.release(hw);
4940 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4942 if (hw->mac.type == e1000_ich8lan)
4943 e1000_gig_downshift_workaround_ich8lan(hw);
4945 if (hw->mac.type >= e1000_pchlan) {
4946 e1000_oem_bits_config_ich8lan(hw, FALSE);
4948 /* Reset PHY to activate OEM bits on 82577/8 */
4949 if (hw->mac.type == e1000_pchlan)
4950 e1000_phy_hw_reset_generic(hw);
4952 ret_val = hw->phy.ops.acquire(hw);
4955 e1000_write_smbus_addr(hw);
4956 hw->phy.ops.release(hw);
4963 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4964 * @hw: pointer to the HW structure
4966 * During Sx to S0 transitions on non-managed devices or managed devices
4967 * on which PHY resets are not blocked, if the PHY registers cannot be
4968 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
4970 * On i217, setup Intel Rapid Start Technology.
4972 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4976 DEBUGFUNC("e1000_resume_workarounds_pchlan");
4978 if (hw->mac.type < e1000_pch2lan)
4981 ret_val = e1000_init_phy_workarounds_pchlan(hw);
4983 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
4987 /* For i217 Intel Rapid Start Technology support when the system
4988 * is transitioning from Sx and no manageability engine is present
4989 * configure SMBus to restore on reset, disable proxy, and enable
4990 * the reset on MTA (Multicast table array).
4992 if (hw->phy.type == e1000_phy_i217) {
4995 ret_val = hw->phy.ops.acquire(hw);
4997 DEBUGOUT("Failed to setup iRST\n");
5001 /* Clear Auto Enable LPI after link up */
5002 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5003 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5004 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5006 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5007 E1000_ICH_FWSM_FW_VALID)) {
5008 /* Restore clear on SMB if no manageability engine
5011 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5015 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5016 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5019 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5021 /* Enable reset on MTA */
5022 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5026 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5027 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5030 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5031 hw->phy.ops.release(hw);
5036 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5037 * @hw: pointer to the HW structure
5039 * Return the LED back to the default configuration.
5041 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5043 DEBUGFUNC("e1000_cleanup_led_ich8lan");
5045 if (hw->phy.type == e1000_phy_ife)
5046 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5049 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5050 return E1000_SUCCESS;
5054 * e1000_led_on_ich8lan - Turn LEDs on
5055 * @hw: pointer to the HW structure
5059 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5061 DEBUGFUNC("e1000_led_on_ich8lan");
5063 if (hw->phy.type == e1000_phy_ife)
5064 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5065 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5067 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5068 return E1000_SUCCESS;
5072 * e1000_led_off_ich8lan - Turn LEDs off
5073 * @hw: pointer to the HW structure
5075 * Turn off the LEDs.
5077 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5079 DEBUGFUNC("e1000_led_off_ich8lan");
5081 if (hw->phy.type == e1000_phy_ife)
5082 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5083 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5085 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5086 return E1000_SUCCESS;
5090 * e1000_setup_led_pchlan - Configures SW controllable LED
5091 * @hw: pointer to the HW structure
5093 * This prepares the SW controllable LED for use.
5095 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5097 DEBUGFUNC("e1000_setup_led_pchlan");
5099 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5100 (u16)hw->mac.ledctl_mode1);
5104 * e1000_cleanup_led_pchlan - Restore the default LED operation
5105 * @hw: pointer to the HW structure
5107 * Return the LED back to the default configuration.
5109 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5111 DEBUGFUNC("e1000_cleanup_led_pchlan");
5113 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5114 (u16)hw->mac.ledctl_default);
5118 * e1000_led_on_pchlan - Turn LEDs on
5119 * @hw: pointer to the HW structure
5123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5125 u16 data = (u16)hw->mac.ledctl_mode2;
5128 DEBUGFUNC("e1000_led_on_pchlan");
5130 /* If no link, then turn LED on by setting the invert bit
5131 * for each LED that's mode is "link_up" in ledctl_mode2.
5133 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5134 for (i = 0; i < 3; i++) {
5135 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5136 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5137 E1000_LEDCTL_MODE_LINK_UP)
5139 if (led & E1000_PHY_LED0_IVRT)
5140 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5142 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5146 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5150 * e1000_led_off_pchlan - Turn LEDs off
5151 * @hw: pointer to the HW structure
5153 * Turn off the LEDs.
5155 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5157 u16 data = (u16)hw->mac.ledctl_mode1;
5160 DEBUGFUNC("e1000_led_off_pchlan");
5162 /* If no link, then turn LED off by clearing the invert bit
5163 * for each LED that's mode is "link_up" in ledctl_mode1.
5165 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5166 for (i = 0; i < 3; i++) {
5167 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5168 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5169 E1000_LEDCTL_MODE_LINK_UP)
5171 if (led & E1000_PHY_LED0_IVRT)
5172 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5174 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5178 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5182 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5183 * @hw: pointer to the HW structure
5185 * Read appropriate register for the config done bit for completion status
5186 * and configure the PHY through s/w for EEPROM-less parts.
5188 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5189 * config done bit, so only an error is logged and continues. If we were
5190 * to return with error, EEPROM-less silicon would not be able to be reset
5193 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5195 s32 ret_val = E1000_SUCCESS;
5199 DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5201 e1000_get_cfg_done_generic(hw);
5203 /* Wait for indication from h/w that it has completed basic config */
5204 if (hw->mac.type >= e1000_ich10lan) {
5205 e1000_lan_init_done_ich8lan(hw);
5207 ret_val = e1000_get_auto_rd_done_generic(hw);
5209 /* When auto config read does not complete, do not
5210 * return with an error. This can happen in situations
5211 * where there is no eeprom and prevents getting link.
5213 DEBUGOUT("Auto Read Done did not complete\n");
5214 ret_val = E1000_SUCCESS;
5218 /* Clear PHY Reset Asserted bit */
5219 status = E1000_READ_REG(hw, E1000_STATUS);
5220 if (status & E1000_STATUS_PHYRA)
5221 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5223 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5225 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5226 if (hw->mac.type <= e1000_ich9lan) {
5227 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5228 (hw->phy.type == e1000_phy_igp_3)) {
5229 e1000_phy_init_script_igp3(hw);
5232 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5233 /* Maybe we should do a basic PHY config */
5234 DEBUGOUT("EEPROM not present\n");
5235 ret_val = -E1000_ERR_CONFIG;
5243 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5244 * @hw: pointer to the HW structure
5246 * In the case of a PHY power down to save power, or to turn off link during a
5247 * driver unload, or wake on lan is not enabled, remove the link.
5249 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5251 /* If the management interface is not enabled, then power down */
5252 if (!(hw->mac.ops.check_mng_mode(hw) ||
5253 hw->phy.ops.check_reset_block(hw)))
5254 e1000_power_down_phy_copper(hw);
5260 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5261 * @hw: pointer to the HW structure
5263 * Clears hardware counters specific to the silicon family and calls
5264 * clear_hw_cntrs_generic to clear all general purpose counters.
5266 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5271 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
5273 e1000_clear_hw_cntrs_base_generic(hw);
5275 E1000_READ_REG(hw, E1000_ALGNERRC);
5276 E1000_READ_REG(hw, E1000_RXERRC);
5277 E1000_READ_REG(hw, E1000_TNCRS);
5278 E1000_READ_REG(hw, E1000_CEXTERR);
5279 E1000_READ_REG(hw, E1000_TSCTC);
5280 E1000_READ_REG(hw, E1000_TSCTFC);
5282 E1000_READ_REG(hw, E1000_MGTPRC);
5283 E1000_READ_REG(hw, E1000_MGTPDC);
5284 E1000_READ_REG(hw, E1000_MGTPTC);
5286 E1000_READ_REG(hw, E1000_IAC);
5287 E1000_READ_REG(hw, E1000_ICRXOC);
5289 /* Clear PHY statistics registers */
5290 if ((hw->phy.type == e1000_phy_82578) ||
5291 (hw->phy.type == e1000_phy_82579) ||
5292 (hw->phy.type == e1000_phy_i217) ||
5293 (hw->phy.type == e1000_phy_82577)) {
5294 ret_val = hw->phy.ops.acquire(hw);
5297 ret_val = hw->phy.ops.set_page(hw,
5298 HV_STATS_PAGE << IGP_PAGE_SHIFT);
5301 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5302 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5303 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5304 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5305 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5306 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5307 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5308 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5309 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5310 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5311 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5312 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5313 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5314 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5316 hw->phy.ops.release(hw);