2 * Interface for the 93C66/56/46/26/06 serial eeprom parts.
4 * Copyright (c) 1995, 1996 Daniel M. Eischen
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. The name of the author may not be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * Alternatively, this software may be distributed under the terms of the
17 * GNU General Public License ("GPL").
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31 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_93cx6.c#17 $
33 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx_93cx6.c,v 1.8.2.6 2002/08/31 07:25:53 gibbs Exp $
34 * $DragonFly: src/sys/dev/disk/aic7xxx/aic7xxx_93cx6.c,v 1.3 2003/08/07 21:16:51 dillon Exp $
38 * The instruction set of the 93C66/56/46/26/06 chips are as follows:
41 * Function Bit Code Address** Data Description
42 * -------------------------------------------------------------------
43 * READ 1 10 A5 - A0 Reads data stored in memory,
44 * starting at specified address
45 * EWEN 1 00 11XXXX Write enable must precede
46 * all programming modes
47 * ERASE 1 11 A5 - A0 Erase register A5A4A3A2A1A0
48 * WRITE 1 01 A5 - A0 D15 - D0 Writes register
49 * ERAL 1 00 10XXXX Erase all registers
50 * WRAL 1 00 01XXXX D15 - D0 Writes to all registers
51 * EWDS 1 00 00XXXX Disables all programming
53 * *Note: A value of X for address is a don't care condition.
54 * **Note: There are 8 address bits for the 93C56/66 chips unlike
55 * the 93C46/26/06 chips which have 6 address bits.
57 * The 93C46 has a four wire interface: clock, chip select, data in, and
58 * data out. In order to perform one of the above functions, you need
59 * to enable the chip select for a clock period (typically a minimum of
60 * 1 usec, with the clock high and low a minimum of 750 and 250 nsec
61 * respectively). While the chip select remains high, you can clock in
62 * the instructions (above) starting with the start bit, followed by the
63 * OP code, Address, and Data (if needed). For the READ instruction, the
64 * requested 16-bit register contents is read from the data out line but
65 * is preceded by an initial zero (leading 0, followed by 16-bits, MSB
66 * first). The clock cycling from low to high initiates the next data
67 * bit to be sent from the chip.
72 #include "aic7xxx_osm.h"
73 #include "aic7xxx_inline.h"
74 #include "aic7xxx_93cx6.h"
76 #include "aic7xxx_osm.h"
77 #include "aic7xxx_inline.h"
78 #include "aic7xxx_93cx6.h"
82 * Right now, we only have to read the SEEPROM. But we make it easier to
83 * add other 93Cx6 functions.
85 static struct seeprom_cmd {
88 } seeprom_read = {3, {1, 1, 0}};
90 static struct seeprom_cmd seeprom_ewen = {9, {1, 0, 0, 1, 1, 0, 0, 0, 0}};
91 static struct seeprom_cmd seeprom_ewds = {9, {1, 0, 0, 0, 0, 0, 0, 0, 0}};
92 static struct seeprom_cmd seeprom_write = {3, {1, 0, 1}};
95 * Wait for the SEERDY to go high; about 800 ns.
97 #define CLOCK_PULSE(sd, rdy) \
98 while ((SEEPROM_STATUS_INB(sd) & rdy) == 0) { \
101 (void)SEEPROM_INB(sd); /* Clear clock */
104 * Send a START condition and the given command
107 send_seeprom_cmd(struct seeprom_descriptor *sd, struct seeprom_cmd *cmd)
112 /* Send chip select for one clock cycle. */
113 temp = sd->sd_MS ^ sd->sd_CS;
114 SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
115 CLOCK_PULSE(sd, sd->sd_RDY);
117 for (i = 0; i < cmd->len; i++) {
118 if (cmd->bits[i] != 0)
120 SEEPROM_OUTB(sd, temp);
121 CLOCK_PULSE(sd, sd->sd_RDY);
122 SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
123 CLOCK_PULSE(sd, sd->sd_RDY);
124 if (cmd->bits[i] != 0)
130 * Clear CS put the chip in the reset state, where it can wait for new commands.
133 reset_seeprom(struct seeprom_descriptor *sd)
138 SEEPROM_OUTB(sd, temp);
139 CLOCK_PULSE(sd, sd->sd_RDY);
140 SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
141 CLOCK_PULSE(sd, sd->sd_RDY);
142 SEEPROM_OUTB(sd, temp);
143 CLOCK_PULSE(sd, sd->sd_RDY);
147 * Read the serial EEPROM and returns 1 if successful and 0 if
151 ahc_read_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
152 u_int start_addr, u_int count)
160 * Read the requested registers of the seeprom. The loop
161 * will range from 0 to count-1.
163 for (k = start_addr; k < count + start_addr; k++) {
165 * Now we're ready to send the read command followed by the
166 * address of the 16-bit register we want to read.
168 send_seeprom_cmd(sd, &seeprom_read);
170 /* Send the 6 or 8 bit address (MSB first, LSB last). */
171 temp = sd->sd_MS ^ sd->sd_CS;
172 for (i = (sd->sd_chip - 1); i >= 0; i--) {
173 if ((k & (1 << i)) != 0)
175 SEEPROM_OUTB(sd, temp);
176 CLOCK_PULSE(sd, sd->sd_RDY);
177 SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
178 CLOCK_PULSE(sd, sd->sd_RDY);
179 if ((k & (1 << i)) != 0)
184 * Now read the 16 bit register. An initial 0 precedes the
185 * register contents which begins with bit 15 (MSB) and ends
186 * with bit 0 (LSB). The initial 0 will be shifted off the
187 * top of our word as we let the loop run from 0 to 16.
190 for (i = 16; i >= 0; i--) {
191 SEEPROM_OUTB(sd, temp);
192 CLOCK_PULSE(sd, sd->sd_RDY);
194 if (SEEPROM_DATA_INB(sd) & sd->sd_DI)
196 SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
197 CLOCK_PULSE(sd, sd->sd_RDY);
200 buf[k - start_addr] = v;
202 /* Reset the chip select for the next command cycle. */
205 #ifdef AHC_DUMP_EEPROM
206 printf("\nSerial EEPROM:\n\t");
207 for (k = 0; k < count; k = k + 1) {
208 if (((k % 8) == 0) && (k != 0)) {
211 printf (" 0x%x", buf[k]);
219 * Write the serial EEPROM and return 1 if successful and 0 if
223 ahc_write_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
224 u_int start_addr, u_int count)
230 /* Place the chip into write-enable mode */
231 send_seeprom_cmd(sd, &seeprom_ewen);
234 /* Write all requested data out to the seeprom. */
235 temp = sd->sd_MS ^ sd->sd_CS;
236 for (k = start_addr; k < count + start_addr; k++) {
237 /* Send the write command */
238 send_seeprom_cmd(sd, &seeprom_write);
240 /* Send the 6 or 8 bit address (MSB first). */
241 for (i = (sd->sd_chip - 1); i >= 0; i--) {
242 if ((k & (1 << i)) != 0)
244 SEEPROM_OUTB(sd, temp);
245 CLOCK_PULSE(sd, sd->sd_RDY);
246 SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
247 CLOCK_PULSE(sd, sd->sd_RDY);
248 if ((k & (1 << i)) != 0)
252 /* Write the 16 bit value, MSB first */
253 v = buf[k - start_addr];
254 for (i = 15; i >= 0; i--) {
255 if ((v & (1 << i)) != 0)
257 SEEPROM_OUTB(sd, temp);
258 CLOCK_PULSE(sd, sd->sd_RDY);
259 SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
260 CLOCK_PULSE(sd, sd->sd_RDY);
261 if ((v & (1 << i)) != 0)
265 /* Wait for the chip to complete the write */
267 SEEPROM_OUTB(sd, temp);
268 CLOCK_PULSE(sd, sd->sd_RDY);
269 temp = sd->sd_MS ^ sd->sd_CS;
271 SEEPROM_OUTB(sd, temp);
272 CLOCK_PULSE(sd, sd->sd_RDY);
273 SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
274 CLOCK_PULSE(sd, sd->sd_RDY);
275 } while ((SEEPROM_DATA_INB(sd) & sd->sd_DI) == 0);
280 /* Put the chip back into write-protect mode */
281 send_seeprom_cmd(sd, &seeprom_ewds);
288 ahc_verify_cksum(struct seeprom_config *sc)
295 maxaddr = (sizeof(*sc)/2) - 1;
297 scarray = (uint16_t *)sc;
299 for (i = 0; i < maxaddr; i++)
300 checksum = checksum + scarray[i];
302 || (checksum & 0xFFFF) != sc->checksum) {