sys/dev/disk/aic7xxx/aic7xxx_pci.c

   1 /*
   2  * Product specific probe and attach routines for:
   3  *      3940, 2940, aic7895, aic7890, aic7880,
   4  *      aic7870, aic7860 and aic7850 SCSI controllers
   5  *
   6  * Copyright (c) 1994-2001 Justin T. Gibbs.
   7  * Copyright (c) 2000-2001 Adaptec Inc.
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions, and the following disclaimer,
  15  *    without modification.
  16  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  17  *    substantially similar to the "NO WARRANTY" disclaimer below
  18  *    ("Disclaimer") and any redistribution must be conditioned upon
  19  *    including a substantially similar Disclaimer requirement for further
  20  *    binary redistribution.
  21  * 3. Neither the names of the above-listed copyright holders nor the names
  22  *    of any contributors may be used to endorse or promote products derived
  23  *    from this software without specific prior written permission.
  24  *
  25  * Alternatively, this software may be distributed under the terms of the
  26  * GNU General Public License ("GPL") version 2 as published by the Free
  27  * Software Foundation.
  28  *
  29  * NO WARRANTY
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  31  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  32  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  33  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  34  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  35  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  36  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  37  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  38  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  39  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  40  * POSSIBILITY OF SUCH DAMAGES.
  41  *
  42  * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#78 $
  43  *
  44  * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.35 2005/09/22 05:11:35 gibbs Exp $
  45  * $DragonFly: src/sys/dev/disk/aic7xxx/aic7xxx_pci.c,v 1.13 2007/08/04 21:42:15 dillon Exp $
  46  */
  47
  48 #ifdef __linux__
  49 #include "aic7xxx_osm.h"
  50 #include "aic7xxx_inline.h"
  51 #include "aic7xxx_93cx6.h"
  52 #else
  53 #include "aic7xxx_osm.h"
  54 #include "aic7xxx_inline.h"
  55 #include "aic7xxx_93cx6.h"
  56 #endif
  57
  58 static __inline uint64_t
  59 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
  60 {
  61         uint64_t id;
  62
  63         id = subvendor
  64            | (subdevice << 16)
  65            | ((uint64_t)vendor << 32)
  66            | ((uint64_t)device << 48);
  67
  68         return (id);
  69 }
  70
  71 #define ID_ALL_MASK                     0xFFFFFFFFFFFFFFFFull
  72 #define ID_DEV_VENDOR_MASK              0xFFFFFFFF00000000ull
  73 #define ID_9005_GENERIC_MASK            0xFFF0FFFF00000000ull
  74 #define ID_9005_SISL_MASK               0x000FFFFF00000000ull
  75 #define ID_9005_SISL_ID                 0x0005900500000000ull
  76 #define ID_AIC7850                      0x5078900400000000ull
  77 #define ID_AHA_2902_04_10_15_20C_30C    0x5078900478509004ull
  78 #define ID_AIC7855                      0x5578900400000000ull
  79 #define ID_AIC7859                      0x3860900400000000ull
  80 #define ID_AHA_2930CU                   0x3860900438699004ull
  81 #define ID_AIC7860                      0x6078900400000000ull
  82 #define ID_AIC7860C                     0x6078900478609004ull
  83 #define ID_AHA_1480A                    0x6075900400000000ull
  84 #define ID_AHA_2940AU_0                 0x6178900400000000ull
  85 #define ID_AHA_2940AU_1                 0x6178900478619004ull
  86 #define ID_AHA_2940AU_CN                0x2178900478219004ull
  87 #define ID_AHA_2930C_VAR                0x6038900438689004ull
  88
  89 #define ID_AIC7870                      0x7078900400000000ull
  90 #define ID_AHA_2940                     0x7178900400000000ull
  91 #define ID_AHA_3940                     0x7278900400000000ull
  92 #define ID_AHA_398X                     0x7378900400000000ull
  93 #define ID_AHA_2944                     0x7478900400000000ull
  94 #define ID_AHA_3944                     0x7578900400000000ull
  95 #define ID_AHA_4944                     0x7678900400000000ull
  96
  97 #define ID_AIC7880                      0x8078900400000000ull
  98 #define ID_AIC7880_B                    0x8078900478809004ull
  99 #define ID_AHA_2940U                    0x8178900400000000ull
 100 #define ID_AHA_3940U                    0x8278900400000000ull
 101 #define ID_AHA_2944U                    0x8478900400000000ull
 102 #define ID_AHA_3944U                    0x8578900400000000ull
 103 #define ID_AHA_398XU                    0x8378900400000000ull
 104 #define ID_AHA_4944U                    0x8678900400000000ull
 105 #define ID_AHA_2940UB                   0x8178900478819004ull
 106 #define ID_AHA_2930U                    0x8878900478889004ull
 107 #define ID_AHA_2940U_PRO                0x8778900478879004ull
 108 #define ID_AHA_2940U_CN                 0x0078900478009004ull
 109
 110 #define ID_AIC7895                      0x7895900478959004ull
 111 #define ID_AIC7895_ARO                  0x7890900478939004ull
 112 #define ID_AIC7895_ARO_MASK             0xFFF0FFFFFFFFFFFFull
 113 #define ID_AHA_2940U_DUAL               0x7895900478919004ull
 114 #define ID_AHA_3940AU                   0x7895900478929004ull
 115 #define ID_AHA_3944AU                   0x7895900478949004ull
 116
 117 #define ID_AIC7890                      0x001F9005000F9005ull
 118 #define ID_AIC7890_ARO                  0x00139005000F9005ull
 119 #define ID_AAA_131U2                    0x0013900500039005ull
 120 #define ID_AHA_2930U2                   0x0011900501819005ull
 121 #define ID_AHA_2940U2B                  0x00109005A1009005ull
 122 #define ID_AHA_2940U2_OEM               0x0010900521809005ull
 123 #define ID_AHA_2940U2                   0x00109005A1809005ull
 124 #define ID_AHA_2950U2B                  0x00109005E1009005ull
 125
 126 #define ID_AIC7892                      0x008F9005FFFF9005ull
 127 #define ID_AIC7892_ARO                  0x00839005FFFF9005ull
 128 #define ID_AHA_29160                    0x00809005E2A09005ull
 129 #define ID_AHA_29160_CPQ                0x00809005E2A00E11ull
 130 #define ID_AHA_29160N                   0x0080900562A09005ull
 131 #define ID_AHA_29160C                   0x0080900562209005ull
 132 #define ID_AHA_29160B                   0x00809005E2209005ull
 133 #define ID_AHA_19160B                   0x0081900562A19005ull
 134 #define ID_AHA_2915_30LP                0x0082900502109005ull
 135
 136 #define ID_AIC7896                      0x005F9005FFFF9005ull
 137 #define ID_AIC7896_ARO                  0x00539005FFFF9005ull
 138 #define ID_AHA_3950U2B_0                0x00509005FFFF9005ull
 139 #define ID_AHA_3950U2B_1                0x00509005F5009005ull
 140 #define ID_AHA_3950U2D_0                0x00519005FFFF9005ull
 141 #define ID_AHA_3950U2D_1                0x00519005B5009005ull
 142
 143 #define ID_AIC7899                      0x00CF9005FFFF9005ull
 144 #define ID_AIC7899_ARO                  0x00C39005FFFF9005ull
 145 #define ID_AHA_3960D                    0x00C09005F6209005ull
 146 #define ID_AHA_3960D_CPQ                0x00C09005F6200E11ull
 147
 148 #define ID_AIC7810                      0x1078900400000000ull
 149 #define ID_AIC7815                      0x7815900400000000ull
 150
 151 #define DEVID_9005_TYPE(id) ((id) & 0xF)
 152 #define         DEVID_9005_TYPE_HBA             0x0     /* Standard Card */
 153 #define         DEVID_9005_TYPE_AAA             0x3     /* RAID Card */
 154 #define         DEVID_9005_TYPE_SISL            0x5     /* Container ROMB */
 155 #define         DEVID_9005_TYPE_MB              0xF     /* On Motherboard */
 156
 157 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
 158 #define         DEVID_9005_MAXRATE_U160         0x0
 159 #define         DEVID_9005_MAXRATE_ULTRA2       0x1
 160 #define         DEVID_9005_MAXRATE_ULTRA        0x2
 161 #define         DEVID_9005_MAXRATE_FAST         0x3
 162
 163 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
 164
 165 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
 166 #define         DEVID_9005_CLASS_SPI            0x0     /* Parallel SCSI */
 167
 168 #define SUBID_9005_TYPE(id) ((id) & 0xF)
 169 #define         SUBID_9005_TYPE_MB              0xF     /* On Motherboard */
 170 #define         SUBID_9005_TYPE_CARD            0x0     /* Standard Card */
 171 #define         SUBID_9005_TYPE_LCCARD          0x1     /* Low Cost Card */
 172 #define         SUBID_9005_TYPE_RAID            0x3     /* Combined with Raid */
 173
 174 #define SUBID_9005_TYPE_KNOWN(id)                       \
 175           ((((id) & 0xF) == SUBID_9005_TYPE_MB)         \
 176         || (((id) & 0xF) == SUBID_9005_TYPE_CARD)       \
 177         || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD)     \
 178         || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
 179
 180 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
 181 #define         SUBID_9005_MAXRATE_ULTRA2       0x0
 182 #define         SUBID_9005_MAXRATE_ULTRA        0x1
 183 #define         SUBID_9005_MAXRATE_U160         0x2
 184 #define         SUBID_9005_MAXRATE_RESERVED     0x3
 185
 186 #define SUBID_9005_SEEPTYPE(id)                                         \
 187         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 188          ? ((id) & 0xC0) >> 6                                           \
 189          : ((id) & 0x300) >> 8)
 190 #define         SUBID_9005_SEEPTYPE_NONE        0x0
 191 #define         SUBID_9005_SEEPTYPE_1K          0x1
 192 #define         SUBID_9005_SEEPTYPE_2K_4K       0x2
 193 #define         SUBID_9005_SEEPTYPE_RESERVED    0x3
 194 #define SUBID_9005_AUTOTERM(id)                                         \
 195         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 196          ? (((id) & 0x400) >> 10) == 0                                  \
 197          : (((id) & 0x40) >> 6) == 0)
 198
 199 #define SUBID_9005_NUMCHAN(id)                                          \
 200         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 201          ? ((id) & 0x300) >> 8                                          \
 202          : ((id) & 0xC00) >> 10)
 203
 204 #define SUBID_9005_LEGACYCONN(id)                                       \
 205         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 206          ? 0                                                            \
 207          : ((id) & 0x80) >> 7)
 208
 209 #define SUBID_9005_MFUNCENB(id)                                         \
 210         ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB)                    \
 211          ? ((id) & 0x800) >> 11                                         \
 212          : ((id) & 0x1000) >> 12)
 213 /*
 214  * Informational only. Should use chip register to be
 215  * certain, but may be use in identification strings.
 216  */
 217 #define SUBID_9005_CARD_SCSIWIDTH_MASK  0x2000
 218 #define SUBID_9005_CARD_PCIWIDTH_MASK   0x4000
 219 #define SUBID_9005_CARD_SEDIFF_MASK     0x8000
 220
 221 static ahc_device_setup_t ahc_aic785X_setup;
 222 static ahc_device_setup_t ahc_aic7860_setup;
 223 static ahc_device_setup_t ahc_apa1480_setup;
 224 static ahc_device_setup_t ahc_aic7870_setup;
 225 static ahc_device_setup_t ahc_aha394X_setup;
 226 static ahc_device_setup_t ahc_aha494X_setup;
 227 static ahc_device_setup_t ahc_aha398X_setup;
 228 static ahc_device_setup_t ahc_aic7880_setup;
 229 static ahc_device_setup_t ahc_aha2940Pro_setup;
 230 static ahc_device_setup_t ahc_aha394XU_setup;
 231 static ahc_device_setup_t ahc_aha398XU_setup;
 232 static ahc_device_setup_t ahc_aic7890_setup;
 233 static ahc_device_setup_t ahc_aic7892_setup;
 234 static ahc_device_setup_t ahc_aic7895_setup;
 235 static ahc_device_setup_t ahc_aic7896_setup;
 236 static ahc_device_setup_t ahc_aic7899_setup;
 237 static ahc_device_setup_t ahc_aha29160C_setup;
 238 static ahc_device_setup_t ahc_raid_setup;
 239 static ahc_device_setup_t ahc_aha394XX_setup;
 240 static ahc_device_setup_t ahc_aha494XX_setup;
 241 static ahc_device_setup_t ahc_aha398XX_setup;
 242
 243 struct ahc_pci_identity ahc_pci_ident_table [] =
 244 {
 245         /* aic7850 based controllers */
 246         {
 247                 ID_AHA_2902_04_10_15_20C_30C,
 248                 ID_ALL_MASK,
 249                 "Adaptec 2902/04/10/15/20C/30C SCSI adapter",
 250                 ahc_aic785X_setup
 251         },
 252         /* aic7860 based controllers */
 253         {
 254                 ID_AHA_2930CU,
 255                 ID_ALL_MASK,
 256                 "Adaptec 2930CU SCSI adapter",
 257                 ahc_aic7860_setup
 258         },
 259         {
 260                 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
 261                 ID_DEV_VENDOR_MASK,
 262                 "Adaptec 1480A Ultra SCSI adapter",
 263                 ahc_apa1480_setup
 264         },
 265         {
 266                 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
 267                 ID_DEV_VENDOR_MASK,
 268                 "Adaptec 2940A Ultra SCSI adapter",
 269                 ahc_aic7860_setup
 270         },
 271         {
 272                 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
 273                 ID_DEV_VENDOR_MASK,
 274                 "Adaptec 2940A/CN Ultra SCSI adapter",
 275                 ahc_aic7860_setup
 276         },
 277         {
 278                 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
 279                 ID_DEV_VENDOR_MASK,
 280                 "Adaptec 2930C Ultra SCSI adapter (VAR)",
 281                 ahc_aic7860_setup
 282         },
 283         /* aic7870 based controllers */
 284         {
 285                 ID_AHA_2940,
 286                 ID_ALL_MASK,
 287                 "Adaptec 2940 SCSI adapter",
 288                 ahc_aic7870_setup
 289         },
 290         {
 291                 ID_AHA_3940,
 292                 ID_ALL_MASK,
 293                 "Adaptec 3940 SCSI adapter",
 294                 ahc_aha394X_setup
 295         },
 296         {
 297                 ID_AHA_398X,
 298                 ID_ALL_MASK,
 299                 "Adaptec 398X SCSI RAID adapter",
 300                 ahc_aha398X_setup
 301         },
 302         {
 303                 ID_AHA_2944,
 304                 ID_ALL_MASK,
 305                 "Adaptec 2944 SCSI adapter",
 306                 ahc_aic7870_setup
 307         },
 308         {
 309                 ID_AHA_3944,
 310                 ID_ALL_MASK,
 311                 "Adaptec 3944 SCSI adapter",
 312                 ahc_aha394X_setup
 313         },
 314         {
 315                 ID_AHA_4944,
 316                 ID_ALL_MASK,
 317                 "Adaptec 4944 SCSI adapter",
 318                 ahc_aha494X_setup
 319         },
 320         /* aic7880 based controllers */
 321         {
 322                 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
 323                 ID_DEV_VENDOR_MASK,
 324                 "Adaptec 2940 Ultra SCSI adapter",
 325                 ahc_aic7880_setup
 326         },
 327         {
 328                 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
 329                 ID_DEV_VENDOR_MASK,
 330                 "Adaptec 3940 Ultra SCSI adapter",
 331                 ahc_aha394XU_setup
 332         },
 333         {
 334                 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
 335                 ID_DEV_VENDOR_MASK,
 336                 "Adaptec 2944 Ultra SCSI adapter",
 337                 ahc_aic7880_setup
 338         },
 339         {
 340                 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
 341                 ID_DEV_VENDOR_MASK,
 342                 "Adaptec 3944 Ultra SCSI adapter",
 343                 ahc_aha394XU_setup
 344         },
 345         {
 346                 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
 347                 ID_DEV_VENDOR_MASK,
 348                 "Adaptec 398X Ultra SCSI RAID adapter",
 349                 ahc_aha398XU_setup
 350         },
 351         {
 352                 /*
 353                  * XXX Don't know the slot numbers
 354                  * so we can't identify channels
 355                  */
 356                 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
 357                 ID_DEV_VENDOR_MASK,
 358                 "Adaptec 4944 Ultra SCSI adapter",
 359                 ahc_aic7880_setup
 360         },
 361         {
 362                 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
 363                 ID_DEV_VENDOR_MASK,
 364                 "Adaptec 2930 Ultra SCSI adapter",
 365                 ahc_aic7880_setup
 366         },
 367         {
 368                 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
 369                 ID_DEV_VENDOR_MASK,
 370                 "Adaptec 2940 Pro Ultra SCSI adapter",
 371                 ahc_aha2940Pro_setup
 372         },
 373         {
 374                 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
 375                 ID_DEV_VENDOR_MASK,
 376                 "Adaptec 2940/CN Ultra SCSI adapter",
 377                 ahc_aic7880_setup
 378         },
 379         /* Ignore all SISL (AAC on MB) based controllers. */
 380         {
 381                 ID_9005_SISL_ID,
 382                 ID_9005_SISL_MASK,
 383                 NULL,
 384                 NULL
 385         },
 386         /* aic7890 based controllers */
 387         {
 388                 ID_AHA_2930U2,
 389                 ID_ALL_MASK,
 390                 "Adaptec 2930 Ultra2 SCSI adapter",
 391                 ahc_aic7890_setup
 392         },
 393         {
 394                 ID_AHA_2940U2B,
 395                 ID_ALL_MASK,
 396                 "Adaptec 2940B Ultra2 SCSI adapter",
 397                 ahc_aic7890_setup
 398         },
 399         {
 400                 ID_AHA_2940U2_OEM,
 401                 ID_ALL_MASK,
 402                 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
 403                 ahc_aic7890_setup
 404         },
 405         {
 406                 ID_AHA_2940U2,
 407                 ID_ALL_MASK,
 408                 "Adaptec 2940 Ultra2 SCSI adapter",
 409                 ahc_aic7890_setup
 410         },
 411         {
 412                 ID_AHA_2950U2B,
 413                 ID_ALL_MASK,
 414                 "Adaptec 2950 Ultra2 SCSI adapter",
 415                 ahc_aic7890_setup
 416         },
 417         {
 418                 ID_AIC7890_ARO,
 419                 ID_ALL_MASK,
 420                 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
 421                 ahc_aic7890_setup
 422         },
 423         {
 424                 ID_AAA_131U2,
 425                 ID_ALL_MASK,
 426                 "Adaptec AAA-131 Ultra2 RAID adapter",
 427                 ahc_aic7890_setup
 428         },
 429         /* aic7892 based controllers */
 430         {
 431                 ID_AHA_29160,
 432                 ID_ALL_MASK,
 433                 "Adaptec 29160 Ultra160 SCSI adapter",
 434                 ahc_aic7892_setup
 435         },
 436         {
 437                 ID_AHA_29160_CPQ,
 438                 ID_ALL_MASK,
 439                 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
 440                 ahc_aic7892_setup
 441         },
 442         {
 443                 ID_AHA_29160N,
 444                 ID_ALL_MASK,
 445                 "Adaptec 29160N Ultra160 SCSI adapter",
 446                 ahc_aic7892_setup
 447         },
 448         {
 449                 ID_AHA_29160C,
 450                 ID_ALL_MASK,
 451                 "Adaptec 29160C Ultra160 SCSI adapter",
 452                 ahc_aha29160C_setup
 453         },
 454         {
 455                 ID_AHA_29160B,
 456                 ID_ALL_MASK,
 457                 "Adaptec 29160B Ultra160 SCSI adapter",
 458                 ahc_aic7892_setup
 459         },
 460         {
 461                 ID_AHA_19160B,
 462                 ID_ALL_MASK,
 463                 "Adaptec 19160B Ultra160 SCSI adapter",
 464                 ahc_aic7892_setup
 465         },
 466         {
 467                 ID_AIC7892_ARO,
 468                 ID_ALL_MASK,
 469                 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
 470                 ahc_aic7892_setup
 471         },
 472         {
 473                 ID_AHA_2915_30LP,
 474                 ID_ALL_MASK,
 475                 "Adaptec 2915/30LP Ultra160 SCSI adapter",
 476                 ahc_aic7892_setup
 477         },
 478         /* aic7895 based controllers */
 479         {
 480                 ID_AHA_2940U_DUAL,
 481                 ID_ALL_MASK,
 482                 "Adaptec 2940/DUAL Ultra SCSI adapter",
 483                 ahc_aic7895_setup
 484         },
 485         {
 486                 ID_AHA_3940AU,
 487                 ID_ALL_MASK,
 488                 "Adaptec 3940A Ultra SCSI adapter",
 489                 ahc_aic7895_setup
 490         },
 491         {
 492                 ID_AHA_3944AU,
 493                 ID_ALL_MASK,
 494                 "Adaptec 3944A Ultra SCSI adapter",
 495                 ahc_aic7895_setup
 496         },
 497         {
 498                 ID_AIC7895_ARO,
 499                 ID_AIC7895_ARO_MASK,
 500                 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
 501                 ahc_aic7895_setup
 502         },
 503         /* aic7896/97 based controllers */
 504         {
 505                 ID_AHA_3950U2B_0,
 506                 ID_ALL_MASK,
 507                 "Adaptec 3950B Ultra2 SCSI adapter",
 508                 ahc_aic7896_setup
 509         },
 510         {
 511                 ID_AHA_3950U2B_1,
 512                 ID_ALL_MASK,
 513                 "Adaptec 3950B Ultra2 SCSI adapter",
 514                 ahc_aic7896_setup
 515         },
 516         {
 517                 ID_AHA_3950U2D_0,
 518                 ID_ALL_MASK,
 519                 "Adaptec 3950D Ultra2 SCSI adapter",
 520                 ahc_aic7896_setup
 521         },
 522         {
 523                 ID_AHA_3950U2D_1,
 524                 ID_ALL_MASK,
 525                 "Adaptec 3950D Ultra2 SCSI adapter",
 526                 ahc_aic7896_setup
 527         },
 528         {
 529                 ID_AIC7896_ARO,
 530                 ID_ALL_MASK,
 531                 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
 532                 ahc_aic7896_setup
 533         },
 534         /* aic7899 based controllers */
 535         {
 536                 ID_AHA_3960D,
 537                 ID_ALL_MASK,
 538                 "Adaptec 3960D Ultra160 SCSI adapter",
 539                 ahc_aic7899_setup
 540         },
 541         {
 542                 ID_AHA_3960D_CPQ,
 543                 ID_ALL_MASK,
 544                 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
 545                 ahc_aic7899_setup
 546         },
 547         {
 548                 ID_AIC7899_ARO,
 549                 ID_ALL_MASK,
 550                 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
 551                 ahc_aic7899_setup
 552         },
 553         /* Generic chip probes for devices we don't know 'exactly' */
 554         {
 555                 ID_AIC7850 & ID_DEV_VENDOR_MASK,
 556                 ID_DEV_VENDOR_MASK,
 557                 "Adaptec aic7850 SCSI adapter",
 558                 ahc_aic785X_setup
 559         },
 560         {
 561                 ID_AIC7855 & ID_DEV_VENDOR_MASK,
 562                 ID_DEV_VENDOR_MASK,
 563                 "Adaptec aic7855 SCSI adapter",
 564                 ahc_aic785X_setup
 565         },
 566         {
 567                 ID_AIC7859 & ID_DEV_VENDOR_MASK,
 568                 ID_DEV_VENDOR_MASK,
 569                 "Adaptec aic7859 SCSI adapter",
 570                 ahc_aic7860_setup
 571         },
 572         {
 573                 ID_AIC7860 & ID_DEV_VENDOR_MASK,
 574                 ID_DEV_VENDOR_MASK,
 575                 "Adaptec aic7860 Ultra SCSI adapter",
 576                 ahc_aic7860_setup
 577         },
 578         {
 579                 ID_AIC7870 & ID_DEV_VENDOR_MASK,
 580                 ID_DEV_VENDOR_MASK,
 581                 "Adaptec aic7870 SCSI adapter",
 582                 ahc_aic7870_setup
 583         },
 584         {
 585                 ID_AIC7880 & ID_DEV_VENDOR_MASK,
 586                 ID_DEV_VENDOR_MASK,
 587                 "Adaptec aic7880 Ultra SCSI adapter",
 588                 ahc_aic7880_setup
 589         },
 590         {
 591                 ID_AIC7890 & ID_9005_GENERIC_MASK,
 592                 ID_9005_GENERIC_MASK,
 593                 "Adaptec aic7890/91 Ultra2 SCSI adapter",
 594                 ahc_aic7890_setup
 595         },
 596         {
 597                 ID_AIC7892 & ID_9005_GENERIC_MASK,
 598                 ID_9005_GENERIC_MASK,
 599                 "Adaptec aic7892 Ultra160 SCSI adapter",
 600                 ahc_aic7892_setup
 601         },
 602         {
 603                 ID_AIC7895 & ID_DEV_VENDOR_MASK,
 604                 ID_DEV_VENDOR_MASK,
 605                 "Adaptec aic7895 Ultra SCSI adapter",
 606                 ahc_aic7895_setup
 607         },
 608         {
 609                 ID_AIC7896 & ID_9005_GENERIC_MASK,
 610                 ID_9005_GENERIC_MASK,
 611                 "Adaptec aic7896/97 Ultra2 SCSI adapter",
 612                 ahc_aic7896_setup
 613         },
 614         {
 615                 ID_AIC7899 & ID_9005_GENERIC_MASK,
 616                 ID_9005_GENERIC_MASK,
 617                 "Adaptec aic7899 Ultra160 SCSI adapter",
 618                 ahc_aic7899_setup
 619         },
 620         {
 621                 ID_AIC7810 & ID_DEV_VENDOR_MASK,
 622                 ID_DEV_VENDOR_MASK,
 623                 "Adaptec aic7810 RAID memory controller",
 624                 ahc_raid_setup
 625         },
 626         {
 627                 ID_AIC7815 & ID_DEV_VENDOR_MASK,
 628                 ID_DEV_VENDOR_MASK,
 629                 "Adaptec aic7815 RAID memory controller",
 630                 ahc_raid_setup
 631         }
 632 };
 633
 634 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table);
 635
 636 #define AHC_394X_SLOT_CHANNEL_A 4
 637 #define AHC_394X_SLOT_CHANNEL_B 5
 638
 639 #define AHC_398X_SLOT_CHANNEL_A 4
 640 #define AHC_398X_SLOT_CHANNEL_B 8
 641 #define AHC_398X_SLOT_CHANNEL_C 12
 642
 643 #define AHC_494X_SLOT_CHANNEL_A 4
 644 #define AHC_494X_SLOT_CHANNEL_B 5
 645 #define AHC_494X_SLOT_CHANNEL_C 6
 646 #define AHC_494X_SLOT_CHANNEL_D 7
 647
 648 #define DEVCONFIG               0x40
 649 #define         PCIERRGENDIS    0x80000000ul
 650 #define         SCBSIZE32       0x00010000ul    /* aic789X only */
 651 #define         REXTVALID       0x00001000ul    /* ultra cards only */
 652 #define         MPORTMODE       0x00000400ul    /* aic7870+ only */
 653 #define         RAMPSM          0x00000200ul    /* aic7870+ only */
 654 #define         VOLSENSE        0x00000100ul
 655 #define         PCI64BIT        0x00000080ul    /* 64Bit PCI bus (Ultra2 Only)*/
 656 #define         SCBRAMSEL       0x00000080ul
 657 #define         MRDCEN          0x00000040ul
 658 #define         EXTSCBTIME      0x00000020ul    /* aic7870 only */
 659 #define         EXTSCBPEN       0x00000010ul    /* aic7870 only */
 660 #define         BERREN          0x00000008ul
 661 #define         DACEN           0x00000004ul
 662 #define         STPWLEVEL       0x00000002ul
 663 #define         DIFACTNEGEN     0x00000001ul    /* aic7870 only */
 664
 665 #define CSIZE_LATTIME           0x0c
 666 #define         CACHESIZE       0x0000003ful    /* only 5 bits */
 667 #define         LATTIME         0x0000ff00ul
 668
 669 /* PCI STATUS definitions */
 670 #define DPE     0x80
 671 #define SSE     0x40
 672 #define RMA     0x20
 673 #define RTA     0x10
 674 #define STA     0x08
 675 #define DPR     0x01
 676
 677 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device,
 678                                      uint16_t subvendor, uint16_t subdevice);
 679 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
 680 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
 681                                   int pcheck, int fast, int large);
 682 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
 683 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
 684 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
 685                                  struct seeprom_config *sc);
 686 static void configure_termination(struct ahc_softc *ahc,
 687                                   struct seeprom_descriptor *sd,
 688                                   u_int adapter_control,
 689                                   u_int *sxfrctl1);
 690
 691 static void ahc_new_term_detect(struct ahc_softc *ahc,
 692                                 int *enableSEC_low,
 693                                 int *enableSEC_high,
 694                                 int *enablePRI_low,
 695                                 int *enablePRI_high,
 696                                 int *eeprom_present);
 697 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
 698                                  int *internal68_present,
 699                                  int *externalcable_present,
 700                                  int *eeprom_present);
 701 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
 702                                  int *externalcable_present,
 703                                  int *eeprom_present);
 704 static void    write_brdctl(struct ahc_softc *ahc, uint8_t value);
 705 static uint8_t read_brdctl(struct ahc_softc *ahc);
 706 static void ahc_pci_intr(struct ahc_softc *ahc);
 707 static int  ahc_pci_chip_init(struct ahc_softc *ahc);
 708 static int  ahc_pci_suspend(struct ahc_softc *ahc);
 709 static int  ahc_pci_resume(struct ahc_softc *ahc);
 710
 711 static int
 712 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
 713                           uint16_t subdevice, uint16_t subvendor)
 714 {
 715         int result;
 716
 717         /* Default to invalid. */
 718         result = 0;
 719         if (vendor == 0x9005
 720          && subvendor == 0x9005
 721          && subdevice != device
 722          && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
 723
 724                 switch (SUBID_9005_TYPE(subdevice)) {
 725                 case SUBID_9005_TYPE_MB:
 726                         break;
 727                 case SUBID_9005_TYPE_CARD:
 728                 case SUBID_9005_TYPE_LCCARD:
 729                         /*
 730                          * Currently only trust Adaptec cards to
 731                          * get the sub device info correct.
 732                          */
 733                         if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
 734                                 result = 1;
 735                         break;
 736                 case SUBID_9005_TYPE_RAID:
 737                         break;
 738                 default:
 739                         break;
 740                 }
 741         }
 742         return (result);
 743 }
 744
 745 struct ahc_pci_identity *
 746 ahc_find_pci_device(aic_dev_softc_t pci)
 747 {
 748         uint64_t  full_id;
 749         uint16_t  device;
 750         uint16_t  vendor;
 751         uint16_t  subdevice;
 752         uint16_t  subvendor;
 753         struct    ahc_pci_identity *entry;
 754         u_int     i;
 755
 756         vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
 757         device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
 758         subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
 759         subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
 760         full_id = ahc_compose_id(device, vendor, subdevice, subvendor);
 761
 762         /*
 763          * If the second function is not hooked up, ignore it.
 764          * Unfortunately, not all MB vendors implement the
 765          * subdevice ID as per the Adaptec spec, so do our best
 766          * to sanity check it prior to accepting the subdevice
 767          * ID as valid.
 768          */
 769         if (aic_get_pci_function(pci) > 0
 770          && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice)
 771          && SUBID_9005_MFUNCENB(subdevice) == 0)
 772                 return (NULL);
 773
 774         for (i = 0; i < ahc_num_pci_devs; i++) {
 775                 entry = &ahc_pci_ident_table[i];
 776                 if (entry->full_id == (full_id & entry->id_mask)) {
 777                         /* Honor exclusion entries. */
 778                         if (entry->name == NULL)
 779                                 return (NULL);
 780                         return (entry);
 781                 }
 782         }
 783         return (NULL);
 784 }
 785
 786 int
 787 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
 788 {
 789         u_int    command;
 790         u_int    our_id;
 791         u_int    sxfrctl1;
 792         u_int    scsiseq;
 793         u_int    dscommand0;
 794         uint32_t devconfig;
 795         int      error;
 796         uint8_t  sblkctl;
 797
 798         our_id = 0;
 799         error = entry->setup(ahc);
 800         if (error != 0)
 801                 return (error);
 802         ahc->chip |= AHC_PCI;
 803         ahc->description = entry->name;
 804
 805         aic_power_state_change(ahc, AIC_POWER_STATE_D0);
 806
 807         error = ahc_pci_map_registers(ahc);
 808         if (error != 0)
 809                 return (error);
 810
 811         /*
 812          * Before we continue probing the card, ensure that
 813          * its interrupts are *disabled*.  We don't want
 814          * a misstep to hang the machine in an interrupt
 815          * storm.
 816          */
 817         ahc_intr_enable(ahc, FALSE);
 818
 819         devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
 820
 821         /*
 822          * If we need to support high memory, enable dual
 823          * address cycles.  This bit must be set to enable
 824          * high address bit generation even if we are on a
 825          * 64bit bus (PCI64BIT set in devconfig).
 826          */
 827         if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
 828
 829                 if (bootverbose)
 830                         kprintf("%s: Enabling 39Bit Addressing\n",
 831                                ahc_name(ahc));
 832                 devconfig |= DACEN;
 833         }
 834
 835         /* Ensure that pci error generation, a test feature, is disabled. */
 836         devconfig |= PCIERRGENDIS;
 837
 838         aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
 839
 840         /* Ensure busmastering is enabled */
 841         command = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
 842         command |= PCIM_CMD_BUSMASTEREN;
 843
 844         aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
 845
 846         /* On all PCI adapters, we allow SCB paging */
 847         ahc->flags |= AHC_PAGESCBS;
 848
 849         error = ahc_softc_init(ahc);
 850         if (error != 0)
 851                 return (error);
 852
 853         /*
 854          * Disable PCI parity error checking.  Users typically
 855          * do this to work around broken PCI chipsets that get
 856          * the parity timing wrong and thus generate lots of spurious
 857          * errors.  The chip only allows us to disable *all* parity
 858          * error reporting when doing this, so CIO bus, scb ram, and
 859          * scratch ram parity errors will be ignored too.
 860          */
 861         if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
 862                 ahc->seqctl |= FAILDIS;
 863
 864         ahc->bus_intr = ahc_pci_intr;
 865         ahc->bus_chip_init = ahc_pci_chip_init;
 866         ahc->bus_suspend = ahc_pci_suspend;
 867         ahc->bus_resume = ahc_pci_resume;
 868
 869         /* Remeber how the card was setup in case there is no SEEPROM */
 870         if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
 871                 ahc_pause(ahc);
 872                 if ((ahc->features & AHC_ULTRA2) != 0)
 873                         our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
 874                 else
 875                         our_id = ahc_inb(ahc, SCSIID) & OID;
 876                 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
 877                 scsiseq = ahc_inb(ahc, SCSISEQ);
 878         } else {
 879                 sxfrctl1 = STPWEN;
 880                 our_id = 7;
 881                 scsiseq = 0;
 882         }
 883
 884         error = ahc_reset(ahc, /*reinit*/FALSE);
 885         if (error != 0)
 886                 return (ENXIO);
 887
 888         if ((ahc->features & AHC_DT) != 0) {
 889                 u_int sfunct;
 890
 891                 /* Perform ALT-Mode Setup */
 892                 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
 893                 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
 894                 ahc_outb(ahc, OPTIONMODE,
 895                          OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
 896                 ahc_outb(ahc, SFUNCT, sfunct);
 897
 898                 /* Normal mode setup */
 899                 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
 900                                           |TARGCRCENDEN);
 901         }
 902
 903         dscommand0 = ahc_inb(ahc, DSCOMMAND0);
 904         dscommand0 |= MPARCKEN|CACHETHEN;
 905         if ((ahc->features & AHC_ULTRA2) != 0) {
 906
 907                 /*
 908                  * DPARCKEN doesn't work correctly on
 909                  * some MBs so don't use it.
 910                  */
 911                 dscommand0 &= ~DPARCKEN;
 912         }
 913
 914         /*
 915          * Handle chips that must have cache line
 916          * streaming (dis/en)abled.
 917          */
 918         if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
 919                 dscommand0 |= CACHETHEN;
 920
 921         if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
 922                 dscommand0 &= ~CACHETHEN;
 923
 924         ahc_outb(ahc, DSCOMMAND0, dscommand0);
 925
 926         ahc->pci_cachesize =
 927             aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME,
 928                                 /*bytes*/1) & CACHESIZE;
 929         ahc->pci_cachesize *= 4;
 930
 931         if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
 932          && ahc->pci_cachesize == 4) {
 933
 934                 aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
 935                                      0, /*bytes*/1);
 936                 ahc->pci_cachesize = 0;
 937         }
 938
 939         /*
 940          * We cannot perform ULTRA speeds without the presense
 941          * of the external precision resistor.
 942          */
 943         if ((ahc->features & AHC_ULTRA) != 0) {
 944                 uint32_t devconfig;
 945
 946                 devconfig = aic_pci_read_config(ahc->dev_softc,
 947                                                 DEVCONFIG, /*bytes*/4);
 948                 if ((devconfig & REXTVALID) == 0)
 949                         ahc->features &= ~AHC_ULTRA;
 950         }
 951
 952         /* See if we have a SEEPROM and perform auto-term */
 953         check_extport(ahc, &sxfrctl1);
 954
 955         /*
 956          * Take the LED out of diagnostic mode
 957          */
 958         sblkctl = ahc_inb(ahc, SBLKCTL);
 959         ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
 960
 961         if ((ahc->features & AHC_ULTRA2) != 0) {
 962                 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
 963         } else {
 964                 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
 965         }
 966
 967         if (ahc->flags & AHC_USEDEFAULTS) {
 968                 /*
 969                  * PCI Adapter default setup
 970                  * Should only be used if the adapter does not have
 971                  * a SEEPROM.
 972                  */
 973                 /* See if someone else set us up already */
 974                 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
 975                  && scsiseq != 0) {
 976                         kprintf("%s: Using left over BIOS settings\n",
 977                                 ahc_name(ahc));
 978                         ahc->flags &= ~AHC_USEDEFAULTS;
 979                         ahc->flags |= AHC_BIOS_ENABLED;
 980                 } else {
 981                         /*
 982                          * Assume only one connector and always turn
 983                          * on termination.
 984                          */
 985                         our_id = 0x07;
 986                         sxfrctl1 = STPWEN;
 987                 }
 988                 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
 989
 990                 ahc->our_id = our_id;
 991         }
 992
 993         /*
 994          * Take a look to see if we have external SRAM.
 995          * We currently do not attempt to use SRAM that is
 996          * shared among multiple controllers.
 997          */
 998         ahc_probe_ext_scbram(ahc);
 999
1000         /*
1001          * Record our termination setting for the
1002          * generic initialization routine.
1003          */
1004         if ((sxfrctl1 & STPWEN) != 0)
1005                 ahc->flags |= AHC_TERM_ENB_A;
1006
1007         /*
1008          * Save chip register configuration data for chip resets
1009          * that occur during runtime and resume events.
1010          */
1011         ahc->bus_softc.pci_softc.devconfig =
1012             aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1013         ahc->bus_softc.pci_softc.command =
1014             aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
1015         ahc->bus_softc.pci_softc.csize_lattime =
1016             aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1);
1017         ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1018         ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
1019         if ((ahc->features & AHC_DT) != 0) {
1020                 u_int sfunct;
1021
1022                 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
1023                 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
1024                 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
1025                 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
1026                 ahc_outb(ahc, SFUNCT, sfunct);
1027                 ahc->bus_softc.pci_softc.crccontrol1 =
1028                     ahc_inb(ahc, CRCCONTROL1);
1029         }
1030         if ((ahc->features & AHC_MULTI_FUNC) != 0)
1031                 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
1032
1033         if ((ahc->features & AHC_ULTRA2) != 0)
1034                 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
1035
1036         /* Core initialization */
1037         error = ahc_init(ahc);
1038         if (error != 0)
1039                 return (error);
1040
1041         /*
1042          * Allow interrupts now that we are completely setup.
1043          */
1044         error = ahc_pci_map_int(ahc);
1045         if (error != 0)
1046                 return (error);
1047
1048         /*
1049          * Link this softc in with all other ahc instances.
1050          */
1051         ahc_softc_insert(ahc);
1052         return (0);
1053 }
1054
1055 /*
1056  * Test for the presense of external sram in an
1057  * "unshared" configuration.
1058  */
1059 static int
1060 ahc_ext_scbram_present(struct ahc_softc *ahc)
1061 {
1062         u_int chip;
1063         int ramps;
1064         int single_user;
1065         uint32_t devconfig;
1066
1067         chip = ahc->chip & AHC_CHIPID_MASK;
1068         devconfig = aic_pci_read_config(ahc->dev_softc,
1069                                         DEVCONFIG, /*bytes*/4);
1070         single_user = (devconfig & MPORTMODE) != 0;
1071
1072         if ((ahc->features & AHC_ULTRA2) != 0)
1073                 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
1074         else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
1075                 /*
1076                  * External SCBRAM arbitration is flakey
1077                  * on these chips.  Unfortunately this means
1078                  * we don't use the extra SCB ram space on the
1079                  * 3940AUW.
1080                  */
1081                 ramps = 0;
1082         else if (chip >= AHC_AIC7870)
1083                 ramps = (devconfig & RAMPSM) != 0;
1084         else
1085                 ramps = 0;
1086
1087         if (ramps && single_user)
1088                 return (1);
1089         return (0);
1090 }
1091
1092 /*
1093  * Enable external scbram.
1094  */
1095 static void
1096 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1097                   int fast, int large)
1098 {
1099         uint32_t devconfig;
1100
1101         if (ahc->features & AHC_MULTI_FUNC) {
1102                 /*
1103                  * Set the SCB Base addr (highest address bit)
1104                  * depending on which channel we are.
1105                  */
1106                 ahc_outb(ahc, SCBBADDR, aic_get_pci_function(ahc->dev_softc));
1107         }
1108
1109         ahc->flags &= ~AHC_LSCBS_ENABLED;
1110         if (large)
1111                 ahc->flags |= AHC_LSCBS_ENABLED;
1112         devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1113         if ((ahc->features & AHC_ULTRA2) != 0) {
1114                 u_int dscommand0;
1115
1116                 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1117                 if (enable)
1118                         dscommand0 &= ~INTSCBRAMSEL;
1119                 else
1120                         dscommand0 |= INTSCBRAMSEL;
1121                 if (large)
1122                         dscommand0 &= ~USCBSIZE32;
1123                 else
1124                         dscommand0 |= USCBSIZE32;
1125                 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1126         } else {
1127                 if (fast)
1128                         devconfig &= ~EXTSCBTIME;
1129                 else
1130                         devconfig |= EXTSCBTIME;
1131                 if (enable)
1132                         devconfig &= ~SCBRAMSEL;
1133                 else
1134                         devconfig |= SCBRAMSEL;
1135                 if (large)
1136                         devconfig &= ~SCBSIZE32;
1137                 else
1138                         devconfig |= SCBSIZE32;
1139         }
1140         if (pcheck)
1141                 devconfig |= EXTSCBPEN;
1142         else
1143                 devconfig &= ~EXTSCBPEN;
1144
1145         aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
1146 }
1147
1148 /*
1149  * Take a look to see if we have external SRAM.
1150  * We currently do not attempt to use SRAM that is
1151  * shared among multiple controllers.
1152  */
1153 static void
1154 ahc_probe_ext_scbram(struct ahc_softc *ahc)
1155 {
1156         int num_scbs;
1157         int test_num_scbs;
1158         int enable;
1159         int pcheck;
1160         int fast;
1161         int large;
1162
1163         enable = FALSE;
1164         pcheck = FALSE;
1165         fast = FALSE;
1166         large = FALSE;
1167         num_scbs = 0;
1168
1169         if (ahc_ext_scbram_present(ahc) == 0)
1170                 goto done;
1171
1172         /*
1173          * Probe for the best parameters to use.
1174          */
1175         ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1176         num_scbs = ahc_probe_scbs(ahc);
1177         if (num_scbs == 0) {
1178                 /* The SRAM wasn't really present. */
1179                 goto done;
1180         }
1181         enable = TRUE;
1182
1183         /*
1184          * Clear any outstanding parity error
1185          * and ensure that parity error reporting
1186          * is enabled.
1187          */
1188         ahc_outb(ahc, SEQCTL, 0);
1189         ahc_outb(ahc, CLRINT, CLRPARERR);
1190         ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1191
1192         /* Now see if we can do parity */
1193         ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1194         num_scbs = ahc_probe_scbs(ahc);
1195         if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1196          || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1197                 pcheck = TRUE;
1198
1199         /* Clear any resulting parity error */
1200         ahc_outb(ahc, CLRINT, CLRPARERR);
1201         ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1202
1203         /* Now see if we can do fast timing */
1204         ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1205         test_num_scbs = ahc_probe_scbs(ahc);
1206         if (test_num_scbs == num_scbs
1207          && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1208           || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1209                 fast = TRUE;
1210
1211         /*
1212          * See if we can use large SCBs and still maintain
1213          * the same overall count of SCBs.
1214          */
1215         if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1216                 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1217                 test_num_scbs = ahc_probe_scbs(ahc);
1218                 if (test_num_scbs >= num_scbs) {
1219                         large = TRUE;
1220                         num_scbs = test_num_scbs;
1221                         if (num_scbs >= 64) {
1222                                 /*
1223                                  * We have enough space to move the
1224                                  * "busy targets table" into SCB space
1225                                  * and make it qualify all the way to the
1226                                  * lun level.
1227                                  */
1228                                 ahc->flags |= AHC_SCB_BTT;
1229                         }
1230                 }
1231         }
1232 done:
1233         /*
1234          * Disable parity error reporting until we
1235          * can load instruction ram.
1236          */
1237         ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1238         /* Clear any latched parity error */
1239         ahc_outb(ahc, CLRINT, CLRPARERR);
1240         ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1241         if (bootverbose && enable) {
1242                 kprintf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1243                        ahc_name(ahc), fast ? "fast" : "slow",
1244                        pcheck ? ", parity checking enabled" : "",
1245                        large ? 64 : 32);
1246         }
1247         ahc_scbram_config(ahc, enable, pcheck, fast, large);
1248 }
1249
1250 /*
1251  * Perform some simple tests that should catch situations where
1252  * our registers are invalidly mapped.
1253  */
1254 int
1255 ahc_pci_test_register_access(struct ahc_softc *ahc)
1256 {
1257         int      error;
1258         u_int    status1;
1259         uint32_t cmd;
1260         uint8_t  hcntrl;
1261
1262         error = EIO;
1263
1264         /*
1265          * Enable PCI error interrupt status, but suppress NMIs
1266          * generated by SERR raised due to target aborts.
1267          */
1268         cmd = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
1269         aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
1270                              cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
1271
1272         /*
1273          * First a simple test to see if any
1274          * registers can be read.  Reading
1275          * HCNTRL has no side effects and has
1276          * at least one bit that is guaranteed to
1277          * be zero so it is a good register to
1278          * use for this test.
1279          */
1280         hcntrl = ahc_inb(ahc, HCNTRL);
1281
1282         if (hcntrl == 0xFF)
1283                 goto fail;
1284
1285         if ((hcntrl & CHIPRST) != 0) {
1286                 /*
1287                  * The chip has not been initialized since
1288                  * PCI/EISA/VLB bus reset.  Don't trust
1289                  * "left over BIOS data".
1290                  */
1291                 ahc->flags |= AHC_NO_BIOS_INIT;
1292         }
1293
1294         /*
1295          * Next create a situation where write combining
1296          * or read prefetching could be initiated by the
1297          * CPU or host bridge.  Our device does not support
1298          * either, so look for data corruption and/or flagged
1299          * PCI errors.  First pause without causing another
1300          * chip reset.
1301          */
1302         hcntrl &= ~CHIPRST;
1303         ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1304         while (ahc_is_paused(ahc) == 0)
1305                 ;
1306
1307         /* Clear any PCI errors that occurred before our driver attached. */
1308         status1 = aic_pci_read_config(ahc->dev_softc,
1309                                       PCIR_STATUS + 1, /*bytes*/1);
1310         aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1311                              status1, /*bytes*/1);
1312         ahc_outb(ahc, CLRINT, CLRPARERR);
1313
1314         ahc_outb(ahc, SEQCTL, PERRORDIS);
1315         ahc_outb(ahc, SCBPTR, 0);
1316         ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1317         if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1318                 goto fail;
1319
1320         status1 = aic_pci_read_config(ahc->dev_softc,
1321                                       PCIR_STATUS + 1, /*bytes*/1);
1322         if ((status1 & STA) != 0)
1323                 goto fail;
1324
1325         error = 0;
1326
1327 fail:
1328         /* Silently clear any latched errors. */
1329         status1 = aic_pci_read_config(ahc->dev_softc,
1330                                       PCIR_STATUS + 1, /*bytes*/1);
1331         aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1332                              status1, /*bytes*/1);
1333         ahc_outb(ahc, CLRINT, CLRPARERR);
1334         ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1335         aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1336         return (error);
1337 }
1338
1339 /*
1340  * Check the external port logic for a serial eeprom
1341  * and termination/cable detection contrls.
1342  */
1343 static void
1344 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
1345 {
1346         struct  seeprom_descriptor sd;
1347         struct  seeprom_config *sc;
1348         int     have_seeprom;
1349         int     have_autoterm;
1350
1351         sd.sd_ahc = ahc;
1352         sd.sd_control_offset = SEECTL;
1353         sd.sd_status_offset = SEECTL;
1354         sd.sd_dataout_offset = SEECTL;
1355         sc = ahc->seep_config;
1356
1357         /*
1358          * For some multi-channel devices, the c46 is simply too
1359          * small to work.  For the other controller types, we can
1360          * get our information from either SEEPROM type.  Set the
1361          * type to start our probe with accordingly.
1362          */
1363         if (ahc->flags & AHC_LARGE_SEEPROM)
1364                 sd.sd_chip = C56_66;
1365         else
1366                 sd.sd_chip = C46;
1367
1368         sd.sd_MS = SEEMS;
1369         sd.sd_RDY = SEERDY;
1370         sd.sd_CS = SEECS;
1371         sd.sd_CK = SEECK;
1372         sd.sd_DO = SEEDO;
1373         sd.sd_DI = SEEDI;
1374
1375         have_seeprom = ahc_acquire_seeprom(ahc, &sd);
1376         if (have_seeprom) {
1377
1378                 if (bootverbose)
1379                         kprintf("%s: Reading SEEPROM...", ahc_name(ahc));
1380
1381                 for (;;) {
1382                         u_int start_addr;
1383
1384                         start_addr = 32 * (ahc->channel - 'A');
1385
1386                         have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
1387                                                         start_addr,
1388                                                         sizeof(*sc)/2);
1389
1390                         if (have_seeprom)
1391                                 have_seeprom = ahc_verify_cksum(sc);
1392
1393                         if (have_seeprom != 0 || sd.sd_chip == C56_66) {
1394                                 if (bootverbose) {
1395                                         if (have_seeprom == 0)
1396                                                 kprintf ("checksum error\n");
1397                                         else
1398                                                 kprintf ("done.\n");
1399                                 }
1400                                 break;
1401                         }
1402                         sd.sd_chip = C56_66;
1403                 }
1404                 ahc_release_seeprom(&sd);
1405
1406                 /* Remember the SEEPROM type for later */
1407                 if (sd.sd_chip == C56_66)
1408                         ahc->flags |= AHC_LARGE_SEEPROM;
1409         }
1410
1411         if (!have_seeprom) {
1412                 /*
1413                  * Pull scratch ram settings and treat them as
1414                  * if they are the contents of an seeprom if
1415                  * the 'ADPT' signature is found in SCB2.
1416                  * We manually compose the data as 16bit values
1417                  * to avoid endian issues.
1418                  */
1419                 ahc_outb(ahc, SCBPTR, 2);
1420                 if (ahc_inb(ahc, SCB_BASE) == 'A'
1421                  && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1422                  && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1423                  && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1424                         uint16_t *sc_data;
1425                         int       i;
1426
1427                         sc_data = (uint16_t *)sc;
1428                         for (i = 0; i < 32; i++, sc_data++) {
1429                                 int     j;
1430
1431                                 j = i * 2;
1432                                 *sc_data = ahc_inb(ahc, SRAM_BASE + j)
1433                                          | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
1434                         }
1435                         have_seeprom = ahc_verify_cksum(sc);
1436                         if (have_seeprom)
1437                                 ahc->flags |= AHC_SCB_CONFIG_USED;
1438                 }
1439                 /*
1440                  * Clear any SCB parity errors in case this data and
1441                  * its associated parity was not initialized by the BIOS
1442                  */
1443                 ahc_outb(ahc, CLRINT, CLRPARERR);
1444                 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1445         }
1446
1447         if (!have_seeprom) {
1448                 if (bootverbose)
1449                         kprintf("%s: No SEEPROM available.\n", ahc_name(ahc));
1450                 ahc->flags |= AHC_USEDEFAULTS;
1451                 kfree(ahc->seep_config, M_DEVBUF);
1452                 ahc->seep_config = NULL;
1453                 sc = NULL;
1454         } else {
1455                 ahc_parse_pci_eeprom(ahc, sc);
1456         }
1457
1458         /*
1459          * Cards that have the external logic necessary to talk to
1460          * a SEEPROM, are almost certain to have the remaining logic
1461          * necessary for auto-termination control.  This assumption
1462          * hasn't failed yet...
1463          */
1464         have_autoterm = have_seeprom;
1465
1466         /*
1467          * Some low-cost chips have SEEPROM and auto-term control built
1468          * in, instead of using a GAL.  They can tell us directly
1469          * if the termination logic is enabled.
1470          */
1471         if ((ahc->features & AHC_SPIOCAP) != 0) {
1472                 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
1473                         have_autoterm = FALSE;
1474         }
1475
1476         if (have_autoterm) {
1477                 ahc->flags |= AHC_HAS_TERM_LOGIC;
1478                 ahc_acquire_seeprom(ahc, &sd);
1479                 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
1480                 ahc_release_seeprom(&sd);
1481         } else if (have_seeprom) {
1482                 *sxfrctl1 &= ~STPWEN;
1483                 if ((sc->adapter_control & CFSTERM) != 0)
1484                         *sxfrctl1 |= STPWEN;
1485                 if (bootverbose)
1486                         kprintf("%s: Low byte termination %sabled\n",
1487                                ahc_name(ahc),
1488                                (*sxfrctl1 & STPWEN) ? "en" : "dis");
1489         }
1490 }
1491
1492 static void
1493 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
1494 {
1495         /*
1496          * Put the data we've collected down into SRAM
1497          * where ahc_init will find it.
1498          */
1499         int      i;
1500         int      max_targ = sc->max_targets & CFMAXTARG;
1501         u_int    scsi_conf;
1502         uint16_t discenable;
1503         uint16_t ultraenb;
1504
1505         discenable = 0;
1506         ultraenb = 0;
1507         if ((sc->adapter_control & CFULTRAEN) != 0) {
1508                 /*
1509                  * Determine if this adapter has a "newstyle"
1510                  * SEEPROM format.
1511                  */
1512                 for (i = 0; i < max_targ; i++) {
1513                         if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
1514                                 ahc->flags |= AHC_NEWEEPROM_FMT;
1515                                 break;
1516                         }
1517                 }
1518         }
1519
1520         for (i = 0; i < max_targ; i++) {
1521                 u_int     scsirate;
1522                 uint16_t target_mask;
1523
1524                 target_mask = 0x01 << i;
1525                 if (sc->device_flags[i] & CFDISC)
1526                         discenable |= target_mask;
1527                 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
1528                         if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
1529                                 ultraenb |= target_mask;
1530                 } else if ((sc->adapter_control & CFULTRAEN) != 0) {
1531                         ultraenb |= target_mask;
1532                 }
1533                 if ((sc->device_flags[i] & CFXFER) == 0x04
1534                  && (ultraenb & target_mask) != 0) {
1535                         /* Treat 10MHz as a non-ultra speed */
1536                         sc->device_flags[i] &= ~CFXFER;
1537                         ultraenb &= ~target_mask;
1538                 }
1539                 if ((ahc->features & AHC_ULTRA2) != 0) {
1540                         u_int offset;
1541
1542                         if (sc->device_flags[i] & CFSYNCH)
1543                                 offset = MAX_OFFSET_ULTRA2;
1544                         else
1545                                 offset = 0;
1546                         ahc_outb(ahc, TARG_OFFSET + i, offset);
1547
1548                         /*
1549                          * The ultra enable bits contain the
1550                          * high bit of the ultra2 sync rate
1551                          * field.
1552                          */
1553                         scsirate = (sc->device_flags[i] & CFXFER)
1554                                  | ((ultraenb & target_mask) ? 0x8 : 0x0);
1555                         if (sc->device_flags[i] & CFWIDEB)
1556                                 scsirate |= WIDEXFER;
1557                 } else {
1558                         scsirate = (sc->device_flags[i] & CFXFER) << 4;
1559                         if (sc->device_flags[i] & CFSYNCH)
1560                                 scsirate |= SOFS;
1561                         if (sc->device_flags[i] & CFWIDEB)
1562                                 scsirate |= WIDEXFER;
1563                 }
1564                 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
1565         }
1566         ahc->our_id = sc->brtime_id & CFSCSIID;
1567
1568         scsi_conf = (ahc->our_id & 0x7);
1569         if (sc->adapter_control & CFSPARITY)
1570                 scsi_conf |= ENSPCHK;
1571         if (sc->adapter_control & CFRESETB)
1572                 scsi_conf |= RESET_SCSI;
1573
1574         ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
1575
1576         if (sc->bios_control & CFEXTEND)
1577                 ahc->flags |= AHC_EXTENDED_TRANS_A;
1578
1579         if (sc->bios_control & CFBIOSEN)
1580                 ahc->flags |= AHC_BIOS_ENABLED;
1581         if (ahc->features & AHC_ULTRA
1582          && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1583                 /* Should we enable Ultra mode? */
1584                 if (!(sc->adapter_control & CFULTRAEN))
1585                         /* Treat us as a non-ultra card */
1586                         ultraenb = 0;
1587         }
1588
1589         if (sc->signature == CFSIGNATURE
1590          || sc->signature == CFSIGNATURE2) {
1591                 uint32_t devconfig;
1592
1593                 /* Honor the STPWLEVEL settings */
1594                 devconfig = aic_pci_read_config(ahc->dev_softc,
1595                                                 DEVCONFIG, /*bytes*/4);
1596                 devconfig &= ~STPWLEVEL;
1597                 if ((sc->bios_control & CFSTPWLEVEL) != 0)
1598                         devconfig |= STPWLEVEL;
1599                 aic_pci_write_config(ahc->dev_softc, DEVCONFIG,
1600                                      devconfig, /*bytes*/4);
1601         }
1602         /* Set SCSICONF info */
1603         ahc_outb(ahc, SCSICONF, scsi_conf);
1604         ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
1605         ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
1606         ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
1607         ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
1608 }
1609
1610 static void
1611 configure_termination(struct ahc_softc *ahc,
1612                       struct seeprom_descriptor *sd,
1613                       u_int adapter_control,
1614                       u_int *sxfrctl1)
1615 {
1616         uint8_t brddat;
1617
1618         brddat = 0;
1619
1620         /*
1621          * Update the settings in sxfrctl1 to match the
1622          * termination settings
1623          */
1624         *sxfrctl1 = 0;
1625
1626         /*
1627          * SEECS must be on for the GALS to latch
1628          * the data properly.  Be sure to leave MS
1629          * on or we will release the seeprom.
1630          */
1631         SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
1632         if ((adapter_control & CFAUTOTERM) != 0
1633          || (ahc->features & AHC_NEW_TERMCTL) != 0) {
1634                 int internal50_present;
1635                 int internal68_present;
1636                 int externalcable_present;
1637                 int eeprom_present;
1638                 int enableSEC_low;
1639                 int enableSEC_high;
1640                 int enablePRI_low;
1641                 int enablePRI_high;
1642                 int sum;
1643
1644                 enableSEC_low = 0;
1645                 enableSEC_high = 0;
1646                 enablePRI_low = 0;
1647                 enablePRI_high = 0;
1648                 if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
1649                         ahc_new_term_detect(ahc, &enableSEC_low,
1650                                             &enableSEC_high,
1651                                             &enablePRI_low,
1652                                             &enablePRI_high,
1653                                             &eeprom_present);
1654                         if ((adapter_control & CFSEAUTOTERM) == 0) {
1655                                 if (bootverbose)
1656                                         kprintf("%s: Manual SE Termination\n",
1657                                                ahc_name(ahc));
1658                                 enableSEC_low = (adapter_control & CFSELOWTERM);
1659                                 enableSEC_high =
1660                                     (adapter_control & CFSEHIGHTERM);
1661                         }
1662                         if ((adapter_control & CFAUTOTERM) == 0) {
1663                                 if (bootverbose)
1664                                         kprintf("%s: Manual LVD Termination\n",
1665                                                ahc_name(ahc));
1666                                 enablePRI_low = (adapter_control & CFSTERM);
1667                                 enablePRI_high = (adapter_control & CFWSTERM);
1668                         }
1669                         /* Make the table calculations below happy */
1670                         internal50_present = 0;
1671                         internal68_present = 1;
1672                         externalcable_present = 1;
1673                 } else if ((ahc->features & AHC_SPIOCAP) != 0) {
1674                         aic785X_cable_detect(ahc, &internal50_present,
1675                                              &externalcable_present,
1676                                              &eeprom_present);
1677                         /* Can never support a wide connector. */
1678                         internal68_present = 0;
1679                 } else {
1680                         aic787X_cable_detect(ahc, &internal50_present,
1681                                              &internal68_present,
1682                                              &externalcable_present,
1683                                              &eeprom_present);
1684                 }
1685
1686                 if ((ahc->features & AHC_WIDE) == 0)
1687                         internal68_present = 0;
1688
1689                 if (bootverbose
1690                  && (ahc->features & AHC_ULTRA2) == 0) {
1691                         kprintf("%s: internal 50 cable %s present",
1692                                ahc_name(ahc),
1693                                internal50_present ? "is":"not");
1694
1695                         if ((ahc->features & AHC_WIDE) != 0)
1696                                 kprintf(", internal 68 cable %s present",
1697                                        internal68_present ? "is":"not");
1698                         kprintf("\n%s: external cable %s present\n",
1699                                ahc_name(ahc),
1700                                externalcable_present ? "is":"not");
1701                 }
1702                 if (bootverbose)
1703                         kprintf("%s: BIOS eeprom %s present\n",
1704                                ahc_name(ahc), eeprom_present ? "is" : "not");
1705
1706                 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) {
1707                         /*
1708                          * The 50 pin connector is a separate bus,
1709                          * so force it to always be terminated.
1710                          * In the future, perform current sensing
1711                          * to determine if we are in the middle of
1712                          * a properly terminated bus.
1713                          */
1714                         internal50_present = 0;
1715                 }
1716
1717                 /*
1718                  * Now set the termination based on what
1719                  * we found.
1720                  * Flash Enable = BRDDAT7
1721                  * Secondary High Term Enable = BRDDAT6
1722                  * Secondary Low Term Enable = BRDDAT5 (7890)
1723                  * Primary High Term Enable = BRDDAT4 (7890)
1724                  */
1725                 if ((ahc->features & AHC_ULTRA2) == 0
1726                  && (internal50_present != 0)
1727                  && (internal68_present != 0)
1728                  && (externalcable_present != 0)) {
1729                         kprintf("%s: Illegal cable configuration!!. "
1730                                "Only two connectors on the "
1731                                "adapter may be used at a "
1732                                "time!\n", ahc_name(ahc));
1733
1734                         /*
1735                          * Pretend there are no cables in the hope
1736                          * that having all of the termination on
1737                          * gives us a more stable bus.
1738                          */
1739                         internal50_present = 0;
1740                         internal68_present = 0;
1741                         externalcable_present = 0;
1742                 }
1743
1744                 if ((ahc->features & AHC_WIDE) != 0
1745                  && ((externalcable_present == 0)
1746                   || (internal68_present == 0)
1747                   || (enableSEC_high != 0))) {
1748                         brddat |= BRDDAT6;
1749                         if (bootverbose) {
1750                                 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1751                                         kprintf("%s: 68 pin termination "
1752                                                "Enabled\n", ahc_name(ahc));
1753                                 else
1754                                         kprintf("%s: %sHigh byte termination "
1755                                                "Enabled\n", ahc_name(ahc),
1756                                                enableSEC_high ? "Secondary "
1757                                                               : "");
1758                         }
1759                 }
1760
1761                 sum = internal50_present + internal68_present
1762                     + externalcable_present;
1763                 if (sum < 2 || (enableSEC_low != 0)) {
1764                         if ((ahc->features & AHC_ULTRA2) != 0)
1765                                 brddat |= BRDDAT5;
1766                         else
1767                                 *sxfrctl1 |= STPWEN;
1768                         if (bootverbose) {
1769                                 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1770                                         kprintf("%s: 50 pin termination "
1771                                                "Enabled\n", ahc_name(ahc));
1772                                 else
1773                                         kprintf("%s: %sLow byte termination "
1774                                                "Enabled\n", ahc_name(ahc),
1775                                                enableSEC_low ? "Secondary "
1776                                                              : "");
1777                         }
1778                 }
1779
1780                 if (enablePRI_low != 0) {
1781                         *sxfrctl1 |= STPWEN;
1782                         if (bootverbose)
1783                                 kprintf("%s: Primary Low Byte termination "
1784                                        "Enabled\n", ahc_name(ahc));
1785                 }
1786
1787                 /*
1788                  * Setup STPWEN before setting up the rest of
1789                  * the termination per the tech note on the U160 cards.
1790                  */
1791                 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1792
1793                 if (enablePRI_high != 0) {
1794                         brddat |= BRDDAT4;
1795                         if (bootverbose)
1796                                 kprintf("%s: Primary High Byte "
1797                                        "termination Enabled\n",
1798                                        ahc_name(ahc));
1799                 }
1800
1801                 write_brdctl(ahc, brddat);
1802
1803         } else {
1804                 if ((adapter_control & CFSTERM) != 0) {
1805                         *sxfrctl1 |= STPWEN;
1806
1807                         if (bootverbose)
1808                                 kprintf("%s: %sLow byte termination Enabled\n",
1809                                        ahc_name(ahc),
1810                                        (ahc->features & AHC_ULTRA2) ? "Primary "
1811                                                                     : "");
1812                 }
1813
1814                 if ((adapter_control & CFWSTERM) != 0
1815                  && (ahc->features & AHC_WIDE) != 0) {
1816                         brddat |= BRDDAT6;
1817                         if (bootverbose)
1818                                 kprintf("%s: %sHigh byte termination Enabled\n",
1819                                        ahc_name(ahc),
1820                                        (ahc->features & AHC_ULTRA2)
1821                                      ? "Secondary " : "");
1822                 }
1823
1824                 /*
1825                  * Setup STPWEN before setting up the rest of
1826                  * the termination per the tech note on the U160 cards.
1827                  */
1828                 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1829
1830                 if ((ahc->features & AHC_WIDE) != 0)
1831                         write_brdctl(ahc, brddat);
1832         }
1833         SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
1834 }
1835
1836 static void
1837 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
1838                     int *enableSEC_high, int *enablePRI_low,
1839                     int *enablePRI_high, int *eeprom_present)
1840 {
1841         uint8_t brdctl;
1842
1843         /*
1844          * BRDDAT7 = Eeprom
1845          * BRDDAT6 = Enable Secondary High Byte termination
1846          * BRDDAT5 = Enable Secondary Low Byte termination
1847          * BRDDAT4 = Enable Primary high byte termination
1848          * BRDDAT3 = Enable Primary low byte termination
1849          */
1850         brdctl = read_brdctl(ahc);
1851         *eeprom_present = brdctl & BRDDAT7;
1852         *enableSEC_high = (brdctl & BRDDAT6);
1853         *enableSEC_low = (brdctl & BRDDAT5);
1854         *enablePRI_high = (brdctl & BRDDAT4);
1855         *enablePRI_low = (brdctl & BRDDAT3);
1856 }
1857
1858 static void
1859 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1860                      int *internal68_present, int *externalcable_present,
1861                      int *eeprom_present)
1862 {
1863         uint8_t brdctl;
1864
1865         /*
1866          * First read the status of our cables.
1867          * Set the rom bank to 0 since the
1868          * bank setting serves as a multiplexor
1869          * for the cable detection logic.
1870          * BRDDAT5 controls the bank switch.
1871          */
1872         write_brdctl(ahc, 0);
1873
1874         /*
1875          * Now read the state of the internal
1876          * connectors.  BRDDAT6 is INT50 and
1877          * BRDDAT7 is INT68.
1878          */
1879         brdctl = read_brdctl(ahc);
1880         *internal50_present = (brdctl & BRDDAT6) ? 0 : 1;
1881         *internal68_present = (brdctl & BRDDAT7) ? 0 : 1;
1882
1883         /*
1884          * Set the rom bank to 1 and determine
1885          * the other signals.
1886          */
1887         write_brdctl(ahc, BRDDAT5);
1888
1889         /*
1890          * Now read the state of the external
1891          * connectors.  BRDDAT6 is EXT68 and
1892          * BRDDAT7 is EPROMPS.
1893          */
1894         brdctl = read_brdctl(ahc);
1895         *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1896         *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0;
1897 }
1898
1899 static void
1900 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1901                      int *externalcable_present, int *eeprom_present)
1902 {
1903         uint8_t brdctl;
1904         uint8_t spiocap;
1905
1906         spiocap = ahc_inb(ahc, SPIOCAP);
1907         spiocap &= ~SOFTCMDEN;
1908         spiocap |= EXT_BRDCTL;
1909         ahc_outb(ahc, SPIOCAP, spiocap);
1910         ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
1911         ahc_flush_device_writes(ahc);
1912         aic_delay(500);
1913         ahc_outb(ahc, BRDCTL, 0);
1914         ahc_flush_device_writes(ahc);
1915         aic_delay(500);
1916         brdctl = ahc_inb(ahc, BRDCTL);
1917         *internal50_present = (brdctl & BRDDAT5) ? 0 : 1;
1918         *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1919         *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0;
1920 }
1921
1922 int
1923 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
1924 {
1925         int wait;
1926
1927         if ((ahc->features & AHC_SPIOCAP) != 0
1928          && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
1929                 return (0);
1930
1931         /*
1932          * Request access of the memory port.  When access is
1933          * granted, SEERDY will go high.  We use a 1 second
1934          * timeout which should be near 1 second more than
1935          * is needed.  Reason: after the chip reset, there
1936          * should be no contention.
1937          */
1938         SEEPROM_OUTB(sd, sd->sd_MS);
1939         wait = 1000;  /* 1 second timeout in msec */
1940         while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
1941                 aic_delay(1000);  /* delay 1 msec */
1942         }
1943         if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
1944                 SEEPROM_OUTB(sd, 0);
1945                 return (0);
1946         }
1947         return(1);
1948 }
1949
1950 void
1951 ahc_release_seeprom(struct seeprom_descriptor *sd)
1952 {
1953         /* Release access to the memory port and the serial EEPROM. */
1954         SEEPROM_OUTB(sd, 0);
1955 }
1956
1957 static void
1958 write_brdctl(struct ahc_softc *ahc, uint8_t value)
1959 {
1960         uint8_t brdctl;
1961
1962         if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1963                 brdctl = BRDSTB;
1964                 if (ahc->channel == 'B')
1965                         brdctl |= BRDCS;
1966         } else if ((ahc->features & AHC_ULTRA2) != 0) {
1967                 brdctl = 0;
1968         } else {
1969                 brdctl = BRDSTB|BRDCS;
1970         }
1971         ahc_outb(ahc, BRDCTL, brdctl);
1972         ahc_flush_device_writes(ahc);
1973         brdctl |= value;
1974         ahc_outb(ahc, BRDCTL, brdctl);
1975         ahc_flush_device_writes(ahc);
1976         if ((ahc->features & AHC_ULTRA2) != 0)
1977                 brdctl |= BRDSTB_ULTRA2;
1978         else
1979                 brdctl &= ~BRDSTB;
1980         ahc_outb(ahc, BRDCTL, brdctl);
1981         ahc_flush_device_writes(ahc);
1982         if ((ahc->features & AHC_ULTRA2) != 0)
1983                 brdctl = 0;
1984         else
1985                 brdctl &= ~BRDCS;
1986         ahc_outb(ahc, BRDCTL, brdctl);
1987 }
1988
1989 static uint8_t
1990 read_brdctl(struct ahc_softc *ahc)
1991 {
1992         uint8_t brdctl;
1993         uint8_t value;
1994
1995         if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1996                 brdctl = BRDRW;
1997                 if (ahc->channel == 'B')
1998                         brdctl |= BRDCS;
1999         } else if ((ahc->features & AHC_ULTRA2) != 0) {
2000                 brdctl = BRDRW_ULTRA2;
2001         } else {
2002                 brdctl = BRDRW|BRDCS;
2003         }
2004         ahc_outb(ahc, BRDCTL, brdctl);
2005         ahc_flush_device_writes(ahc);
2006         value = ahc_inb(ahc, BRDCTL);
2007         ahc_outb(ahc, BRDCTL, 0);
2008         return (value);
2009 }
2010
2011 static void
2012 ahc_pci_intr(struct ahc_softc *ahc)
2013 {
2014         u_int error;
2015         u_int status1;
2016
2017         error = ahc_inb(ahc, ERROR);
2018         if ((error & PCIERRSTAT) == 0)
2019                 return;
2020
2021         status1 = aic_pci_read_config(ahc->dev_softc,
2022                                       PCIR_STATUS + 1, /*bytes*/1);
2023
2024         if ((status1 & ~DPE) != 0
2025          || (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2026                 kprintf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
2027                        ahc_name(ahc),
2028                        ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
2029         }
2030
2031         if (status1 & DPE
2032          && (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2033                 ahc->pci_target_perr_count++;
2034                 kprintf("%s: Data Parity Error Detected during address "
2035                        "or write data phase\n", ahc_name(ahc));
2036         }
2037         if (status1 & SSE) {
2038                 kprintf("%s: Signal System Error Detected\n", ahc_name(ahc));
2039         }
2040         if (status1 & RMA) {
2041                 kprintf("%s: Received a Master Abort\n", ahc_name(ahc));
2042         }
2043         if (status1 & RTA) {
2044                 kprintf("%s: Received a Target Abort\n", ahc_name(ahc));
2045         }
2046         if (status1 & STA) {
2047                 kprintf("%s: Signaled a Target Abort\n", ahc_name(ahc));
2048         }
2049         if (status1 & DPR) {
2050                 kprintf("%s: Data Parity Error has been reported via PERR#\n",
2051                        ahc_name(ahc));
2052         }
2053
2054         /* Clear latched errors. */
2055         aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
2056                              status1, /*bytes*/1);
2057
2058         if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
2059                 kprintf("%s: Latched PCIERR interrupt with "
2060                        "no status bits set\n", ahc_name(ahc));
2061         } else {
2062                 ahc_outb(ahc, CLRINT, CLRPARERR);
2063         }
2064
2065         if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH
2066          && (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2067                 kprintf(
2068 "%s: WARNING WARNING WARNING WARNING\n"
2069 "%s: Too many PCI parity errors observed as a target.\n"
2070 "%s: Some device on this PCI bus is generating bad parity.\n"
2071 "%s: This is an error *observed by*, not *generated by*, %s.\n"
2072 "%s: PCI parity error checking has been disabled.\n"
2073 "%s: WARNING WARNING WARNING WARNING\n",
2074                        ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2075                        ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2076                        ahc_name(ahc));
2077                 ahc->seqctl |= FAILDIS;
2078                 ahc->flags |= AHC_DISABLE_PCI_PERR;
2079                 ahc_outb(ahc, SEQCTL, ahc->seqctl);
2080         }
2081         ahc_unpause(ahc);
2082 }
2083
2084 static int
2085 ahc_pci_chip_init(struct ahc_softc *ahc)
2086 {
2087         ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
2088         ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
2089         if ((ahc->features & AHC_DT) != 0) {
2090                 u_int sfunct;
2091
2092                 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
2093                 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
2094                 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
2095                 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
2096                 ahc_outb(ahc, SFUNCT, sfunct);
2097                 ahc_outb(ahc, CRCCONTROL1,
2098                          ahc->bus_softc.pci_softc.crccontrol1);
2099         }
2100         if ((ahc->features & AHC_MULTI_FUNC) != 0)
2101                 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
2102
2103         if ((ahc->features & AHC_ULTRA2) != 0)
2104                 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
2105
2106         return (ahc_chip_init(ahc));
2107 }
2108
2109 static int
2110 ahc_pci_suspend(struct ahc_softc *ahc)
2111 {
2112         return (ahc_suspend(ahc));
2113 }
2114
2115 static int
2116 ahc_pci_resume(struct ahc_softc *ahc)
2117 {
2118
2119         aic_power_state_change(ahc, AIC_POWER_STATE_D0);
2120
2121         /*
2122          * We assume that the OS has restored our register
2123          * mappings, etc.  Just update the config space registers
2124          * that the OS doesn't know about and rely on our chip
2125          * reset handler to handle the rest.
2126          */
2127         aic_pci_write_config(ahc->dev_softc, DEVCONFIG,
2128                              ahc->bus_softc.pci_softc.devconfig, /*bytes*/4);
2129         aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
2130                              ahc->bus_softc.pci_softc.command, /*bytes*/1);
2131         aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
2132                              ahc->bus_softc.pci_softc.csize_lattime,
2133                              /*bytes*/1);
2134         if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
2135                 struct  seeprom_descriptor sd;
2136                 u_int   sxfrctl1;
2137
2138                 sd.sd_ahc = ahc;
2139                 sd.sd_control_offset = SEECTL;
2140                 sd.sd_status_offset = SEECTL;
2141                 sd.sd_dataout_offset = SEECTL;
2142
2143                 ahc_acquire_seeprom(ahc, &sd);
2144                 configure_termination(ahc, &sd,
2145                                       ahc->seep_config->adapter_control,
2146                                       &sxfrctl1);
2147                 ahc_release_seeprom(&sd);
2148         }
2149         return (ahc_resume(ahc));
2150 }
2151
2152 static int
2153 ahc_aic785X_setup(struct ahc_softc *ahc)
2154 {
2155         aic_dev_softc_t pci;
2156         uint8_t rev;
2157
2158         pci = ahc->dev_softc;
2159         ahc->channel = 'A';
2160         ahc->chip = AHC_AIC7850;
2161         ahc->features = AHC_AIC7850_FE;
2162         ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2163         rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2164         if (rev >= 1)
2165                 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2166         ahc->instruction_ram_size = 512;
2167         return (0);
2168 }
2169
2170 static int
2171 ahc_aic7860_setup(struct ahc_softc *ahc)
2172 {
2173         aic_dev_softc_t pci;
2174         uint8_t rev;
2175
2176         pci = ahc->dev_softc;
2177         ahc->channel = 'A';
2178         ahc->chip = AHC_AIC7860;
2179         ahc->features = AHC_AIC7860_FE;
2180         ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2181         rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2182         if (rev >= 1)
2183                 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2184         ahc->instruction_ram_size = 512;
2185         return (0);
2186 }
2187
2188 static int
2189 ahc_apa1480_setup(struct ahc_softc *ahc)
2190 {
2191         int error;
2192
2193         error = ahc_aic7860_setup(ahc);
2194         if (error != 0)
2195                 return (error);
2196         ahc->features |= AHC_REMOVABLE;
2197         return (0);
2198 }
2199
2200 static int
2201 ahc_aic7870_setup(struct ahc_softc *ahc)
2202 {
2203
2204         ahc->channel = 'A';
2205         ahc->chip = AHC_AIC7870;
2206         ahc->features = AHC_AIC7870_FE;
2207         ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2208         ahc->instruction_ram_size = 512;
2209         return (0);
2210 }
2211
2212 static int
2213 ahc_aha394X_setup(struct ahc_softc *ahc)
2214 {
2215         int error;
2216
2217         error = ahc_aic7870_setup(ahc);
2218         if (error == 0)
2219                 error = ahc_aha394XX_setup(ahc);
2220         return (error);
2221 }
2222
2223 static int
2224 ahc_aha398X_setup(struct ahc_softc *ahc)
2225 {
2226         int error;
2227
2228         error = ahc_aic7870_setup(ahc);
2229         if (error == 0)
2230                 error = ahc_aha398XX_setup(ahc);
2231         return (error);
2232 }
2233
2234 static int
2235 ahc_aha494X_setup(struct ahc_softc *ahc)
2236 {
2237         int error;
2238
2239         error = ahc_aic7870_setup(ahc);
2240         if (error == 0)
2241                 error = ahc_aha494XX_setup(ahc);
2242         return (error);
2243 }
2244
2245 static int
2246 ahc_aic7880_setup(struct ahc_softc *ahc)
2247 {
2248         aic_dev_softc_t pci;
2249         uint8_t rev;
2250
2251         pci = ahc->dev_softc;
2252         ahc->channel = 'A';
2253         ahc->chip = AHC_AIC7880;
2254         ahc->features = AHC_AIC7880_FE;
2255         ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
2256         rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2257         if (rev >= 1) {
2258                 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2259         } else {
2260                 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2261         }
2262         ahc->instruction_ram_size = 512;
2263         return (0);
2264 }
2265
2266 static int
2267 ahc_aha2940Pro_setup(struct ahc_softc *ahc)
2268 {
2269
2270         ahc->flags |= AHC_INT50_SPEEDFLEX;
2271         return (ahc_aic7880_setup(ahc));
2272 }
2273
2274 static int
2275 ahc_aha394XU_setup(struct ahc_softc *ahc)
2276 {
2277         int error;
2278
2279         error = ahc_aic7880_setup(ahc);
2280         if (error == 0)
2281                 error = ahc_aha394XX_setup(ahc);
2282         return (error);
2283 }
2284
2285 static int
2286 ahc_aha398XU_setup(struct ahc_softc *ahc)
2287 {
2288         int error;
2289
2290         error = ahc_aic7880_setup(ahc);
2291         if (error == 0)
2292                 error = ahc_aha398XX_setup(ahc);
2293         return (error);
2294 }
2295
2296 static int
2297 ahc_aic7890_setup(struct ahc_softc *ahc)
2298 {
2299         aic_dev_softc_t pci;
2300         uint8_t rev;
2301
2302         pci = ahc->dev_softc;
2303         ahc->channel = 'A';
2304         ahc->chip = AHC_AIC7890;
2305         ahc->features = AHC_AIC7890_FE;
2306         ahc->flags |= AHC_NEWEEPROM_FMT;
2307         rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2308         if (rev == 0)
2309                 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
2310         ahc->instruction_ram_size = 768;
2311         return (0);
2312 }
2313
2314 static int
2315 ahc_aic7892_setup(struct ahc_softc *ahc)
2316 {
2317
2318         ahc->channel = 'A';
2319         ahc->chip = AHC_AIC7892;
2320         ahc->features = AHC_AIC7892_FE;
2321         ahc->flags |= AHC_NEWEEPROM_FMT;
2322         ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2323         ahc->instruction_ram_size = 1024;
2324         return (0);
2325 }
2326
2327 static int
2328 ahc_aic7895_setup(struct ahc_softc *ahc)
2329 {
2330         aic_dev_softc_t pci;
2331         uint8_t rev;
2332
2333         pci = ahc->dev_softc;
2334         ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2335         /*
2336          * The 'C' revision of the aic7895 has a few additional features.
2337          */
2338         rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2339         if (rev >= 4) {
2340                 ahc->chip = AHC_AIC7895C;
2341                 ahc->features = AHC_AIC7895C_FE;
2342         } else  {
2343                 u_int command;
2344
2345                 ahc->chip = AHC_AIC7895;
2346                 ahc->features = AHC_AIC7895_FE;
2347
2348                 /*
2349                  * The BIOS disables the use of MWI transactions
2350                  * since it does not have the MWI bug work around
2351                  * we have.  Disabling MWI reduces performance, so
2352                  * turn it on again.
2353                  */
2354                 command = aic_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
2355                 command |= PCIM_CMD_MWRICEN;
2356                 aic_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
2357                 ahc->bugs |= AHC_PCI_MWI_BUG;
2358         }
2359         /*
2360          * XXX Does CACHETHEN really not work???  What about PCI retry?
2361          * on C level chips.  Need to test, but for now, play it safe.
2362          */
2363         ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
2364                   |  AHC_CACHETHEN_BUG;
2365
2366 #if 0
2367         uint32_t devconfig;
2368
2369         /*
2370          * Cachesize must also be zero due to stray DAC
2371          * problem when sitting behind some bridges.
2372          */
2373         aic_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1);
2374         devconfig = aic_pci_read_config(pci, DEVCONFIG, /*bytes*/1);
2375         devconfig |= MRDCEN;
2376         aic_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1);
2377 #endif
2378         ahc->flags |= AHC_NEWEEPROM_FMT;
2379         ahc->instruction_ram_size = 512;
2380         return (0);
2381 }
2382
2383 static int
2384 ahc_aic7896_setup(struct ahc_softc *ahc)
2385 {
2386         aic_dev_softc_t pci;
2387
2388         pci = ahc->dev_softc;
2389         ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2390         ahc->chip = AHC_AIC7896;
2391         ahc->features = AHC_AIC7896_FE;
2392         ahc->flags |= AHC_NEWEEPROM_FMT;
2393         ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
2394         ahc->instruction_ram_size = 768;
2395         return (0);
2396 }
2397
2398 static int
2399 ahc_aic7899_setup(struct ahc_softc *ahc)
2400 {
2401         aic_dev_softc_t pci;
2402
2403         pci = ahc->dev_softc;
2404         ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2405         ahc->chip = AHC_AIC7899;
2406         ahc->features = AHC_AIC7899_FE;
2407         ahc->flags |= AHC_NEWEEPROM_FMT;
2408         ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2409         ahc->instruction_ram_size = 1024;
2410         return (0);
2411 }
2412
2413 static int
2414 ahc_aha29160C_setup(struct ahc_softc *ahc)
2415 {
2416         int error;
2417
2418         error = ahc_aic7899_setup(ahc);
2419         if (error != 0)
2420                 return (error);
2421         ahc->features |= AHC_REMOVABLE;
2422         return (0);
2423 }
2424
2425 static int
2426 ahc_raid_setup(struct ahc_softc *ahc)
2427 {
2428         kprintf("RAID functionality unsupported\n");
2429         return (ENXIO);
2430 }
2431
2432 static int
2433 ahc_aha394XX_setup(struct ahc_softc *ahc)
2434 {
2435         aic_dev_softc_t pci;
2436
2437         pci = ahc->dev_softc;
2438         switch (aic_get_pci_slot(pci)) {
2439         case AHC_394X_SLOT_CHANNEL_A:
2440                 ahc->channel = 'A';
2441                 break;
2442         case AHC_394X_SLOT_CHANNEL_B:
2443                 ahc->channel = 'B';
2444                 break;
2445         default:
2446                 kprintf("adapter at unexpected slot %d\n"
2447                        "unable to map to a channel\n",
2448                        aic_get_pci_slot(pci));
2449                 ahc->channel = 'A';
2450         }
2451         return (0);
2452 }
2453
2454 static int
2455 ahc_aha398XX_setup(struct ahc_softc *ahc)
2456 {
2457         aic_dev_softc_t pci;
2458
2459         pci = ahc->dev_softc;
2460         switch (aic_get_pci_slot(pci)) {
2461         case AHC_398X_SLOT_CHANNEL_A:
2462                 ahc->channel = 'A';
2463                 break;
2464         case AHC_398X_SLOT_CHANNEL_B:
2465                 ahc->channel = 'B';
2466                 break;
2467         case AHC_398X_SLOT_CHANNEL_C:
2468                 ahc->channel = 'C';
2469                 break;
2470         default:
2471                 kprintf("adapter at unexpected slot %d\n"
2472                        "unable to map to a channel\n",
2473                        aic_get_pci_slot(pci));
2474                 ahc->channel = 'A';
2475                 break;
2476         }
2477         ahc->flags |= AHC_LARGE_SEEPROM;
2478         return (0);
2479 }
2480
2481 static int
2482 ahc_aha494XX_setup(struct ahc_softc *ahc)
2483 {
2484         aic_dev_softc_t pci;
2485
2486         pci = ahc->dev_softc;
2487         switch (aic_get_pci_slot(pci)) {
2488         case AHC_494X_SLOT_CHANNEL_A:
2489                 ahc->channel = 'A';
2490                 break;
2491         case AHC_494X_SLOT_CHANNEL_B:
2492                 ahc->channel = 'B';
2493                 break;
2494         case AHC_494X_SLOT_CHANNEL_C:
2495                 ahc->channel = 'C';
2496                 break;
2497         case AHC_494X_SLOT_CHANNEL_D:
2498                 ahc->channel = 'D';
2499                 break;
2500         default:
2501                 kprintf("adapter at unexpected slot %d\n"
2502                        "unable to map to a channel\n",
2503                        aic_get_pci_slot(pci));
2504                 ahc->channel = 'A';
2505         }
2506         ahc->flags |= AHC_LARGE_SEEPROM;
2507         return (0);
2508 }