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38 * EMX_TXD: Maximum number of Transmit Descriptors
39 * Valid Range: 256-4096 for others
41 * This value is the number of transmit descriptors allocated by the driver.
42 * Increasing this value allows the driver to queue more transmits. Each
43 * descriptor is 16 bytes.
44 * Since TDLEN should be multiple of 128bytes, the number of transmit
45 * desscriptors should meet the following condition.
46 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
48 #define EMX_MIN_TXD 256
49 #define EMX_MAX_TXD 4096
50 #define EMX_DEFAULT_TXD 512
53 * EMX_RXD - Maximum number of receive Descriptors
54 * Valid Range: 256-4096 for others
56 * This value is the number of receive descriptors allocated by the driver.
57 * Increasing this value allows the driver to buffer more incoming packets.
58 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
59 * descriptor. The maximum MTU size is 16110.
60 * Since TDLEN should be multiple of 128bytes, the number of transmit
61 * desscriptors should meet the following condition.
62 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
64 #define EMX_MIN_RXD 256
65 #define EMX_MAX_RXD 4096
66 #define EMX_DEFAULT_RXD 512
69 * Receive Interrupt Delay Timer (Packet Timer)
72 * RDTR and RADV are deprecated; use ITR instead. They are only used to
73 * workaround hardware bug on certain 82573 based NICs.
75 #define EMX_RDTR_82573 32
78 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
81 * RDTR and RADV are deprecated; use ITR instead. They are only used to
82 * workaround hardware bug on certain 82573 based NICs.
84 #define EMX_RADV_82573 64
87 * This parameter controls the duration of transmit watchdog timer.
89 #define EMX_TX_TIMEOUT 5
91 /* One for TX csum offloading desc, the other is reserved */
92 #define EMX_TX_RESERVED 2
94 /* Large enough for 16K jumbo frame */
95 #define EMX_TX_SPARE 8
97 #define EMX_TX_OACTIVE_MAX 64
99 /* Interrupt throttle rate */
100 #define EMX_DEFAULT_ITR 10000
103 * This parameter controls whether or not autonegotation is enabled.
104 * 0 - Disable autonegotiation
105 * 1 - Enable autonegotiation
107 #define EMX_DO_AUTO_NEG 1
109 /* Tunables -- End */
111 #define EMX_AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | \
112 ADVERTISE_10_FULL | \
113 ADVERTISE_100_HALF | \
114 ADVERTISE_100_FULL | \
117 #define EMX_AUTO_ALL_MODES 0
119 /* PHY master/slave setting */
120 #define EMX_MASTER_SLAVE e1000_ms_hw_default
123 * Micellaneous constants
125 #define EMX_VENDOR_ID 0x8086
127 #define EMX_BAR_MEM PCIR_BAR(0)
129 #define EMX_JUMBO_PBA 0x00000028
130 #define EMX_DEFAULT_PBA 0x00000030
131 #define EMX_SMARTSPEED_DOWNSHIFT 3
132 #define EMX_SMARTSPEED_MAX 15
133 #define EMX_MAX_INTR 10
135 #define EMX_MCAST_ADDR_MAX 128
136 #define EMX_FC_PAUSE_TIME 1000
137 #define EMX_EEPROM_APME 0x400;
140 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
141 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
142 * also optimize cache line size effect. H/W supports up to cache line size 128.
144 #define EMX_DBA_ALIGN 128
147 * Speed mode bit in TARC0/TARC1.
148 * 82571EB/82572EI only, used to improve small packet transmit performance.
150 #define EMX_TARC_SPEED_MODE (1 << 21)
152 #define EMX_MAX_SCATTER 64
153 #define EMX_TSO_SIZE (65535 + \
154 sizeof(struct ether_vlan_header))
155 #define EMX_MAX_SEGSIZE 4096
156 #define EMX_MSIX_MASK 0x01F00000 /* For 82574 use */
158 #define EMX_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
159 #define EMX_IPVHL_SIZE 1 /* sizeof(ip.ip_vhl) */
160 #define EMX_TXCSUM_MINHL (ETHER_HDR_LEN + EVL_ENCAPLEN + \
164 * 82574 has a nonstandard address for EIAC
165 * and since its only used in MSIX, and in
166 * the em driver only 82574 uses MSIX we can
167 * solve it just using this define.
169 #define EMX_EIAC 0x000DC
171 #define EMX_NRSSRK 10
174 #define EMX_NRX_RING 2
176 typedef union e1000_rx_desc_extended emx_rxdesc_t;
178 #define rxd_bufaddr read.buffer_addr /* 64bits */
179 #define rxd_length wb.upper.length /* 16bits */
180 #define rxd_vlan wb.upper.vlan /* 16bits */
181 #define rxd_staterr wb.upper.status_error /* 32bits */
182 #define rxd_mrq wb.lower.mrq /* 32bits */
183 #define rxd_rss wb.lower.hi_dword.rss /* 32bits */
187 * Receive definitions
189 * we have an array of num_rx_desc rx_desc (handled by the
190 * controller), and paired with an array of rx_buffers
191 * (at rx_buffer_area).
192 * The next pair to check on receive is at offset next_rx_desc_to_check
194 emx_rxdesc_t *rx_desc;
195 uint32_t next_rx_desc_to_check;
197 struct emx_rxbuf *rx_buf;
199 bus_dmamap_t rx_sparemap;
202 * First/last mbuf pointers, for
203 * collecting multisegment RX packets.
209 unsigned long rx_pkts;
210 unsigned long mbuf_cluster_failed;
212 bus_dma_tag_t rx_desc_dtag;
213 bus_dmamap_t rx_desc_dmap;
214 bus_addr_t rx_desc_paddr;
218 struct arpcom arpcom;
221 /* DragonFly operating-system-specific structures. */
222 struct e1000_osdep osdep;
225 bus_dma_tag_t parent_dtag;
227 bus_dma_tag_t tx_desc_dtag;
228 bus_dmamap_t tx_desc_dmap;
229 bus_addr_t tx_desc_paddr;
231 struct resource *memory;
234 struct resource *intr_res;
238 struct ifmedia media;
239 struct callout timer;
244 /* Management and WOL features */
248 /* Info about the board itself */
251 uint16_t link_duplex;
253 int int_throttle_ceil;
256 * Transmit definitions
258 * We have an array of num_tx_desc descriptors (handled
259 * by the controller) paired with an array of tx_buffers
260 * (at tx_buffer_area).
261 * The index of the next available descriptor is next_avail_tx_desc.
262 * The number of remaining tx_desc is num_tx_desc_avail.
264 struct e1000_tx_desc *tx_desc_base;
265 struct emx_txbuf *tx_buf;
266 uint32_t next_avail_tx_desc;
267 uint32_t next_tx_to_clean;
268 int num_tx_desc_avail;
270 bus_dma_tag_t txtag; /* dma tag for tx */
274 /* Saved csum offloading context information */
278 uint32_t csum_txd_upper;
279 uint32_t csum_txd_lower;
282 * Variables used to reduce TX interrupt rate and
283 * number of device's TX ring write requests.
286 * Number of TX descriptors setup so far.
289 * Once tx_nsegs > tx_int_nsegs, RS bit will be set
290 * in the last TX descriptor of the packet, and
291 * tx_nsegs will be reset to 0. So TX interrupt and
292 * TX ring write request should be generated roughly
293 * every tx_int_nsegs TX descriptors.
296 * Index of the TX descriptors which have RS bit set,
297 * i.e. DD bit will be set on this TX descriptor after
298 * the data of the TX descriptor are transfered to
299 * hardware's internal packet buffer. Only the TX
300 * descriptors listed in tx_dd[] will be checked upon
301 * TX interrupt. This array is used as circular ring.
303 * tx_dd_tail, tx_dd_head:
304 * Tail and head index of valid elements in tx_dd[].
305 * tx_dd_tail == tx_dd_head means there is no valid
306 * elements in tx_dd[]. tx_dd_tail points to the position
307 * which is one beyond the last valid element in tx_dd[].
308 * tx_dd_head points to the first valid element in
315 #define EMX_TXDD_MAX 64
316 #define EMX_TXDD_SAFE 48 /* 48 <= val < EMX_TXDD_MAX */
317 int tx_dd[EMX_TXDD_MAX];
319 struct emx_rxdata rx_data[EMX_NRX_RING];
321 /* Misc stats maintained by the driver */
322 unsigned long dropped_pkts;
323 unsigned long mbuf_alloc_failed;
324 unsigned long no_tx_desc_avail1;
325 unsigned long no_tx_desc_avail2;
326 unsigned long no_tx_map_avail;
327 unsigned long no_tx_dma_setup;
328 unsigned long watchdog_events;
329 unsigned long rx_overruns;
330 unsigned long rx_irq;
331 unsigned long tx_irq;
332 unsigned long link_irq;
333 unsigned long tx_csum_try_pullup;
334 unsigned long tx_csum_pullup1;
335 unsigned long tx_csum_pullup1_failed;
336 unsigned long tx_csum_pullup2;
337 unsigned long tx_csum_pullup2_failed;
338 unsigned long tx_csum_drop1;
339 unsigned long tx_csum_drop2;
341 /* sysctl tree glue */
342 struct sysctl_ctx_list sysctl_ctx;
343 struct sysctl_oid *sysctl_tree;
347 struct e1000_hw_stats stats;
361 #define EMX_IS_OACTIVE(sc) ((sc)->num_tx_desc_avail <= (sc)->oact_tx_desc)
363 #define EMX_INC_TXDD_IDX(idx) \
365 if (++(idx) == EMX_TXDD_MAX) \
369 #endif /* !_IF_EMX_H_ */