sys/dev/drm/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*-
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "dev/drm/drmP.h"
  30 #include "dev/drm/drm.h"
  31 #include "dev/drm/i915_drm.h"
  32 #include "dev/drm/i915_drv.h"
  33
  34 #define MAX_NOPID ((u32)~0)
  35
  36 /**
  37  * Interrupts that are always left unmasked.
  38  *
  39  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  40  * we leave them always unmasked in IMR and then control enabling them through
  41  * PIPESTAT alone.
  42  */
  43 #define I915_INTERRUPT_ENABLE_FIX       (I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
  44                                          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
  45
  46 /** Interrupts that we mask and unmask at runtime. */
  47 #define I915_INTERRUPT_ENABLE_VAR       (I915_USER_INTERRUPT)
  48
  49 /** These are all of the interrupts used by the driver */
  50 #define I915_INTERRUPT_ENABLE_MASK      (I915_INTERRUPT_ENABLE_FIX | \
  51                                          I915_INTERRUPT_ENABLE_VAR)
  52
  53 #define I915_PIPE_VBLANK_STATUS         (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  54                                          PIPE_VBLANK_INTERRUPT_STATUS)
  55
  56 #define I915_PIPE_VBLANK_ENABLE         (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  57                                          PIPE_VBLANK_INTERRUPT_ENABLE)
  58
  59 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  60                                          DRM_I915_VBLANK_PIPE_B)
  61
  62 static inline void
  63 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
  64 {
  65         mask &= I915_INTERRUPT_ENABLE_VAR;
  66         if ((dev_priv->irq_mask_reg & mask) != 0) {
  67                 dev_priv->irq_mask_reg &= ~mask;
  68                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
  69                 (void) I915_READ(IMR);
  70         }
  71 }
  72
  73 static inline void
  74 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
  75 {
  76         mask &= I915_INTERRUPT_ENABLE_VAR;
  77         if ((dev_priv->irq_mask_reg & mask) != mask) {
  78                 dev_priv->irq_mask_reg |= mask;
  79                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
  80                 (void) I915_READ(IMR);
  81         }
  82 }
  83
  84 static inline u32
  85 i915_pipestat(int pipe)
  86 {
  87         if (pipe == 0)
  88             return PIPEASTAT;
  89         if (pipe == 1)
  90             return PIPEBSTAT;
  91         return -EINVAL;
  92 }
  93
  94 void
  95 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  96 {
  97         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  98                 u32 reg = i915_pipestat(pipe);
  99
 100                 dev_priv->pipestat[pipe] |= mask;
 101                 /* Enable the interrupt, clear any pending status */
 102                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 103                 (void) I915_READ(reg);
 104         }
 105 }
 106
 107 void
 108 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 109 {
 110         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 111                 u32 reg = i915_pipestat(pipe);
 112
 113                 dev_priv->pipestat[pipe] &= ~mask;
 114                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 115                 (void) I915_READ(reg);
 116         }
 117 }
 118
 119 /**
 120  * i915_pipe_enabled - check if a pipe is enabled
 121  * @dev: DRM device
 122  * @pipe: pipe to check
 123  *
 124  * Reading certain registers when the pipe is disabled can hang the chip.
 125  * Use this routine to make sure the PLL is running and the pipe is active
 126  * before reading such registers if unsure.
 127  */
 128 static int
 129 i915_pipe_enabled(struct drm_device *dev, int pipe)
 130 {
 131         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 132         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 133
 134         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 135                 return 1;
 136
 137         return 0;
 138 }
 139
 140 /* Called from drm generic code, passed a 'crtc', which
 141  * we use as a pipe index
 142  */
 143 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 144 {
 145         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 146         unsigned long high_frame;
 147         unsigned long low_frame;
 148         u32 high1, high2, low, count;
 149
 150         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 151         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 152
 153         if (!i915_pipe_enabled(dev, pipe)) {
 154                 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
 155                 return 0;
 156         }
 157
 158         /*
 159          * High & low register fields aren't synchronized, so make sure
 160          * we get a low value that's stable across two reads of the high
 161          * register.
 162          */
 163         do {
 164                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 165                          PIPE_FRAME_HIGH_SHIFT);
 166                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 167                         PIPE_FRAME_LOW_SHIFT);
 168                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 169                          PIPE_FRAME_HIGH_SHIFT);
 170         } while (high1 != high2);
 171
 172         count = (high1 << 8) | low;
 173
 174         return count;
 175 }
 176
 177 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 178 {
 179         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 180         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 181
 182         if (!i915_pipe_enabled(dev, pipe)) {
 183                 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
 184                 return 0;
 185         }
 186
 187         return I915_READ(reg);
 188 }
 189
 190 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 191 {
 192         struct drm_device *dev = (struct drm_device *) arg;
 193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 194         u32 iir, new_iir;
 195         u32 pipea_stats, pipeb_stats;
 196         u32 vblank_status;
 197         u32 vblank_enable;
 198         int irq_received;
 199
 200         atomic_inc(&dev_priv->irq_received);
 201
 202         iir = I915_READ(IIR);
 203
 204         if (IS_I965G(dev)) {
 205                 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
 206                 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
 207         } else {
 208                 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
 209                 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
 210         }
 211
 212         for (;;) {
 213                 irq_received = iir != 0;
 214
 215                 /* Can't rely on pipestat interrupt bit in iir as it might
 216                  * have been cleared after the pipestat interrupt was received.
 217                  * It doesn't set the bit in iir again, but it still produces
 218                  * interrupts (for non-MSI).
 219                  */
 220                 DRM_SPINLOCK(&dev_priv->user_irq_lock);
 221                 pipea_stats = I915_READ(PIPEASTAT);
 222                 pipeb_stats = I915_READ(PIPEBSTAT);
 223
 224                 /*
 225                  * Clear the PIPE(A|B)STAT regs before the IIR
 226                  */
 227                 if (pipea_stats & 0x8000ffff) {
 228                         I915_WRITE(PIPEASTAT, pipea_stats);
 229                         irq_received = 1;
 230                 }
 231
 232                 if (pipeb_stats & 0x8000ffff) {
 233                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 234                         irq_received = 1;
 235                 }
 236                 DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 237
 238                 if (!irq_received)
 239                         break;
 240
 241                 I915_WRITE(IIR, iir);
 242                 new_iir = I915_READ(IIR); /* Flush posted writes */
 243
 244                 if (dev_priv->sarea_priv)
 245                         dev_priv->sarea_priv->last_dispatch =
 246                             READ_BREADCRUMB(dev_priv);
 247
 248                 if (iir & I915_USER_INTERRUPT) {
 249                         DRM_WAKEUP(&dev_priv->irq_queue);
 250                 }
 251
 252                 if (pipea_stats & vblank_status)
 253                         drm_handle_vblank(dev, 0);
 254
 255                 if (pipeb_stats & vblank_status)
 256                         drm_handle_vblank(dev, 1);
 257
 258                 /* With MSI, interrupts are only generated when iir
 259                  * transitions from zero to nonzero.  If another bit got
 260                  * set while we were handling the existing iir bits, then
 261                  * we would never get another interrupt.
 262                  *
 263                  * This is fine on non-MSI as well, as if we hit this path
 264                  * we avoid exiting the interrupt handler only to generate
 265                  * another one.
 266                  *
 267                  * Note that for MSI this could cause a stray interrupt report
 268                  * if an interrupt landed in the time between writing IIR and
 269                  * the posting read.  This should be rare enough to never
 270                  * trigger the 99% of 100,000 interrupts test for disabling
 271                  * stray interrupts.
 272                  */
 273                 iir = new_iir;
 274         }
 275 }
 276
 277 static int i915_emit_irq(struct drm_device * dev)
 278 {
 279         drm_i915_private_t *dev_priv = dev->dev_private;
 280         RING_LOCALS;
 281
 282         i915_kernel_lost_context(dev);
 283
 284         if (++dev_priv->counter > 0x7FFFFFFFUL)
 285                 dev_priv->counter = 0;
 286         if (dev_priv->sarea_priv)
 287                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 288
 289         DRM_DEBUG("emitting: %d\n", dev_priv->counter);
 290
 291         BEGIN_LP_RING(4);
 292         OUT_RING(MI_STORE_DWORD_INDEX);
 293         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 294         OUT_RING(dev_priv->counter);
 295         OUT_RING(MI_USER_INTERRUPT);
 296         ADVANCE_LP_RING();
 297
 298         return dev_priv->counter;
 299 }
 300
 301 void i915_user_irq_get(struct drm_device *dev)
 302 {
 303         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 304
 305         DRM_DEBUG("\n");
 306         DRM_SPINLOCK(&dev_priv->user_irq_lock);
 307         if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1))
 308                 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 309         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 310 }
 311
 312 void i915_user_irq_put(struct drm_device *dev)
 313 {
 314         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 315
 316         DRM_SPINLOCK(&dev_priv->user_irq_lock);
 317         if (dev->irq_enabled) {
 318                 KASSERT(dev_priv->user_irq_refcount > 0, ("invalid refcount"));
 319                 if (--dev_priv->user_irq_refcount == 0)
 320                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 321         }
 322         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 323 }
 324
 325 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 326 {
 327         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 328         int ret = 0;
 329
 330         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 331                 if (dev_priv->sarea_priv) {
 332                         dev_priv->sarea_priv->last_dispatch =
 333                                 READ_BREADCRUMB(dev_priv);
 334                 }
 335                 return 0;
 336         }
 337
 338         if (dev_priv->sarea_priv)
 339                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 340
 341         DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
 342                   READ_BREADCRUMB(dev_priv));
 343
 344         i915_user_irq_get(dev);
 345         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
 346                     READ_BREADCRUMB(dev_priv) >= irq_nr);
 347         i915_user_irq_put(dev);
 348
 349         if (ret == -ERESTART)
 350                 DRM_DEBUG("restarting syscall\n");
 351
 352         if (ret == -EBUSY) {
 353                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 354                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 355         }
 356
 357         return ret;
 358 }
 359
 360 /* Needs the lock as it touches the ring.
 361  */
 362 int i915_irq_emit(struct drm_device *dev, void *data,
 363                          struct drm_file *file_priv)
 364 {
 365         drm_i915_private_t *dev_priv = dev->dev_private;
 366         drm_i915_irq_emit_t *emit = data;
 367         int result;
 368
 369         if (!dev_priv) {
 370                 DRM_ERROR("called with no initialization\n");
 371                 return -EINVAL;
 372         }
 373
 374         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 375
 376         result = i915_emit_irq(dev);
 377
 378         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 379                 DRM_ERROR("copy_to_user\n");
 380                 return -EFAULT;
 381         }
 382
 383         return 0;
 384 }
 385
 386 /* Doesn't need the hardware lock.
 387  */
 388 int i915_irq_wait(struct drm_device *dev, void *data,
 389                          struct drm_file *file_priv)
 390 {
 391         drm_i915_private_t *dev_priv = dev->dev_private;
 392         drm_i915_irq_wait_t *irqwait = data;
 393
 394         if (!dev_priv) {
 395                 DRM_ERROR("called with no initialization\n");
 396                 return -EINVAL;
 397         }
 398
 399         return i915_wait_irq(dev, irqwait->irq_seq);
 400 }
 401
 402 /* Called from drm generic code, passed 'crtc' which
 403  * we use as a pipe index
 404  */
 405 int i915_enable_vblank(struct drm_device *dev, int pipe)
 406 {
 407         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 408         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
 409         u32 pipeconf;
 410
 411         pipeconf = I915_READ(pipeconf_reg);
 412         if (!(pipeconf & PIPEACONF_ENABLE))
 413                 return -EINVAL;
 414
 415         DRM_SPINLOCK(&dev_priv->user_irq_lock);
 416         if (IS_I965G(dev))
 417                 i915_enable_pipestat(dev_priv, pipe,
 418                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
 419         else
 420                 i915_enable_pipestat(dev_priv, pipe,
 421                                      PIPE_VBLANK_INTERRUPT_ENABLE);
 422         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 423         return 0;
 424 }
 425
 426 /* Called from drm generic code, passed 'crtc' which
 427  * we use as a pipe index
 428  */
 429 void i915_disable_vblank(struct drm_device *dev, int pipe)
 430 {
 431         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 432
 433         DRM_SPINLOCK(&dev_priv->user_irq_lock);
 434         i915_disable_pipestat(dev_priv, pipe,
 435                               PIPE_VBLANK_INTERRUPT_ENABLE |
 436                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
 437         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 438 }
 439
 440 /* Set the vblank monitor pipe
 441  */
 442 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 443                          struct drm_file *file_priv)
 444 {
 445         drm_i915_private_t *dev_priv = dev->dev_private;
 446
 447         if (!dev_priv) {
 448                 DRM_ERROR("called with no initialization\n");
 449                 return -EINVAL;
 450         }
 451
 452         return 0;
 453 }
 454
 455 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 456                          struct drm_file *file_priv)
 457 {
 458         drm_i915_private_t *dev_priv = dev->dev_private;
 459         drm_i915_vblank_pipe_t *pipe = data;
 460
 461         if (!dev_priv) {
 462                 DRM_ERROR("called with no initialization\n");
 463                 return -EINVAL;
 464         }
 465
 466         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 467
 468         return 0;
 469 }
 470
 471 /**
 472  * Schedule buffer swap at given vertical blank.
 473  */
 474 int i915_vblank_swap(struct drm_device *dev, void *data,
 475                      struct drm_file *file_priv)
 476 {
 477         /* The delayed swap mechanism was fundamentally racy, and has been
 478          * removed.  The model was that the client requested a delayed flip/swap
 479          * from the kernel, then waited for vblank before continuing to perform
 480          * rendering.  The problem was that the kernel might wake the client
 481          * up before it dispatched the vblank swap (since the lock has to be
 482          * held while touching the ringbuffer), in which case the client would
 483          * clear and start the next frame before the swap occurred, and
 484          * flicker would occur in addition to likely missing the vblank.
 485          *
 486          * In the absence of this ioctl, userland falls back to a correct path
 487          * of waiting for a vblank, then dispatching the swap on its own.
 488          * Context switching to userland and back is plenty fast enough for
 489          * meeting the requirements of vblank swapping.
 490          */
 491         return -EINVAL;
 492 }
 493
 494 /* drm_dma.h hooks
 495 */
 496 void i915_driver_irq_preinstall(struct drm_device * dev)
 497 {
 498         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 499
 500         atomic_set_int(&dev_priv->irq_received, 0);
 501
 502         I915_WRITE(HWSTAM, 0xeffe);
 503         I915_WRITE(PIPEASTAT, 0);
 504         I915_WRITE(PIPEBSTAT, 0);
 505         I915_WRITE(IMR, 0xffffffff);
 506         I915_WRITE(IER, 0x0);
 507         (void) I915_READ(IER);
 508 }
 509
 510 int i915_driver_irq_postinstall(struct drm_device *dev)
 511 {
 512         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 513
 514         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 515
 516         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
 517
 518         /* Unmask the interrupts that we always want on. */
 519         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
 520
 521         dev_priv->pipestat[0] = 0;
 522         dev_priv->pipestat[1] = 0;
 523
 524         /* Disable pipe interrupt enables, clear pending pipe status */
 525         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
 526         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
 527
 528         /* Clear pending interrupt status */
 529         I915_WRITE(IIR, I915_READ(IIR));
 530
 531         I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
 532         I915_WRITE(IMR, dev_priv->irq_mask_reg);
 533         (void) I915_READ(IER);
 534
 535         return 0;
 536 }
 537
 538 void i915_driver_irq_uninstall(struct drm_device * dev)
 539 {
 540         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 541
 542         if (!dev_priv)
 543                 return;
 544
 545         dev_priv->vblank_pipe = 0;
 546
 547         I915_WRITE(HWSTAM, 0xffffffff);
 548         I915_WRITE(PIPEASTAT, 0);
 549         I915_WRITE(PIPEBSTAT, 0);
 550         I915_WRITE(IMR, 0xffffffff);
 551         I915_WRITE(IER, 0x0);
 552
 553         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
 554         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
 555         I915_WRITE(IIR, I915_READ(IIR));
 556 }