2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
26 * This driver exists largely as a result of other people's efforts.
27 * Much of register handling is based on NetBSD CMI8x38 audio driver
28 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien
29 * <cltien@cmedia.com.tw> clarified points regarding the DMA related
30 * registers and the 8738 mixer devices. His Linux driver was also a
31 * useful reference point.
35 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>.
37 * This card/code does not always manage to sample at 44100 - actual
38 * rate drifts slightly between recordings (usually 0-3%). No
39 * differences visible in register dumps between times that work and
42 * $FreeBSD: src/sys/dev/sound/pci/cmi.c,v 1.32.2.2 2006/01/24 18:54:22 joel Exp $
45 #include <dev/sound/pcm/sound.h>
46 #include <dev/sound/pci/cmireg.h>
48 #include <bus/pci/pcireg.h>
49 #include <bus/pci/pcivar.h>
51 #include <sys/sysctl.h>
55 /* Supported chip ID's */
56 #define CMI8338A_PCI_ID 0x010013f6
57 #define CMI8338B_PCI_ID 0x010113f6
58 #define CMI8738_PCI_ID 0x011113f6
59 #define CMI8738B_PCI_ID 0x011213f6
61 /* Buffer size max is 64k for permitted DMA boundaries */
62 #define CMI_DEFAULT_BUFSZ 16384
64 /* Interrupts per length of buffer */
65 #define CMI_INTR_PER_BUFFER 2
67 /* Clarify meaning of named defines in cmireg.h */
68 #define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES
69 #define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES
70 #define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES
71 #define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES
73 /* Our indication of custom mixer control */
74 #define CMPCI_NON_SB16_CONTROL 0xff
76 /* Debugging macro's */
79 #define DEB(x) /* x */
83 #define DEBMIX(x) /* x */
86 /* ------------------------------------------------------------------------- */
92 struct sc_info *parent;
93 struct pcm_channel *channel;
94 struct snd_dbuf *buffer;
95 u_int32_t fmt, spd, phys_buf, bps;
96 u_int32_t dma_active:1, dma_was_active:1;
104 bus_space_handle_t sh;
105 bus_dma_tag_t parent_dmat;
106 struct resource *reg, *irq;
113 struct sc_chinfo pch, rch;
118 static u_int32_t cmi_fmt[] = {
120 AFMT_STEREO | AFMT_U8,
122 AFMT_STEREO | AFMT_S16_LE,
126 static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0};
128 /* ------------------------------------------------------------------------- */
129 /* Register Utilities */
132 cmi_rd(struct sc_info *sc, int regno, int size)
136 return bus_space_read_1(sc->st, sc->sh, regno);
138 return bus_space_read_2(sc->st, sc->sh, regno);
140 return bus_space_read_4(sc->st, sc->sh, regno);
142 DEB(kprintf("cmi_rd: failed 0x%04x %d\n", regno, size));
148 cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
152 bus_space_write_1(sc->st, sc->sh, regno, data);
155 bus_space_write_2(sc->st, sc->sh, regno, data);
158 bus_space_write_4(sc->st, sc->sh, regno, data);
164 cmi_partial_wr4(struct sc_info *sc,
165 int reg, int shift, u_int32_t mask, u_int32_t val)
169 r = cmi_rd(sc, reg, 4);
170 r &= ~(mask << shift);
172 cmi_wr(sc, reg, r, 4);
176 cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask)
180 r = cmi_rd(sc, reg, 4);
182 cmi_wr(sc, reg, r, 4);
186 cmi_set4(struct sc_info *sc, int reg, u_int32_t mask)
190 r = cmi_rd(sc, reg, 4);
192 cmi_wr(sc, reg, r, 4);
195 /* ------------------------------------------------------------------------- */
198 static int cmi_rates[] = {5512, 8000, 11025, 16000,
199 22050, 32000, 44100, 48000};
200 #define NUM_CMI_RATES NELEM(cmi_rates)
202 /* cmpci_rate_to_regvalue returns sampling freq selector for FCR1
203 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */
206 cmpci_rate_to_regvalue(int rate)
210 for(i = 0; i < NUM_CMI_RATES - 1; i++) {
211 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) {
216 DEB(kprintf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i]));
218 r = ((i >> 1) | (i << 2)) & 0x07;
223 cmpci_regvalue_to_rate(u_int32_t r)
227 i = ((r << 1) | (r >> 2)) & 0x07;
228 DEB(kprintf("cmpci_regvalue_to_rate: %d -> %d\n", r, i));
232 /* ------------------------------------------------------------------------- */
233 /* ADC/DAC control - there are 2 dma channels on 8738, either can be
234 * playback or capture. We use ch0 for playback and ch1 for capture. */
237 cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base)
241 ch->phys_buf = sndbuf_getbufaddr(ch->buffer);
243 cmi_wr(sc, base, ch->phys_buf, 4);
244 sz = (u_int32_t)sndbuf_getsize(ch->buffer);
246 s = sz / ch->bps - 1;
247 cmi_wr(sc, base + 4, s, 2);
249 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1;
250 cmi_wr(sc, base + 6, i, 2);
255 cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch)
257 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
259 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
260 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
261 CMPCI_REG_CH0_INTR_ENABLE);
267 cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch)
269 u_int32_t r = ch->dma_active;
271 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
272 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
273 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
274 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
280 cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch)
282 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
283 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
284 /* Enable Interrupts */
285 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
286 CMPCI_REG_CH1_INTR_ENABLE);
287 DEB(kprintf("cmi_ch1_start: dma prog\n"));
292 cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch)
294 u_int32_t r = ch->dma_active;
296 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
297 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
298 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
299 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
305 cmi_spdif_speed(struct sc_info *sc, int speed) {
306 u_int32_t fcr1, lcr, mcr;
308 if (speed >= 44100) {
309 fcr1 = CMPCI_REG_SPDIF0_ENABLE;
310 lcr = CMPCI_REG_XSPDIF_ENABLE;
311 mcr = (speed == 48000) ?
312 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0;
314 fcr1 = mcr = lcr = 0;
317 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0,
318 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr);
319 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0,
320 CMPCI_REG_SPDIF0_ENABLE, fcr1);
321 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0,
322 CMPCI_REG_XSPDIF_ENABLE, lcr);
325 /* ------------------------------------------------------------------------- */
326 /* Channel Interface implementation */
329 cmichan_init(kobj_t obj, void *devinfo,
330 struct snd_dbuf *b, struct pcm_channel *c, int dir)
332 struct sc_info *sc = devinfo;
333 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
339 ch->spd = DSP_DEFAULT_SPEED;
342 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) != 0) {
343 DEB(kprintf("cmichan_init failed\n"));
348 snd_mtxlock(sc->lock);
349 if (ch->dir == PCMDIR_PLAY) {
350 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
352 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
354 snd_mtxunlock(sc->lock);
360 cmichan_setformat(kobj_t obj, void *data, u_int32_t format)
362 struct sc_chinfo *ch = data;
363 struct sc_info *sc = ch->parent;
366 if (format & AFMT_S16_LE) {
367 f = CMPCI_REG_FORMAT_16BIT;
370 f = CMPCI_REG_FORMAT_8BIT;
374 if (format & AFMT_STEREO) {
375 f |= CMPCI_REG_FORMAT_STEREO;
378 f |= CMPCI_REG_FORMAT_MONO;
381 snd_mtxlock(sc->lock);
382 if (ch->dir == PCMDIR_PLAY) {
383 cmi_partial_wr4(ch->parent,
384 CMPCI_REG_CHANNEL_FORMAT,
385 CMPCI_REG_CH0_FORMAT_SHIFT,
386 CMPCI_REG_CH0_FORMAT_MASK,
389 cmi_partial_wr4(ch->parent,
390 CMPCI_REG_CHANNEL_FORMAT,
391 CMPCI_REG_CH1_FORMAT_SHIFT,
392 CMPCI_REG_CH1_FORMAT_MASK,
395 snd_mtxunlock(sc->lock);
402 cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed)
404 struct sc_chinfo *ch = data;
405 struct sc_info *sc = ch->parent;
408 r = cmpci_rate_to_regvalue(speed);
409 snd_mtxlock(sc->lock);
410 if (ch->dir == PCMDIR_PLAY) {
412 /* disable if req before rate change */
413 cmi_spdif_speed(ch->parent, speed);
415 cmi_partial_wr4(ch->parent,
417 CMPCI_REG_DAC_FS_SHIFT,
418 CMPCI_REG_DAC_FS_MASK,
420 if (speed >= 44100 && ch->parent->spdif_enabled) {
421 /* enable if req after rate change */
422 cmi_spdif_speed(ch->parent, speed);
424 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
425 rsp >>= CMPCI_REG_DAC_FS_SHIFT;
426 rsp &= CMPCI_REG_DAC_FS_MASK;
428 cmi_partial_wr4(ch->parent,
430 CMPCI_REG_ADC_FS_SHIFT,
431 CMPCI_REG_ADC_FS_MASK,
433 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
434 rsp >>= CMPCI_REG_ADC_FS_SHIFT;
435 rsp &= CMPCI_REG_ADC_FS_MASK;
437 snd_mtxunlock(sc->lock);
438 ch->spd = cmpci_regvalue_to_rate(r);
440 DEB(kprintf("cmichan_setspeed (%s) %d -> %d (%d)\n",
441 (ch->dir == PCMDIR_PLAY) ? "play" : "rec",
442 speed, ch->spd, cmpci_regvalue_to_rate(rsp)));
448 cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
450 struct sc_chinfo *ch = data;
451 struct sc_info *sc = ch->parent;
453 /* user has requested interrupts every blocksize bytes */
454 if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) {
455 blocksize = sc->bufsz / CMI_INTR_PER_BUFFER;
457 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize);
463 cmichan_trigger(kobj_t obj, void *data, int go)
465 struct sc_chinfo *ch = data;
466 struct sc_info *sc = ch->parent;
468 snd_mtxlock(sc->lock);
469 if (ch->dir == PCMDIR_PLAY) {
472 cmi_ch0_start(sc, ch);
475 cmi_ch0_stop(sc, ch);
481 cmi_ch1_start(sc, ch);
484 cmi_ch1_stop(sc, ch);
488 snd_mtxunlock(sc->lock);
493 cmichan_getptr(kobj_t obj, void *data)
495 struct sc_chinfo *ch = data;
496 struct sc_info *sc = ch->parent;
497 u_int32_t physptr, bufptr, sz;
499 snd_mtxlock(sc->lock);
500 if (ch->dir == PCMDIR_PLAY) {
501 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4);
503 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4);
505 snd_mtxunlock(sc->lock);
507 sz = sndbuf_getsize(ch->buffer);
508 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz;
516 struct sc_info *sc = data;
520 snd_mtxlock(sc->lock);
521 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4);
522 if ((intrstat & CMPCI_REG_ANY_INTR) != 0) {
525 if (intrstat & CMPCI_REG_CH0_INTR) {
526 toclear |= CMPCI_REG_CH0_INTR_ENABLE;
527 /* cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE); */
530 if (intrstat & CMPCI_REG_CH1_INTR) {
531 toclear |= CMPCI_REG_CH1_INTR_ENABLE;
532 /* cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE); */
536 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, toclear);
537 snd_mtxunlock(sc->lock);
539 /* Signal interrupts to channel */
540 if (intrstat & CMPCI_REG_CH0_INTR) {
541 chn_intr(sc->pch.channel);
544 if (intrstat & CMPCI_REG_CH1_INTR) {
545 chn_intr(sc->rch.channel);
548 snd_mtxlock(sc->lock);
549 cmi_set4(sc, CMPCI_REG_INTR_CTRL, toclear);
553 snd_mtxunlock(sc->lock);
557 static struct pcmchan_caps *
558 cmichan_getcaps(kobj_t obj, void *data)
563 static kobj_method_t cmichan_methods[] = {
564 KOBJMETHOD(channel_init, cmichan_init),
565 KOBJMETHOD(channel_setformat, cmichan_setformat),
566 KOBJMETHOD(channel_setspeed, cmichan_setspeed),
567 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize),
568 KOBJMETHOD(channel_trigger, cmichan_trigger),
569 KOBJMETHOD(channel_getptr, cmichan_getptr),
570 KOBJMETHOD(channel_getcaps, cmichan_getcaps),
573 CHANNEL_DECLARE(cmichan);
575 /* ------------------------------------------------------------------------- */
576 /* Mixer - sb16 with kinks */
579 cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val)
581 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
582 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1);
586 cmimix_rd(struct sc_info *sc, u_int8_t port)
588 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
589 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1);
592 static const struct sb16props {
593 u_int8_t rreg; /* right reg chan register */
594 u_int8_t stereo:1; /* (no explanation needed, honest) */
595 u_int8_t rec:1; /* recording source */
596 u_int8_t bits:3; /* num bits to represent maximum gain rep */
597 u_int8_t oselect; /* output select mask */
598 u_int8_t iselect; /* right input select mask */
599 } cmt[SOUND_MIXER_NRDEVICES] = {
600 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5,
601 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R},
602 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5,
603 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R},
604 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5,
605 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R},
606 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5,
607 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC},
608 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0},
609 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0},
610 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0},
611 /* These controls are not implemented in CMI8738, but maybe at a
612 future date. They are not documented in C-Media documentation,
613 though appear in other drivers for future h/w (ALSA, Linux, NetBSD).
615 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0},
616 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0},
617 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0},
618 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0},
619 /* The mic pre-amp is implemented with non-SB16 compatible
621 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0},
624 #define MIXER_GAIN_REG_RTOL(r) (r - 1)
627 cmimix_init(struct snd_mixer *m)
629 struct sc_info *sc = mix_getdevinfo(m);
632 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
633 if (cmt[i].bits) v |= 1 << i;
637 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
638 if (cmt[i].rec) v |= 1 << i;
640 mix_setrecdevs(m, v);
642 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0);
643 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0);
644 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0);
645 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX,
646 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE);
651 cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
653 struct sc_info *sc = mix_getdevinfo(m);
657 max = (1 << cmt[dev].bits) - 1;
659 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) {
660 /* For time being this can only be one thing (mic in
662 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0;
663 l = left * max / 100;
664 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */
665 v |= ((l << 1) | (~l >> 3)) & 0x0f;
666 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1);
670 l = (left * max / 100) << (8 - cmt[dev].bits);
671 if (cmt[dev].stereo) {
672 r = (right * max / 100) << (8 - cmt[dev].bits);
673 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l);
674 cmimix_wr(sc, cmt[dev].rreg, r);
675 DEBMIX(kprintf("Mixer stereo write dev %d reg 0x%02x "\
676 "value 0x%02x:0x%02x\n",
677 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r));
680 cmimix_wr(sc, cmt[dev].rreg, l);
681 DEBMIX(kprintf("Mixer mono write dev %d reg 0x%02x " \
682 "value 0x%02x:0x%02x\n",
683 dev, cmt[dev].rreg, l, l));
686 /* Zero gain does not mute channel from output, but this does... */
687 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX);
688 if (l == 0 && r == 0) {
689 v &= ~cmt[dev].oselect;
691 v |= cmt[dev].oselect;
693 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v);
699 cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src)
701 struct sc_info *sc = mix_getdevinfo(m);
705 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
708 sl |= cmt[i].iselect;
710 ml |= cmt[i].iselect;
714 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml);
715 DEBMIX(kprintf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
716 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml));
717 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml);
718 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml);
719 DEBMIX(kprintf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
720 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml));
725 /* Optional SPDIF support. */
728 cmi_initsys(struct sc_info* sc)
731 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev),
732 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)),
733 OID_AUTO, "spdif_enabled", CTLFLAG_RW,
734 &sc->spdif_enabled, 0,
735 "enable SPDIF output at 44.1 kHz and above");
736 #endif /* SND_DYNSYSCTL */
740 /* ------------------------------------------------------------------------- */
741 static kobj_method_t cmi_mixer_methods[] = {
742 KOBJMETHOD(mixer_init, cmimix_init),
743 KOBJMETHOD(mixer_set, cmimix_set),
744 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc),
747 MIXER_DECLARE(cmi_mixer);
749 /* ------------------------------------------------------------------------- */
750 /* Power and reset */
753 cmi_power(struct sc_info *sc, int state)
756 case 0: /* full power */
757 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
761 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
767 cmi_init(struct sc_info *sc)
770 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
772 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
774 /* Disable interrupts and channels */
775 cmi_clr4(sc, CMPCI_REG_FUNC_0,
776 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
777 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
778 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE);
780 /* Configure DMA channels, ch0 = play, ch1 = capture */
781 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR);
782 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR);
784 /* Attempt to enable 4 Channel output */
785 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D);
787 /* Disable SPDIF1 - not compatible with config */
788 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE);
789 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
795 cmi_uninit(struct sc_info *sc)
797 /* Disable interrupts and channels */
798 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
799 CMPCI_REG_CH0_INTR_ENABLE |
800 CMPCI_REG_CH1_INTR_ENABLE |
801 CMPCI_REG_TDMA_INTR_ENABLE);
802 cmi_clr4(sc, CMPCI_REG_FUNC_0,
803 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
806 /* ------------------------------------------------------------------------- */
807 /* Bus and device registration */
809 cmi_probe(device_t dev)
811 switch(pci_get_devid(dev)) {
812 case CMI8338A_PCI_ID:
813 device_set_desc(dev, "CMedia CMI8338A");
814 return BUS_PROBE_DEFAULT;
815 case CMI8338B_PCI_ID:
816 device_set_desc(dev, "CMedia CMI8338B");
817 return BUS_PROBE_DEFAULT;
819 device_set_desc(dev, "CMedia CMI8738");
820 return BUS_PROBE_DEFAULT;
821 case CMI8738B_PCI_ID:
822 device_set_desc(dev, "CMedia CMI8738B");
823 return BUS_PROBE_DEFAULT;
830 cmi_attach(device_t dev)
834 char status[SND_STATUSLEN];
836 sc = kmalloc(sizeof(struct sc_info), M_DEVBUF, M_WAITOK | M_ZERO);
837 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc");
838 data = pci_read_config(dev, PCIR_COMMAND, 2);
839 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN);
840 pci_write_config(dev, PCIR_COMMAND, data, 2);
841 data = pci_read_config(dev, PCIR_COMMAND, 2);
844 sc->regid = PCIR_BAR(0);
845 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid,
848 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n");
851 sc->st = rman_get_bustag(sc->reg);
852 sc->sh = rman_get_bushandle(sc->reg);
855 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
856 RF_ACTIVE | RF_SHAREABLE);
858 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) {
859 device_printf(dev, "cmi_attach: Unable to map interrupt\n");
863 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536);
865 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
866 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
867 /*highaddr*/BUS_SPACE_MAXADDR,
868 /*filter*/NULL, /*filterarg*/NULL,
869 /*maxsize*/sc->bufsz, /*nsegments*/1,
870 /*maxsegz*/0x3ffff, /*flags*/0,
871 &sc->parent_dmat) != 0) {
872 device_printf(dev, "cmi_attach: Unable to create dma tag\n");
880 if (mixer_init(dev, &cmi_mixer_class, sc))
883 if (pcm_register(dev, sc, 1, 1))
888 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc);
889 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc);
891 ksnprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s",
892 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cmi));
893 pcm_setstatus(dev, status);
895 DEB(kprintf("cmi_attach: succeeded\n"));
900 bus_dma_tag_destroy(sc->parent_dmat);
902 bus_teardown_intr(dev, sc->irq, sc->ih);
904 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
906 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
908 snd_mtxfree(sc->lock);
916 cmi_detach(device_t dev)
921 r = pcm_unregister(dev);
924 sc = pcm_getdevinfo(dev);
928 bus_dma_tag_destroy(sc->parent_dmat);
929 bus_teardown_intr(dev, sc->irq, sc->ih);
930 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
931 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
932 snd_mtxfree(sc->lock);
939 cmi_suspend(device_t dev)
941 struct sc_info *sc = pcm_getdevinfo(dev);
943 snd_mtxlock(sc->lock);
944 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch);
945 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch);
947 snd_mtxunlock(sc->lock);
952 cmi_resume(device_t dev)
954 struct sc_info *sc = pcm_getdevinfo(dev);
956 snd_mtxlock(sc->lock);
958 if (cmi_init(sc) != 0) {
959 device_printf(dev, "unable to reinitialize the card\n");
960 snd_mtxunlock(sc->lock);
964 if (mixer_reinit(dev) == -1) {
965 device_printf(dev, "unable to reinitialize the mixer\n");
966 snd_mtxunlock(sc->lock);
970 if (sc->pch.dma_was_active) {
971 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd);
972 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt);
973 cmi_ch0_start(sc, &sc->pch);
976 if (sc->rch.dma_was_active) {
977 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd);
978 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt);
979 cmi_ch1_start(sc, &sc->rch);
981 snd_mtxunlock(sc->lock);
985 static device_method_t cmi_methods[] = {
986 DEVMETHOD(device_probe, cmi_probe),
987 DEVMETHOD(device_attach, cmi_attach),
988 DEVMETHOD(device_detach, cmi_detach),
989 DEVMETHOD(device_resume, cmi_resume),
990 DEVMETHOD(device_suspend, cmi_suspend),
994 static driver_t cmi_driver = {
1000 DRIVER_MODULE(snd_cmi, pci, cmi_driver, pcm_devclass, NULL, NULL);
1001 MODULE_DEPEND(snd_cmi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1002 MODULE_VERSION(snd_cmi, 1);