2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include <sys/param.h>
36 #include <sys/bitops.h>
37 #include <sys/endian.h>
38 #include <sys/kernel.h>
40 #include <sys/malloc.h>
43 #include <sys/serialize.h>
44 #include <sys/socket.h>
45 #include <sys/sysctl.h>
47 #include <net/ethernet.h>
50 #include <net/if_arp.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/ifq_var.h>
55 #include <netproto/802_11/ieee80211_radiotap.h>
56 #include <netproto/802_11/ieee80211_var.h>
57 #include <netproto/802_11/wlan_ratectl/onoe/ieee80211_onoe_param.h>
59 #include <bus/pci/pcireg.h>
60 #include <bus/pci/pcivar.h>
61 #include <bus/pci/pcidevs.h>
63 #include <dev/netif/bwi/if_bwireg.h>
64 #include <dev/netif/bwi/if_bwivar.h>
65 #include <dev/netif/bwi/bwiphy.h>
66 #include <dev/netif/bwi/bwirf.h>
67 #include <dev/netif/bwi/bwimac.h>
69 #define RF_LO_WRITE(mac, lo) bwi_rf_lo_write((mac), (lo))
71 #define BWI_RF_2GHZ_CHAN(chan) \
72 (ieee80211_ieee2mhz((chan), IEEE80211_CHAN_2GHZ) - 2400)
74 #define BWI_DEFAULT_IDLE_TSSI 52
97 #define SAVE_RF_REG(mac, regs, n) (regs)->rf_##n = RF_READ((mac), 0x##n)
98 #define RESTORE_RF_REG(mac, regs, n) RF_WRITE((mac), 0x##n, (regs)->rf_##n)
100 #define SAVE_PHY_REG(mac, regs, n) (regs)->phy_##n = PHY_READ((mac), 0x##n)
101 #define RESTORE_PHY_REG(mac, regs, n) PHY_WRITE((mac), 0x##n, (regs)->phy_##n)
103 static int bwi_rf_calc_txpower(int8_t *, uint8_t, const int16_t[]);
104 static void bwi_rf_workaround(struct bwi_mac *, u_int);
105 static int bwi_rf_gain_max_reached(struct bwi_mac *, int);
106 static uint16_t bwi_rf_calibval(struct bwi_mac *);
107 static uint16_t bwi_rf_get_tp_ctrl2(struct bwi_mac *);
109 static void bwi_rf_lo_update_11b(struct bwi_mac *);
110 static uint16_t bwi_rf_lo_measure_11b(struct bwi_mac *);
112 static void bwi_rf_lo_update_11g(struct bwi_mac *);
113 static uint32_t bwi_rf_lo_devi_measure(struct bwi_mac *, uint16_t);
114 static void bwi_rf_lo_measure_11g(struct bwi_mac *,
115 const struct bwi_rf_lo *, struct bwi_rf_lo *, uint8_t);
116 static uint8_t _bwi_rf_lo_update_11g(struct bwi_mac *, uint16_t);
117 static void bwi_rf_lo_write(struct bwi_mac *, const struct bwi_rf_lo *);
119 static void bwi_rf_set_nrssi_ofs_11g(struct bwi_mac *);
120 static void bwi_rf_calc_nrssi_slope_11b(struct bwi_mac *);
121 static void bwi_rf_calc_nrssi_slope_11g(struct bwi_mac *);
122 static void bwi_rf_set_nrssi_thr_11b(struct bwi_mac *);
123 static void bwi_rf_set_nrssi_thr_11g(struct bwi_mac *);
125 static void bwi_rf_init_sw_nrssi_table(struct bwi_mac *);
127 static int bwi_rf_calc_rssi_bcm2050(struct bwi_mac *,
128 const struct bwi_rxbuf_hdr *);
129 static int bwi_rf_calc_rssi_bcm2053(struct bwi_mac *,
130 const struct bwi_rxbuf_hdr *);
131 static int bwi_rf_calc_rssi_bcm2060(struct bwi_mac *,
132 const struct bwi_rxbuf_hdr *);
134 static void bwi_rf_on_11a(struct bwi_mac *);
135 static void bwi_rf_on_11bg(struct bwi_mac *);
137 static void bwi_rf_off_11a(struct bwi_mac *);
138 static void bwi_rf_off_11bg(struct bwi_mac *);
139 static void bwi_rf_off_11g_rev5(struct bwi_mac *);
141 static const int8_t bwi_txpower_map_11b[BWI_TSSI_MAX] =
142 { BWI_TXPOWER_MAP_11B };
143 static const int8_t bwi_txpower_map_11g[BWI_TSSI_MAX] =
144 { BWI_TXPOWER_MAP_11G };
146 static __inline int16_t
147 bwi_nrssi_11g(struct bwi_mac *mac)
151 #define NRSSI_11G_MASK __BITS(13, 8)
153 val = (int16_t)__SHIFTOUT(PHY_READ(mac, 0x47f), NRSSI_11G_MASK);
158 #undef NRSSI_11G_MASK
161 static __inline struct bwi_rf_lo *
162 bwi_get_rf_lo(struct bwi_mac *mac, uint16_t rf_atten, uint16_t bbp_atten)
166 n = rf_atten + (14 * (bbp_atten / 2));
167 KKASSERT(n < BWI_RFLO_MAX);
169 return &mac->mac_rf.rf_lo[n];
173 bwi_rf_lo_isused(struct bwi_mac *mac, const struct bwi_rf_lo *lo)
175 struct bwi_rf *rf = &mac->mac_rf;
178 idx = lo - rf->rf_lo;
179 KKASSERT(idx >= 0 && idx < BWI_RFLO_MAX);
181 return isset(rf->rf_lo_used, idx);
185 bwi_rf_write(struct bwi_mac *mac, uint16_t ctrl, uint16_t data)
187 struct bwi_softc *sc = mac->mac_sc;
189 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
190 CSR_WRITE_2(sc, BWI_RF_DATA_LO, data);
194 bwi_rf_read(struct bwi_mac *mac, uint16_t ctrl)
196 struct bwi_rf *rf = &mac->mac_rf;
197 struct bwi_softc *sc = mac->mac_sc;
199 ctrl |= rf->rf_ctrl_rd;
200 if (rf->rf_ctrl_adj) {
204 else if (ctrl < 0x80)
208 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
209 return CSR_READ_2(sc, BWI_RF_DATA_LO);
213 bwi_rf_attach(struct bwi_mac *mac)
215 struct bwi_softc *sc = mac->mac_sc;
216 struct bwi_phy *phy = &mac->mac_phy;
217 struct bwi_rf *rf = &mac->mac_rf;
222 * Get RF manufacture/type/revision
224 if (sc->sc_bbp_id == BWI_BBPID_BCM4317) {
228 manu = BWI_RF_MANUFACT_BCM;
229 type = BWI_RF_T_BCM2050;
230 if (sc->sc_bbp_rev == 0)
232 else if (sc->sc_bbp_rev == 1)
239 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
240 val = CSR_READ_2(sc, BWI_RF_DATA_HI);
243 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
244 val |= CSR_READ_2(sc, BWI_RF_DATA_LO);
246 manu = __SHIFTOUT(val, BWI_RFINFO_MANUFACT_MASK);
247 type = __SHIFTOUT(val, BWI_RFINFO_TYPE_MASK);
248 rev = __SHIFTOUT(val, BWI_RFINFO_REV_MASK);
250 device_printf(sc->sc_dev, "RF: manu 0x%03x, type 0x%04x, rev %u\n",
254 * Verify whether the RF is supported
258 switch (phy->phy_mode) {
259 case IEEE80211_MODE_11A:
260 if (manu != BWI_RF_MANUFACT_BCM ||
261 type != BWI_RF_T_BCM2060 ||
263 device_printf(sc->sc_dev, "only BCM2060 rev 1 RF "
264 "is supported for 11A PHY\n");
267 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11A;
268 rf->rf_on = bwi_rf_on_11a;
269 rf->rf_off = bwi_rf_off_11a;
270 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2060;
272 case IEEE80211_MODE_11B:
273 if (type == BWI_RF_T_BCM2050) {
274 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11BG;
275 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2050;
276 } else if (type == BWI_RF_T_BCM2053) {
278 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2053;
280 device_printf(sc->sc_dev, "only BCM2050/BCM2053 RF "
281 "is supported for 11B PHY\n");
284 rf->rf_on = bwi_rf_on_11bg;
285 rf->rf_off = bwi_rf_off_11bg;
286 rf->rf_calc_nrssi_slope = bwi_rf_calc_nrssi_slope_11b;
287 rf->rf_set_nrssi_thr = bwi_rf_set_nrssi_thr_11b;
288 if (phy->phy_rev == 6)
289 rf->rf_lo_update = bwi_rf_lo_update_11g;
291 rf->rf_lo_update = bwi_rf_lo_update_11b;
293 case IEEE80211_MODE_11G:
294 if (type != BWI_RF_T_BCM2050) {
295 device_printf(sc->sc_dev, "only BCM2050 RF "
296 "is supported for 11G PHY\n");
299 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11BG;
300 rf->rf_on = bwi_rf_on_11bg;
301 if (mac->mac_rev >= 5)
302 rf->rf_off = bwi_rf_off_11g_rev5;
304 rf->rf_off = bwi_rf_off_11bg;
305 rf->rf_calc_nrssi_slope = bwi_rf_calc_nrssi_slope_11g;
306 rf->rf_set_nrssi_thr = bwi_rf_set_nrssi_thr_11g;
307 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2050;
308 rf->rf_lo_update = bwi_rf_lo_update_11g;
311 device_printf(sc->sc_dev, "unsupported PHY mode\n");
318 rf->rf_curchan = IEEE80211_CHAN_ANY;
319 rf->rf_ant_mode = BWI_ANT_MODE_AUTO;
324 bwi_rf_set_chan(struct bwi_mac *mac, u_int chan, int work_around)
326 struct bwi_softc *sc = mac->mac_sc;
328 if (chan == IEEE80211_CHAN_ANY)
331 MOBJ_WRITE_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_CHAN, chan);
336 bwi_rf_workaround(mac, chan);
338 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
341 if (sc->sc_locale == BWI_SPROM_LOCALE_JAPAN)
342 HFLAGS_CLRBITS(mac, BWI_HFLAG_NOT_JAPAN);
344 HFLAGS_SETBITS(mac, BWI_HFLAG_NOT_JAPAN);
345 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, (1 << 11)); /* XXX */
347 CSR_CLRBITS_2(sc, BWI_RF_CHAN_EX, 0x840); /* XXX */
349 DELAY(8000); /* DELAY(2000); */
351 mac->mac_rf.rf_curchan = chan;
355 bwi_rf_get_gains(struct bwi_mac *mac)
357 #define SAVE_PHY_MAX 15
358 #define SAVE_RF_MAX 3
360 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
361 { 0x52, 0x43, 0x7a };
362 static const uint16_t save_phy_regs[SAVE_PHY_MAX] = {
363 0x0429, 0x0001, 0x0811, 0x0812,
364 0x0814, 0x0815, 0x005a, 0x0059,
365 0x0058, 0x000a, 0x0003, 0x080f,
366 0x0810, 0x002b, 0x0015
369 struct bwi_phy *phy = &mac->mac_phy;
370 struct bwi_rf *rf = &mac->mac_rf;
371 uint16_t save_phy[SAVE_PHY_MAX];
372 uint16_t save_rf[SAVE_RF_MAX];
374 int i, j, loop1_max, loop1, loop2;
377 * Save PHY/RF registers for later restoration
379 for (i = 0; i < SAVE_PHY_MAX; ++i)
380 save_phy[i] = PHY_READ(mac, save_phy_regs[i]);
381 PHY_READ(mac, 0x2d); /* dummy read */
383 for (i = 0; i < SAVE_RF_MAX; ++i)
384 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
386 PHY_CLRBITS(mac, 0x429, 0xc000);
387 PHY_SETBITS(mac, 0x1, 0x8000);
389 PHY_SETBITS(mac, 0x811, 0x2);
390 PHY_CLRBITS(mac, 0x812, 0x2);
391 PHY_SETBITS(mac, 0x811, 0x1);
392 PHY_CLRBITS(mac, 0x812, 0x1);
394 PHY_SETBITS(mac, 0x814, 0x1);
395 PHY_CLRBITS(mac, 0x815, 0x1);
396 PHY_SETBITS(mac, 0x814, 0x2);
397 PHY_CLRBITS(mac, 0x815, 0x2);
399 PHY_SETBITS(mac, 0x811, 0xc);
400 PHY_SETBITS(mac, 0x812, 0xc);
401 PHY_SETBITS(mac, 0x811, 0x30);
402 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x10);
404 PHY_WRITE(mac, 0x5a, 0x780);
405 PHY_WRITE(mac, 0x59, 0xc810);
406 PHY_WRITE(mac, 0x58, 0xd);
407 PHY_SETBITS(mac, 0xa, 0x2000);
409 PHY_SETBITS(mac, 0x814, 0x4);
410 PHY_CLRBITS(mac, 0x815, 0x4);
412 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40);
414 if (rf->rf_rev == 8) {
416 RF_WRITE(mac, 0x43, loop1_max);
419 RF_WRITE(mac, 0x52, 0x0);
420 RF_FILT_SETBITS(mac, 0x43, 0xfff0, loop1_max);
423 bwi_phy_set_bbp_atten(mac, 11);
425 if (phy->phy_rev >= 3)
426 PHY_WRITE(mac, 0x80f, 0xc020);
428 PHY_WRITE(mac, 0x80f, 0x8020);
429 PHY_WRITE(mac, 0x810, 0);
431 PHY_FILT_SETBITS(mac, 0x2b, 0xffc0, 0x1);
432 PHY_FILT_SETBITS(mac, 0x2b, 0xc0ff, 0x800);
433 PHY_SETBITS(mac, 0x811, 0x100);
434 PHY_CLRBITS(mac, 0x812, 0x3000);
436 if ((mac->mac_sc->sc_card_flags & BWI_CARD_F_EXT_LNA) &&
438 PHY_SETBITS(mac, 0x811, 0x800);
439 PHY_SETBITS(mac, 0x812, 0x8000);
441 RF_CLRBITS(mac, 0x7a, 0xff08);
444 * Find out 'loop1/loop2', which will be used to calculate
445 * max loopback gain later
448 for (i = 0; i < loop1_max; ++i) {
449 for (j = 0; j < 16; ++j) {
450 RF_WRITE(mac, 0x43, i);
452 if (bwi_rf_gain_max_reached(mac, j))
461 * Find out 'trsw', which will be used to calculate
462 * TRSW(TX/RX switch) RX gain later
465 PHY_SETBITS(mac, 0x812, 0x30);
467 for (i = loop2 - 8; i < 16; ++i) {
469 if (bwi_rf_gain_max_reached(mac, i))
477 * Restore saved PHY/RF registers
479 /* First 4 saved PHY registers need special processing */
480 for (i = 4; i < SAVE_PHY_MAX; ++i)
481 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]);
483 bwi_phy_set_bbp_atten(mac, mac->mac_tpctl.bbp_atten);
485 for (i = 0; i < SAVE_RF_MAX; ++i)
486 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
488 PHY_WRITE(mac, save_phy_regs[2], save_phy[2] | 0x3);
490 PHY_WRITE(mac, save_phy_regs[2], save_phy[2]);
491 PHY_WRITE(mac, save_phy_regs[3], save_phy[3]);
492 PHY_WRITE(mac, save_phy_regs[0], save_phy[0]);
493 PHY_WRITE(mac, save_phy_regs[1], save_phy[1]);
498 rf->rf_lo_gain = (loop2 * 6) - (loop1 * 4) - 11;
499 rf->rf_rx_gain = trsw * 2;
500 DPRINTF(mac->mac_sc, BWI_DBG_RF | BWI_DBG_INIT,
501 "lo gain: %u, rx gain: %u\n",
502 rf->rf_lo_gain, rf->rf_rx_gain);
509 bwi_rf_init(struct bwi_mac *mac)
511 struct bwi_rf *rf = &mac->mac_rf;
513 if (rf->rf_type == BWI_RF_T_BCM2060) {
516 if (rf->rf_flags & BWI_RF_F_INITED)
517 RF_WRITE(mac, 0x78, rf->rf_calib);
519 bwi_rf_init_bcm2050(mac);
524 bwi_rf_off_11a(struct bwi_mac *mac)
526 RF_WRITE(mac, 0x4, 0xff);
527 RF_WRITE(mac, 0x5, 0xfb);
529 PHY_SETBITS(mac, 0x10, 0x8);
530 PHY_SETBITS(mac, 0x11, 0x8);
532 PHY_WRITE(mac, 0x15, 0xaa00);
536 bwi_rf_off_11bg(struct bwi_mac *mac)
538 PHY_WRITE(mac, 0x15, 0xaa00);
542 bwi_rf_off_11g_rev5(struct bwi_mac *mac)
544 PHY_SETBITS(mac, 0x811, 0x8c);
545 PHY_CLRBITS(mac, 0x812, 0x8c);
549 bwi_rf_workaround(struct bwi_mac *mac, u_int chan)
551 struct bwi_softc *sc = mac->mac_sc;
552 struct bwi_rf *rf = &mac->mac_rf;
554 if (chan == IEEE80211_CHAN_ANY) {
555 if_printf(&mac->mac_sc->sc_ic.ic_if,
556 "%s invalid channel!!\n", __func__);
560 if (rf->rf_type != BWI_RF_T_BCM2050 || rf->rf_rev >= 6)
564 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan + 4));
566 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(1));
568 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
571 static __inline struct bwi_rf_lo *
572 bwi_rf_lo_find(struct bwi_mac *mac, const struct bwi_tpctl *tpctl)
574 uint16_t rf_atten, bbp_atten;
582 if (tpctl->tp_ctrl1 == 3)
585 bbp_atten = tpctl->bbp_atten;
586 rf_atten = tpctl->rf_atten;
592 if (remap_rf_atten) {
594 static const uint16_t map[MAP_MAX] =
595 { 11, 10, 11, 12, 13, 12, 13, 12, 13, 12 };
598 KKASSERT(rf_atten < MAP_MAX);
599 rf_atten = map[rf_atten];
601 if (rf_atten >= MAP_MAX) {
602 rf_atten = 0; /* XXX */
604 rf_atten = map[rf_atten];
610 return bwi_get_rf_lo(mac, rf_atten, bbp_atten);
614 bwi_rf_lo_adjust(struct bwi_mac *mac, const struct bwi_tpctl *tpctl)
616 const struct bwi_rf_lo *lo;
618 lo = bwi_rf_lo_find(mac, tpctl);
619 RF_LO_WRITE(mac, lo);
623 bwi_rf_lo_write(struct bwi_mac *mac, const struct bwi_rf_lo *lo)
627 val = (uint8_t)lo->ctrl_lo;
628 val |= ((uint8_t)lo->ctrl_hi) << 8;
630 PHY_WRITE(mac, BWI_PHYR_RF_LO, val);
634 bwi_rf_gain_max_reached(struct bwi_mac *mac, int idx)
636 PHY_FILT_SETBITS(mac, 0x812, 0xf0ff, idx << 8);
637 PHY_FILT_SETBITS(mac, 0x15, 0xfff, 0xa000);
638 PHY_SETBITS(mac, 0x15, 0xf000);
642 return (PHY_READ(mac, 0x2d) >= 0xdfc);
645 /* XXX use bitmap array */
646 static __inline uint16_t
647 bitswap4(uint16_t val)
651 ret = (val & 0x8) >> 3;
652 ret |= (val & 0x4) >> 1;
653 ret |= (val & 0x2) << 1;
654 ret |= (val & 0x1) << 3;
658 static __inline uint16_t
659 bwi_phy812_value(struct bwi_mac *mac, uint16_t lpd)
661 struct bwi_softc *sc = mac->mac_sc;
662 struct bwi_phy *phy = &mac->mac_phy;
663 struct bwi_rf *rf = &mac->mac_rf;
664 uint16_t lo_gain, ext_lna, loop;
666 if ((phy->phy_flags & BWI_PHY_F_LINKED) == 0)
669 lo_gain = rf->rf_lo_gain;
675 if (lo_gain >= 0x46) {
678 } else if (lo_gain >= 0x3a) {
681 } else if (lo_gain >= 0x2e) {
689 for (loop = 0; loop < 16; ++loop) {
690 lo_gain -= (6 * loop);
695 if (phy->phy_rev >= 7 && (sc->sc_card_flags & BWI_CARD_F_EXT_LNA)) {
698 ext_lna |= (loop << 8);
703 return (0x8092 | ext_lna);
705 return (0x2092 | ext_lna);
707 return (0x2093 | ext_lna);
709 panic("unsupported lpd\n");
712 ext_lna |= (loop << 8);
718 return (0x92 | ext_lna);
720 return (0x93 | ext_lna);
722 panic("unsupported lpd\n");
726 panic("never reached\n");
731 bwi_rf_init_bcm2050(struct bwi_mac *mac)
733 #define SAVE_RF_MAX 3
734 #define SAVE_PHY_COMM_MAX 4
735 #define SAVE_PHY_11G_MAX 6
737 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
738 { 0x0043, 0x0051, 0x0052 };
739 static const uint16_t save_phy_regs_comm[SAVE_PHY_COMM_MAX] =
740 { 0x0015, 0x005a, 0x0059, 0x0058 };
741 static const uint16_t save_phy_regs_11g[SAVE_PHY_11G_MAX] =
742 { 0x0811, 0x0812, 0x0814, 0x0815, 0x0429, 0x0802 };
744 uint16_t save_rf[SAVE_RF_MAX];
745 uint16_t save_phy_comm[SAVE_PHY_COMM_MAX];
746 uint16_t save_phy_11g[SAVE_PHY_11G_MAX];
747 uint16_t phyr_35, phyr_30 = 0, rfr_78, phyr_80f = 0, phyr_810 = 0;
748 uint16_t bphy_ctrl = 0, bbp_atten, rf_chan_ex;
751 uint32_t test_lim, test;
752 struct bwi_softc *sc = mac->mac_sc;
753 struct bwi_phy *phy = &mac->mac_phy;
754 struct bwi_rf *rf = &mac->mac_rf;
758 * Save registers for later restoring
760 for (i = 0; i < SAVE_RF_MAX; ++i)
761 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
762 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
763 save_phy_comm[i] = PHY_READ(mac, save_phy_regs_comm[i]);
765 if (phy->phy_mode == IEEE80211_MODE_11B) {
766 phyr_30 = PHY_READ(mac, 0x30);
767 bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL);
769 PHY_WRITE(mac, 0x30, 0xff);
770 CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x3f3f);
771 } else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
772 for (i = 0; i < SAVE_PHY_11G_MAX; ++i) {
774 PHY_READ(mac, save_phy_regs_11g[i]);
777 PHY_SETBITS(mac, 0x814, 0x3);
778 PHY_CLRBITS(mac, 0x815, 0x3);
779 PHY_CLRBITS(mac, 0x429, 0x8000);
780 PHY_CLRBITS(mac, 0x802, 0x3);
782 phyr_80f = PHY_READ(mac, 0x80f);
783 phyr_810 = PHY_READ(mac, 0x810);
785 if (phy->phy_rev >= 3)
786 PHY_WRITE(mac, 0x80f, 0xc020);
788 PHY_WRITE(mac, 0x80f, 0x8020);
789 PHY_WRITE(mac, 0x810, 0);
791 phy812_val = bwi_phy812_value(mac, 0x011);
792 PHY_WRITE(mac, 0x812, phy812_val);
793 if (phy->phy_rev < 7 ||
794 (sc->sc_card_flags & BWI_CARD_F_EXT_LNA) == 0)
795 PHY_WRITE(mac, 0x811, 0x1b3);
797 PHY_WRITE(mac, 0x811, 0x9b3);
799 CSR_SETBITS_2(sc, BWI_RF_ANTDIV, 0x8000);
801 phyr_35 = PHY_READ(mac, 0x35);
802 PHY_CLRBITS(mac, 0x35, 0x80);
804 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
805 rf_chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
807 if (phy->phy_version == 0) {
808 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
810 if (phy->phy_version >= 2)
811 PHY_FILT_SETBITS(mac, 0x3, 0xffbf, 0x40);
812 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, 0x2000);
815 calib = bwi_rf_calibval(mac);
817 if (phy->phy_mode == IEEE80211_MODE_11B)
818 RF_WRITE(mac, 0x78, 0x26);
820 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
821 phy812_val = bwi_phy812_value(mac, 0x011);
822 PHY_WRITE(mac, 0x812, phy812_val);
825 PHY_WRITE(mac, 0x15, 0xbfaf);
826 PHY_WRITE(mac, 0x2b, 0x1403);
828 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
829 phy812_val = bwi_phy812_value(mac, 0x001);
830 PHY_WRITE(mac, 0x812, phy812_val);
833 PHY_WRITE(mac, 0x15, 0xbfa0);
835 RF_SETBITS(mac, 0x51, 0x4);
836 if (rf->rf_rev == 8) {
837 RF_WRITE(mac, 0x43, 0x1f);
839 RF_WRITE(mac, 0x52, 0);
840 RF_FILT_SETBITS(mac, 0x43, 0xfff0, 0x9);
844 PHY_WRITE(mac, 0x58, 0);
845 for (i = 0; i < 16; ++i) {
846 PHY_WRITE(mac, 0x5a, 0x480);
847 PHY_WRITE(mac, 0x59, 0xc810);
849 PHY_WRITE(mac, 0x58, 0xd);
850 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
851 phy812_val = bwi_phy812_value(mac, 0x101);
852 PHY_WRITE(mac, 0x812, phy812_val);
854 PHY_WRITE(mac, 0x15, 0xafb0);
857 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
858 phy812_val = bwi_phy812_value(mac, 0x101);
859 PHY_WRITE(mac, 0x812, phy812_val);
861 PHY_WRITE(mac, 0x15, 0xefb0);
864 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
865 phy812_val = bwi_phy812_value(mac, 0x100);
866 PHY_WRITE(mac, 0x812, phy812_val);
868 PHY_WRITE(mac, 0x15, 0xfff0);
871 test_lim += PHY_READ(mac, 0x2d);
873 PHY_WRITE(mac, 0x58, 0);
874 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
875 phy812_val = bwi_phy812_value(mac, 0x101);
876 PHY_WRITE(mac, 0x812, phy812_val);
878 PHY_WRITE(mac, 0x15, 0xafb0);
886 PHY_WRITE(mac, 0x58, 0);
887 for (i = 0; i < 16; ++i) {
890 rfr_78 = (bitswap4(i) << 1) | 0x20;
891 RF_WRITE(mac, 0x78, rfr_78);
894 /* NB: This block is slight different than the above one */
895 for (j = 0; j < 16; ++j) {
896 PHY_WRITE(mac, 0x5a, 0xd80);
897 PHY_WRITE(mac, 0x59, 0xc810);
899 PHY_WRITE(mac, 0x58, 0xd);
900 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
902 phy812_val = bwi_phy812_value(mac, 0x101);
903 PHY_WRITE(mac, 0x812, phy812_val);
905 PHY_WRITE(mac, 0x15, 0xafb0);
908 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
910 phy812_val = bwi_phy812_value(mac, 0x101);
911 PHY_WRITE(mac, 0x812, phy812_val);
913 PHY_WRITE(mac, 0x15, 0xefb0);
916 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
918 phy812_val = bwi_phy812_value(mac, 0x100);
919 PHY_WRITE(mac, 0x812, phy812_val);
921 PHY_WRITE(mac, 0x15, 0xfff0);
924 test += PHY_READ(mac, 0x2d);
926 PHY_WRITE(mac, 0x58, 0);
927 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
929 phy812_val = bwi_phy812_value(mac, 0x101);
930 PHY_WRITE(mac, 0x812, phy812_val);
932 PHY_WRITE(mac, 0x15, 0xafb0);
942 rf->rf_calib = rfr_78;
944 rf->rf_calib = calib;
945 if (rf->rf_calib != 0xffff) {
946 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_INIT,
947 "RF calibration value: 0x%04x\n", rf->rf_calib);
948 rf->rf_flags |= BWI_RF_F_INITED;
952 * Restore trashes registers
954 PHY_WRITE(mac, save_phy_regs_comm[0], save_phy_comm[0]);
956 for (i = 0; i < SAVE_RF_MAX; ++i) {
957 int pos = (i + 1) % SAVE_RF_MAX;
959 RF_WRITE(mac, save_rf_regs[pos], save_rf[pos]);
961 for (i = 1; i < SAVE_PHY_COMM_MAX; ++i)
962 PHY_WRITE(mac, save_phy_regs_comm[i], save_phy_comm[i]);
964 CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
965 if (phy->phy_version != 0)
966 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, rf_chan_ex);
968 PHY_WRITE(mac, 0x35, phyr_35);
969 bwi_rf_workaround(mac, rf->rf_curchan);
971 if (phy->phy_mode == IEEE80211_MODE_11B) {
972 PHY_WRITE(mac, 0x30, phyr_30);
973 CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);
974 } else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
975 /* XXX Spec only says when PHY is linked (gmode) */
976 CSR_CLRBITS_2(sc, BWI_RF_ANTDIV, 0x8000);
978 for (i = 0; i < SAVE_PHY_11G_MAX; ++i) {
979 PHY_WRITE(mac, save_phy_regs_11g[i],
983 PHY_WRITE(mac, 0x80f, phyr_80f);
984 PHY_WRITE(mac, 0x810, phyr_810);
987 #undef SAVE_PHY_11G_MAX
988 #undef SAVE_PHY_COMM_MAX
993 bwi_rf_calibval(struct bwi_mac *mac)
995 /* http://bcm-specs.sipsolutions.net/RCCTable */
996 static const uint16_t rf_calibvals[] = {
997 0x2, 0x3, 0x1, 0xf, 0x6, 0x7, 0x5, 0xf,
998 0xa, 0xb, 0x9, 0xf, 0xe, 0xf, 0xd, 0xf
1000 uint16_t val, calib;
1003 val = RF_READ(mac, BWI_RFR_BBP_ATTEN);
1004 idx = __SHIFTOUT(val, BWI_RFR_BBP_ATTEN_CALIB_IDX);
1005 KKASSERT(idx < (int)(NELEM(rf_calibvals)));
1007 calib = rf_calibvals[idx] << 1;
1008 if (val & BWI_RFR_BBP_ATTEN_CALIB_BIT)
1015 static __inline int32_t
1016 _bwi_adjust_devide(int32_t num, int32_t den)
1021 return (num + den / 2) / den;
1025 * http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table
1026 * "calculating table entries"
1029 bwi_rf_calc_txpower(int8_t *txpwr, uint8_t idx, const int16_t pa_params[])
1031 int32_t m1, m2, f, dbm;
1034 m1 = _bwi_adjust_devide(16 * pa_params[0] + idx * pa_params[1], 32);
1035 m2 = imax(_bwi_adjust_devide(32768 + idx * pa_params[2], 256), 1);
1040 for (i = 0; i < ITER_MAX; ++i) {
1043 q = _bwi_adjust_devide(
1044 f * 4096 - _bwi_adjust_devide(m2 * f, 16) * f, 2048);
1056 dbm = _bwi_adjust_devide(m1 * f, 8192);
1067 bwi_rf_map_txpower(struct bwi_mac *mac)
1069 struct bwi_softc *sc = mac->mac_sc;
1070 struct bwi_rf *rf = &mac->mac_rf;
1071 struct bwi_phy *phy = &mac->mac_phy;
1072 uint16_t sprom_ofs, val, mask;
1073 int16_t pa_params[3];
1074 int error = 0, i, ant_gain, reg_txpower_max;
1077 * Find out max TX power
1079 val = bwi_read_sprom(sc, BWI_SPROM_MAX_TXPWR);
1080 if (phy->phy_mode == IEEE80211_MODE_11A) {
1081 rf->rf_txpower_max = __SHIFTOUT(val,
1082 BWI_SPROM_MAX_TXPWR_MASK_11A);
1084 rf->rf_txpower_max = __SHIFTOUT(val,
1085 BWI_SPROM_MAX_TXPWR_MASK_11BG);
1087 if ((sc->sc_card_flags & BWI_CARD_F_PA_GPIO9) &&
1088 phy->phy_mode == IEEE80211_MODE_11G)
1089 rf->rf_txpower_max -= 3;
1091 if (rf->rf_txpower_max <= 0) {
1092 device_printf(sc->sc_dev, "invalid max txpower in sprom\n");
1093 rf->rf_txpower_max = 74;
1095 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1096 "max txpower from sprom: %d dBm\n", rf->rf_txpower_max);
1099 * Find out region/domain max TX power, which is adjusted
1100 * by antenna gain and 1.5 dBm fluctuation as mentioned
1103 val = bwi_read_sprom(sc, BWI_SPROM_ANT_GAIN);
1104 if (phy->phy_mode == IEEE80211_MODE_11A)
1105 ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11A);
1107 ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11BG);
1108 if (ant_gain == 0xff) {
1109 device_printf(sc->sc_dev, "invalid antenna gain in sprom\n");
1113 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1114 "ant gain %d dBm\n", ant_gain);
1116 reg_txpower_max = 90 - ant_gain - 6; /* XXX magic number */
1117 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1118 "region/domain max txpower %d dBm\n", reg_txpower_max);
1121 * Force max TX power within region/domain TX power limit
1123 if (rf->rf_txpower_max > reg_txpower_max)
1124 rf->rf_txpower_max = reg_txpower_max;
1125 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1126 "max txpower %d dBm\n", rf->rf_txpower_max);
1129 * Create TSSI to TX power mapping
1132 if (sc->sc_bbp_id == BWI_BBPID_BCM4301 &&
1133 rf->rf_type != BWI_RF_T_BCM2050) {
1134 rf->rf_idle_tssi0 = BWI_DEFAULT_IDLE_TSSI;
1135 bcopy(bwi_txpower_map_11b, rf->rf_txpower_map0,
1136 sizeof(rf->rf_txpower_map0));
1140 #define IS_VALID_PA_PARAM(p) ((p) != 0 && (p) != -1)
1143 * Extract PA parameters
1145 if (phy->phy_mode == IEEE80211_MODE_11A)
1146 sprom_ofs = BWI_SPROM_PA_PARAM_11A;
1148 sprom_ofs = BWI_SPROM_PA_PARAM_11BG;
1149 for (i = 0; i < NELEM(pa_params); ++i)
1150 pa_params[i] = (int16_t)bwi_read_sprom(sc, sprom_ofs + (i * 2));
1152 for (i = 0; i < NELEM(pa_params); ++i) {
1154 * If one of the PA parameters from SPROM is not valid,
1155 * fall back to the default values, if there are any.
1157 if (!IS_VALID_PA_PARAM(pa_params[i])) {
1158 const int8_t *txpower_map;
1160 if (phy->phy_mode == IEEE80211_MODE_11A) {
1161 if_printf(&sc->sc_ic.ic_if,
1162 "no tssi2dbm table for 11a PHY\n");
1166 if (phy->phy_mode == IEEE80211_MODE_11G) {
1168 BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1169 "%s\n", "use default 11g TSSI map");
1170 txpower_map = bwi_txpower_map_11g;
1173 BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1174 "%s\n", "use default 11b TSSI map");
1175 txpower_map = bwi_txpower_map_11b;
1178 rf->rf_idle_tssi0 = BWI_DEFAULT_IDLE_TSSI;
1179 bcopy(txpower_map, rf->rf_txpower_map0,
1180 sizeof(rf->rf_txpower_map0));
1186 * All of the PA parameters from SPROM are valid.
1190 * Extract idle TSSI from SPROM.
1192 val = bwi_read_sprom(sc, BWI_SPROM_IDLE_TSSI);
1193 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1194 "sprom idle tssi: 0x%04x\n", val);
1196 if (phy->phy_mode == IEEE80211_MODE_11A)
1197 mask = BWI_SPROM_IDLE_TSSI_MASK_11A;
1199 mask = BWI_SPROM_IDLE_TSSI_MASK_11BG;
1201 rf->rf_idle_tssi0 = (int)__SHIFTOUT(val, mask);
1202 if (!IS_VALID_PA_PARAM(rf->rf_idle_tssi0))
1203 rf->rf_idle_tssi0 = 62;
1205 #undef IS_VALID_PA_PARAM
1208 * Calculate TX power map, which is indexed by TSSI
1210 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1211 "%s\n", "TSSI-TX power map:");
1212 for (i = 0; i < BWI_TSSI_MAX; ++i) {
1213 error = bwi_rf_calc_txpower(&rf->rf_txpower_map0[i], i,
1216 if_printf(&sc->sc_ic.ic_if,
1217 "bwi_rf_calc_txpower failed\n");
1222 if (i != 0 && i % 8 == 0) {
1224 BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1228 _DPRINTF(sc, BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1229 "%d ", rf->rf_txpower_map0[i]);
1231 _DPRINTF(sc, BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1234 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1235 "idle tssi0: %d\n", rf->rf_idle_tssi0);
1240 bwi_rf_lo_update_11g(struct bwi_mac *mac)
1242 struct bwi_softc *sc = mac->mac_sc;
1243 struct ifnet *ifp = &sc->sc_ic.ic_if;
1244 struct bwi_rf *rf = &mac->mac_rf;
1245 struct bwi_phy *phy = &mac->mac_phy;
1246 struct bwi_tpctl *tpctl = &mac->mac_tpctl;
1247 struct rf_saveregs regs;
1248 uint16_t ant_div, chan_ex;
1252 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_INIT, "%s enter\n", __func__);
1255 * Save RF/PHY registers for later restoration
1257 orig_chan = rf->rf_curchan;
1258 bzero(®s, sizeof(regs));
1260 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1261 SAVE_PHY_REG(mac, ®s, 429);
1262 SAVE_PHY_REG(mac, ®s, 802);
1264 PHY_WRITE(mac, 0x429, regs.phy_429 & 0x7fff);
1265 PHY_WRITE(mac, 0x802, regs.phy_802 & 0xfffc);
1268 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1269 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div | 0x8000);
1270 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1272 SAVE_PHY_REG(mac, ®s, 15);
1273 SAVE_PHY_REG(mac, ®s, 2a);
1274 SAVE_PHY_REG(mac, ®s, 35);
1275 SAVE_PHY_REG(mac, ®s, 60);
1276 SAVE_RF_REG(mac, ®s, 43);
1277 SAVE_RF_REG(mac, ®s, 7a);
1278 SAVE_RF_REG(mac, ®s, 52);
1279 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1280 SAVE_PHY_REG(mac, ®s, 811);
1281 SAVE_PHY_REG(mac, ®s, 812);
1282 SAVE_PHY_REG(mac, ®s, 814);
1283 SAVE_PHY_REG(mac, ®s, 815);
1286 /* Force to channel 6 */
1287 bwi_rf_set_chan(mac, 6, 0);
1289 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1290 PHY_WRITE(mac, 0x429, regs.phy_429 & 0x7fff);
1291 PHY_WRITE(mac, 0x802, regs.phy_802 & 0xfffc);
1292 bwi_mac_dummy_xmit(mac);
1294 RF_WRITE(mac, 0x43, 0x6);
1296 bwi_phy_set_bbp_atten(mac, 2);
1298 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0);
1300 PHY_WRITE(mac, 0x2e, 0x7f);
1301 PHY_WRITE(mac, 0x80f, 0x78);
1302 PHY_WRITE(mac, 0x35, regs.phy_35 & 0xff7f);
1303 RF_WRITE(mac, 0x7a, regs.rf_7a & 0xfff0);
1304 PHY_WRITE(mac, 0x2b, 0x203);
1305 PHY_WRITE(mac, 0x2a, 0x8a3);
1307 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1308 PHY_WRITE(mac, 0x814, regs.phy_814 | 0x3);
1309 PHY_WRITE(mac, 0x815, regs.phy_815 & 0xfffc);
1310 PHY_WRITE(mac, 0x811, 0x1b3);
1311 PHY_WRITE(mac, 0x812, 0xb2);
1314 if ((ifp->if_flags & IFF_RUNNING) == 0)
1315 tpctl->tp_ctrl2 = bwi_rf_get_tp_ctrl2(mac);
1316 PHY_WRITE(mac, 0x80f, 0x8078);
1321 devi_ctrl = _bwi_rf_lo_update_11g(mac, regs.rf_7a);
1324 * Restore saved RF/PHY registers
1326 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1327 PHY_WRITE(mac, 0x15, 0xe300);
1328 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa0);
1330 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa2);
1332 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa3);
1334 PHY_WRITE(mac, 0x15, devi_ctrl | 0xefa0);
1337 if ((ifp->if_flags & IFF_RUNNING) == 0)
1339 bwi_rf_lo_adjust(mac, tpctl);
1341 PHY_WRITE(mac, 0x2e, 0x807f);
1342 if (phy->phy_flags & BWI_PHY_F_LINKED)
1343 PHY_WRITE(mac, 0x2f, 0x202);
1345 PHY_WRITE(mac, 0x2f, 0x101);
1347 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
1349 RESTORE_PHY_REG(mac, ®s, 15);
1350 RESTORE_PHY_REG(mac, ®s, 2a);
1351 RESTORE_PHY_REG(mac, ®s, 35);
1352 RESTORE_PHY_REG(mac, ®s, 60);
1354 RESTORE_RF_REG(mac, ®s, 43);
1355 RESTORE_RF_REG(mac, ®s, 7a);
1358 regs.rf_52 |= (RF_READ(mac, 0x52) & 0xf);
1359 RF_WRITE(mac, 0x52, regs.rf_52);
1361 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
1363 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1364 RESTORE_PHY_REG(mac, ®s, 811);
1365 RESTORE_PHY_REG(mac, ®s, 812);
1366 RESTORE_PHY_REG(mac, ®s, 814);
1367 RESTORE_PHY_REG(mac, ®s, 815);
1368 RESTORE_PHY_REG(mac, ®s, 429);
1369 RESTORE_PHY_REG(mac, ®s, 802);
1372 bwi_rf_set_chan(mac, orig_chan, 1);
1376 bwi_rf_lo_devi_measure(struct bwi_mac *mac, uint16_t ctrl)
1378 struct bwi_phy *phy = &mac->mac_phy;
1382 if (phy->phy_flags & BWI_PHY_F_LINKED)
1385 for (i = 0; i < 8; ++i) {
1386 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1387 PHY_WRITE(mac, 0x15, 0xe300);
1388 PHY_WRITE(mac, 0x812, ctrl | 0xb0);
1390 PHY_WRITE(mac, 0x812, ctrl | 0xb2);
1392 PHY_WRITE(mac, 0x812, ctrl | 0xb3);
1394 PHY_WRITE(mac, 0x15, 0xf300);
1396 PHY_WRITE(mac, 0x15, ctrl | 0xefa0);
1398 PHY_WRITE(mac, 0x15, ctrl | 0xefe0);
1400 PHY_WRITE(mac, 0x15, ctrl | 0xffe0);
1403 devi += PHY_READ(mac, 0x2d);
1409 bwi_rf_get_tp_ctrl2(struct bwi_mac *mac)
1412 uint16_t tp_ctrl2 = 0;
1415 RF_WRITE(mac, 0x52, 0);
1417 devi_min = bwi_rf_lo_devi_measure(mac, 0);
1419 for (i = 0; i < 16; ++i) {
1422 RF_WRITE(mac, 0x52, i);
1424 devi = bwi_rf_lo_devi_measure(mac, 0);
1426 if (devi < devi_min) {
1435 _bwi_rf_lo_update_11g(struct bwi_mac *mac, uint16_t orig_rf7a)
1437 #define RF_ATTEN_LISTSZ 14
1438 #define BBP_ATTEN_MAX 4 /* half */
1440 static const int rf_atten_list[RF_ATTEN_LISTSZ] =
1441 { 3, 1, 5, 7, 9, 2, 0, 4, 6, 8, 1, 2, 3, 4 };
1442 static const int rf_atten_init_list[RF_ATTEN_LISTSZ] =
1443 { 0, 3, 1, 5, 7, 3, 2, 0, 4, 6, -1, -1, -1, -1 };
1444 static const int rf_lo_measure_order[RF_ATTEN_LISTSZ] =
1445 { 3, 1, 5, 7, 9, 2, 0, 4, 6, 8, 10, 11, 12, 13 };
1447 struct ifnet *ifp = &mac->mac_sc->sc_ic.ic_if;
1448 struct bwi_rf_lo lo_save, *lo;
1449 uint8_t devi_ctrl = 0;
1450 int idx, adj_rf7a = 0;
1452 bzero(&lo_save, sizeof(lo_save));
1453 for (idx = 0; idx < RF_ATTEN_LISTSZ; ++idx) {
1454 int init_rf_atten = rf_atten_init_list[idx];
1455 int rf_atten = rf_atten_list[idx];
1458 for (bbp_atten = 0; bbp_atten < BBP_ATTEN_MAX; ++bbp_atten) {
1459 uint16_t tp_ctrl2, rf7a;
1461 if ((ifp->if_flags & IFF_RUNNING) == 0) {
1463 bzero(&lo_save, sizeof(lo_save));
1464 } else if (init_rf_atten < 0) {
1465 lo = bwi_get_rf_lo(mac,
1466 rf_atten, 2 * bbp_atten);
1467 bcopy(lo, &lo_save, sizeof(lo_save));
1469 lo = bwi_get_rf_lo(mac,
1471 bcopy(lo, &lo_save, sizeof(lo_save));
1479 * Linux driver overflows 'val'
1481 if (init_rf_atten >= 0) {
1484 val = rf_atten * 2 + bbp_atten;
1494 lo = bwi_get_rf_lo(mac,
1495 rf_atten, 2 * bbp_atten);
1496 if (!bwi_rf_lo_isused(mac, lo))
1498 bcopy(lo, &lo_save, sizeof(lo_save));
1504 RF_WRITE(mac, BWI_RFR_ATTEN, rf_atten);
1506 tp_ctrl2 = mac->mac_tpctl.tp_ctrl2;
1507 if (init_rf_atten < 0)
1508 tp_ctrl2 |= (3 << 4);
1509 RF_WRITE(mac, BWI_RFR_TXPWR, tp_ctrl2);
1513 bwi_phy_set_bbp_atten(mac, bbp_atten * 2);
1515 rf7a = orig_rf7a & 0xfff0;
1518 RF_WRITE(mac, 0x7a, rf7a);
1520 lo = bwi_get_rf_lo(mac,
1521 rf_lo_measure_order[idx], bbp_atten * 2);
1522 bwi_rf_lo_measure_11g(mac, &lo_save, lo, devi_ctrl);
1527 #undef RF_ATTEN_LISTSZ
1528 #undef BBP_ATTEN_MAX
1532 bwi_rf_lo_measure_11g(struct bwi_mac *mac, const struct bwi_rf_lo *src_lo,
1533 struct bwi_rf_lo *dst_lo, uint8_t devi_ctrl)
1535 #define LO_ADJUST_MIN 1
1536 #define LO_ADJUST_MAX 8
1537 #define LO_ADJUST(hi, lo) { .ctrl_hi = hi, .ctrl_lo = lo }
1538 static const struct bwi_rf_lo rf_lo_adjust[LO_ADJUST_MAX] = {
1550 struct bwi_rf_lo lo_min;
1552 int found, loop_count, adjust_state;
1554 bcopy(src_lo, &lo_min, sizeof(lo_min));
1555 RF_LO_WRITE(mac, &lo_min);
1556 devi_min = bwi_rf_lo_devi_measure(mac, devi_ctrl);
1558 loop_count = 12; /* XXX */
1561 struct bwi_rf_lo lo_base;
1565 if (adjust_state == 0) {
1567 fin = LO_ADJUST_MAX;
1568 } else if (adjust_state % 2 == 0) {
1569 i = adjust_state - 1;
1570 fin = adjust_state + 1;
1572 i = adjust_state - 2;
1573 fin = adjust_state + 2;
1576 if (i < LO_ADJUST_MIN)
1578 KKASSERT(i <= LO_ADJUST_MAX && i >= LO_ADJUST_MIN);
1580 if (fin > LO_ADJUST_MAX)
1581 fin -= LO_ADJUST_MAX;
1582 KKASSERT(fin <= LO_ADJUST_MAX && fin >= LO_ADJUST_MIN);
1584 bcopy(&lo_min, &lo_base, sizeof(lo_base));
1586 struct bwi_rf_lo lo;
1588 lo.ctrl_hi = lo_base.ctrl_hi +
1589 rf_lo_adjust[i - 1].ctrl_hi;
1590 lo.ctrl_lo = lo_base.ctrl_lo +
1591 rf_lo_adjust[i - 1].ctrl_lo;
1593 if (abs(lo.ctrl_lo) < 9 && abs(lo.ctrl_hi) < 9) {
1596 RF_LO_WRITE(mac, &lo);
1597 devi = bwi_rf_lo_devi_measure(mac, devi_ctrl);
1598 if (devi < devi_min) {
1602 bcopy(&lo, &lo_min, sizeof(lo_min));
1607 if (i == LO_ADJUST_MAX)
1612 } while (loop_count-- && found);
1614 bcopy(&lo_min, dst_lo, sizeof(*dst_lo));
1616 #undef LO_ADJUST_MIN
1617 #undef LO_ADJUST_MAX
1621 bwi_rf_calc_nrssi_slope_11b(struct bwi_mac *mac)
1623 #define SAVE_RF_MAX 3
1624 #define SAVE_PHY_MAX 8
1626 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
1627 { 0x7a, 0x52, 0x43 };
1628 static const uint16_t save_phy_regs[SAVE_PHY_MAX] =
1629 { 0x30, 0x26, 0x15, 0x2a, 0x20, 0x5a, 0x59, 0x58 };
1631 struct bwi_softc *sc = mac->mac_sc;
1632 struct bwi_rf *rf = &mac->mac_rf;
1633 struct bwi_phy *phy = &mac->mac_phy;
1634 uint16_t save_rf[SAVE_RF_MAX];
1635 uint16_t save_phy[SAVE_PHY_MAX];
1636 uint16_t ant_div, bbp_atten, chan_ex;
1641 * Save RF/PHY registers for later restoration
1643 for (i = 0; i < SAVE_RF_MAX; ++i)
1644 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
1645 for (i = 0; i < SAVE_PHY_MAX; ++i)
1646 save_phy[i] = PHY_READ(mac, save_phy_regs[i]);
1648 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1649 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
1650 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1655 if (phy->phy_rev >= 5)
1656 RF_CLRBITS(mac, 0x7a, 0xff80);
1658 RF_CLRBITS(mac, 0x7a, 0xfff0);
1659 PHY_WRITE(mac, 0x30, 0xff);
1661 CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x7f7f);
1663 PHY_WRITE(mac, 0x26, 0);
1664 PHY_SETBITS(mac, 0x15, 0x20);
1665 PHY_WRITE(mac, 0x2a, 0x8a3);
1666 RF_SETBITS(mac, 0x7a, 0x80);
1668 nrssi[0] = (int16_t)PHY_READ(mac, 0x27);
1673 RF_CLRBITS(mac, 0x7a, 0xff80);
1674 if (phy->phy_version >= 2)
1675 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x40);
1676 else if (phy->phy_version == 0)
1677 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
1679 CSR_CLRBITS_2(sc, BWI_RF_CHAN_EX, 0xdfff);
1681 PHY_WRITE(mac, 0x20, 0x3f3f);
1682 PHY_WRITE(mac, 0x15, 0xf330);
1684 RF_WRITE(mac, 0x5a, 0x60);
1685 RF_CLRBITS(mac, 0x43, 0xff0f);
1687 PHY_WRITE(mac, 0x5a, 0x480);
1688 PHY_WRITE(mac, 0x59, 0x810);
1689 PHY_WRITE(mac, 0x58, 0xd);
1693 nrssi[1] = (int16_t)PHY_READ(mac, 0x27);
1696 * Restore saved RF/PHY registers
1698 PHY_WRITE(mac, save_phy_regs[0], save_phy[0]);
1699 RF_WRITE(mac, save_rf_regs[0], save_rf[0]);
1701 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
1703 for (i = 1; i < 4; ++i)
1704 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]);
1706 bwi_rf_workaround(mac, rf->rf_curchan);
1708 if (phy->phy_version != 0)
1709 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
1711 for (; i < SAVE_PHY_MAX; ++i)
1712 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]);
1714 for (i = 1; i < SAVE_RF_MAX; ++i)
1715 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
1718 * Install calculated narrow RSSI values
1720 if (nrssi[0] == nrssi[1])
1721 rf->rf_nrssi_slope = 0x10000;
1723 rf->rf_nrssi_slope = 0x400000 / (nrssi[0] - nrssi[1]);
1724 if (nrssi[0] <= -4) {
1725 rf->rf_nrssi[0] = nrssi[0];
1726 rf->rf_nrssi[1] = nrssi[1];
1734 bwi_rf_set_nrssi_ofs_11g(struct bwi_mac *mac)
1736 #define SAVE_RF_MAX 2
1737 #define SAVE_PHY_COMM_MAX 10
1738 #define SAVE_PHY6_MAX 8
1740 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
1742 static const uint16_t save_phy_comm_regs[SAVE_PHY_COMM_MAX] = {
1743 0x0001, 0x0811, 0x0812, 0x0814,
1744 0x0815, 0x005a, 0x0059, 0x0058,
1747 static const uint16_t save_phy6_regs[SAVE_PHY6_MAX] = {
1748 0x002e, 0x002f, 0x080f, 0x0810,
1749 0x0801, 0x0060, 0x0014, 0x0478
1752 struct bwi_phy *phy = &mac->mac_phy;
1753 uint16_t save_rf[SAVE_RF_MAX];
1754 uint16_t save_phy_comm[SAVE_PHY_COMM_MAX];
1755 uint16_t save_phy6[SAVE_PHY6_MAX];
1756 uint16_t rf7b = 0xffff;
1758 int i, phy6_idx = 0;
1760 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
1761 save_phy_comm[i] = PHY_READ(mac, save_phy_comm_regs[i]);
1762 for (i = 0; i < SAVE_RF_MAX; ++i)
1763 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
1765 PHY_CLRBITS(mac, 0x429, 0x8000);
1766 PHY_FILT_SETBITS(mac, 0x1, 0x3fff, 0x4000);
1767 PHY_SETBITS(mac, 0x811, 0xc);
1768 PHY_FILT_SETBITS(mac, 0x812, 0xfff3, 0x4);
1769 PHY_CLRBITS(mac, 0x802, 0x3);
1771 if (phy->phy_rev >= 6) {
1772 for (i = 0; i < SAVE_PHY6_MAX; ++i)
1773 save_phy6[i] = PHY_READ(mac, save_phy6_regs[i]);
1775 PHY_WRITE(mac, 0x2e, 0);
1776 PHY_WRITE(mac, 0x2f, 0);
1777 PHY_WRITE(mac, 0x80f, 0);
1778 PHY_WRITE(mac, 0x810, 0);
1779 PHY_SETBITS(mac, 0x478, 0x100);
1780 PHY_SETBITS(mac, 0x801, 0x40);
1781 PHY_SETBITS(mac, 0x60, 0x40);
1782 PHY_SETBITS(mac, 0x14, 0x200);
1785 RF_SETBITS(mac, 0x7a, 0x70);
1786 RF_SETBITS(mac, 0x7a, 0x80);
1790 nrssi = bwi_nrssi_11g(mac);
1792 for (i = 7; i >= 4; --i) {
1793 RF_WRITE(mac, 0x7b, i);
1795 nrssi = bwi_nrssi_11g(mac);
1796 if (nrssi < 31 && rf7b == 0xffff)
1802 struct bwi_gains gains;
1804 RF_CLRBITS(mac, 0x7a, 0xff80);
1806 PHY_SETBITS(mac, 0x814, 0x1);
1807 PHY_CLRBITS(mac, 0x815, 0x1);
1808 PHY_SETBITS(mac, 0x811, 0xc);
1809 PHY_SETBITS(mac, 0x812, 0xc);
1810 PHY_SETBITS(mac, 0x811, 0x30);
1811 PHY_SETBITS(mac, 0x812, 0x30);
1812 PHY_WRITE(mac, 0x5a, 0x480);
1813 PHY_WRITE(mac, 0x59, 0x810);
1814 PHY_WRITE(mac, 0x58, 0xd);
1815 if (phy->phy_version == 0)
1816 PHY_WRITE(mac, 0x3, 0x122);
1818 PHY_SETBITS(mac, 0xa, 0x2000);
1819 PHY_SETBITS(mac, 0x814, 0x4);
1820 PHY_CLRBITS(mac, 0x815, 0x4);
1821 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40);
1822 RF_SETBITS(mac, 0x7a, 0xf);
1824 bzero(&gains, sizeof(gains));
1825 gains.tbl_gain1 = 3;
1826 gains.tbl_gain2 = 0;
1828 bwi_set_gains(mac, &gains);
1830 RF_FILT_SETBITS(mac, 0x43, 0xf0, 0xf);
1833 nrssi = bwi_nrssi_11g(mac);
1835 for (i = 0; i < 4; ++i) {
1836 RF_WRITE(mac, 0x7b, i);
1838 nrssi = bwi_nrssi_11g(mac);
1839 if (nrssi > -31 && rf7b == 0xffff)
1848 RF_WRITE(mac, 0x7b, rf7b);
1851 * Restore saved RF/PHY registers
1853 if (phy->phy_rev >= 6) {
1854 for (phy6_idx = 0; phy6_idx < 4; ++phy6_idx) {
1855 PHY_WRITE(mac, save_phy6_regs[phy6_idx],
1856 save_phy6[phy6_idx]);
1860 /* Saved PHY registers 0, 1, 2 are handled later */
1861 for (i = 3; i < SAVE_PHY_COMM_MAX; ++i)
1862 PHY_WRITE(mac, save_phy_comm_regs[i], save_phy_comm[i]);
1864 for (i = SAVE_RF_MAX - 1; i >= 0; --i)
1865 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
1867 PHY_SETBITS(mac, 0x802, 0x3);
1868 PHY_SETBITS(mac, 0x429, 0x8000);
1870 bwi_set_gains(mac, NULL);
1872 if (phy->phy_rev >= 6) {
1873 for (; phy6_idx < SAVE_PHY6_MAX; ++phy6_idx) {
1874 PHY_WRITE(mac, save_phy6_regs[phy6_idx],
1875 save_phy6[phy6_idx]);
1879 PHY_WRITE(mac, save_phy_comm_regs[0], save_phy_comm[0]);
1880 PHY_WRITE(mac, save_phy_comm_regs[2], save_phy_comm[2]);
1881 PHY_WRITE(mac, save_phy_comm_regs[1], save_phy_comm[1]);
1884 #undef SAVE_PHY_COMM_MAX
1885 #undef SAVE_PHY6_MAX
1889 bwi_rf_calc_nrssi_slope_11g(struct bwi_mac *mac)
1891 #define SAVE_RF_MAX 3
1892 #define SAVE_PHY_COMM_MAX 4
1893 #define SAVE_PHY3_MAX 8
1895 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
1896 { 0x7a, 0x52, 0x43 };
1897 static const uint16_t save_phy_comm_regs[SAVE_PHY_COMM_MAX] =
1898 { 0x15, 0x5a, 0x59, 0x58 };
1899 static const uint16_t save_phy3_regs[SAVE_PHY3_MAX] = {
1900 0x002e, 0x002f, 0x080f, 0x0810,
1901 0x0801, 0x0060, 0x0014, 0x0478
1904 struct bwi_softc *sc = mac->mac_sc;
1905 struct bwi_phy *phy = &mac->mac_phy;
1906 struct bwi_rf *rf = &mac->mac_rf;
1907 uint16_t save_rf[SAVE_RF_MAX];
1908 uint16_t save_phy_comm[SAVE_PHY_COMM_MAX];
1909 uint16_t save_phy3[SAVE_PHY3_MAX];
1910 uint16_t ant_div, bbp_atten, chan_ex;
1911 struct bwi_gains gains;
1913 int i, phy3_idx = 0;
1915 if (rf->rf_rev >= 9)
1917 else if (rf->rf_rev == 8)
1918 bwi_rf_set_nrssi_ofs_11g(mac);
1920 PHY_CLRBITS(mac, 0x429, 0x8000);
1921 PHY_CLRBITS(mac, 0x802, 0x3);
1924 * Save RF/PHY registers for later restoration
1926 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1927 CSR_SETBITS_2(sc, BWI_RF_ANTDIV, 0x8000);
1929 for (i = 0; i < SAVE_RF_MAX; ++i)
1930 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
1931 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
1932 save_phy_comm[i] = PHY_READ(mac, save_phy_comm_regs[i]);
1934 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
1935 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1937 if (phy->phy_rev >= 3) {
1938 for (i = 0; i < SAVE_PHY3_MAX; ++i)
1939 save_phy3[i] = PHY_READ(mac, save_phy3_regs[i]);
1941 PHY_WRITE(mac, 0x2e, 0);
1942 PHY_WRITE(mac, 0x810, 0);
1944 if (phy->phy_rev == 4 || phy->phy_rev == 6 ||
1945 phy->phy_rev == 7) {
1946 PHY_SETBITS(mac, 0x478, 0x100);
1947 PHY_SETBITS(mac, 0x810, 0x40);
1948 } else if (phy->phy_rev == 3 || phy->phy_rev == 5) {
1949 PHY_CLRBITS(mac, 0x810, 0x40);
1952 PHY_SETBITS(mac, 0x60, 0x40);
1953 PHY_SETBITS(mac, 0x14, 0x200);
1959 RF_SETBITS(mac, 0x7a, 0x70);
1961 bzero(&gains, sizeof(gains));
1962 gains.tbl_gain1 = 0;
1963 gains.tbl_gain2 = 8;
1965 bwi_set_gains(mac, &gains);
1967 RF_CLRBITS(mac, 0x7a, 0xff08);
1968 if (phy->phy_rev >= 2) {
1969 PHY_FILT_SETBITS(mac, 0x811, 0xffcf, 0x30);
1970 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x10);
1973 RF_SETBITS(mac, 0x7a, 0x80);
1975 nrssi[0] = bwi_nrssi_11g(mac);
1980 RF_CLRBITS(mac, 0x7a, 0xff80);
1981 if (phy->phy_version >= 2)
1982 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40);
1983 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, 0x2000);
1985 RF_SETBITS(mac, 0x7a, 0xf);
1986 PHY_WRITE(mac, 0x15, 0xf330);
1987 if (phy->phy_rev >= 2) {
1988 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x20);
1989 PHY_FILT_SETBITS(mac, 0x811, 0xffcf, 0x20);
1992 bzero(&gains, sizeof(gains));
1993 gains.tbl_gain1 = 3;
1994 gains.tbl_gain2 = 0;
1996 bwi_set_gains(mac, &gains);
1998 if (rf->rf_rev == 8) {
1999 RF_WRITE(mac, 0x43, 0x1f);
2001 RF_FILT_SETBITS(mac, 0x52, 0xff0f, 0x60);
2002 RF_FILT_SETBITS(mac, 0x43, 0xfff0, 0x9);
2004 PHY_WRITE(mac, 0x5a, 0x480);
2005 PHY_WRITE(mac, 0x59, 0x810);
2006 PHY_WRITE(mac, 0x58, 0xd);
2009 nrssi[1] = bwi_nrssi_11g(mac);
2012 * Install calculated narrow RSSI values
2014 if (nrssi[1] == nrssi[0])
2015 rf->rf_nrssi_slope = 0x10000;
2017 rf->rf_nrssi_slope = 0x400000 / (nrssi[0] - nrssi[1]);
2018 if (nrssi[0] >= -4) {
2019 rf->rf_nrssi[0] = nrssi[1];
2020 rf->rf_nrssi[1] = nrssi[0];
2024 * Restore saved RF/PHY registers
2026 if (phy->phy_rev >= 3) {
2027 for (phy3_idx = 0; phy3_idx < 4; ++phy3_idx) {
2028 PHY_WRITE(mac, save_phy3_regs[phy3_idx],
2029 save_phy3[phy3_idx]);
2032 if (phy->phy_rev >= 2) {
2033 PHY_CLRBITS(mac, 0x812, 0x30);
2034 PHY_CLRBITS(mac, 0x811, 0x30);
2037 for (i = 0; i < SAVE_RF_MAX; ++i)
2038 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
2040 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
2041 CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
2042 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
2044 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
2045 PHY_WRITE(mac, save_phy_comm_regs[i], save_phy_comm[i]);
2047 bwi_rf_workaround(mac, rf->rf_curchan);
2048 PHY_SETBITS(mac, 0x802, 0x3);
2049 bwi_set_gains(mac, NULL);
2050 PHY_SETBITS(mac, 0x429, 0x8000);
2052 if (phy->phy_rev >= 3) {
2053 for (; phy3_idx < SAVE_PHY3_MAX; ++phy3_idx) {
2054 PHY_WRITE(mac, save_phy3_regs[phy3_idx],
2055 save_phy3[phy3_idx]);
2059 bwi_rf_init_sw_nrssi_table(mac);
2060 bwi_rf_set_nrssi_thr_11g(mac);
2063 #undef SAVE_PHY_COMM_MAX
2064 #undef SAVE_PHY3_MAX
2068 bwi_rf_init_sw_nrssi_table(struct bwi_mac *mac)
2070 struct bwi_rf *rf = &mac->mac_rf;
2073 d = 0x1f - rf->rf_nrssi[0];
2074 for (i = 0; i < BWI_NRSSI_TBLSZ; ++i) {
2077 val = (((i - d) * rf->rf_nrssi_slope) / 0x10000) + 0x3a;
2080 else if (val > 0x3f)
2083 rf->rf_nrssi_table[i] = val;
2088 bwi_rf_init_hw_nrssi_table(struct bwi_mac *mac, uint16_t adjust)
2092 for (i = 0; i < BWI_NRSSI_TBLSZ; ++i) {
2095 val = bwi_nrssi_read(mac, i);
2103 bwi_nrssi_write(mac, i, val);
2108 bwi_rf_set_nrssi_thr_11b(struct bwi_mac *mac)
2110 struct bwi_rf *rf = &mac->mac_rf;
2113 if (rf->rf_type != BWI_RF_T_BCM2050 ||
2114 (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) == 0)
2118 * Calculate nrssi threshold
2120 if (rf->rf_rev >= 6) {
2121 thr = (rf->rf_nrssi[1] - rf->rf_nrssi[0]) * 32;
2122 thr += 20 * (rf->rf_nrssi[0] + 1);
2125 thr = rf->rf_nrssi[1] - 5;
2129 else if (thr > 0x3e)
2132 PHY_READ(mac, BWI_PHYR_NRSSI_THR_11B); /* dummy read */
2133 PHY_WRITE(mac, BWI_PHYR_NRSSI_THR_11B, (((uint16_t)thr) << 8) | 0x1c);
2135 if (rf->rf_rev >= 6) {
2136 PHY_WRITE(mac, 0x87, 0xe0d);
2137 PHY_WRITE(mac, 0x86, 0xc0b);
2138 PHY_WRITE(mac, 0x85, 0xa09);
2139 PHY_WRITE(mac, 0x84, 0x808);
2140 PHY_WRITE(mac, 0x83, 0x808);
2141 PHY_WRITE(mac, 0x82, 0x604);
2142 PHY_WRITE(mac, 0x81, 0x302);
2143 PHY_WRITE(mac, 0x80, 0x100);
2147 static __inline int32_t
2148 _nrssi_threshold(const struct bwi_rf *rf, int32_t val)
2150 val *= (rf->rf_nrssi[1] - rf->rf_nrssi[0]);
2151 val += (rf->rf_nrssi[0] << 6);
2165 bwi_rf_set_nrssi_thr_11g(struct bwi_mac *mac)
2171 * Find the two nrssi thresholds
2173 if ((mac->mac_phy.phy_flags & BWI_PHY_F_LINKED) == 0 ||
2174 (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) == 0) {
2177 nrssi = bwi_nrssi_read(mac, 0x20);
2189 /* TODO Interfere mode */
2190 thr1 = _nrssi_threshold(&mac->mac_rf, 0x11);
2191 thr2 = _nrssi_threshold(&mac->mac_rf, 0xe);
2194 #define NRSSI_THR1_MASK __BITS(5, 0)
2195 #define NRSSI_THR2_MASK __BITS(11, 6)
2197 thr = __SHIFTIN((uint32_t)thr1, NRSSI_THR1_MASK) |
2198 __SHIFTIN((uint32_t)thr2, NRSSI_THR2_MASK);
2199 PHY_FILT_SETBITS(mac, BWI_PHYR_NRSSI_THR_11G, 0xf000, thr);
2201 #undef NRSSI_THR1_MASK
2202 #undef NRSSI_THR2_MASK
2206 bwi_rf_clear_tssi(struct bwi_mac *mac)
2208 /* XXX use function pointer */
2209 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11A) {
2215 val = __SHIFTIN(BWI_INVALID_TSSI, BWI_LO_TSSI_MASK) |
2216 __SHIFTIN(BWI_INVALID_TSSI, BWI_HI_TSSI_MASK);
2218 for (i = 0; i < 2; ++i) {
2219 MOBJ_WRITE_2(mac, BWI_COMM_MOBJ,
2220 BWI_COMM_MOBJ_TSSI_DS + (i * 2), val);
2223 for (i = 0; i < 2; ++i) {
2224 MOBJ_WRITE_2(mac, BWI_COMM_MOBJ,
2225 BWI_COMM_MOBJ_TSSI_OFDM + (i * 2), val);
2231 bwi_rf_clear_state(struct bwi_rf *rf)
2235 rf->rf_flags &= ~BWI_RF_CLEAR_FLAGS;
2236 bzero(rf->rf_lo, sizeof(rf->rf_lo));
2237 bzero(rf->rf_lo_used, sizeof(rf->rf_lo_used));
2239 rf->rf_nrssi_slope = 0;
2240 rf->rf_nrssi[0] = BWI_INVALID_NRSSI;
2241 rf->rf_nrssi[1] = BWI_INVALID_NRSSI;
2243 for (i = 0; i < BWI_NRSSI_TBLSZ; ++i)
2244 rf->rf_nrssi_table[i] = i;
2249 bcopy(rf->rf_txpower_map0, rf->rf_txpower_map,
2250 sizeof(rf->rf_txpower_map));
2251 rf->rf_idle_tssi = rf->rf_idle_tssi0;
2255 bwi_rf_on_11a(struct bwi_mac *mac)
2261 bwi_rf_on_11bg(struct bwi_mac *mac)
2263 struct bwi_phy *phy = &mac->mac_phy;
2265 PHY_WRITE(mac, 0x15, 0x8000);
2266 PHY_WRITE(mac, 0x15, 0xcc00);
2267 if (phy->phy_flags & BWI_PHY_F_LINKED)
2268 PHY_WRITE(mac, 0x15, 0xc0);
2270 PHY_WRITE(mac, 0x15, 0);
2272 bwi_rf_set_chan(mac, 6 /* XXX */, 1);
2276 bwi_rf_set_ant_mode(struct bwi_mac *mac, int ant_mode)
2278 struct bwi_softc *sc = mac->mac_sc;
2279 struct bwi_phy *phy = &mac->mac_phy;
2282 KKASSERT(ant_mode == BWI_ANT_MODE_0 ||
2283 ant_mode == BWI_ANT_MODE_1 ||
2284 ant_mode == BWI_ANT_MODE_AUTO);
2286 HFLAGS_CLRBITS(mac, BWI_HFLAG_AUTO_ANTDIV);
2288 if (phy->phy_mode == IEEE80211_MODE_11B) {
2289 /* NOTE: v4/v3 conflicts, take v3 */
2290 if (mac->mac_rev == 2)
2291 val = BWI_ANT_MODE_AUTO;
2295 PHY_FILT_SETBITS(mac, 0x3e2, 0xfe7f, val);
2296 } else { /* 11a/g */
2297 /* XXX reg/value naming */
2298 val = ant_mode << 7;
2299 PHY_FILT_SETBITS(mac, 0x401, 0x7e7f, val);
2301 if (ant_mode == BWI_ANT_MODE_AUTO)
2302 PHY_CLRBITS(mac, 0x42b, 0x100);
2304 if (phy->phy_mode == IEEE80211_MODE_11A) {
2307 if (ant_mode == BWI_ANT_MODE_AUTO)
2308 PHY_SETBITS(mac, 0x48c, 0x2000);
2310 PHY_CLRBITS(mac, 0x48c, 0x2000);
2312 if (phy->phy_rev >= 2) {
2313 PHY_SETBITS(mac, 0x461, 0x10);
2314 PHY_FILT_SETBITS(mac, 0x4ad, 0xff00, 0x15);
2315 if (phy->phy_rev == 2) {
2316 PHY_WRITE(mac, 0x427, 0x8);
2318 PHY_FILT_SETBITS(mac, 0x427,
2322 if (phy->phy_rev >= 6)
2323 PHY_WRITE(mac, 0x49b, 0xdc);
2328 /* XXX v4 set AUTO_ANTDIV unconditionally */
2329 if (ant_mode == BWI_ANT_MODE_AUTO)
2330 HFLAGS_SETBITS(mac, BWI_HFLAG_AUTO_ANTDIV);
2332 val = ant_mode << 8;
2333 MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_BEACON,
2335 MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_ACK,
2337 MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_PROBE_RESP,
2340 /* XXX what's these */
2341 if (phy->phy_mode == IEEE80211_MODE_11B)
2342 CSR_SETBITS_2(sc, 0x5e, 0x4);
2344 CSR_WRITE_4(sc, 0x100, 0x1000000);
2345 if (mac->mac_rev < 5)
2346 CSR_WRITE_4(sc, 0x10c, 0x1000000);
2348 mac->mac_rf.rf_ant_mode = ant_mode;
2352 bwi_rf_get_latest_tssi(struct bwi_mac *mac, int8_t tssi[], uint16_t ofs)
2356 for (i = 0; i < 4; ) {
2359 val = MOBJ_READ_2(mac, BWI_COMM_MOBJ, ofs + i);
2360 tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_LO_TSSI_MASK);
2361 tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_HI_TSSI_MASK);
2364 for (i = 0; i < 4; ++i) {
2365 if (tssi[i] == BWI_INVALID_TSSI)
2372 bwi_rf_tssi2dbm(struct bwi_mac *mac, int8_t tssi, int8_t *txpwr)
2374 struct bwi_rf *rf = &mac->mac_rf;
2377 pwr_idx = rf->rf_idle_tssi + (int)tssi - rf->rf_base_tssi;
2379 if (pwr_idx < 0 || pwr_idx >= BWI_TSSI_MAX)
2384 else if (pwr_idx >= BWI_TSSI_MAX)
2385 pwr_idx = BWI_TSSI_MAX - 1;
2388 *txpwr = rf->rf_txpower_map[pwr_idx];
2393 bwi_rf_calc_rssi_bcm2050(struct bwi_mac *mac, const struct bwi_rxbuf_hdr *hdr)
2395 uint16_t flags1, flags3;
2398 rssi = hdr->rxh_rssi;
2399 flags1 = le16toh(hdr->rxh_flags1);
2400 flags3 = le16toh(hdr->rxh_flags3);
2402 #define NEW_BCM2050_RSSI
2403 #ifdef NEW_BCM2050_RSSI
2404 if (flags1 & BWI_RXH_F1_OFDM) {
2407 if (flags3 & BWI_RXH_F3_BCM2050_RSSI)
2414 if (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) {
2415 struct bwi_rf *rf = &mac->mac_rf;
2417 if (rssi >= BWI_NRSSI_TBLSZ)
2418 rssi = BWI_NRSSI_TBLSZ - 1;
2420 rssi = ((31 - (int)rf->rf_nrssi_table[rssi]) * -131) / 128;
2423 rssi = ((31 - rssi) * -149) / 128;
2427 if (mac->mac_phy.phy_mode != IEEE80211_MODE_11G)
2430 if (flags3 & BWI_RXH_F3_BCM2050_RSSI)
2433 lna_gain = __SHIFTOUT(le16toh(hdr->rxh_phyinfo),
2434 BWI_RXH_PHYINFO_LNAGAIN);
2435 DPRINTF(mac->mac_sc, BWI_DBG_RF | BWI_DBG_RX,
2436 "lna_gain %d, phyinfo 0x%04x\n",
2437 lna_gain, le16toh(hdr->rxh_phyinfo));
2451 * According to v3 spec, we should do _nothing_ here,
2452 * but it seems that the result RSSI will be too low
2453 * (relative to what ath(4) says). Raise it a little
2459 panic("impossible lna gain %d", lna_gain);
2461 #else /* !NEW_BCM2050_RSSI */
2462 lna_gain = 0; /* shut up gcc warning */
2464 if (flags1 & BWI_RXH_F1_OFDM) {
2467 rssi = (rssi * 73) / 64;
2469 if (flags3 & BWI_RXH_F3_BCM2050_RSSI)
2476 if (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) {
2477 struct bwi_rf *rf = &mac->mac_rf;
2479 if (rssi >= BWI_NRSSI_TBLSZ)
2480 rssi = BWI_NRSSI_TBLSZ - 1;
2482 rssi = ((31 - (int)rf->rf_nrssi_table[rssi]) * -131) / 128;
2485 rssi = ((31 - rssi) * -149) / 128;
2489 if (mac->mac_phy.phy_mode != IEEE80211_MODE_11G)
2492 if (flags3 & BWI_RXH_F3_BCM2050_RSSI)
2494 #endif /* NEW_BCM2050_RSSI */
2499 bwi_rf_calc_rssi_bcm2053(struct bwi_mac *mac, const struct bwi_rxbuf_hdr *hdr)
2504 rssi = (((int)hdr->rxh_rssi - 11) * 103) / 64;
2506 flags1 = le16toh(hdr->rxh_flags1);
2507 if (flags1 & BWI_RXH_F1_BCM2053_RSSI)
2515 bwi_rf_calc_rssi_bcm2060(struct bwi_mac *mac, const struct bwi_rxbuf_hdr *hdr)
2519 rssi = hdr->rxh_rssi;
2526 bwi_rf_lo_measure_11b(struct bwi_mac *mac)
2532 for (i = 0; i < 10; ++i) {
2533 PHY_WRITE(mac, 0x15, 0xafa0);
2535 PHY_WRITE(mac, 0x15, 0xefa0);
2537 PHY_WRITE(mac, 0x15, 0xffa0);
2540 val += PHY_READ(mac, 0x2c);
2546 bwi_rf_lo_update_11b(struct bwi_mac *mac)
2548 struct bwi_softc *sc = mac->mac_sc;
2549 struct bwi_rf *rf = &mac->mac_rf;
2550 struct rf_saveregs regs;
2551 uint16_t rf_val, phy_val, min_val, val;
2552 uint16_t rf52, bphy_ctrl;
2555 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_INIT, "%s enter\n", __func__);
2557 bzero(®s, sizeof(regs));
2561 * Save RF/PHY registers for later restoration
2563 SAVE_PHY_REG(mac, ®s, 15);
2564 rf52 = RF_READ(mac, 0x52) & 0xfff0;
2565 if (rf->rf_type == BWI_RF_T_BCM2050) {
2566 SAVE_PHY_REG(mac, ®s, 0a);
2567 SAVE_PHY_REG(mac, ®s, 2a);
2568 SAVE_PHY_REG(mac, ®s, 35);
2569 SAVE_PHY_REG(mac, ®s, 03);
2570 SAVE_PHY_REG(mac, ®s, 01);
2571 SAVE_PHY_REG(mac, ®s, 30);
2573 SAVE_RF_REG(mac, ®s, 43);
2574 SAVE_RF_REG(mac, ®s, 7a);
2576 bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL);
2578 SAVE_RF_REG(mac, ®s, 52);
2581 PHY_WRITE(mac, 0x30, 0xff);
2582 CSR_WRITE_2(sc, BWI_PHY_CTRL, 0x3f3f);
2583 PHY_WRITE(mac, 0x35, regs.phy_35 & 0xff7f);
2584 RF_WRITE(mac, 0x7a, regs.rf_7a & 0xfff0);
2587 PHY_WRITE(mac, 0x15, 0xb000);
2589 if (rf->rf_type == BWI_RF_T_BCM2050) {
2590 PHY_WRITE(mac, 0x2b, 0x203);
2591 PHY_WRITE(mac, 0x2a, 0x8a3);
2593 PHY_WRITE(mac, 0x2b, 0x1402);
2600 min_val = UINT16_MAX;
2602 for (i = 0; i < 4; ++i) {
2603 RF_WRITE(mac, 0x52, rf52 | i);
2604 bwi_rf_lo_measure_11b(mac); /* Ignore return value */
2606 for (i = 0; i < 10; ++i) {
2607 RF_WRITE(mac, 0x52, rf52 | i);
2609 val = bwi_rf_lo_measure_11b(mac) / 10;
2610 if (val < min_val) {
2615 RF_WRITE(mac, 0x52, rf52 | rf_val);
2621 min_val = UINT16_MAX;
2623 for (i = -4; i < 5; i += 2) {
2626 for (j = -4; j < 5; j += 2) {
2629 phy2f = (0x100 * i) + j;
2632 PHY_WRITE(mac, 0x2f, phy2f);
2634 val = bwi_rf_lo_measure_11b(mac) / 10;
2635 if (val < min_val) {
2641 PHY_WRITE(mac, 0x2f, phy_val + 0x101);
2644 * Restore saved RF/PHY registers
2646 if (rf->rf_type == BWI_RF_T_BCM2050) {
2647 RESTORE_PHY_REG(mac, ®s, 0a);
2648 RESTORE_PHY_REG(mac, ®s, 2a);
2649 RESTORE_PHY_REG(mac, ®s, 35);
2650 RESTORE_PHY_REG(mac, ®s, 03);
2651 RESTORE_PHY_REG(mac, ®s, 01);
2652 RESTORE_PHY_REG(mac, ®s, 30);
2654 RESTORE_RF_REG(mac, ®s, 43);
2655 RESTORE_RF_REG(mac, ®s, 7a);
2657 RF_FILT_SETBITS(mac, 0x52, 0xf, regs.rf_52);
2659 CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);
2661 RESTORE_PHY_REG(mac, ®s, 15);
2663 bwi_rf_workaround(mac, rf->rf_curchan);