2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <machine/smp.h>
53 #include <machine_base/apic/apicreg.h>
54 #include <machine/atomic.h>
55 #include <machine/cpufunc.h>
56 #include <machine_base/apic/mpapic.h>
57 #include <machine/psl.h>
58 #include <machine/segments.h>
59 #include <machine/tss.h>
60 #include <machine/specialreg.h>
61 #include <machine/globaldata.h>
63 #include <machine/md_var.h> /* setidt() */
64 #include <machine_base/icu/icu.h> /* IPIs */
65 #include <machine_base/isa/intr_machdep.h> /* IPIs */
67 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
69 #define WARMBOOT_TARGET 0
70 #define WARMBOOT_OFF (KERNBASE + 0x0467)
71 #define WARMBOOT_SEG (KERNBASE + 0x0469)
73 #define BIOS_BASE (0xf0000)
74 #define BIOS_SIZE (0x10000)
75 #define BIOS_COUNT (BIOS_SIZE/4)
77 #define CMOS_REG (0x70)
78 #define CMOS_DATA (0x71)
79 #define BIOS_RESET (0x0f)
80 #define BIOS_WARM (0x0a)
82 #define PROCENTRY_FLAG_EN 0x01
83 #define PROCENTRY_FLAG_BP 0x02
84 #define IOAPICENTRY_FLAG_EN 0x01
87 /* MP Floating Pointer Structure */
88 typedef struct MPFPS {
101 /* MP Configuration Table Header */
102 typedef struct MPCTH {
104 u_short base_table_length;
108 u_char product_id[12];
109 void *oem_table_pointer;
110 u_short oem_table_size;
113 u_short extended_table_length;
114 u_char extended_table_checksum;
119 typedef struct PROCENTRY {
124 u_long cpu_signature;
125 u_long feature_flags;
130 typedef struct BUSENTRY {
136 typedef struct IOAPICENTRY {
142 } *io_apic_entry_ptr;
144 typedef struct INTENTRY {
154 /* descriptions of MP basetable entries */
155 typedef struct BASETABLE_ENTRY {
162 * this code MUST be enabled here and in mpboot.s.
163 * it follows the very early stages of AP boot by placing values in CMOS ram.
164 * it NORMALLY will never be needed and thus the primitive method for enabling.
167 #if defined(CHECK_POINTS)
168 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
169 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
171 #define CHECK_INIT(D); \
172 CHECK_WRITE(0x34, (D)); \
173 CHECK_WRITE(0x35, (D)); \
174 CHECK_WRITE(0x36, (D)); \
175 CHECK_WRITE(0x37, (D)); \
176 CHECK_WRITE(0x38, (D)); \
177 CHECK_WRITE(0x39, (D));
179 #define CHECK_PRINT(S); \
180 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
189 #else /* CHECK_POINTS */
191 #define CHECK_INIT(D)
192 #define CHECK_PRINT(S)
194 #endif /* CHECK_POINTS */
197 * Values to send to the POST hardware.
199 #define MP_BOOTADDRESS_POST 0x10
200 #define MP_PROBE_POST 0x11
201 #define MPTABLE_PASS1_POST 0x12
203 #define MP_START_POST 0x13
204 #define MP_ENABLE_POST 0x14
205 #define MPTABLE_PASS2_POST 0x15
207 #define START_ALL_APS_POST 0x16
208 #define INSTALL_AP_TRAMP_POST 0x17
209 #define START_AP_POST 0x18
211 #define MP_ANNOUNCE_POST 0x19
213 static int need_hyperthreading_fixup;
214 static u_int logical_cpus;
215 u_int logical_cpus_mask;
217 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
218 int current_postcode;
220 /** XXX FIXME: what system files declare these??? */
221 extern struct region_descriptor r_gdt, r_idt;
223 int bsp_apic_ready = 0; /* flags useability of BSP apic */
224 int mp_naps; /* # of Applications processors */
225 int mp_nbusses; /* # of busses */
227 int mp_napics; /* # of IO APICs */
229 int boot_cpu_id; /* designated BSP */
230 vm_offset_t cpu_apic_address;
232 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
233 u_int32_t *io_apic_versions;
237 u_int32_t cpu_apic_versions[MAXCPU];
239 extern int64_t tsc_offsets[];
242 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
246 * APIC ID logical/physical mapping structures.
247 * We oversize these to simplify boot-time config.
249 int cpu_num_to_apic_id[NAPICID];
251 int io_num_to_apic_id[NAPICID];
253 int apic_id_to_logical[NAPICID];
255 /* AP uses this during bootstrap. Do not staticize. */
259 /* Hotwire a 0->4MB V==P mapping */
260 extern pt_entry_t *KPTphys;
263 * SMP page table page. Setup by locore to point to a page table
264 * page from which we allocate per-cpu privatespace areas io_apics,
268 #define IO_MAPPING_START_INDEX \
269 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
271 extern pt_entry_t *SMPpt;
272 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
274 struct pcb stoppcbs[MAXCPU];
276 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
278 extern void initializecpu(void);
281 * Local data and functions.
284 static int mp_capable;
285 static u_int boot_address;
286 static u_int base_memory;
287 static int mp_finish;
289 static mpfps_t mpfps;
290 static int search_for_sig(u_int32_t target, int count);
291 static void mp_enable(u_int boot_addr);
293 static void mptable_hyperthread_fixup(u_int id_mask);
294 static void mptable_pass1(void);
295 static int mptable_pass2(void);
296 static void default_mp_table(int type);
297 static void fix_mp_table(void);
299 static void setup_apic_irq_mapping(void);
300 static int apic_int_is_bus_type(int intr, int bus_type);
302 static int start_all_aps(u_int boot_addr);
303 static void install_ap_tramp(u_int boot_addr);
304 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
306 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
307 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
308 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
309 static u_int bootMP_size;
312 * Calculate usable address in base memory for AP trampoline code.
315 mp_bootaddress(u_int basemem)
317 POSTCODE(MP_BOOTADDRESS_POST);
319 bootMP_size = mptramp_end - mptramp_start;
320 base_memory = basemem;
322 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
323 if ((base_memory - boot_address) < bootMP_size)
324 boot_address -= 4096; /* not enough, lower by 4k */
325 /* 3 levels of page table pages */
326 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
328 return mptramp_pagetables;
333 * Look for an Intel MP spec table (ie, SMP capable hardware).
343 * Make sure our SMPpt[] page table is big enough to hold all the
346 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
348 POSTCODE(MP_PROBE_POST);
350 /* see if EBDA exists */
351 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
352 /* search first 1K of EBDA */
353 target = (u_int32_t) (segment << 4);
354 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
357 /* last 1K of base memory, effective 'top of base' passed in */
358 target = (u_int32_t) (base_memory - 0x400);
359 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
363 /* search the BIOS */
364 target = (u_int32_t) BIOS_BASE;
365 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
375 * Calculate needed resources. We can safely map physical
376 * memory into SMPpt after mptable_pass1() completes.
381 /* flag fact that we are running multiple processors */
388 * Startup the SMP processors.
393 POSTCODE(MP_START_POST);
395 /* look for MP capable motherboard */
397 mp_enable(boot_address);
399 panic("MP hardware not found!");
404 * Print various information about the SMP system hardware and setup.
411 POSTCODE(MP_ANNOUNCE_POST);
413 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
414 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
415 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
416 kprintf(", at 0x%08x\n", cpu_apic_address);
417 for (x = 1; x <= mp_naps; ++x) {
418 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
419 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
420 kprintf(", at 0x%08x\n", cpu_apic_address);
424 for (x = 0; x < mp_napics; ++x) {
425 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
426 kprintf(", version: 0x%08x", io_apic_versions[x]);
427 kprintf(", at 0x%08x\n", io_apic_address[x]);
430 kprintf(" Warning: APIC I/O disabled\n");
435 * AP cpu's call this to sync up protected mode.
437 * WARNING! We must ensure that the cpu is sufficiently initialized to
438 * be able to use to the FP for our optimized bzero/bcopy code before
439 * we enter more mainstream C code.
441 * WARNING! %fs is not set up on entry. This routine sets up %fs.
447 int x, myid = bootAP;
449 struct mdglobaldata *md;
450 struct privatespace *ps;
452 ps = &CPU_prvspace[myid];
454 gdt_segs[GPROC0_SEL].ssd_base =
455 (long) &ps->mdglobaldata.gd_common_tss;
456 ps->mdglobaldata.mi.gd_prvspace = ps;
458 /* We fill the 32-bit segment descriptors */
459 for (x = 0; x < NGDT; x++) {
460 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
461 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
463 /* And now a 64-bit one */
464 ssdtosyssd(&gdt_segs[GPROC0_SEL],
465 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
467 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
468 r_gdt.rd_base = (long) &gdt[myid * NGDT];
469 lgdt(&r_gdt); /* does magic intra-segment return */
475 mdcpu->gd_currentldt = _default_ldt;
478 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
479 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
481 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
483 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
485 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
487 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
488 md->gd_common_tssd = *md->gd_tss_gdt;
490 md->gd_common_tss.tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
494 wrmsr(MSR_FSBASE, 0); /* User value */
495 wrmsr(MSR_GSBASE, (u_int64_t)md);
496 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
499 * Set to a known state:
500 * Set by mpboot.s: CR0_PG, CR0_PE
501 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
504 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
507 /* Set up the fast syscall stuff */
508 msr = rdmsr(MSR_EFER) | EFER_SCE;
509 wrmsr(MSR_EFER, msr);
510 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
511 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
512 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
513 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
514 wrmsr(MSR_STAR, msr);
515 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
517 pmap_set_opt(); /* PSE/4MB pages, etc */
519 /* Initialize the PAT MSR. */
523 /* set up CPU registers and state */
526 /* set up SSE/NX registers */
529 /* set up FPU state on the AP */
530 npxinit(__INITIAL_NPXCW__);
533 /*******************************************************************
534 * local functions and data
538 * start the SMP system
541 mp_enable(u_int boot_addr)
549 POSTCODE(MP_ENABLE_POST);
552 /* turn on 4MB of V == P addressing so we can get to MP table */
553 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
556 /* examine the MP table for needed info, uses physical addresses */
563 /* can't process default configs till the CPU APIC is pmapped */
567 /* post scan cleanup */
572 setup_apic_irq_mapping();
574 /* fill the LOGICAL io_apic_versions table */
575 for (apic = 0; apic < mp_napics; ++apic) {
576 ux = io_apic_read(apic, IOAPIC_VER);
577 io_apic_versions[apic] = ux;
578 io_apic_set_id(apic, IO_TO_ID(apic));
581 /* program each IO APIC in the system */
582 for (apic = 0; apic < mp_napics; ++apic)
583 if (io_apic_setup(apic) < 0)
584 panic("IO APIC setup failure");
589 * These are required for SMP operation
592 /* install a 'Spurious INTerrupt' vector */
593 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
594 SDT_SYSIGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
596 /* install an inter-CPU IPI for TLB invalidation */
597 setidt(XINVLTLB_OFFSET, Xinvltlb,
598 SDT_SYSIGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
600 /* install an inter-CPU IPI for IPIQ messaging */
601 setidt(XIPIQ_OFFSET, Xipiq,
602 SDT_SYSIGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
604 /* install a timer vector */
605 setidt(XTIMER_OFFSET, Xtimer,
606 SDT_SYSIGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
608 /* install an inter-CPU IPI for CPU stop/restart */
609 setidt(XCPUSTOP_OFFSET, Xcpustop,
610 SDT_SYSIGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
612 /* start each Application Processor */
613 start_all_aps(boot_addr);
618 * look for the MP spec signature
621 /* string defined by the Intel MP Spec as identifying the MP table */
622 #define MP_SIG 0x5f504d5f /* _MP_ */
623 #define NEXT(X) ((X) += 4)
625 search_for_sig(u_int32_t target, int count)
628 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
630 for (x = 0; x < count; NEXT(x))
631 if (addr[x] == MP_SIG)
632 /* make array index a byte index */
633 return (target + (x * sizeof(u_int32_t)));
639 static basetable_entry basetable_entry_types[] =
641 {0, 20, "Processor"},
648 typedef struct BUSDATA {
650 enum busTypes bus_type;
653 typedef struct INTDATA {
663 typedef struct BUSTYPENAME {
668 static bus_type_name bus_type_table[] =
674 {UNKNOWN_BUSTYPE, "---"},
677 {UNKNOWN_BUSTYPE, "---"},
678 {UNKNOWN_BUSTYPE, "---"},
679 {UNKNOWN_BUSTYPE, "---"},
680 {UNKNOWN_BUSTYPE, "---"},
681 {UNKNOWN_BUSTYPE, "---"},
683 {UNKNOWN_BUSTYPE, "---"},
684 {UNKNOWN_BUSTYPE, "---"},
685 {UNKNOWN_BUSTYPE, "---"},
686 {UNKNOWN_BUSTYPE, "---"},
688 {UNKNOWN_BUSTYPE, "---"}
690 /* from MP spec v1.4, table 5-1 */
691 static int default_data[7][5] =
693 /* nbus, id0, type0, id1, type1 */
694 {1, 0, ISA, 255, 255},
695 {1, 0, EISA, 255, 255},
696 {1, 0, EISA, 255, 255},
697 {1, 0, MCA, 255, 255},
699 {2, 0, EISA, 1, PCI},
705 static bus_datum *bus_data;
708 /* the IO INT data, one entry per possible APIC INTerrupt */
709 static io_int *io_apic_ints;
713 static int processor_entry (proc_entry_ptr entry, int cpu);
714 static int bus_entry (bus_entry_ptr entry, int bus);
716 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
717 static int int_entry (int_entry_ptr entry, int intr);
719 static int lookup_bus_type (char *name);
723 * 1st pass on motherboard's Intel MP specification table.
729 * cpu_apic_address (common to all CPUs)
749 POSTCODE(MPTABLE_PASS1_POST);
752 /* clear various tables */
753 for (x = 0; x < NAPICID; ++x) {
754 io_apic_address[x] = ~0; /* IO APIC address table */
758 /* init everything to empty */
767 /* check for use of 'default' configuration */
768 if (mpfps->mpfb1 != 0) {
769 /* use default addresses */
770 cpu_apic_address = DEFAULT_APIC_BASE;
772 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
775 /* fill in with defaults */
776 mp_naps = 2; /* includes BSP */
777 mp_nbusses = default_data[mpfps->mpfb1 - 1][0];
784 if ((cth = mpfps->pap) == 0)
785 panic("MP Configuration Table Header MISSING!");
787 cpu_apic_address = (vm_offset_t) cth->apic_address;
789 /* walk the table, recording info of interest */
790 totalSize = cth->base_table_length - sizeof(struct MPCTH);
791 position = (u_char *) cth + sizeof(struct MPCTH);
792 count = cth->entry_count;
795 switch (type = *(u_char *) position) {
796 case 0: /* processor_entry */
797 if (((proc_entry_ptr)position)->cpu_flags
798 & PROCENTRY_FLAG_EN) {
801 ((proc_entry_ptr)position)->apic_id;
804 case 1: /* bus_entry */
807 case 2: /* io_apic_entry */
809 if (((io_apic_entry_ptr)position)->apic_flags
810 & IOAPICENTRY_FLAG_EN)
811 io_apic_address[mp_napics++] =
812 (vm_offset_t)((io_apic_entry_ptr)
813 position)->apic_address;
816 case 3: /* int_entry */
821 case 4: /* int_entry */
824 panic("mpfps Base Table HOSED!");
828 totalSize -= basetable_entry_types[type].length;
829 position = (uint8_t *)position +
830 basetable_entry_types[type].length;
834 /* qualify the numbers */
835 if (mp_naps > MAXCPU) {
836 kprintf("Warning: only using %d of %d available CPUs!\n",
841 /* See if we need to fixup HT logical CPUs. */
842 mptable_hyperthread_fixup(id_mask);
846 * This is also used as a counter while starting the APs.
850 --mp_naps; /* subtract the BSP */
855 * 2nd pass on motherboard's Intel MP specification table.
859 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
860 * CPU_TO_ID(N), logical CPU to APIC ID table
861 * IO_TO_ID(N), logical IO to APIC ID table
868 struct PROCENTRY proc;
875 int apic, bus, cpu, intr;
878 POSTCODE(MPTABLE_PASS2_POST);
880 /* Initialize fake proc entry for use with HT fixup. */
881 bzero(&proc, sizeof(proc));
883 proc.cpu_flags = PROCENTRY_FLAG_EN;
886 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
888 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
889 M_DEVBUF, M_WAITOK | M_ZERO);
890 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
893 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
897 for (i = 0; i < mp_napics; i++) {
898 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
902 /* clear various tables */
903 for (x = 0; x < NAPICID; ++x) {
904 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
906 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
907 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
911 /* clear bus data table */
912 for (x = 0; x < mp_nbusses; ++x)
913 bus_data[x].bus_id = 0xff;
916 /* clear IO APIC INT table */
917 for (x = 0; x < (nintrs + 1); ++x) {
918 io_apic_ints[x].int_type = 0xff;
919 io_apic_ints[x].int_vector = 0xff;
923 /* setup the cpu/apic mapping arrays */
926 /* record whether PIC or virtual-wire mode */
927 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, mpfps->mpfb2 & 0x80);
929 /* check for use of 'default' configuration */
930 if (mpfps->mpfb1 != 0)
931 return mpfps->mpfb1; /* return default configuration type */
933 if ((cth = mpfps->pap) == 0)
934 panic("MP Configuration Table Header MISSING!");
936 /* walk the table, recording info of interest */
937 totalSize = cth->base_table_length - sizeof(struct MPCTH);
938 position = (u_char *) cth + sizeof(struct MPCTH);
939 count = cth->entry_count;
940 apic = bus = intr = 0;
941 cpu = 1; /* pre-count the BSP */
944 switch (type = *(u_char *) position) {
946 if (processor_entry(position, cpu))
949 if (need_hyperthreading_fixup) {
951 * Create fake mptable processor entries
952 * and feed them to processor_entry() to
953 * enumerate the logical CPUs.
955 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
956 for (i = 1; i < logical_cpus; i++) {
958 processor_entry(&proc, cpu);
959 logical_cpus_mask |= (1 << cpu);
965 if (bus_entry(position, bus))
970 if (io_apic_entry(position, apic))
976 if (int_entry(position, intr))
981 /* int_entry(position); */
984 panic("mpfps Base Table HOSED!");
988 totalSize -= basetable_entry_types[type].length;
989 position = (uint8_t *)position + basetable_entry_types[type].length;
992 if (boot_cpu_id == -1)
993 panic("NO BSP found!");
995 /* report fact that its NOT a default configuration */
1000 * Check if we should perform a hyperthreading "fix-up" to
1001 * enumerate any logical CPU's that aren't already listed
1004 * XXX: We assume that all of the physical CPUs in the
1005 * system have the same number of logical CPUs.
1007 * XXX: We assume that APIC ID's are allocated such that
1008 * the APIC ID's for a physical processor are aligned
1009 * with the number of logical CPU's in the processor.
1012 mptable_hyperthread_fixup(u_int id_mask)
1016 /* Nothing to do if there is no HTT support. */
1017 if ((cpu_feature & CPUID_HTT) == 0)
1019 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1020 if (logical_cpus <= 1)
1024 * For each APIC ID of a CPU that is set in the mask,
1025 * scan the other candidate APIC ID's for this
1026 * physical processor. If any of those ID's are
1027 * already in the table, then kill the fixup.
1029 for (id = 0; id <= MAXCPU; id++) {
1030 if ((id_mask & 1 << id) == 0)
1032 /* First, make sure we are on a logical_cpus boundary. */
1033 if (id % logical_cpus != 0)
1035 for (i = id + 1; i < id + logical_cpus; i++)
1036 if ((id_mask & 1 << i) != 0)
1041 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1042 * mp_naps right now.
1044 need_hyperthreading_fixup = 1;
1045 mp_naps *= logical_cpus;
1051 assign_apic_irq(int apic, int intpin, int irq)
1055 if (int_to_apicintpin[irq].ioapic != -1)
1056 panic("assign_apic_irq: inconsistent table");
1058 int_to_apicintpin[irq].ioapic = apic;
1059 int_to_apicintpin[irq].int_pin = intpin;
1060 int_to_apicintpin[irq].apic_address = ioapic[apic];
1061 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1063 for (x = 0; x < nintrs; x++) {
1064 if ((io_apic_ints[x].int_type == 0 ||
1065 io_apic_ints[x].int_type == 3) &&
1066 io_apic_ints[x].int_vector == 0xff &&
1067 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1068 io_apic_ints[x].dst_apic_int == intpin)
1069 io_apic_ints[x].int_vector = irq;
1074 revoke_apic_irq(int irq)
1080 if (int_to_apicintpin[irq].ioapic == -1)
1081 panic("revoke_apic_irq: inconsistent table");
1083 oldapic = int_to_apicintpin[irq].ioapic;
1084 oldintpin = int_to_apicintpin[irq].int_pin;
1086 int_to_apicintpin[irq].ioapic = -1;
1087 int_to_apicintpin[irq].int_pin = 0;
1088 int_to_apicintpin[irq].apic_address = NULL;
1089 int_to_apicintpin[irq].redirindex = 0;
1091 for (x = 0; x < nintrs; x++) {
1092 if ((io_apic_ints[x].int_type == 0 ||
1093 io_apic_ints[x].int_type == 3) &&
1094 io_apic_ints[x].int_vector != 0xff &&
1095 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1096 io_apic_ints[x].dst_apic_int == oldintpin)
1097 io_apic_ints[x].int_vector = 0xff;
1105 allocate_apic_irq(int intr)
1111 if (io_apic_ints[intr].int_vector != 0xff)
1112 return; /* Interrupt handler already assigned */
1114 if (io_apic_ints[intr].int_type != 0 &&
1115 (io_apic_ints[intr].int_type != 3 ||
1116 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1117 io_apic_ints[intr].dst_apic_int == 0)))
1118 return; /* Not INT or ExtInt on != (0, 0) */
1121 while (irq < APIC_INTMAPSIZE &&
1122 int_to_apicintpin[irq].ioapic != -1)
1125 if (irq >= APIC_INTMAPSIZE)
1126 return; /* No free interrupt handlers */
1128 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1129 intpin = io_apic_ints[intr].dst_apic_int;
1131 assign_apic_irq(apic, intpin, irq);
1132 io_apic_setup_intpin(apic, intpin);
1137 swap_apic_id(int apic, int oldid, int newid)
1144 return; /* Nothing to do */
1146 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1147 apic, oldid, newid);
1149 /* Swap physical APIC IDs in interrupt entries */
1150 for (x = 0; x < nintrs; x++) {
1151 if (io_apic_ints[x].dst_apic_id == oldid)
1152 io_apic_ints[x].dst_apic_id = newid;
1153 else if (io_apic_ints[x].dst_apic_id == newid)
1154 io_apic_ints[x].dst_apic_id = oldid;
1157 /* Swap physical APIC IDs in IO_TO_ID mappings */
1158 for (oapic = 0; oapic < mp_napics; oapic++)
1159 if (IO_TO_ID(oapic) == newid)
1162 if (oapic < mp_napics) {
1163 kprintf("Changing APIC ID for IO APIC #%d from "
1164 "%d to %d in MP table\n",
1165 oapic, newid, oldid);
1166 IO_TO_ID(oapic) = oldid;
1168 IO_TO_ID(apic) = newid;
1173 fix_id_to_io_mapping(void)
1177 for (x = 0; x < NAPICID; x++)
1180 for (x = 0; x <= mp_naps; x++)
1181 if (CPU_TO_ID(x) < NAPICID)
1182 ID_TO_IO(CPU_TO_ID(x)) = x;
1184 for (x = 0; x < mp_napics; x++)
1185 if (IO_TO_ID(x) < NAPICID)
1186 ID_TO_IO(IO_TO_ID(x)) = x;
1191 first_free_apic_id(void)
1195 for (freeid = 0; freeid < NAPICID; freeid++) {
1196 for (x = 0; x <= mp_naps; x++)
1197 if (CPU_TO_ID(x) == freeid)
1201 for (x = 0; x < mp_napics; x++)
1202 if (IO_TO_ID(x) == freeid)
1213 io_apic_id_acceptable(int apic, int id)
1215 int cpu; /* Logical CPU number */
1216 int oapic; /* Logical IO APIC number for other IO APIC */
1219 return 0; /* Out of range */
1221 for (cpu = 0; cpu <= mp_naps; cpu++)
1222 if (CPU_TO_ID(cpu) == id)
1223 return 0; /* Conflict with CPU */
1225 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1226 if (IO_TO_ID(oapic) == id)
1227 return 0; /* Conflict with other APIC */
1229 return 1; /* ID is acceptable for IO APIC */
1234 io_apic_find_int_entry(int apic, int pin)
1238 /* search each of the possible INTerrupt sources */
1239 for (x = 0; x < nintrs; ++x) {
1240 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1241 (pin == io_apic_ints[x].dst_apic_int))
1242 return (&io_apic_ints[x]);
1250 * parse an Intel MP specification table
1258 int apic; /* IO APIC unit number */
1259 int freeid; /* Free physical APIC ID */
1260 int physid; /* Current physical IO APIC ID */
1263 int bus_0 = 0; /* Stop GCC warning */
1264 int bus_pci = 0; /* Stop GCC warning */
1268 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1269 * did it wrong. The MP spec says that when more than 1 PCI bus
1270 * exists the BIOS must begin with bus entries for the PCI bus and use
1271 * actual PCI bus numbering. This implies that when only 1 PCI bus
1272 * exists the BIOS can choose to ignore this ordering, and indeed many
1273 * MP motherboards do ignore it. This causes a problem when the PCI
1274 * sub-system makes requests of the MP sub-system based on PCI bus
1275 * numbers. So here we look for the situation and renumber the
1276 * busses and associated INTs in an effort to "make it right".
1279 /* find bus 0, PCI bus, count the number of PCI busses */
1280 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1281 if (bus_data[x].bus_id == 0) {
1284 if (bus_data[x].bus_type == PCI) {
1290 * bus_0 == slot of bus with ID of 0
1291 * bus_pci == slot of last PCI bus encountered
1294 /* check the 1 PCI bus case for sanity */
1295 /* if it is number 0 all is well */
1296 if (num_pci_bus == 1 &&
1297 bus_data[bus_pci].bus_id != 0) {
1299 /* mis-numbered, swap with whichever bus uses slot 0 */
1301 /* swap the bus entry types */
1302 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1303 bus_data[bus_0].bus_type = PCI;
1306 /* swap each relavant INTerrupt entry */
1307 id = bus_data[bus_pci].bus_id;
1308 for (x = 0; x < nintrs; ++x) {
1309 if (io_apic_ints[x].src_bus_id == id) {
1310 io_apic_ints[x].src_bus_id = 0;
1312 else if (io_apic_ints[x].src_bus_id == 0) {
1313 io_apic_ints[x].src_bus_id = id;
1320 /* Assign IO APIC IDs.
1322 * First try the existing ID. If a conflict is detected, try
1323 * the ID in the MP table. If a conflict is still detected, find
1326 * We cannot use the ID_TO_IO table before all conflicts has been
1327 * resolved and the table has been corrected.
1329 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1331 /* First try to use the value set by the BIOS */
1332 physid = io_apic_get_id(apic);
1333 if (io_apic_id_acceptable(apic, physid)) {
1334 if (IO_TO_ID(apic) != physid)
1335 swap_apic_id(apic, IO_TO_ID(apic), physid);
1339 /* Then check if the value in the MP table is acceptable */
1340 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1343 /* Last resort, find a free APIC ID and use it */
1344 freeid = first_free_apic_id();
1345 if (freeid >= NAPICID)
1346 panic("No free physical APIC IDs found");
1348 if (io_apic_id_acceptable(apic, freeid)) {
1349 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1352 panic("Free physical APIC ID not usable");
1354 fix_id_to_io_mapping();
1358 /* detect and fix broken Compaq MP table */
1359 if (apic_int_type(0, 0) == -1) {
1360 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1361 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1362 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1363 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1364 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1365 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1367 } else if (apic_int_type(0, 0) == 0) {
1368 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1369 for (x = 0; x < nintrs; ++x)
1370 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1371 (0 == io_apic_ints[x].dst_apic_int)) {
1372 io_apic_ints[x].int_type = 3;
1373 io_apic_ints[x].int_vector = 0xff;
1379 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1380 * controllers universally come in pairs. If IRQ 14 is specified
1381 * as an ISA interrupt, then IRQ 15 had better be too.
1383 * [ Shuttle XPC / AMD Athlon X2 ]
1384 * The MPTable is missing an entry for IRQ 15. Note that the
1385 * ACPI table has an entry for both 14 and 15.
1387 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1388 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1389 io14 = io_apic_find_int_entry(0, 14);
1390 io_apic_ints[nintrs] = *io14;
1391 io_apic_ints[nintrs].src_bus_irq = 15;
1392 io_apic_ints[nintrs].dst_apic_int = 15;
1400 /* Assign low level interrupt handlers */
1402 setup_apic_irq_mapping(void)
1408 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1409 int_to_apicintpin[x].ioapic = -1;
1410 int_to_apicintpin[x].int_pin = 0;
1411 int_to_apicintpin[x].apic_address = NULL;
1412 int_to_apicintpin[x].redirindex = 0;
1415 /* First assign ISA/EISA interrupts */
1416 for (x = 0; x < nintrs; x++) {
1417 int_vector = io_apic_ints[x].src_bus_irq;
1418 if (int_vector < APIC_INTMAPSIZE &&
1419 io_apic_ints[x].int_vector == 0xff &&
1420 int_to_apicintpin[int_vector].ioapic == -1 &&
1421 (apic_int_is_bus_type(x, ISA) ||
1422 apic_int_is_bus_type(x, EISA)) &&
1423 io_apic_ints[x].int_type == 0) {
1424 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1425 io_apic_ints[x].dst_apic_int,
1430 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1431 for (x = 0; x < nintrs; x++) {
1432 if (io_apic_ints[x].dst_apic_int == 0 &&
1433 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1434 io_apic_ints[x].int_vector == 0xff &&
1435 int_to_apicintpin[0].ioapic == -1 &&
1436 io_apic_ints[x].int_type == 3) {
1437 assign_apic_irq(0, 0, 0);
1441 /* PCI interrupt assignment is deferred */
1447 processor_entry(proc_entry_ptr entry, int cpu)
1449 /* check for usability */
1450 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1453 if(entry->apic_id >= NAPICID)
1454 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1455 /* check for BSP flag */
1456 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1457 boot_cpu_id = entry->apic_id;
1458 CPU_TO_ID(0) = entry->apic_id;
1459 ID_TO_CPU(entry->apic_id) = 0;
1460 return 0; /* its already been counted */
1463 /* add another AP to list, if less than max number of CPUs */
1464 else if (cpu < MAXCPU) {
1465 CPU_TO_ID(cpu) = entry->apic_id;
1466 ID_TO_CPU(entry->apic_id) = cpu;
1475 bus_entry(bus_entry_ptr entry, int bus)
1480 /* encode the name into an index */
1481 for (x = 0; x < 6; ++x) {
1482 if ((c = entry->bus_type[x]) == ' ')
1488 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1489 panic("unknown bus type: '%s'", name);
1491 bus_data[bus].bus_id = entry->bus_id;
1492 bus_data[bus].bus_type = x;
1500 io_apic_entry(io_apic_entry_ptr entry, int apic)
1502 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1505 IO_TO_ID(apic) = entry->apic_id;
1506 if (entry->apic_id < NAPICID)
1507 ID_TO_IO(entry->apic_id) = apic;
1515 lookup_bus_type(char *name)
1519 for (x = 0; x < MAX_BUSTYPE; ++x)
1520 if (strcmp(bus_type_table[x].name, name) == 0)
1521 return bus_type_table[x].type;
1523 return UNKNOWN_BUSTYPE;
1529 int_entry(int_entry_ptr entry, int intr)
1533 io_apic_ints[intr].int_type = entry->int_type;
1534 io_apic_ints[intr].int_flags = entry->int_flags;
1535 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1536 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1537 if (entry->dst_apic_id == 255) {
1538 /* This signal goes to all IO APICS. Select an IO APIC
1539 with sufficient number of interrupt pins */
1540 for (apic = 0; apic < mp_napics; apic++)
1541 if (((io_apic_read(apic, IOAPIC_VER) &
1542 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1543 entry->dst_apic_int)
1545 if (apic < mp_napics)
1546 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1548 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1550 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1551 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1557 apic_int_is_bus_type(int intr, int bus_type)
1561 for (bus = 0; bus < mp_nbusses; ++bus)
1562 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1563 && ((int) bus_data[bus].bus_type == bus_type))
1570 * Given a traditional ISA INT mask, return an APIC mask.
1573 isa_apic_mask(u_int isa_mask)
1578 #if defined(SKIP_IRQ15_REDIRECT)
1579 if (isa_mask == (1 << 15)) {
1580 kprintf("skipping ISA IRQ15 redirect\n");
1583 #endif /* SKIP_IRQ15_REDIRECT */
1585 isa_irq = ffs(isa_mask); /* find its bit position */
1586 if (isa_irq == 0) /* doesn't exist */
1588 --isa_irq; /* make it zero based */
1590 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1594 return (1 << apic_pin); /* convert pin# to a mask */
1598 * Determine which APIC pin an ISA/EISA INT is attached to.
1600 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1601 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1602 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1603 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1605 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1607 isa_apic_irq(int isa_irq)
1611 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1612 if (INTTYPE(intr) == 0) { /* standard INT */
1613 if (SRCBUSIRQ(intr) == isa_irq) {
1614 if (apic_int_is_bus_type(intr, ISA) ||
1615 apic_int_is_bus_type(intr, EISA)) {
1616 if (INTIRQ(intr) == 0xff)
1617 return -1; /* unassigned */
1618 return INTIRQ(intr); /* found */
1623 return -1; /* NOT found */
1628 * Determine which APIC pin a PCI INT is attached to.
1630 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1631 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1632 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1634 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1638 --pciInt; /* zero based */
1640 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1641 if ((INTTYPE(intr) == 0) /* standard INT */
1642 && (SRCBUSID(intr) == pciBus)
1643 && (SRCBUSDEVICE(intr) == pciDevice)
1644 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1645 if (apic_int_is_bus_type(intr, PCI)) {
1646 if (INTIRQ(intr) == 0xff)
1647 allocate_apic_irq(intr);
1648 if (INTIRQ(intr) == 0xff)
1649 return -1; /* unassigned */
1650 return INTIRQ(intr); /* exact match */
1655 return -1; /* NOT found */
1659 next_apic_irq(int irq)
1666 for (intr = 0; intr < nintrs; intr++) {
1667 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1669 bus = SRCBUSID(intr);
1670 bustype = apic_bus_type(bus);
1671 if (bustype != ISA &&
1677 if (intr >= nintrs) {
1680 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1681 if (INTTYPE(ointr) != 0)
1683 if (bus != SRCBUSID(ointr))
1685 if (bustype == PCI) {
1686 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1688 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1691 if (bustype == ISA || bustype == EISA) {
1692 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1695 if (INTPIN(intr) == INTPIN(ointr))
1699 if (ointr >= nintrs) {
1702 return INTIRQ(ointr);
1717 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1720 * Exactly what this means is unclear at this point. It is a solution
1721 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1722 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1723 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1727 undirect_isa_irq(int rirq)
1731 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1732 /** FIXME: tickle the MB redirector chip */
1736 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1743 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1746 undirect_pci_irq(int rirq)
1750 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1752 /** FIXME: tickle the MB redirector chip */
1756 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1764 * given a bus ID, return:
1765 * the bus type if found
1769 apic_bus_type(int id)
1773 for (x = 0; x < mp_nbusses; ++x)
1774 if (bus_data[x].bus_id == id)
1775 return bus_data[x].bus_type;
1783 * given a LOGICAL APIC# and pin#, return:
1784 * the associated src bus ID if found
1788 apic_src_bus_id(int apic, int pin)
1792 /* search each of the possible INTerrupt sources */
1793 for (x = 0; x < nintrs; ++x)
1794 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1795 (pin == io_apic_ints[x].dst_apic_int))
1796 return (io_apic_ints[x].src_bus_id);
1798 return -1; /* NOT found */
1802 * given a LOGICAL APIC# and pin#, return:
1803 * the associated src bus IRQ if found
1807 apic_src_bus_irq(int apic, int pin)
1811 for (x = 0; x < nintrs; x++)
1812 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1813 (pin == io_apic_ints[x].dst_apic_int))
1814 return (io_apic_ints[x].src_bus_irq);
1816 return -1; /* NOT found */
1821 * given a LOGICAL APIC# and pin#, return:
1822 * the associated INTerrupt type if found
1826 apic_int_type(int apic, int pin)
1830 /* search each of the possible INTerrupt sources */
1831 for (x = 0; x < nintrs; ++x) {
1832 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1833 (pin == io_apic_ints[x].dst_apic_int))
1834 return (io_apic_ints[x].int_type);
1836 return -1; /* NOT found */
1840 * Return the IRQ associated with an APIC pin
1843 apic_irq(int apic, int pin)
1848 for (x = 0; x < nintrs; ++x) {
1849 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1850 (pin == io_apic_ints[x].dst_apic_int)) {
1851 res = io_apic_ints[x].int_vector;
1854 if (apic != int_to_apicintpin[res].ioapic)
1855 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1856 if (pin != int_to_apicintpin[res].int_pin)
1857 panic("apic_irq inconsistent table (2)");
1866 * given a LOGICAL APIC# and pin#, return:
1867 * the associated trigger mode if found
1871 apic_trigger(int apic, int pin)
1875 /* search each of the possible INTerrupt sources */
1876 for (x = 0; x < nintrs; ++x)
1877 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1878 (pin == io_apic_ints[x].dst_apic_int))
1879 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1881 return -1; /* NOT found */
1886 * given a LOGICAL APIC# and pin#, return:
1887 * the associated 'active' level if found
1891 apic_polarity(int apic, int pin)
1895 /* search each of the possible INTerrupt sources */
1896 for (x = 0; x < nintrs; ++x)
1897 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1898 (pin == io_apic_ints[x].dst_apic_int))
1899 return (io_apic_ints[x].int_flags & 0x03);
1901 return -1; /* NOT found */
1907 * set data according to MP defaults
1908 * FIXME: probably not complete yet...
1911 default_mp_table(int type)
1914 #if defined(APIC_IO)
1917 #endif /* APIC_IO */
1920 kprintf(" MP default config type: %d\n", type);
1923 kprintf(" bus: ISA, APIC: 82489DX\n");
1926 kprintf(" bus: EISA, APIC: 82489DX\n");
1929 kprintf(" bus: EISA, APIC: 82489DX\n");
1932 kprintf(" bus: MCA, APIC: 82489DX\n");
1935 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
1938 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
1941 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
1944 kprintf(" future type\n");
1950 boot_cpu_id = (lapic->id & APIC_ID_MASK) >> 24;
1951 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1954 CPU_TO_ID(0) = boot_cpu_id;
1955 ID_TO_CPU(boot_cpu_id) = 0;
1957 /* one and only AP */
1958 CPU_TO_ID(1) = ap_cpu_id;
1959 ID_TO_CPU(ap_cpu_id) = 1;
1961 #if defined(APIC_IO)
1962 /* one and only IO APIC */
1963 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1966 * sanity check, refer to MP spec section 3.6.6, last paragraph
1967 * necessary as some hardware isn't properly setting up the IO APIC
1969 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1970 if (io_apic_id != 2) {
1972 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1973 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1974 io_apic_set_id(0, 2);
1977 IO_TO_ID(0) = io_apic_id;
1978 ID_TO_IO(io_apic_id) = 0;
1979 #endif /* APIC_IO */
1981 /* fill out bus entries */
1990 bus_data[0].bus_id = default_data[type - 1][1];
1991 bus_data[0].bus_type = default_data[type - 1][2];
1992 bus_data[1].bus_id = default_data[type - 1][3];
1993 bus_data[1].bus_type = default_data[type - 1][4];
1996 /* case 4: case 7: MCA NOT supported */
1997 default: /* illegal/reserved */
1998 panic("BAD default MP config: %d", type);
2002 #if defined(APIC_IO)
2003 /* general cases from MP v1.4, table 5-2 */
2004 for (pin = 0; pin < 16; ++pin) {
2005 io_apic_ints[pin].int_type = 0;
2006 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2007 io_apic_ints[pin].src_bus_id = 0;
2008 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2009 io_apic_ints[pin].dst_apic_id = io_apic_id;
2010 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2013 /* special cases from MP v1.4, table 5-2 */
2015 io_apic_ints[2].int_type = 0xff; /* N/C */
2016 io_apic_ints[13].int_type = 0xff; /* N/C */
2017 #if !defined(APIC_MIXED_MODE)
2019 panic("sorry, can't support type 2 default yet");
2020 #endif /* APIC_MIXED_MODE */
2023 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2026 io_apic_ints[0].int_type = 0xff; /* N/C */
2028 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2029 #endif /* APIC_IO */
2033 * Map a physical memory address representing I/O into KVA. The I/O
2034 * block is assumed not to cross a page boundary.
2037 permanent_io_mapping(vm_paddr_t pa)
2043 KKASSERT(pa < 0x100000000LL);
2045 pgeflag = 0; /* not used for SMP yet */
2048 * If the requested physical address has already been incidently
2049 * mapped, just use the existing mapping. Otherwise create a new
2052 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2053 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2054 ((vm_offset_t)pa & PG_FRAME)) {
2058 if (i == SMPpt_alloc_index) {
2059 if (i == NPTEPG - 2) {
2060 panic("permanent_io_mapping: We ran out of space"
2063 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | pgeflag |
2064 ((vm_offset_t)pa & PG_FRAME));
2065 ++SMPpt_alloc_index;
2067 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2068 ((vm_offset_t)pa & PAGE_MASK);
2069 return ((void *)vaddr);
2073 * start each AP in our list
2076 start_all_aps(u_int boot_addr)
2078 vm_offset_t va = boot_address + KERNBASE;
2079 u_int64_t *pt4, *pt3, *pt2;
2082 u_char mpbiosreason;
2083 u_long mpbioswarmvec;
2084 struct mdglobaldata *gd;
2085 struct privatespace *ps;
2089 POSTCODE(START_ALL_APS_POST);
2091 /* Initialize BSP's local APIC */
2092 apic_initialize(TRUE);
2095 /* install the AP 1st level boot code */
2096 pmap_kenter(va, boot_address);
2097 cpu_invlpg(va); /* JG XXX */
2098 bcopy(mptramp_start, (void *)va, bootMP_size);
2100 /* Locate the page tables, they'll be below the trampoline */
2101 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2102 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2103 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2105 /* Create the initial 1GB replicated page tables */
2106 for (i = 0; i < 512; i++) {
2107 /* Each slot of the level 4 pages points to the same level 3 page */
2108 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2109 pt4[i] |= PG_V | PG_RW | PG_U;
2111 /* Each slot of the level 3 pages points to the same level 2 page */
2112 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2113 pt3[i] |= PG_V | PG_RW | PG_U;
2115 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2116 pt2[i] = i * (2 * 1024 * 1024);
2117 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2120 /* save the current value of the warm-start vector */
2121 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2122 outb(CMOS_REG, BIOS_RESET);
2123 mpbiosreason = inb(CMOS_DATA);
2125 /* setup a vector to our boot code */
2126 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2127 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2128 outb(CMOS_REG, BIOS_RESET);
2129 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2132 for (x = 1; x <= mp_naps; ++x) {
2134 /* This is a bit verbose, it will go away soon. */
2136 /* first page of AP's private space */
2137 pg = x * amd64_btop(sizeof(struct privatespace));
2139 /* allocate new private data page(s) */
2140 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2141 MDGLOBALDATA_BASEALLOC_SIZE);
2143 /* wire it into the private page table page */
2144 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2145 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2146 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2148 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2150 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2151 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2152 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2153 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2155 /* allocate and set up an idle stack data page */
2156 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2157 for (i = 0; i < UPAGES; i++) {
2158 SMPpt[pg + 4 + i] = (pt_entry_t)
2159 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2163 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2164 bzero(gd, sizeof(*gd));
2165 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2167 /* prime data page for it to use */
2168 mi_gdinit(&gd->mi, x);
2170 gd->gd_CMAP1 = &SMPpt[pg + 0];
2171 gd->gd_CMAP2 = &SMPpt[pg + 1];
2172 gd->gd_CMAP3 = &SMPpt[pg + 2];
2173 gd->gd_PMAP1 = &SMPpt[pg + 3];
2174 gd->gd_CADDR1 = ps->CPAGE1;
2175 gd->gd_CADDR2 = ps->CPAGE2;
2176 gd->gd_CADDR3 = ps->CPAGE3;
2177 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2178 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2179 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2181 /* setup a vector to our boot code */
2182 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2183 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2184 outb(CMOS_REG, BIOS_RESET);
2185 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2188 * Setup the AP boot stack
2190 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2193 /* attempt to start the Application Processor */
2194 CHECK_INIT(99); /* setup checkpoints */
2195 if (!start_ap(gd, boot_addr)) {
2196 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2197 CHECK_PRINT("trace"); /* show checkpoints */
2198 /* better panic as the AP may be running loose */
2199 kprintf("panic y/n? [y] ");
2200 if (cngetc() != 'n')
2203 CHECK_PRINT("trace"); /* show checkpoints */
2205 /* record its version info */
2206 cpu_apic_versions[x] = cpu_apic_versions[0];
2209 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2212 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2213 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2216 ncpus2_shift = shift;
2217 ncpus2 = 1 << shift;
2218 ncpus2_mask = ncpus2 - 1;
2220 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2221 if ((1 << shift) < ncpus)
2223 ncpus_fit = 1 << shift;
2224 ncpus_fit_mask = ncpus_fit - 1;
2226 /* build our map of 'other' CPUs */
2227 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2228 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2229 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2231 /* fill in our (BSP) APIC version */
2232 cpu_apic_versions[0] = lapic->version;
2234 /* restore the warmstart vector */
2235 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2236 outb(CMOS_REG, BIOS_RESET);
2237 outb(CMOS_DATA, mpbiosreason);
2240 * NOTE! The idlestack for the BSP was setup by locore. Finish
2241 * up, clean out the P==V mapping we did earlier.
2244 for (x = 0; x < NKPT; x++)
2249 /* number of APs actually started */
2255 * load the 1st level AP boot code into base memory.
2258 /* targets for relocation */
2259 extern void bigJump(void);
2260 extern void bootCodeSeg(void);
2261 extern void bootDataSeg(void);
2262 extern void MPentry(void);
2263 extern u_int MP_GDT;
2264 extern u_int mp_gdtbase;
2267 install_ap_tramp(u_int boot_addr)
2270 int size = *(int *) ((u_long) & bootMP_size);
2271 u_char *src = (u_char *) ((u_long) bootMP);
2272 u_char *dst = (u_char *) boot_addr + KERNBASE;
2273 u_int boot_base = (u_int) bootMP;
2278 POSTCODE(INSTALL_AP_TRAMP_POST);
2280 for (x = 0; x < size; ++x)
2284 * modify addresses in code we just moved to basemem. unfortunately we
2285 * need fairly detailed info about mpboot.s for this to work. changes
2286 * to mpboot.s might require changes here.
2289 /* boot code is located in KERNEL space */
2290 dst = (u_char *) boot_addr + KERNBASE;
2292 /* modify the lgdt arg */
2293 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2294 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2296 /* modify the ljmp target for MPentry() */
2297 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2298 *dst32 = ((u_int) MPentry - KERNBASE);
2300 /* modify the target for boot code segment */
2301 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2302 dst8 = (u_int8_t *) (dst16 + 1);
2303 *dst16 = (u_int) boot_addr & 0xffff;
2304 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2306 /* modify the target for boot data segment */
2307 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2308 dst8 = (u_int8_t *) (dst16 + 1);
2309 *dst16 = (u_int) boot_addr & 0xffff;
2310 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2315 * this function starts the AP (application processor) identified
2316 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2317 * to accomplish this. This is necessary because of the nuances
2318 * of the different hardware we might encounter. It ain't pretty,
2319 * but it seems to work.
2321 * NOTE: eventually an AP gets to ap_init(), which is called just
2322 * before the AP goes into the LWKT scheduler's idle loop.
2325 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2329 u_long icr_lo, icr_hi;
2331 POSTCODE(START_AP_POST);
2333 /* get the PHYSICAL APIC ID# */
2334 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2336 /* calculate the vector */
2337 vector = (boot_addr >> 12) & 0xff;
2339 /* Make sure the target cpu sees everything */
2343 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2344 * and running the target CPU. OR this INIT IPI might be latched (P5
2345 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2349 /* setup the address for the target AP */
2350 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2351 icr_hi |= (physical_cpu << 24);
2352 lapic->icr_hi = icr_hi;
2354 /* do an INIT IPI: assert RESET */
2355 icr_lo = lapic->icr_lo & 0xfff00000;
2356 lapic->icr_lo = icr_lo | 0x0000c500;
2358 /* wait for pending status end */
2359 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2362 /* do an INIT IPI: deassert RESET */
2363 lapic->icr_lo = icr_lo | 0x00008500;
2365 /* wait for pending status end */
2366 u_sleep(10000); /* wait ~10mS */
2367 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2371 * next we do a STARTUP IPI: the previous INIT IPI might still be
2372 * latched, (P5 bug) this 1st STARTUP would then terminate
2373 * immediately, and the previously started INIT IPI would continue. OR
2374 * the previous INIT IPI has already run. and this STARTUP IPI will
2375 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2379 /* do a STARTUP IPI */
2380 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2381 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2383 u_sleep(200); /* wait ~200uS */
2386 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2387 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2388 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2389 * recognized after hardware RESET or INIT IPI.
2392 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2393 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2395 u_sleep(200); /* wait ~200uS */
2397 /* wait for it to start, see ap_init() */
2398 set_apic_timer(5000000);/* == 5 seconds */
2399 while (read_apic_timer()) {
2400 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2401 return 1; /* return SUCCESS */
2403 return 0; /* return FAILURE */
2408 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2410 * If for some reason we were unable to start all cpus we cannot safely
2411 * use broadcast IPIs.
2417 if (smp_startup_mask == smp_active_mask) {
2418 all_but_self_ipi(XINVLTLB_OFFSET);
2420 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2421 APIC_DELMODE_FIXED);
2427 * When called the executing CPU will send an IPI to all other CPUs
2428 * requesting that they halt execution.
2430 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2432 * - Signals all CPUs in map to stop.
2433 * - Waits for each to stop.
2440 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2441 * from executing at same time.
2444 stop_cpus(u_int map)
2446 map &= smp_active_mask;
2448 /* send the Xcpustop IPI to all CPUs in map */
2449 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2451 while ((stopped_cpus & map) != map)
2459 * Called by a CPU to restart stopped CPUs.
2461 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2463 * - Signals all CPUs in map to restart.
2464 * - Waits for each to restart.
2472 restart_cpus(u_int map)
2474 /* signal other cpus to restart */
2475 started_cpus = map & smp_active_mask;
2477 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2484 * This is called once the mpboot code has gotten us properly relocated
2485 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2486 * and when it returns the scheduler will call the real cpu_idle() main
2487 * loop for the idlethread. Interrupts are disabled on entry and should
2488 * remain disabled at return.
2496 * Adjust smp_startup_mask to signal the BSP that we have started
2497 * up successfully. Note that we do not yet hold the BGL. The BSP
2498 * is waiting for our signal.
2500 * We can't set our bit in smp_active_mask yet because we are holding
2501 * interrupts physically disabled and remote cpus could deadlock
2502 * trying to send us an IPI.
2504 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2508 * Interlock for finalization. Wait until mp_finish is non-zero,
2509 * then get the MP lock.
2511 * Note: We are in a critical section.
2513 * Note: We have to synchronize td_mpcount to our desired MP state
2514 * before calling cpu_try_mplock().
2516 * Note: we are the idle thread, we can only spin.
2518 * Note: The load fence is memory volatile and prevents the compiler
2519 * from improperly caching mp_finish, and the cpu from improperly
2522 while (mp_finish == 0)
2524 ++curthread->td_mpcount;
2525 while (cpu_try_mplock() == 0)
2528 if (cpu_feature & CPUID_TSC) {
2530 * The BSP is constantly updating tsc0_offset, figure out the
2531 * relative difference to synchronize ktrdump.
2533 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2536 /* BSP may have changed PTD while we're waiting for the lock */
2539 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2543 /* Build our map of 'other' CPUs. */
2544 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2546 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2548 /* A quick check from sanity claus */
2549 apic_id = (apic_id_to_logical[(lapic->id & 0x0f000000) >> 24]);
2550 if (mycpu->gd_cpuid != apic_id) {
2551 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2552 kprintf("SMP: apic_id = %d\n", apic_id);
2554 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2556 panic("cpuid mismatch! boom!!");
2559 /* Initialize AP's local APIC for irq's */
2560 apic_initialize(FALSE);
2562 /* Set memory range attributes for this CPU to match the BSP */
2563 mem_range_AP_init();
2566 * Once we go active we must process any IPIQ messages that may
2567 * have been queued, because no actual IPI will occur until we
2568 * set our bit in the smp_active_mask. If we don't the IPI
2569 * message interlock could be left set which would also prevent
2572 * The idle loop doesn't expect the BGL to be held and while
2573 * lwkt_switch() normally cleans things up this is a special case
2574 * because we returning almost directly into the idle loop.
2576 * The idle thread is never placed on the runq, make sure
2577 * nothing we've done put it there.
2579 KKASSERT(curthread->td_mpcount == 1);
2580 smp_active_mask |= 1 << mycpu->gd_cpuid;
2583 * Enable interrupts here. idle_restore will also do it, but
2584 * doing it here lets us clean up any strays that got posted to
2585 * the CPU during the AP boot while we are still in a critical
2588 __asm __volatile("sti; pause; pause"::);
2589 mdcpu->gd_fpending = 0;
2590 mdcpu->gd_ipending = 0;
2592 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2593 lwkt_process_ipiq();
2596 * Releasing the mp lock lets the BSP finish up the SMP init
2599 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2603 * Get SMP fully working before we start initializing devices.
2611 kprintf("Finish MP startup\n");
2612 if (cpu_feature & CPUID_TSC)
2613 tsc0_offset = rdtsc();
2616 while (smp_active_mask != smp_startup_mask) {
2618 if (cpu_feature & CPUID_TSC)
2619 tsc0_offset = rdtsc();
2621 while (try_mplock() == 0)
2624 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2627 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2630 cpu_send_ipiq(int dcpu)
2632 if ((1 << dcpu) & smp_active_mask)
2633 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2636 #if 0 /* single_apic_ipi_passive() not working yet */
2638 * Returns 0 on failure, 1 on success
2641 cpu_send_ipiq_passive(int dcpu)
2644 if ((1 << dcpu) & smp_active_mask) {
2645 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2646 APIC_DELMODE_FIXED);