2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $
33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.13 2004/04/16 14:21:58 joerg Exp $
35 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $
39 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
40 * available from http://www.sis.com.tw.
42 * This driver also supports the NatSemi DP83815. Datasheets are
43 * available from http://www.national.com.
45 * Written by Bill Paul <wpaul@ee.columbia.edu>
46 * Electrical Engineering Department
47 * Columbia University, New York City
51 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
52 * simple TX and RX descriptors of 3 longwords in size. The receiver
53 * has a single perfect filter entry for the station address and a
54 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
55 * transceiver while the 7016 requires an external transceiver chip.
56 * Both chips offer the standard bit-bang MII interface as well as
57 * an enchanced PHY interface which simplifies accessing MII registers.
59 * The only downside to this chipset is that RX descriptors must be
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 #include <sys/sockio.h>
67 #include <sys/malloc.h>
68 #include <sys/kernel.h>
69 #include <sys/socket.h>
70 #include <sys/sysctl.h>
73 #include <net/if_arp.h>
74 #include <net/ethernet.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/vlan/if_vlan_var.h>
82 #include <machine/bus_pio.h>
83 #include <machine/bus_memio.h>
84 #include <machine/bus.h>
85 #include <machine/resource.h>
89 #include <dev/netif/mii_layer/mii.h>
90 #include <dev/netif/mii_layer/miivar.h>
92 #include <bus/pci/pcireg.h>
93 #include <bus/pci/pcivar.h>
95 #define SIS_USEIOSPACE
97 #include "if_sisreg.h"
99 /* "controller miibus0" required. See GENERIC if you get errors here. */
100 #include "miibus_if.h"
103 * Various supported device vendors/types and their names.
105 static struct sis_type sis_devs[] = {
106 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
107 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
108 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
112 static int sis_probe(device_t);
113 static int sis_attach(device_t);
114 static int sis_detach(device_t);
116 static int sis_newbuf(struct sis_softc *, struct sis_desc *,
118 static int sis_encap(struct sis_softc *, struct mbuf *, uint32_t *);
119 static void sis_rxeof(struct sis_softc *);
120 static void sis_rxeoc(struct sis_softc *);
121 static void sis_txeof(struct sis_softc *);
122 static void sis_intr(void *);
123 static void sis_tick(void *);
124 static void sis_start(struct ifnet *);
125 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
126 static void sis_init(void *);
127 static void sis_stop(struct sis_softc *);
128 static void sis_watchdog(struct ifnet *);
129 static void sis_shutdown(device_t);
130 static int sis_ifmedia_upd(struct ifnet *);
131 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
133 static uint16_t sis_reverse(uint16_t);
134 static void sis_delay(struct sis_softc *);
135 static void sis_eeprom_idle(struct sis_softc *);
136 static void sis_eeprom_putbyte(struct sis_softc *, int);
137 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *);
138 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int);
140 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int);
141 static void sis_read_mac(struct sis_softc *, device_t, caddr_t);
142 static device_t sis_find_bridge(device_t);
145 static void sis_mii_sync(struct sis_softc *);
146 static void sis_mii_send(struct sis_softc *, uint32_t, int);
147 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *);
148 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *);
149 static int sis_miibus_readreg(device_t, int, int);
150 static int sis_miibus_writereg(device_t, int, int, int);
151 static void sis_miibus_statchg(device_t);
153 static void sis_setmulti_sis(struct sis_softc *);
154 static void sis_setmulti_ns(struct sis_softc *);
155 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *);
156 static void sis_reset(struct sis_softc *);
157 static int sis_list_rx_init(struct sis_softc *);
158 static int sis_list_tx_init(struct sis_softc *);
160 static void sis_dma_map_desc_ptr(void *, bus_dma_segment_t *, int, int);
161 static void sis_dma_map_desc_next(void *, bus_dma_segment_t *, int, int);
162 static void sis_dma_map_ring(void *, bus_dma_segment_t *, int, int);
163 #ifdef SIS_USEIOSPACE
164 #define SIS_RES SYS_RES_IOPORT
165 #define SIS_RID SIS_PCI_LOIO
167 #define SIS_RES SYS_RES_MEMORY
168 #define SIS_RID SIS_PCI_LOMEM
171 static device_method_t sis_methods[] = {
172 /* Device interface */
173 DEVMETHOD(device_probe, sis_probe),
174 DEVMETHOD(device_attach, sis_attach),
175 DEVMETHOD(device_detach, sis_detach),
176 DEVMETHOD(device_shutdown, sis_shutdown),
179 DEVMETHOD(bus_print_child, bus_generic_print_child),
180 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
183 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
184 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
185 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
190 static driver_t sis_driver = {
193 sizeof(struct sis_softc)
196 static devclass_t sis_devclass;
198 DECLARE_DUMMY_MODULE(if_sis);
199 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0);
200 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
202 #define SIS_SETBIT(sc, reg, x) \
203 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
205 #define SIS_CLRBIT(sc, reg, x) \
206 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
209 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
212 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
215 sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error)
220 r->sis_next = segs->ds_addr;
224 sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
229 r->sis_ptr = segs->ds_addr;
233 sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error)
242 * Routine to reverse the bits in a word. Stolen almost
243 * verbatim from /usr/games/fortune.
246 sis_reverse(uint16_t n)
248 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
249 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
250 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
251 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
257 sis_delay(struct sis_softc *sc)
261 for (idx = (300 / 33) + 1; idx > 0; idx--)
262 CSR_READ_4(sc, SIS_CSR);
266 sis_eeprom_idle(struct sis_softc *sc)
270 SIO_SET(SIS_EECTL_CSEL);
272 SIO_SET(SIS_EECTL_CLK);
275 for (i = 0; i < 25; i++) {
276 SIO_CLR(SIS_EECTL_CLK);
278 SIO_SET(SIS_EECTL_CLK);
282 SIO_CLR(SIS_EECTL_CLK);
284 SIO_CLR(SIS_EECTL_CSEL);
286 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
290 * Send a read command and address to the EEPROM, check for ACK.
293 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
297 d = addr | SIS_EECMD_READ;
300 * Feed in each bit and stobe the clock.
302 for (i = 0x400; i; i >>= 1) {
304 SIO_SET(SIS_EECTL_DIN);
306 SIO_CLR(SIS_EECTL_DIN);
308 SIO_SET(SIS_EECTL_CLK);
310 SIO_CLR(SIS_EECTL_CLK);
316 * Read a word of data stored in the EEPROM at address 'addr.'
319 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
324 /* Force EEPROM to idle state. */
327 /* Enter EEPROM access mode. */
329 SIO_CLR(SIS_EECTL_CLK);
331 SIO_SET(SIS_EECTL_CSEL);
335 * Send address of word we want to read.
337 sis_eeprom_putbyte(sc, addr);
340 * Start reading bits from EEPROM.
342 for (i = 0x8000; i; i >>= 1) {
343 SIO_SET(SIS_EECTL_CLK);
345 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
348 SIO_CLR(SIS_EECTL_CLK);
352 /* Turn off EEPROM access mode. */
359 * Read a sequence of words from the EEPROM.
362 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
365 uint16_t word = 0, *ptr;
367 for (i = 0; i < cnt; i++) {
368 sis_eeprom_getword(sc, off + i, &word);
369 ptr = (uint16_t *)(dest + (i * 2));
379 sis_find_bridge(device_t dev)
381 devclass_t pci_devclass;
382 device_t *pci_devices;
384 device_t *pci_children;
385 int pci_childcount = 0;
386 device_t *busp, *childp;
387 device_t child = NULL;
390 if ((pci_devclass = devclass_find("pci")) == NULL)
393 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
395 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
397 device_get_children(*busp, &pci_children, &pci_childcount);
398 for (j = 0, childp = pci_children; j < pci_childcount;
400 if (pci_get_vendor(*childp) == SIS_VENDORID &&
401 pci_get_device(*childp) == 0x0008) {
409 free(pci_devices, M_TEMP);
410 free(pci_children, M_TEMP);
415 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off,
421 bus_space_tag_t btag;
423 bridge = sis_find_bridge(dev);
426 reg = pci_read_config(bridge, 0x48, 1);
427 pci_write_config(bridge, 0x48, reg|0x40, 1);
430 btag = I386_BUS_SPACE_IO;
432 for (i = 0; i < cnt; i++) {
433 bus_space_write_1(btag, 0x0, 0x70, i + off);
434 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
437 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
441 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
443 uint32_t filtsave, csrsave;
445 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
446 csrsave = CSR_READ_4(sc, SIS_CSR);
448 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
449 CSR_WRITE_4(sc, SIS_CSR, 0);
451 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
453 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
454 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
455 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
456 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
457 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
458 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
460 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
461 CSR_WRITE_4(sc, SIS_CSR, csrsave);
466 * Sync the PHYs by setting data bit and strobing the clock 32 times.
469 sis_mii_sync(struct sis_softc *sc)
473 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
475 for (i = 0; i < 32; i++) {
476 SIO_SET(SIS_MII_CLK);
478 SIO_CLR(SIS_MII_CLK);
484 * Clock a series of bits through the MII.
487 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
491 SIO_CLR(SIS_MII_CLK);
493 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
495 SIO_SET(SIS_MII_DATA);
497 SIO_CLR(SIS_MII_DATA);
499 SIO_CLR(SIS_MII_CLK);
501 SIO_SET(SIS_MII_CLK);
506 * Read an PHY register through the MII.
509 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
516 * Set up frame for RX.
518 frame->mii_stdelim = SIS_MII_STARTDELIM;
519 frame->mii_opcode = SIS_MII_READOP;
520 frame->mii_turnaround = 0;
526 SIO_SET(SIS_MII_DIR);
531 * Send command/address info.
533 sis_mii_send(sc, frame->mii_stdelim, 2);
534 sis_mii_send(sc, frame->mii_opcode, 2);
535 sis_mii_send(sc, frame->mii_phyaddr, 5);
536 sis_mii_send(sc, frame->mii_regaddr, 5);
539 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
541 SIO_SET(SIS_MII_CLK);
545 SIO_CLR(SIS_MII_DIR);
548 SIO_CLR(SIS_MII_CLK);
550 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
551 SIO_SET(SIS_MII_CLK);
555 * Now try reading data bits. If the ack failed, we still
556 * need to clock through 16 cycles to keep the PHY(s) in sync.
559 for(i = 0; i < 16; i++) {
560 SIO_CLR(SIS_MII_CLK);
562 SIO_SET(SIS_MII_CLK);
568 for (i = 0x8000; i; i >>= 1) {
569 SIO_CLR(SIS_MII_CLK);
572 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
573 frame->mii_data |= i;
576 SIO_SET(SIS_MII_CLK);
582 SIO_CLR(SIS_MII_CLK);
584 SIO_SET(SIS_MII_CLK);
595 * Write to a PHY register through the MII.
598 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
604 * Set up frame for TX.
607 frame->mii_stdelim = SIS_MII_STARTDELIM;
608 frame->mii_opcode = SIS_MII_WRITEOP;
609 frame->mii_turnaround = SIS_MII_TURNAROUND;
612 * Turn on data output.
614 SIO_SET(SIS_MII_DIR);
618 sis_mii_send(sc, frame->mii_stdelim, 2);
619 sis_mii_send(sc, frame->mii_opcode, 2);
620 sis_mii_send(sc, frame->mii_phyaddr, 5);
621 sis_mii_send(sc, frame->mii_regaddr, 5);
622 sis_mii_send(sc, frame->mii_turnaround, 2);
623 sis_mii_send(sc, frame->mii_data, 16);
626 SIO_SET(SIS_MII_CLK);
628 SIO_CLR(SIS_MII_CLK);
634 SIO_CLR(SIS_MII_DIR);
642 sis_miibus_readreg(device_t dev, int phy, int reg)
644 struct sis_softc *sc;
645 struct sis_mii_frame frame;
647 sc = device_get_softc(dev);
649 if (sc->sis_type == SIS_TYPE_83815) {
653 * The NatSemi chip can take a while after
654 * a reset to come ready, during which the BMSR
655 * returns a value of 0. This is *never* supposed
656 * to happen: some of the BMSR bits are meant to
657 * be hardwired in the on position, and this can
658 * confuse the miibus code a bit during the probe
659 * and attach phase. So we make an effort to check
660 * for this condition and wait for it to clear.
662 if (!CSR_READ_4(sc, NS_BMSR))
664 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
667 * Chipsets < SIS_635 seem not to be able to read/write
668 * through mdio. Use the enhanced PHY access register
671 if (sc->sis_type == SIS_TYPE_900 &&
672 sc->sis_rev < SIS_REV_635) {
678 CSR_WRITE_4(sc, SIS_PHYCTL,
679 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
680 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
682 for (i = 0; i < SIS_TIMEOUT; i++) {
683 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
687 if (i == SIS_TIMEOUT) {
688 device_printf(dev, "PHY failed to come ready\n");
692 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
699 bzero((char *)&frame, sizeof(frame));
701 frame.mii_phyaddr = phy;
702 frame.mii_regaddr = reg;
703 sis_mii_readreg(sc, &frame);
705 return(frame.mii_data);
710 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
712 struct sis_softc *sc;
713 struct sis_mii_frame frame;
715 sc = device_get_softc(dev);
717 if (sc->sis_type == SIS_TYPE_83815) {
720 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
724 if (sc->sis_type == SIS_TYPE_900 &&
725 sc->sis_rev < SIS_REV_635) {
731 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
732 (reg << 6) | SIS_PHYOP_WRITE);
733 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
735 for (i = 0; i < SIS_TIMEOUT; i++) {
736 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
740 if (i == SIS_TIMEOUT)
741 device_printf(dev, "PHY failed to come ready\n");
743 bzero((char *)&frame, sizeof(frame));
745 frame.mii_phyaddr = phy;
746 frame.mii_regaddr = reg;
747 frame.mii_data = data;
748 sis_mii_writereg(sc, &frame);
753 static void sis_miibus_statchg(device_t dev)
755 struct sis_softc *sc;
757 sc = device_get_softc(dev);
762 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
768 /* Compute CRC for the address value. */
769 crc = 0xFFFFFFFF; /* initial value */
771 for (i = 0; i < 6; i++) {
773 for (j = 0; j < 8; j++) {
774 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
778 crc = (crc ^ 0x04c11db6) | carry;
783 * return the filter bit position
785 * The NatSemi chip has a 512-bit filter, which is
786 * different than the SiS, so we special-case it.
788 if (sc->sis_type == SIS_TYPE_83815)
790 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
797 sis_setmulti_ns(struct sis_softc *sc)
800 struct ifmultiaddr *ifma;
801 uint32_t h = 0, i, filtsave;
804 ifp = &sc->arpcom.ac_if;
806 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
807 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
808 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
813 * We have to explicitly enable the multicast hash table
814 * on the NatSemi chip if we want to use it, which we do.
816 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
817 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
819 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
821 /* first, zot all the existing hash bits */
822 for (i = 0; i < 32; i++) {
823 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
824 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
827 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
828 if (ifma->ifma_addr->sa_family != AF_LINK)
831 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
834 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
837 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
840 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
844 sis_setmulti_sis(struct sis_softc *sc)
847 struct ifmultiaddr *ifma;
848 uint32_t h, i, n, ctl;
851 ifp = &sc->arpcom.ac_if;
853 /* hash table size */
854 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
859 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
861 if (ifp->if_flags & IFF_BROADCAST)
862 ctl |= SIS_RXFILTCTL_BROAD;
864 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
865 ctl |= SIS_RXFILTCTL_ALLMULTI;
866 if (ifp->if_flags & IFF_PROMISC)
867 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
868 for (i = 0; i < n; i++)
871 for (i = 0; i < n; i++)
874 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
875 if (ifma->ifma_addr->sa_family != AF_LINK)
878 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
879 hashes[h >> 4] |= 1 << (h & 0xf);
883 ctl |= SIS_RXFILTCTL_ALLMULTI;
884 for (i = 0; i < n; i++)
889 for (i = 0; i < n; i++) {
890 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
891 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
894 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
898 sis_reset(struct sis_softc *sc)
900 struct ifnet *ifp = &sc->arpcom.ac_if;
903 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
905 for (i = 0; i < SIS_TIMEOUT; i++) {
906 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
910 if (i == SIS_TIMEOUT)
911 if_printf(ifp, "reset never completed\n");
913 /* Wait a little while for the chip to get its brains in order. */
917 * If this is a NetSemi chip, make sure to clear
920 if (sc->sis_type == SIS_TYPE_83815) {
921 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
922 CSR_WRITE_4(sc, NS_CLKRUN, 0);
927 * Probe for an SiS chip. Check the PCI vendor and device
928 * IDs against our list and return a device name if we find a match.
931 sis_probe(device_t dev)
937 while(t->sis_name != NULL) {
938 if ((pci_get_vendor(dev) == t->sis_vid) &&
939 (pci_get_device(dev) == t->sis_did)) {
940 device_set_desc(dev, t->sis_name);
950 * Attach the interface. Allocate softc structures, do ifmedia
951 * setup and ethernet/BPF attach.
954 sis_attach(device_t dev)
956 uint8_t eaddr[ETHER_ADDR_LEN];
958 struct sis_softc *sc;
960 int error, rid, waittime;
962 error = waittime = 0;
963 sc = device_get_softc(dev);
964 bzero(sc, sizeof(struct sis_softc));
966 if (pci_get_device(dev) == SIS_DEVICEID_900)
967 sc->sis_type = SIS_TYPE_900;
968 if (pci_get_device(dev) == SIS_DEVICEID_7016)
969 sc->sis_type = SIS_TYPE_7016;
970 if (pci_get_vendor(dev) == NS_VENDORID)
971 sc->sis_type = SIS_TYPE_83815;
973 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
976 * Handle power management nonsense.
979 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF;
980 if (command == 0x01) {
982 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4);
983 if (command & SIS_PSTATE_MASK) {
984 uint32_t iobase, membase, irq;
986 /* Save important PCI config data. */
987 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4);
988 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4);
989 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4);
991 /* Reset the power state. */
992 device_printf(dev, "chip is in D%d power mode "
993 "-- setting to D0\n", command & SIS_PSTATE_MASK);
994 command &= 0xFFFFFFFC;
995 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4);
997 /* Restore PCI config data. */
998 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4);
999 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4);
1000 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4);
1005 * Map control/status registers.
1007 command = pci_read_config(dev, PCIR_COMMAND, 4);
1008 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1009 pci_write_config(dev, PCIR_COMMAND, command, 4);
1010 command = pci_read_config(dev, PCIR_COMMAND, 4);
1012 #ifdef SIS_USEIOSPACE
1013 if (!(command & PCIM_CMD_PORTEN)) {
1014 device_printf(dev, "failed to enable I/O ports!\n");
1019 if (!(command & PCIM_CMD_MEMEN)) {
1020 device_printf(dev, "failed to enable memory mapping!\n");
1027 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid,
1028 0, ~0, 1, RF_ACTIVE);
1030 if (sc->sis_res == NULL) {
1031 device_printf(dev, "couldn't map ports/memory\n");
1036 sc->sis_btag = rman_get_bustag(sc->sis_res);
1037 sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
1039 /* Allocate interrupt */
1041 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1042 RF_SHAREABLE | RF_ACTIVE);
1044 if (sc->sis_irq == NULL) {
1045 device_printf(dev, "couldn't map interrupt\n");
1050 /* Reset the adapter. */
1053 if (sc->sis_type == SIS_TYPE_900 &&
1054 (sc->sis_rev == SIS_REV_635 ||
1055 sc->sis_rev == SIS_REV_900B)) {
1056 SIO_SET(SIS_CFG_RND_CNT);
1057 SIO_SET(SIS_CFG_PERR_DETECT);
1061 * Get station address from the EEPROM.
1063 switch (pci_get_vendor(dev)) {
1066 * Reading the MAC address out of the EEPROM on
1067 * the NatSemi chip takes a bit more work than
1068 * you'd expect. The address spans 4 16-bit words,
1069 * with the first word containing only a single bit.
1070 * You have to shift everything over one bit to
1071 * get it aligned properly. Also, the bits are
1072 * stored backwards (the LSB is really the MSB,
1073 * and so on) so you have to reverse them in order
1074 * to get the MAC address into the form we want.
1075 * Why? Who the hell knows.
1080 sis_read_eeprom(sc, (caddr_t)&tmp,
1081 NS_EE_NODEADDR, 4, 0);
1083 /* Shift everything over one bit. */
1084 tmp[3] = tmp[3] >> 1;
1085 tmp[3] |= tmp[2] << 15;
1086 tmp[2] = tmp[2] >> 1;
1087 tmp[2] |= tmp[1] << 15;
1088 tmp[1] = tmp[1] >> 1;
1089 tmp[1] |= tmp[0] << 15;
1091 /* Now reverse all the bits. */
1092 tmp[3] = sis_reverse(tmp[3]);
1093 tmp[2] = sis_reverse(tmp[2]);
1094 tmp[1] = sis_reverse(tmp[1]);
1096 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
1103 * If this is a SiS 630E chipset with an embedded
1104 * SiS 900 controller, we have to read the MAC address
1105 * from the APC CMOS RAM. Our method for doing this
1106 * is very ugly since we have to reach out and grab
1107 * ahold of hardware for which we cannot properly
1108 * allocate resources. This code is only compiled on
1109 * the i386 architecture since the SiS 630E chipset
1110 * is for x86 motherboards only. Note that there are
1111 * a lot of magic numbers in this hack. These are
1112 * taken from SiS's Linux driver. I'd like to replace
1113 * them with proper symbolic definitions, but that
1114 * requires some datasheets that I don't have access
1117 if (sc->sis_rev == SIS_REV_630S ||
1118 sc->sis_rev == SIS_REV_630E ||
1119 sc->sis_rev == SIS_REV_630EA1)
1120 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1122 else if (sc->sis_rev == SIS_REV_635 ||
1123 sc->sis_rev == SIS_REV_630ET)
1124 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1125 else if (sc->sis_rev == SIS_REV_96x) {
1127 * Allow to read EEPROM from LAN. It is shared
1128 * between a 1394 controller and the NIC and each
1129 * time we access it, we need to set SIS_EECMD_REQ.
1131 SIO_SET(SIS_EECMD_REQ);
1132 for (waittime = 0; waittime < SIS_TIMEOUT;
1134 /* Force EEPROM to idle state. */
1135 sis_eeprom_idle(sc);
1136 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1137 sis_read_eeprom(sc, (caddr_t)&eaddr,
1138 SIS_EE_NODEADDR, 3, 0);
1144 * Set SIS_EECTL_CLK to high, so a other master
1145 * can operate on the i2c bus.
1147 SIO_SET(SIS_EECTL_CLK);
1148 /* Refuse EEPROM access by LAN */
1149 SIO_SET(SIS_EECMD_DONE);
1152 sis_read_eeprom(sc, (caddr_t)&eaddr,
1153 SIS_EE_NODEADDR, 3, 0);
1158 * A SiS chip was detected. Inform the world.
1160 device_printf(dev, "Ethernet address: %6D\n", eaddr, ":");
1162 callout_handle_init(&sc->sis_stat_ch);
1165 * Allocate the parent bus DMA tag appropriate for PCI.
1167 #define SIS_NSEG_NEW 32
1168 error = bus_dma_tag_create(NULL, /* parent */
1169 1, 0, /* alignment, boundary */
1170 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1171 BUS_SPACE_MAXADDR, /* highaddr */
1172 NULL, NULL, /* filter, filterarg */
1173 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */
1174 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1175 BUS_DMA_ALLOCNOW, /* flags */
1176 &sc->sis_parent_tag);
1181 * Now allocate a tag for the DMA descriptor lists and a chunk
1182 * of DMA-able memory based on the tag. Also obtain the physical
1183 * addresses of the RX and TX ring, which we'll need later.
1184 * All of our lists are allocated as a contiguous block of memory.
1186 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1187 1, 0, /* alignment, boundary */
1188 BUS_SPACE_MAXADDR, /* lowaddr */
1189 BUS_SPACE_MAXADDR, /* highaddr */
1190 NULL, NULL, /* filter, filterarg */
1191 SIS_RX_LIST_SZ, 1, /* maxsize, nsegments */
1192 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1194 &sc->sis_ldata.sis_rx_tag);
1198 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag,
1199 (void **)&sc->sis_ldata.sis_rx_list,
1200 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1201 &sc->sis_ldata.sis_rx_dmamap);
1204 device_printf(dev, "no memory for rx list buffers!\n");
1205 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1206 sc->sis_ldata.sis_rx_tag = NULL;
1210 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1211 sc->sis_ldata.sis_rx_dmamap,
1212 sc->sis_ldata.sis_rx_list,
1213 sizeof(struct sis_desc), sis_dma_map_ring,
1214 &sc->sis_cdata.sis_rx_paddr, 0);
1217 device_printf(dev, "cannot get address of the rx ring!\n");
1218 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1219 sc->sis_ldata.sis_rx_list,
1220 sc->sis_ldata.sis_rx_dmamap);
1221 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1222 sc->sis_ldata.sis_rx_tag = NULL;
1226 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1227 1, 0, /* alignment, boundary */
1228 BUS_SPACE_MAXADDR, /* lowaddr */
1229 BUS_SPACE_MAXADDR, /* highaddr */
1230 NULL, NULL, /* filter, filterarg */
1231 SIS_TX_LIST_SZ, 1, /* maxsize, nsegments */
1232 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1234 &sc->sis_ldata.sis_tx_tag);
1238 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag,
1239 (void **)&sc->sis_ldata.sis_tx_list,
1240 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1241 &sc->sis_ldata.sis_tx_dmamap);
1244 device_printf(dev, "no memory for tx list buffers!\n");
1245 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1246 sc->sis_ldata.sis_tx_tag = NULL;
1250 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1251 sc->sis_ldata.sis_tx_dmamap,
1252 sc->sis_ldata.sis_tx_list,
1253 sizeof(struct sis_desc), sis_dma_map_ring,
1254 &sc->sis_cdata.sis_tx_paddr, 0);
1257 device_printf(dev, "cannot get address of the tx ring!\n");
1258 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
1259 sc->sis_ldata.sis_tx_list,
1260 sc->sis_ldata.sis_tx_dmamap);
1261 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1262 sc->sis_ldata.sis_tx_tag = NULL;
1266 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1267 1, 0, /* alignment, boundary */
1268 BUS_SPACE_MAXADDR, /* lowaddr */
1269 BUS_SPACE_MAXADDR, /* highaddr */
1270 NULL, NULL, /* filter, filterarg */
1271 MCLBYTES, 1, /* maxsize, nsegments */
1272 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1278 ifp = &sc->arpcom.ac_if;
1280 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1281 ifp->if_mtu = ETHERMTU;
1282 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1283 ifp->if_ioctl = sis_ioctl;
1284 ifp->if_output = ether_output;
1285 ifp->if_start = sis_start;
1286 ifp->if_watchdog = sis_watchdog;
1287 ifp->if_init = sis_init;
1288 ifp->if_baudrate = 10000000;
1289 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1;
1294 if (mii_phy_probe(dev, &sc->sis_miibus,
1295 sis_ifmedia_upd, sis_ifmedia_sts)) {
1296 device_printf(dev, "MII without any PHY!\n");
1302 * Call MI attach routine.
1304 ether_ifattach(ifp, eaddr);
1307 * Tell the upper layer(s) we support long frames.
1309 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1311 callout_handle_init(&sc->sis_stat_ch);
1313 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET,
1314 sis_intr, sc, &sc->sis_intrhand);
1317 device_printf(dev, "couldn't set up irq\n");
1318 ether_ifdetach(ifp);
1330 * Shutdown hardware and free up resources. It is called in both the error case
1331 * and the normal detach case so it needs to be careful about only freeing
1332 * resources that have actually been allocated.
1335 sis_detach(device_t dev)
1337 struct sis_softc *sc;
1343 sc = device_get_softc(dev);
1344 ifp = &sc->arpcom.ac_if;
1346 if (device_is_attached(dev)) {
1349 ether_ifdetach(ifp);
1352 device_delete_child(dev, sc->sis_miibus);
1353 bus_generic_detach(dev);
1355 if (sc->sis_intrhand)
1356 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1358 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1360 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1362 if (sc->sis_ldata.sis_rx_tag) {
1363 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag,
1364 sc->sis_ldata.sis_rx_dmamap);
1365 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1366 sc->sis_ldata.sis_rx_list,
1367 sc->sis_ldata.sis_rx_dmamap);
1368 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1371 if (sc->sis_ldata.sis_tx_tag) {
1372 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag,
1373 sc->sis_ldata.sis_tx_dmamap);
1374 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
1375 sc->sis_ldata.sis_tx_list,
1376 sc->sis_ldata.sis_tx_dmamap);
1377 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1380 bus_dma_tag_destroy(sc->sis_tag);
1381 if (sc->sis_parent_tag)
1382 bus_dma_tag_destroy(sc->sis_parent_tag);
1390 * Initialize the transmit descriptors.
1393 sis_list_tx_init(struct sis_softc *sc)
1395 struct sis_list_data *ld;
1396 struct sis_ring_data *cd;
1399 cd = &sc->sis_cdata;
1400 ld = &sc->sis_ldata;
1402 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1403 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1;
1404 ld->sis_tx_list[i].sis_nextdesc =
1405 &ld->sis_tx_list[nexti];
1406 bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1407 sc->sis_ldata.sis_tx_dmamap,
1408 &ld->sis_tx_list[nexti],
1409 sizeof(struct sis_desc), sis_dma_map_desc_next,
1410 &ld->sis_tx_list[i], 0);
1411 ld->sis_tx_list[i].sis_mbuf = NULL;
1412 ld->sis_tx_list[i].sis_ptr = 0;
1413 ld->sis_tx_list[i].sis_ctl = 0;
1416 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0;
1418 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_dmamap,
1419 BUS_DMASYNC_PREWRITE);
1425 * Initialize the RX descriptors and allocate mbufs for them. Note that
1426 * we arrange the descriptors in a closed ring, so that the last descriptor
1427 * points back to the first.
1430 sis_list_rx_init(struct sis_softc *sc)
1432 struct sis_list_data *ld;
1433 struct sis_ring_data *cd;
1436 ld = &sc->sis_ldata;
1437 cd = &sc->sis_cdata;
1439 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1440 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS)
1442 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1;
1443 ld->sis_rx_list[i].sis_nextdesc =
1444 &ld->sis_rx_list[nexti];
1445 bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1446 sc->sis_ldata.sis_rx_dmamap,
1447 &ld->sis_rx_list[nexti],
1448 sizeof(struct sis_desc), sis_dma_map_desc_next,
1449 &ld->sis_rx_list[i], 0);
1452 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_dmamap,
1453 BUS_DMASYNC_PREWRITE);
1455 cd->sis_rx_prod = 0;
1461 * Initialize an RX descriptor and attach an MBUF cluster.
1464 sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m)
1467 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1471 m->m_data = m->m_ext.ext_buf;
1475 c->sis_ctl = SIS_RXLEN;
1477 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map);
1478 bus_dmamap_load(sc->sis_tag, c->sis_map, mtod(m, void *), MCLBYTES,
1479 sis_dma_map_desc_ptr, c, 0);
1480 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE);
1486 * A frame has been uploaded: pass the resulting mbuf chain up to
1487 * the higher level protocols.
1490 sis_rxeof(struct sis_softc *sc)
1494 struct sis_desc *cur_rx;
1495 int i, total_len = 0;
1498 ifp = &sc->arpcom.ac_if;
1499 i = sc->sis_cdata.sis_rx_prod;
1501 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) {
1503 #ifdef DEVICE_POLLING
1504 if (ifp->if_flags & IFF_POLLING) {
1505 if (sc->rxcycles <= 0)
1509 #endif /* DEVICE_POLLING */
1510 cur_rx = &sc->sis_ldata.sis_rx_list[i];
1511 rxstat = cur_rx->sis_rxstat;
1512 bus_dmamap_sync(sc->sis_tag, cur_rx->sis_map,
1513 BUS_DMASYNC_POSTWRITE);
1514 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map);
1515 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map);
1516 m = cur_rx->sis_mbuf;
1517 cur_rx->sis_mbuf = NULL;
1518 total_len = SIS_RXBYTES(cur_rx);
1519 SIS_INC(i, SIS_RX_LIST_CNT);
1522 * If an error occurs, update stats, clear the
1523 * status word and leave the mbuf cluster in place:
1524 * it should simply get re-used next time this descriptor
1525 * comes up in the ring.
1527 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
1529 if (rxstat & SIS_RXSTAT_COLL)
1530 ifp->if_collisions++;
1531 sis_newbuf(sc, cur_rx, m);
1535 /* No errors; receive the packet. */
1538 * On the x86 we do not have alignment problems, so try to
1539 * allocate a new buffer for the receive ring, and pass up
1540 * the one where the packet is already, saving the expensive
1541 * copy done in m_devget().
1542 * If we are on an architecture with alignment problems, or
1543 * if the allocation fails, then use m_devget and leave the
1544 * existing buffer in the receive ring.
1546 if (sis_newbuf(sc, cur_rx, NULL) == 0)
1547 m->m_pkthdr.len = m->m_len = total_len;
1552 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1553 total_len + ETHER_ALIGN, 0, ifp, NULL);
1554 sis_newbuf(sc, cur_rx, m);
1559 m_adj(m0, ETHER_ALIGN);
1564 ether_input(ifp, NULL, m);
1567 sc->sis_cdata.sis_rx_prod = i;
1571 sis_rxeoc(struct sis_softc *sc)
1578 * A frame was downloaded to the chip. It's safe for us to clean up
1583 sis_txeof(struct sis_softc *sc)
1585 struct sis_desc *cur_tx;
1589 ifp = &sc->arpcom.ac_if;
1592 * Go through our tx list and free mbufs for those
1593 * frames that have been transmitted.
1595 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0;
1596 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) {
1597 cur_tx = &sc->sis_ldata.sis_tx_list[idx];
1599 if (SIS_OWNDESC(cur_tx))
1602 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE)
1605 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1607 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1608 ifp->if_collisions++;
1609 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1610 ifp->if_collisions++;
1613 ifp->if_collisions +=
1614 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
1617 if (cur_tx->sis_mbuf != NULL) {
1618 m_freem(cur_tx->sis_mbuf);
1619 cur_tx->sis_mbuf = NULL;
1620 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map);
1621 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map);
1625 if (idx != sc->sis_cdata.sis_tx_cons) {
1626 /* we freed up some buffers */
1627 sc->sis_cdata.sis_tx_cons = idx;
1628 ifp->if_flags &= ~IFF_OACTIVE;
1631 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5;
1637 struct sis_softc *sc;
1638 struct mii_data *mii;
1645 ifp = &sc->arpcom.ac_if;
1647 mii = device_get_softc(sc->sis_miibus);
1650 if (!sc->sis_link) {
1652 if (mii->mii_media_status & IFM_ACTIVE &&
1653 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1655 if (ifp->if_snd.ifq_head != NULL)
1659 sc->sis_stat_ch = timeout(sis_tick, sc, hz);
1664 #ifdef DEVICE_POLLING
1665 static poll_handler_t sis_poll;
1668 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1670 struct sis_softc *sc = ifp->if_softc;
1672 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1673 CSR_WRITE_4(sc, SIS_IER, 1);
1678 * On the sis, reading the status register also clears it.
1679 * So before returning to intr mode we must make sure that all
1680 * possible pending sources of interrupts have been served.
1681 * In practice this means run to completion the *eof routines,
1682 * and then call the interrupt routine
1684 sc->rxcycles = count;
1687 if (ifp->if_snd.ifq_head != NULL)
1690 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1693 /* Reading the ISR register clears all interrupts. */
1694 status = CSR_READ_4(sc, SIS_ISR);
1696 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1699 if (status & (SIS_ISR_RX_IDLE))
1700 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1702 if (status & SIS_ISR_SYSERR) {
1708 #endif /* DEVICE_POLLING */
1713 struct sis_softc *sc;
1718 ifp = &sc->arpcom.ac_if;
1720 #ifdef DEVICE_POLLING
1721 if (ifp->if_flags & IFF_POLLING)
1723 if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */
1724 CSR_WRITE_4(sc, SIS_IER, 0);
1725 sis_poll(ifp, 0, 1);
1728 #endif /* DEVICE_POLLING */
1730 /* Supress unwanted interrupts */
1731 if (!(ifp->if_flags & IFF_UP)) {
1736 /* Disable interrupts. */
1737 CSR_WRITE_4(sc, SIS_IER, 0);
1740 /* Reading the ISR register clears all interrupts. */
1741 status = CSR_READ_4(sc, SIS_ISR);
1743 if ((status & SIS_INTRS) == 0)
1747 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK |
1752 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE))
1755 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
1758 if (status & (SIS_ISR_RX_IDLE))
1759 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1761 if (status & SIS_ISR_SYSERR) {
1767 /* Re-enable interrupts. */
1768 CSR_WRITE_4(sc, SIS_IER, 1);
1770 if (ifp->if_snd.ifq_head != NULL)
1775 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1776 * pointers to the fragment pointers.
1779 sis_encap(struct sis_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1781 struct sis_desc *f = NULL;
1783 int frag, cur, cnt = 0;
1786 * If there's no way we can send any packets, return now.
1788 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2)
1792 * Start packing the mbufs in this chain into
1793 * the fragment pointers. Stop when we run out
1794 * of fragments or hit the end of the mbuf chain.
1797 cur = frag = *txidx;
1799 for (m = m_head; m != NULL; m = m->m_next) {
1800 if (m->m_len != 0) {
1801 if ((SIS_TX_LIST_CNT -
1802 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2)
1804 f = &sc->sis_ldata.sis_tx_list[frag];
1805 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len;
1806 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map);
1807 bus_dmamap_load(sc->sis_tag, f->sis_map,
1808 mtod(m, void *), m->m_len,
1809 sis_dma_map_desc_ptr, f, 0);
1810 bus_dmamap_sync(sc->sis_tag, f->sis_map,
1811 BUS_DMASYNC_PREREAD);
1813 f->sis_ctl |= SIS_CMDSTS_OWN;
1815 SIS_INC(frag, SIS_TX_LIST_CNT);
1823 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head;
1824 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1825 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
1826 sc->sis_cdata.sis_tx_cnt += cnt;
1833 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1834 * to the mbuf data regions directly in the transmit lists. We also save a
1835 * copy of the pointers since the transmit list fragment pointers are
1836 * physical addresses.
1840 sis_start(struct ifnet *ifp)
1842 struct sis_softc *sc;
1843 struct mbuf *m_head = NULL;
1851 idx = sc->sis_cdata.sis_tx_prod;
1853 if (ifp->if_flags & IFF_OACTIVE)
1856 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) {
1857 IF_DEQUEUE(&ifp->if_snd, m_head);
1861 if (sis_encap(sc, m_head, &idx)) {
1862 IF_PREPEND(&ifp->if_snd, m_head);
1863 ifp->if_flags |= IFF_OACTIVE;
1868 * If there's a BPF listener, bounce a copy of this frame
1871 BPF_MTAP(ifp, m_head);
1875 sc->sis_cdata.sis_tx_prod = idx;
1876 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1879 * Set a timeout in case the chip goes out to lunch.
1887 struct sis_softc *sc = xsc;
1888 struct ifnet *ifp = &sc->arpcom.ac_if;
1889 struct mii_data *mii;
1895 * Cancel pending I/O and free all RX/TX buffers.
1899 mii = device_get_softc(sc->sis_miibus);
1901 /* Set MAC address */
1902 if (sc->sis_type == SIS_TYPE_83815) {
1903 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1904 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1905 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1906 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1907 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1908 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1909 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1910 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1911 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1913 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1914 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1915 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1916 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1917 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1918 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1919 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1920 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1921 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1924 /* Init circular RX list. */
1925 if (sis_list_rx_init(sc) == ENOBUFS) {
1926 if_printf(ifp, "initialization failed: "
1927 "no memory for rx buffers\n");
1934 * Init tx descriptors.
1936 sis_list_tx_init(sc);
1939 * For the NatSemi chip, we have to explicitly enable the
1940 * reception of ARP frames, as well as turn on the 'perfect
1941 * match' filter where we store the station address, otherwise
1942 * we won't receive unicasts meant for this host.
1944 if (sc->sis_type == SIS_TYPE_83815) {
1945 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
1946 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
1949 /* If we want promiscuous mode, set the allframes bit. */
1950 if (ifp->if_flags & IFF_PROMISC)
1951 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1953 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1956 * Set the capture broadcast bit to capture broadcast frames.
1958 if (ifp->if_flags & IFF_BROADCAST)
1959 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1961 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1964 * Load the multicast filter.
1966 if (sc->sis_type == SIS_TYPE_83815)
1967 sis_setmulti_ns(sc);
1969 sis_setmulti_sis(sc);
1971 /* Turn the receive filter on */
1972 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
1975 * Load the address of the RX and TX lists.
1977 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr);
1978 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr);
1980 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
1981 * the PCI bus. When this bit is set, the Max DMA Burst Size
1982 * for TX/RX DMA should be no larger than 16 double words.
1984 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN)
1985 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
1987 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
1989 /* Accept Long Packets for VLAN support */
1990 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
1992 /* Set TX configuration */
1993 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)
1994 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
1996 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
1998 /* Set full/half duplex mode. */
1999 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
2000 SIS_SETBIT(sc, SIS_TX_CFG,
2001 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
2002 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
2004 SIS_CLRBIT(sc, SIS_TX_CFG,
2005 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
2006 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
2010 * Enable interrupts.
2012 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
2013 #ifdef DEVICE_POLLING
2015 * ... only enable interrupts if we are not polling, make sure
2016 * they are off otherwise.
2018 if (ifp->if_flags & IFF_POLLING)
2019 CSR_WRITE_4(sc, SIS_IER, 0);
2021 #endif /* DEVICE_POLLING */
2022 CSR_WRITE_4(sc, SIS_IER, 1);
2024 /* Enable receiver and transmitter. */
2025 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2026 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2033 * Page 75 of the DP83815 manual recommends the
2034 * following register settings "for optimum
2035 * performance." Note however that at least three
2036 * of the registers are listed as "reserved" in
2037 * the register map, so who knows what they do.
2039 if (sc->sis_type == SIS_TYPE_83815) {
2040 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2041 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
2042 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
2043 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
2044 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
2047 ifp->if_flags |= IFF_RUNNING;
2048 ifp->if_flags &= ~IFF_OACTIVE;
2052 sc->sis_stat_ch = timeout(sis_tick, sc, hz);
2056 * Set media options.
2059 sis_ifmedia_upd(struct ifnet *ifp)
2061 struct sis_softc *sc;
2062 struct mii_data *mii;
2066 mii = device_get_softc(sc->sis_miibus);
2068 if (mii->mii_instance) {
2069 struct mii_softc *miisc;
2070 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2071 mii_phy_reset(miisc);
2079 * Report current media status.
2082 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2084 struct sis_softc *sc;
2085 struct mii_data *mii;
2089 mii = device_get_softc(sc->sis_miibus);
2091 ifmr->ifm_active = mii->mii_media_active;
2092 ifmr->ifm_status = mii->mii_media_status;
2096 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2098 struct sis_softc *sc = ifp->if_softc;
2099 struct ifreq *ifr = (struct ifreq *) data;
2100 struct mii_data *mii;
2105 if (ifp->if_flags & IFF_UP) {
2108 if (ifp->if_flags & IFF_RUNNING)
2116 if (sc->sis_type == SIS_TYPE_83815)
2117 sis_setmulti_ns(sc);
2119 sis_setmulti_sis(sc);
2125 mii = device_get_softc(sc->sis_miibus);
2127 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2131 error = ether_ioctl(ifp, command, data);
2139 sis_watchdog(struct ifnet *ifp)
2141 struct sis_softc *sc;
2146 if_printf(ifp, "watchdog timeout\n");
2152 if (ifp->if_snd.ifq_head != NULL)
2157 * Stop the adapter and free any mbufs allocated to the
2161 sis_stop(struct sis_softc *sc)
2166 ifp = &sc->arpcom.ac_if;
2169 untimeout(sis_tick, sc, sc->sis_stat_ch);
2171 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2172 #ifdef DEVICE_POLLING
2173 ether_poll_deregister(ifp);
2175 CSR_WRITE_4(sc, SIS_IER, 0);
2176 CSR_WRITE_4(sc, SIS_IMR, 0);
2177 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2179 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2180 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2185 * Free data in the RX lists.
2187 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2188 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) {
2189 bus_dmamap_unload(sc->sis_tag,
2190 sc->sis_ldata.sis_rx_list[i].sis_map);
2191 bus_dmamap_destroy(sc->sis_tag,
2192 sc->sis_ldata.sis_rx_list[i].sis_map);
2193 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf);
2194 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL;
2197 bzero(sc->sis_ldata.sis_rx_list, sizeof(sc->sis_ldata.sis_rx_list));
2200 * Free the TX list buffers.
2202 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2203 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) {
2204 bus_dmamap_unload(sc->sis_tag,
2205 sc->sis_ldata.sis_tx_list[i].sis_map);
2206 bus_dmamap_destroy(sc->sis_tag,
2207 sc->sis_ldata.sis_tx_list[i].sis_map);
2208 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf);
2209 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL;
2213 bzero(sc->sis_ldata.sis_tx_list, sizeof(sc->sis_ldata.sis_tx_list));
2217 * Stop all chip I/O so that the kernel's probe routines don't
2218 * get confused by errant DMAs when rebooting.
2221 sis_shutdown(device_t dev)
2223 struct sis_softc *sc;
2225 sc = device_get_softc(dev);