sys/dev/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/i915_drm.h>
  31 #include <drm/drm_panel.h>
  32 #include <drm/drm_mipi_dsi.h>
  33 #include <linux/slab.h>
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36 #include "intel_dsi.h"
  37
  38 static const struct {
  39         u16 panel_id;
  40         struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id);
  41 } intel_dsi_drivers[] = {
  42         {
  43                 .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
  44                 .init = vbt_panel_init,
  45         },
  46 };
  47
  48 static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  49 {
  50         struct drm_encoder *encoder = &intel_dsi->base.base;
  51         struct drm_device *dev = encoder->dev;
  52         struct drm_i915_private *dev_priv = dev->dev_private;
  53         u32 mask;
  54
  55         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  56                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  57
  58         if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100))
  59                 DRM_ERROR("DPI FIFOs are not empty\n");
  60 }
  61
  62 static void write_data(struct drm_i915_private *dev_priv, u32 reg,
  63                        const u8 *data, u32 len)
  64 {
  65         u32 i, j;
  66
  67         for (i = 0; i < len; i += 4) {
  68                 u32 val = 0;
  69
  70                 for (j = 0; j < min_t(u32, len - i, 4); j++)
  71                         val |= *data++ << 8 * j;
  72
  73                 I915_WRITE(reg, val);
  74         }
  75 }
  76
  77 static void read_data(struct drm_i915_private *dev_priv, u32 reg,
  78                       u8 *data, u32 len)
  79 {
  80         u32 i, j;
  81
  82         for (i = 0; i < len; i += 4) {
  83                 u32 val = I915_READ(reg);
  84
  85                 for (j = 0; j < min_t(u32, len - i, 4); j++)
  86                         *data++ = val >> 8 * j;
  87         }
  88 }
  89
  90 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
  91                                        const struct mipi_dsi_msg *msg)
  92 {
  93         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
  94         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
  95         struct drm_i915_private *dev_priv = dev->dev_private;
  96         enum port port = intel_dsi_host->port;
  97         struct mipi_dsi_packet packet;
  98         ssize_t ret;
  99         const u8 *header, *data;
 100         u32 data_reg, data_mask, ctrl_reg, ctrl_mask;
 101
 102         ret = mipi_dsi_create_packet(&packet, msg);
 103         if (ret < 0)
 104                 return ret;
 105
 106         header = packet.header;
 107         data = packet.payload;
 108
 109         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 110                 data_reg = MIPI_LP_GEN_DATA(port);
 111                 data_mask = LP_DATA_FIFO_FULL;
 112                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 113                 ctrl_mask = LP_CTRL_FIFO_FULL;
 114         } else {
 115                 data_reg = MIPI_HS_GEN_DATA(port);
 116                 data_mask = HS_DATA_FIFO_FULL;
 117                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 118                 ctrl_mask = HS_CTRL_FIFO_FULL;
 119         }
 120
 121         /* note: this is never true for reads */
 122         if (packet.payload_length) {
 123
 124                 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50))
 125                         DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
 126
 127                 write_data(dev_priv, data_reg, packet.payload,
 128                            packet.payload_length);
 129         }
 130
 131         if (msg->rx_len) {
 132                 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 133         }
 134
 135         if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) {
 136                 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
 137         }
 138
 139         I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
 140
 141         /* ->rx_len is set only for reads */
 142         if (msg->rx_len) {
 143                 data_mask = GEN_READ_DATA_AVAIL;
 144                 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50))
 145                         DRM_ERROR("Timeout waiting for read data.\n");
 146
 147                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 148         }
 149
 150         /* XXX: fix for reads and writes */
 151         return 4 + packet.payload_length;
 152 }
 153
 154 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 155                                  struct mipi_dsi_device *dsi)
 156 {
 157         return 0;
 158 }
 159
 160 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 161                                  struct mipi_dsi_device *dsi)
 162 {
 163         return 0;
 164 }
 165
 166 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 167         .attach = intel_dsi_host_attach,
 168         .detach = intel_dsi_host_detach,
 169         .transfer = intel_dsi_host_transfer,
 170 };
 171
 172 static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
 173                                                   enum port port)
 174 {
 175         struct intel_dsi_host *host;
 176         struct mipi_dsi_device *device;
 177
 178         host = kzalloc(sizeof(*host), GFP_KERNEL);
 179         if (!host)
 180                 return NULL;
 181
 182         host->base.ops = &intel_dsi_host_ops;
 183         host->intel_dsi = intel_dsi;
 184         host->port = port;
 185
 186         /*
 187          * We should call mipi_dsi_host_register(&host->base) here, but we don't
 188          * have a host->dev, and we don't have OF stuff either. So just use the
 189          * dsi framework as a library and hope for the best. Create the dsi
 190          * devices by ourselves here too. Need to be careful though, because we
 191          * don't initialize any of the driver model devices here.
 192          */
 193         device = kzalloc(sizeof(*device), GFP_KERNEL);
 194         if (!device) {
 195                 kfree(host);
 196                 return NULL;
 197         }
 198
 199         device->host = &host->base;
 200         host->device = device;
 201
 202         return host;
 203 }
 204
 205 /*
 206  * send a video mode command
 207  *
 208  * XXX: commands with data in MIPI_DPI_DATA?
 209  */
 210 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 211                         enum port port)
 212 {
 213         struct drm_encoder *encoder = &intel_dsi->base.base;
 214         struct drm_device *dev = encoder->dev;
 215         struct drm_i915_private *dev_priv = dev->dev_private;
 216         u32 mask;
 217
 218         /* XXX: pipe, hs */
 219         if (hs)
 220                 cmd &= ~DPI_LP_MODE;
 221         else
 222                 cmd |= DPI_LP_MODE;
 223
 224         /* clear bit */
 225         I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 226
 227         /* XXX: old code skips write if control unchanged */
 228         if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
 229                 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
 230
 231         I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 232
 233         mask = SPL_PKT_SENT_INTERRUPT;
 234         if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100))
 235                 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
 236
 237         return 0;
 238 }
 239
 240 static void band_gap_reset(struct drm_i915_private *dev_priv)
 241 {
 242         mutex_lock(&dev_priv->dpio_lock);
 243
 244         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 245         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 246         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 247         udelay(150);
 248         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 249         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 250
 251         mutex_unlock(&dev_priv->dpio_lock);
 252 }
 253
 254 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
 255 {
 256         return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
 257 }
 258
 259 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
 260 {
 261         return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
 262 }
 263
 264 static void intel_dsi_hot_plug(struct intel_encoder *encoder)
 265 {
 266         DRM_DEBUG_KMS("\n");
 267 }
 268
 269 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 270                                      struct intel_crtc_state *config)
 271 {
 272         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 273                                                    base);
 274         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 275         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 276         struct drm_display_mode *adjusted_mode = &config->base.adjusted_mode;
 277
 278         DRM_DEBUG_KMS("\n");
 279
 280         if (fixed_mode)
 281                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 282
 283         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 284         adjusted_mode->flags = 0;
 285
 286         return true;
 287 }
 288
 289 static void intel_dsi_port_enable(struct intel_encoder *encoder)
 290 {
 291         struct drm_device *dev = encoder->base.dev;
 292         struct drm_i915_private *dev_priv = dev->dev_private;
 293         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 294         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 295         enum port port;
 296         u32 temp;
 297
 298         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 299                 temp = I915_READ(VLV_CHICKEN_3);
 300                 temp &= ~PIXEL_OVERLAP_CNT_MASK |
 301                                         intel_dsi->pixel_overlap <<
 302                                         PIXEL_OVERLAP_CNT_SHIFT;
 303                 I915_WRITE(VLV_CHICKEN_3, temp);
 304         }
 305
 306         for_each_dsi_port(port, intel_dsi->ports) {
 307                 temp = I915_READ(MIPI_PORT_CTRL(port));
 308                 temp &= ~LANE_CONFIGURATION_MASK;
 309                 temp &= ~DUAL_LINK_MODE_MASK;
 310
 311                 if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
 312                         temp |= (intel_dsi->dual_link - 1)
 313                                                 << DUAL_LINK_MODE_SHIFT;
 314                         temp |= intel_crtc->pipe ?
 315                                         LANE_CONFIGURATION_DUAL_LINK_B :
 316                                         LANE_CONFIGURATION_DUAL_LINK_A;
 317                 }
 318                 /* assert ip_tg_enable signal */
 319                 I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
 320                 POSTING_READ(MIPI_PORT_CTRL(port));
 321         }
 322 }
 323
 324 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 325 {
 326         struct drm_device *dev = encoder->base.dev;
 327         struct drm_i915_private *dev_priv = dev->dev_private;
 328         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 329         enum port port;
 330         u32 temp;
 331
 332         for_each_dsi_port(port, intel_dsi->ports) {
 333                 /* de-assert ip_tg_enable signal */
 334                 temp = I915_READ(MIPI_PORT_CTRL(port));
 335                 I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
 336                 POSTING_READ(MIPI_PORT_CTRL(port));
 337         }
 338 }
 339
 340 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 341 {
 342         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 343         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 344         enum port port;
 345         u32 val;
 346
 347         DRM_DEBUG_KMS("\n");
 348
 349         mutex_lock(&dev_priv->dpio_lock);
 350         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 351          * needed everytime after power gate */
 352         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 353         mutex_unlock(&dev_priv->dpio_lock);
 354
 355         /* bandgap reset is needed after everytime we do power gate */
 356         band_gap_reset(dev_priv);
 357
 358         for_each_dsi_port(port, intel_dsi->ports) {
 359
 360                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
 361                 usleep_range(2500, 3000);
 362
 363                 /* Enable MIPI PHY transparent latch
 364                  * Common bit for both MIPI Port A & MIPI Port C
 365                  * No similar bit in MIPI Port C reg
 366                  */
 367                 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 368                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 369                 usleep_range(1000, 1500);
 370
 371                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
 372                 usleep_range(2500, 3000);
 373
 374                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
 375                 usleep_range(2500, 3000);
 376         }
 377 }
 378
 379 static void intel_dsi_enable(struct intel_encoder *encoder)
 380 {
 381         struct drm_device *dev = encoder->base.dev;
 382         struct drm_i915_private *dev_priv = dev->dev_private;
 383         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 384         enum port port;
 385
 386         DRM_DEBUG_KMS("\n");
 387
 388         if (is_cmd_mode(intel_dsi)) {
 389                 for_each_dsi_port(port, intel_dsi->ports)
 390                         I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 391         } else {
 392                 msleep(20); /* XXX */
 393                 for_each_dsi_port(port, intel_dsi->ports)
 394                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 395                 msleep(100);
 396
 397                 drm_panel_enable(intel_dsi->panel);
 398
 399                 for_each_dsi_port(port, intel_dsi->ports)
 400                         wait_for_dsi_fifo_empty(intel_dsi, port);
 401
 402                 intel_dsi_port_enable(encoder);
 403         }
 404 }
 405
 406 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 407 {
 408         struct drm_device *dev = encoder->base.dev;
 409         struct drm_i915_private *dev_priv = dev->dev_private;
 410         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 411         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 412         enum i915_pipe pipe = intel_crtc->pipe;
 413         enum port port;
 414         u32 tmp;
 415
 416         DRM_DEBUG_KMS("\n");
 417
 418         /* Disable DPOunit clock gating, can stall pipe
 419          * and we need DPLL REFA always enabled */
 420         tmp = I915_READ(DPLL(pipe));
 421         tmp |= DPLL_REFA_CLK_ENABLE_VLV;
 422         I915_WRITE(DPLL(pipe), tmp);
 423
 424         /* update the hw state for DPLL */
 425         intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
 426                 DPLL_REFA_CLK_ENABLE_VLV;
 427
 428         tmp = I915_READ(DSPCLK_GATE_D);
 429         tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
 430         I915_WRITE(DSPCLK_GATE_D, tmp);
 431
 432         /* put device in ready state */
 433         intel_dsi_device_ready(encoder);
 434
 435         msleep(intel_dsi->panel_on_delay);
 436
 437         drm_panel_prepare(intel_dsi->panel);
 438
 439         for_each_dsi_port(port, intel_dsi->ports)
 440                 wait_for_dsi_fifo_empty(intel_dsi, port);
 441
 442         /* Enable port in pre-enable phase itself because as per hw team
 443          * recommendation, port should be enabled befor plane & pipe */
 444         intel_dsi_enable(encoder);
 445 }
 446
 447 static void intel_dsi_enable_nop(struct intel_encoder *encoder)
 448 {
 449         DRM_DEBUG_KMS("\n");
 450
 451         /* for DSI port enable has to be done before pipe
 452          * and plane enable, so port enable is done in
 453          * pre_enable phase itself unlike other encoders
 454          */
 455 }
 456
 457 static void intel_dsi_pre_disable(struct intel_encoder *encoder)
 458 {
 459         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 460         enum port port;
 461
 462         DRM_DEBUG_KMS("\n");
 463
 464         if (is_vid_mode(intel_dsi)) {
 465                 /* Send Shutdown command to the panel in LP mode */
 466                 for_each_dsi_port(port, intel_dsi->ports)
 467                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 468                 msleep(10);
 469         }
 470 }
 471
 472 static void intel_dsi_disable(struct intel_encoder *encoder)
 473 {
 474         struct drm_device *dev = encoder->base.dev;
 475         struct drm_i915_private *dev_priv = dev->dev_private;
 476         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 477         enum port port;
 478         u32 temp;
 479
 480         DRM_DEBUG_KMS("\n");
 481
 482         if (is_vid_mode(intel_dsi)) {
 483                 for_each_dsi_port(port, intel_dsi->ports)
 484                         wait_for_dsi_fifo_empty(intel_dsi, port);
 485
 486                 intel_dsi_port_disable(encoder);
 487                 msleep(2);
 488         }
 489
 490         for_each_dsi_port(port, intel_dsi->ports) {
 491                 /* Panel commands can be sent when clock is in LP11 */
 492                 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
 493
 494                 temp = I915_READ(MIPI_CTRL(port));
 495                 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 496                 I915_WRITE(MIPI_CTRL(port), temp |
 497                            intel_dsi->escape_clk_div <<
 498                            ESCAPE_CLOCK_DIVIDER_SHIFT);
 499
 500                 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 501
 502                 temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
 503                 temp &= ~VID_MODE_FORMAT_MASK;
 504                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
 505
 506                 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
 507         }
 508         /* if disable packets are sent before sending shutdown packet then in
 509          * some next enable sequence send turn on packet error is observed */
 510         drm_panel_disable(intel_dsi->panel);
 511
 512         for_each_dsi_port(port, intel_dsi->ports)
 513                 wait_for_dsi_fifo_empty(intel_dsi, port);
 514 }
 515
 516 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 517 {
 518         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 519         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 520         enum port port;
 521         u32 val;
 522
 523         DRM_DEBUG_KMS("\n");
 524         for_each_dsi_port(port, intel_dsi->ports) {
 525
 526                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 527                                                         ULPS_STATE_ENTER);
 528                 usleep_range(2000, 2500);
 529
 530                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 531                                                         ULPS_STATE_EXIT);
 532                 usleep_range(2000, 2500);
 533
 534                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 535                                                         ULPS_STATE_ENTER);
 536                 usleep_range(2000, 2500);
 537
 538                 /* Wait till Clock lanes are in LP-00 state for MIPI Port A
 539                  * only. MIPI Port C has no similar bit for checking
 540                  */
 541                 if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT)
 542                                                         == 0x00000), 30))
 543                         DRM_ERROR("DSI LP not going Low\n");
 544
 545                 /* Disable MIPI PHY transparent latch
 546                  * Common bit for both MIPI Port A & MIPI Port C
 547                  */
 548                 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 549                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD);
 550                 usleep_range(1000, 1500);
 551
 552                 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
 553                 usleep_range(2000, 2500);
 554         }
 555
 556         vlv_disable_dsi_pll(encoder);
 557 }
 558
 559 static void intel_dsi_post_disable(struct intel_encoder *encoder)
 560 {
 561         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 562         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 563         u32 val;
 564
 565         DRM_DEBUG_KMS("\n");
 566
 567         intel_dsi_disable(encoder);
 568
 569         intel_dsi_clear_device_ready(encoder);
 570
 571         val = I915_READ(DSPCLK_GATE_D);
 572         val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 573         I915_WRITE(DSPCLK_GATE_D, val);
 574
 575         drm_panel_unprepare(intel_dsi->panel);
 576
 577         msleep(intel_dsi->panel_off_delay);
 578         msleep(intel_dsi->panel_pwr_cycle_delay);
 579 }
 580
 581 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 582                                    enum i915_pipe *pipe)
 583 {
 584         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 585         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 586         struct drm_device *dev = encoder->base.dev;
 587         enum intel_display_power_domain power_domain;
 588         u32 dpi_enabled, func;
 589         enum port port;
 590
 591         DRM_DEBUG_KMS("\n");
 592
 593         power_domain = intel_display_port_power_domain(encoder);
 594         if (!intel_display_power_is_enabled(dev_priv, power_domain))
 595                 return false;
 596
 597         /* XXX: this only works for one DSI output */
 598         for_each_dsi_port(port, intel_dsi->ports) {
 599                 func = I915_READ(MIPI_DSI_FUNC_PRG(port));
 600                 dpi_enabled = I915_READ(MIPI_PORT_CTRL(port)) &
 601                                                         DPI_ENABLE;
 602
 603                 /* Due to some hardware limitations on BYT, MIPI Port C DPI
 604                  * Enable bit does not get set. To check whether DSI Port C
 605                  * was enabled in BIOS, check the Pipe B enable bit
 606                  */
 607                 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
 608                     (port == PORT_C))
 609                         dpi_enabled = I915_READ(PIPECONF(PIPE_B)) &
 610                                                         PIPECONF_ENABLE;
 611
 612                 if (dpi_enabled || (func & CMD_MODE_DATA_WIDTH_MASK)) {
 613                         if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) {
 614                                 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
 615                                 return true;
 616                         }
 617                 }
 618         }
 619
 620         return false;
 621 }
 622
 623 static void intel_dsi_get_config(struct intel_encoder *encoder,
 624                                  struct intel_crtc_state *pipe_config)
 625 {
 626         u32 pclk;
 627         DRM_DEBUG_KMS("\n");
 628
 629         /*
 630          * DPLL_MD is not used in case of DSI, reading will get some default value
 631          * set dpll_md = 0
 632          */
 633         pipe_config->dpll_hw_state.dpll_md = 0;
 634
 635         pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
 636         if (!pclk)
 637                 return;
 638
 639         pipe_config->base.adjusted_mode.crtc_clock = pclk;
 640         pipe_config->port_clock = pclk;
 641 }
 642
 643 static enum drm_mode_status
 644 intel_dsi_mode_valid(struct drm_connector *connector,
 645                      struct drm_display_mode *mode)
 646 {
 647         struct intel_connector *intel_connector = to_intel_connector(connector);
 648         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 649
 650         DRM_DEBUG_KMS("\n");
 651
 652         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 653                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
 654                 return MODE_NO_DBLESCAN;
 655         }
 656
 657         if (fixed_mode) {
 658                 if (mode->hdisplay > fixed_mode->hdisplay)
 659                         return MODE_PANEL;
 660                 if (mode->vdisplay > fixed_mode->vdisplay)
 661                         return MODE_PANEL;
 662         }
 663
 664         return MODE_OK;
 665 }
 666
 667 /* return txclkesc cycles in terms of divider and duration in us */
 668 static u16 txclkesc(u32 divider, unsigned int us)
 669 {
 670         switch (divider) {
 671         case ESCAPE_CLOCK_DIVIDER_1:
 672         default:
 673                 return 20 * us;
 674         case ESCAPE_CLOCK_DIVIDER_2:
 675                 return 10 * us;
 676         case ESCAPE_CLOCK_DIVIDER_4:
 677                 return 5 * us;
 678         }
 679 }
 680
 681 /* return pixels in terms of txbyteclkhs */
 682 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
 683                        u16 burst_mode_ratio)
 684 {
 685         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
 686                                          8 * 100), lane_count);
 687 }
 688
 689 static void set_dsi_timings(struct drm_encoder *encoder,
 690                             const struct drm_display_mode *mode)
 691 {
 692         struct drm_device *dev = encoder->dev;
 693         struct drm_i915_private *dev_priv = dev->dev_private;
 694         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 695         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 696         enum port port;
 697         unsigned int bpp = intel_crtc->config->pipe_bpp;
 698         unsigned int lane_count = intel_dsi->lane_count;
 699
 700         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
 701
 702         hactive = mode->hdisplay;
 703         hfp = mode->hsync_start - mode->hdisplay;
 704         hsync = mode->hsync_end - mode->hsync_start;
 705         hbp = mode->htotal - mode->hsync_end;
 706
 707         if (intel_dsi->dual_link) {
 708                 hactive /= 2;
 709                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 710                         hactive += intel_dsi->pixel_overlap;
 711                 hfp /= 2;
 712                 hsync /= 2;
 713                 hbp /= 2;
 714         }
 715
 716         vfp = mode->vsync_start - mode->vdisplay;
 717         vsync = mode->vsync_end - mode->vsync_start;
 718         vbp = mode->vtotal - mode->vsync_end;
 719
 720         /* horizontal values are in terms of high speed byte clock */
 721         hactive = txbyteclkhs(hactive, bpp, lane_count,
 722                               intel_dsi->burst_mode_ratio);
 723         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 724         hsync = txbyteclkhs(hsync, bpp, lane_count,
 725                             intel_dsi->burst_mode_ratio);
 726         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 727
 728         for_each_dsi_port(port, intel_dsi->ports) {
 729                 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
 730                 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
 731
 732                 /* meaningful for video mode non-burst sync pulse mode only,
 733                  * can be zero for non-burst sync events and burst modes */
 734                 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
 735                 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
 736
 737                 /* vertical values are in terms of lines */
 738                 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
 739                 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
 740                 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
 741         }
 742 }
 743
 744 static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 745 {
 746         struct drm_encoder *encoder = &intel_encoder->base;
 747         struct drm_device *dev = encoder->dev;
 748         struct drm_i915_private *dev_priv = dev->dev_private;
 749         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 750         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 751         struct drm_display_mode *adjusted_mode =
 752                 &intel_crtc->config->base.adjusted_mode;
 753         enum port port;
 754         unsigned int bpp = intel_crtc->config->pipe_bpp;
 755         u32 val, tmp;
 756         u16 mode_hdisplay;
 757
 758         DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
 759
 760         mode_hdisplay = adjusted_mode->hdisplay;
 761
 762         if (intel_dsi->dual_link) {
 763                 mode_hdisplay /= 2;
 764                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 765                         mode_hdisplay += intel_dsi->pixel_overlap;
 766         }
 767
 768         for_each_dsi_port(port, intel_dsi->ports) {
 769                 /* escape clock divider, 20MHz, shared for A and C.
 770                  * device ready must be off when doing this! txclkesc? */
 771                 tmp = I915_READ(MIPI_CTRL(PORT_A));
 772                 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 773                 I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
 774
 775                 /* read request priority is per pipe */
 776                 tmp = I915_READ(MIPI_CTRL(port));
 777                 tmp &= ~READ_REQUEST_PRIORITY_MASK;
 778                 I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
 779
 780                 /* XXX: why here, why like this? handling in irq handler?! */
 781                 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
 782                 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
 783
 784                 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
 785
 786                 I915_WRITE(MIPI_DPI_RESOLUTION(port),
 787                         adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
 788                         mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
 789         }
 790
 791         set_dsi_timings(encoder, adjusted_mode);
 792
 793         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
 794         if (is_cmd_mode(intel_dsi)) {
 795                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
 796                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
 797         } else {
 798                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
 799
 800                 /* XXX: cross-check bpp vs. pixel format? */
 801                 val |= intel_dsi->pixel_format;
 802         }
 803
 804         tmp = 0;
 805         if (intel_dsi->eotp_pkt == 0)
 806                 tmp |= EOT_DISABLE;
 807         if (intel_dsi->clock_stop)
 808                 tmp |= CLOCKSTOP;
 809
 810         for_each_dsi_port(port, intel_dsi->ports) {
 811                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
 812
 813                 /* timeouts for recovery. one frame IIUC. if counter expires,
 814                  * EOT and stop state. */
 815
 816                 /*
 817                  * In burst mode, value greater than one DPI line Time in byte
 818                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
 819                  * said value is recommended.
 820                  *
 821                  * In non-burst mode, Value greater than one DPI frame time in
 822                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
 823                  * said value is recommended.
 824                  *
 825                  * In DBI only mode, value greater than one DBI frame time in
 826                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
 827                  * said value is recommended.
 828                  */
 829
 830                 if (is_vid_mode(intel_dsi) &&
 831                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 832                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
 833                                 txbyteclkhs(adjusted_mode->htotal, bpp,
 834                                         intel_dsi->lane_count,
 835                                         intel_dsi->burst_mode_ratio) + 1);
 836                 } else {
 837                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
 838                                 txbyteclkhs(adjusted_mode->vtotal *
 839                                         adjusted_mode->htotal,
 840                                         bpp, intel_dsi->lane_count,
 841                                         intel_dsi->burst_mode_ratio) + 1);
 842                 }
 843                 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
 844                 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
 845                                                 intel_dsi->turn_arnd_val);
 846                 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
 847                                                 intel_dsi->rst_timer_val);
 848
 849                 /* dphy stuff */
 850
 851                 /* in terms of low power clock */
 852                 I915_WRITE(MIPI_INIT_COUNT(port),
 853                                 txclkesc(intel_dsi->escape_clk_div, 100));
 854
 855
 856                 /* recovery disables */
 857                 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
 858
 859                 /* in terms of low power clock */
 860                 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
 861
 862                 /* in terms of txbyteclkhs. actual high to low switch +
 863                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
 864                  *
 865                  * XXX: write MIPI_STOP_STATE_STALL?
 866                  */
 867                 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
 868                                                 intel_dsi->hs_to_lp_count);
 869
 870                 /* XXX: low power clock equivalence in terms of byte clock.
 871                  * the number of byte clocks occupied in one low power clock.
 872                  * based on txbyteclkhs and txclkesc.
 873                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
 874                  * ) / 105.???
 875                  */
 876                 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
 877
 878                 /* the bw essential for transmitting 16 long packets containing
 879                  * 252 bytes meant for dcs write memory command is programmed in
 880                  * this register in terms of byte clocks. based on dsi transfer
 881                  * rate and the number of lanes configured the time taken to
 882                  * transmit 16 long packets in a dsi stream varies. */
 883                 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
 884
 885                 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
 886                 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
 887                 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
 888
 889                 if (is_vid_mode(intel_dsi))
 890                         /* Some panels might have resolution which is not a
 891                          * multiple of 64 like 1366 x 768. Enable RANDOM
 892                          * resolution support for such panels by default */
 893                         I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
 894                                 intel_dsi->video_frmt_cfg_bits |
 895                                 intel_dsi->video_mode_format |
 896                                 IP_TG_CONFIG |
 897                                 RANDOM_DPI_DISPLAY_RESOLUTION);
 898         }
 899 }
 900
 901 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
 902 {
 903         DRM_DEBUG_KMS("\n");
 904
 905         intel_dsi_prepare(encoder);
 906
 907         vlv_enable_dsi_pll(encoder);
 908 }
 909
 910 static enum drm_connector_status
 911 intel_dsi_detect(struct drm_connector *connector, bool force)
 912 {
 913         return connector_status_connected;
 914 }
 915
 916 static int intel_dsi_get_modes(struct drm_connector *connector)
 917 {
 918         struct intel_connector *intel_connector = to_intel_connector(connector);
 919         struct drm_display_mode *mode;
 920
 921         DRM_DEBUG_KMS("\n");
 922
 923         if (!intel_connector->panel.fixed_mode) {
 924                 DRM_DEBUG_KMS("no fixed mode\n");
 925                 return 0;
 926         }
 927
 928         mode = drm_mode_duplicate(connector->dev,
 929                                   intel_connector->panel.fixed_mode);
 930         if (!mode) {
 931                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
 932                 return 0;
 933         }
 934
 935         drm_mode_probed_add(connector, mode);
 936         return 1;
 937 }
 938
 939 static void intel_dsi_connector_destroy(struct drm_connector *connector)
 940 {
 941         struct intel_connector *intel_connector = to_intel_connector(connector);
 942
 943         DRM_DEBUG_KMS("\n");
 944         intel_panel_fini(&intel_connector->panel);
 945         drm_connector_cleanup(connector);
 946         kfree(connector);
 947 }
 948
 949 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
 950 {
 951         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 952
 953         if (intel_dsi->panel) {
 954                 drm_panel_detach(intel_dsi->panel);
 955                 /* XXX: Logically this call belongs in the panel driver. */
 956                 drm_panel_remove(intel_dsi->panel);
 957         }
 958         intel_encoder_destroy(encoder);
 959 }
 960
 961 static const struct drm_encoder_funcs intel_dsi_funcs = {
 962         .destroy = intel_dsi_encoder_destroy,
 963 };
 964
 965 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
 966         .get_modes = intel_dsi_get_modes,
 967         .mode_valid = intel_dsi_mode_valid,
 968         .best_encoder = intel_best_encoder,
 969 };
 970
 971 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
 972         .dpms = intel_connector_dpms,
 973         .detect = intel_dsi_detect,
 974         .destroy = intel_dsi_connector_destroy,
 975         .fill_modes = drm_helper_probe_single_connector_modes,
 976         .atomic_get_property = intel_connector_atomic_get_property,
 977         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 978         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 979 };
 980
 981 void intel_dsi_init(struct drm_device *dev)
 982 {
 983         struct intel_dsi *intel_dsi;
 984         struct intel_encoder *intel_encoder;
 985         struct drm_encoder *encoder;
 986         struct intel_connector *intel_connector;
 987         struct drm_connector *connector;
 988         struct drm_display_mode *scan, *fixed_mode = NULL;
 989         struct drm_i915_private *dev_priv = dev->dev_private;
 990         enum port port;
 991         unsigned int i;
 992
 993         DRM_DEBUG_KMS("\n");
 994
 995         /* There is no detection method for MIPI so rely on VBT */
 996         if (!dev_priv->vbt.has_mipi)
 997                 return;
 998
 999         if (IS_VALLEYVIEW(dev)) {
1000                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1001         } else {
1002                 DRM_ERROR("Unsupported Mipi device to reg base");
1003                 return;
1004         }
1005
1006         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1007         if (!intel_dsi)
1008                 return;
1009
1010         intel_connector = intel_connector_alloc();
1011         if (!intel_connector) {
1012                 kfree(intel_dsi);
1013                 return;
1014         }
1015
1016         intel_encoder = &intel_dsi->base;
1017         encoder = &intel_encoder->base;
1018         intel_dsi->attached_connector = intel_connector;
1019
1020         connector = &intel_connector->base;
1021
1022         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
1023
1024         /* XXX: very likely not all of these are needed */
1025         intel_encoder->hot_plug = intel_dsi_hot_plug;
1026         intel_encoder->compute_config = intel_dsi_compute_config;
1027         intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
1028         intel_encoder->pre_enable = intel_dsi_pre_enable;
1029         intel_encoder->enable = intel_dsi_enable_nop;
1030         intel_encoder->disable = intel_dsi_pre_disable;
1031         intel_encoder->post_disable = intel_dsi_post_disable;
1032         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1033         intel_encoder->get_config = intel_dsi_get_config;
1034
1035         intel_connector->get_hw_state = intel_connector_get_hw_state;
1036         intel_connector->unregister = intel_connector_unregister;
1037
1038         /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
1039         if (dev_priv->vbt.dsi.config->dual_link) {
1040                 /* XXX: does dual link work on either pipe? */
1041                 intel_encoder->crtc_mask = (1 << PIPE_A);
1042                 intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
1043         } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) {
1044                 intel_encoder->crtc_mask = (1 << PIPE_A);
1045                 intel_dsi->ports = (1 << PORT_A);
1046         } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) {
1047                 intel_encoder->crtc_mask = (1 << PIPE_B);
1048                 intel_dsi->ports = (1 << PORT_C);
1049         }
1050
1051         /* Create a DSI host (and a device) for each port. */
1052         for_each_dsi_port(port, intel_dsi->ports) {
1053                 struct intel_dsi_host *host;
1054
1055                 host = intel_dsi_host_init(intel_dsi, port);
1056                 if (!host)
1057                         goto err;
1058
1059                 intel_dsi->dsi_hosts[port] = host;
1060         }
1061
1062         for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) {
1063                 intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi,
1064                                                              intel_dsi_drivers[i].panel_id);
1065                 if (intel_dsi->panel)
1066                         break;
1067         }
1068
1069         if (!intel_dsi->panel) {
1070                 DRM_DEBUG_KMS("no device found\n");
1071                 goto err;
1072         }
1073
1074         intel_encoder->type = INTEL_OUTPUT_DSI;
1075         intel_encoder->cloneable = 0;
1076         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1077                            DRM_MODE_CONNECTOR_DSI);
1078
1079         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1080
1081         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1082         connector->interlace_allowed = false;
1083         connector->doublescan_allowed = false;
1084
1085         intel_connector_attach_encoder(intel_connector, intel_encoder);
1086
1087         drm_connector_register(connector);
1088
1089         drm_panel_attach(intel_dsi->panel, connector);
1090
1091         mutex_lock(&dev->mode_config.mutex);
1092         drm_panel_get_modes(intel_dsi->panel);
1093         list_for_each_entry(scan, &connector->probed_modes, head) {
1094                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1095                         fixed_mode = drm_mode_duplicate(dev, scan);
1096                         break;
1097                 }
1098         }
1099         mutex_unlock(&dev->mode_config.mutex);
1100
1101         if (!fixed_mode) {
1102                 DRM_DEBUG_KMS("no fixed mode\n");
1103                 goto err;
1104         }
1105
1106         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1107
1108         return;
1109
1110 err:
1111         drm_encoder_cleanup(&intel_encoder->base);
1112         kfree(intel_dsi);
1113         kfree(intel_connector);
1114 }