2 * Copyright © 2006 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
25 * Thomas Richter <thor@math.tu-berlin.de>
27 * Minor modifications (Dithering enable):
28 * Thomas Richter <thor@math.tu-berlin.de>
35 * register definitions for the i82807aa.
37 * Documentation on this chipset can be found in datasheet #29069001 at
42 * VCH Revision & GMBus Base Addr
45 # define VR00_BASE_ADDRESS_MASK 0x007f
48 * Functionality Enable
53 * Enable the panel fitter
55 # define VR01_PANEL_FIT_ENABLE (1 << 3)
57 * Enables the LCD display.
59 * This must not be set while VR01_DVO_BYPASS_ENABLE is set.
61 # define VR01_LCD_ENABLE (1 << 2)
62 /** Enables the DVO repeater. */
63 # define VR01_DVO_BYPASS_ENABLE (1 << 1)
64 /** Enables the DVO clock */
65 # define VR01_DVO_ENABLE (1 << 0)
66 /** Enable dithering for 18bpp panels. Not documented. */
67 # define VR01_DITHER_ENABLE (1 << 4)
70 * LCD Interface Format
73 /** Enables LVDS output instead of CMOS */
74 # define VR10_LVDS_ENABLE (1 << 4)
75 /** Enables 18-bit LVDS output. */
76 # define VR10_INTERFACE_1X18 (0 << 2)
77 /** Enables 24-bit LVDS or CMOS output */
78 # define VR10_INTERFACE_1X24 (1 << 2)
79 /** Enables 2x18-bit LVDS or CMOS output. */
80 # define VR10_INTERFACE_2X18 (2 << 2)
81 /** Enables 2x24-bit LVDS output */
82 # define VR10_INTERFACE_2X24 (3 << 2)
83 /** Mask that defines the depth of the pipeline */
84 # define VR10_INTERFACE_DEPTH_MASK (3 << 2)
87 * VR20 LCD Horizontal Display Size
92 * LCD Vertical Display Size
97 * Panel power down status
100 /** Read only bit indicating that the panel is not in a safe poweroff state. */
101 # define VR30_PANEL_ON (1 << 15)
104 # define VR40_STALL_ENABLE (1 << 13)
105 # define VR40_VERTICAL_INTERP_ENABLE (1 << 12)
106 # define VR40_ENHANCED_PANEL_FITTING (1 << 11)
107 # define VR40_HORIZONTAL_INTERP_ENABLE (1 << 10)
108 # define VR40_AUTO_RATIO_ENABLE (1 << 9)
109 # define VR40_CLOCK_GATING_ENABLE (1 << 8)
112 * Panel Fitting Vertical Ratio
113 * (((image_height - 1) << 16) / ((panel_height - 1))) >> 2
118 * Panel Fitting Horizontal Ratio
119 * (((image_width - 1) << 16) / ((panel_width - 1))) >> 2
124 * Horizontal Image Size
143 /* Graphics BIOS scratch 0
146 # define VR8E_PANEL_TYPE_MASK (0xf << 0)
147 # define VR8E_PANEL_INTERFACE_CMOS (0 << 4)
148 # define VR8E_PANEL_INTERFACE_LVDS (1 << 4)
149 # define VR8E_FORCE_DEFAULT_PANEL (1 << 5)
151 /* Graphics BIOS scratch 1
154 # define VR8F_VCH_PRESENT (1 << 0)
155 # define VR8F_DISPLAY_CONN (1 << 1)
156 # define VR8F_POWER_MASK (0x3c)
157 # define VR8F_POWER_POS (2)
159 /* Some Bios implementations do not restore the DVO state upon
160 * resume from standby. Thus, this driver has to handle it
161 * instead. The following list contains all registers that
164 static const uint16_t backup_addresses[] = {
166 0x18, 0x19, 0x1a, 0x1f,
167 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
168 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
170 0x10 /* this must come last */
177 uint16_t width, height;
179 /* Register backup */
181 uint16_t reg_backup[ARRAY_SIZE(backup_addresses)];
185 static void ivch_dump_regs(struct intel_dvo_device *dvo);
187 * Reads a register on the ivch.
189 * Each of the 256 registers are 16 bits long.
191 static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
193 struct intel_iic_softc *sc;
194 struct ivch_priv *priv = dvo->dev_priv;
195 struct i2c_adapter *adapter = dvo->i2c_bus;
199 struct i2c_msg msgs[] = {
201 .slave = dvo->slave_addr << 1,
207 .flags = I2C_M_NOSTART,
212 .slave = dvo->slave_addr << 1,
213 .flags = I2C_M_RD | I2C_M_NOSTART,
221 sc = device_get_softc(adapter);
223 if (iicbus_transfer(adapter, msgs, 3) == 0) {
224 *data = (in_buf[1] << 8) | in_buf[0];
229 DRM_DEBUG_KMS("Unable to read register 0x%02x from "
231 addr, sc->name, dvo->slave_addr);
236 /** Writes a 16-bit register on the ivch */
237 static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
239 struct intel_iic_softc *sc;
240 struct ivch_priv *priv = dvo->dev_priv;
241 struct i2c_adapter *adapter = dvo->i2c_bus;
243 struct i2c_msg msg = {
244 .slave = dvo->slave_addr << 1,
251 out_buf[1] = data & 0xff;
252 out_buf[2] = data >> 8;
254 sc = device_get_softc(adapter);
256 if (iicbus_transfer(adapter, &msg, 1) == 0)
260 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
261 addr, sc->name, dvo->slave_addr);
267 /** Probes the given bus and slave address for an ivch */
268 static bool ivch_init(struct intel_dvo_device *dvo,
269 struct i2c_adapter *adapter)
271 struct ivch_priv *priv;
275 priv = kzalloc(sizeof(struct ivch_priv), GFP_KERNEL);
279 dvo->i2c_bus = adapter;
280 dvo->dev_priv = priv;
283 if (!ivch_read(dvo, VR00, &temp))
287 /* Since the identification bits are probably zeroes, which doesn't seem
288 * very unique, check that the value in the base address field matches
289 * the address it's responding on.
291 if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) {
292 DRM_DEBUG_KMS("ivch detect failed due to address mismatch "
294 (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr);
298 ivch_read(dvo, VR20, &priv->width);
299 ivch_read(dvo, VR21, &priv->height);
301 /* Make a backup of the registers to be able to restore them
304 for (i = 0; i < ARRAY_SIZE(backup_addresses); i++)
305 ivch_read(dvo, backup_addresses[i], priv->reg_backup + i);
316 static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo)
318 return connector_status_connected;
321 static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo,
322 struct drm_display_mode *mode)
324 if (mode->clock > 112000)
325 return MODE_CLOCK_HIGH;
330 /* Restore the DVO registers after a resume
331 * from RAM. Registers have been saved during
332 * the initialization.
334 static void ivch_reset(struct intel_dvo_device *dvo)
336 struct ivch_priv *priv = dvo->dev_priv;
339 DRM_DEBUG_KMS("Resetting the IVCH registers\n");
341 ivch_write(dvo, VR10, 0x0000);
343 for (i = 0; i < ARRAY_SIZE(backup_addresses); i++)
344 ivch_write(dvo, backup_addresses[i], priv->reg_backup[i]);
347 /** Sets the power state of the panel connected to the ivch */
348 static void ivch_dpms(struct intel_dvo_device *dvo, bool enable)
351 uint16_t vr01, vr30, backlight;
355 /* Set the new power state of the panel. */
356 if (!ivch_read(dvo, VR01, &vr01))
364 ivch_write(dvo, VR80, backlight);
367 vr01 |= VR01_LCD_ENABLE | VR01_DVO_ENABLE;
369 vr01 &= ~(VR01_LCD_ENABLE | VR01_DVO_ENABLE);
371 ivch_write(dvo, VR01, vr01);
373 /* Wait for the panel to make its state transition */
374 for (i = 0; i < 100; i++) {
375 if (!ivch_read(dvo, VR30, &vr30))
378 if (((vr30 & VR30_PANEL_ON) != 0) == enable)
382 /* wait some more; vch may fail to resync sometimes without this */
386 static bool ivch_get_hw_state(struct intel_dvo_device *dvo)
392 /* Set the new power state of the panel. */
393 if (!ivch_read(dvo, VR01, &vr01))
396 if (vr01 & VR01_LCD_ENABLE)
402 static void ivch_mode_set(struct intel_dvo_device *dvo,
403 const struct drm_display_mode *mode,
404 const struct drm_display_mode *adjusted_mode)
406 struct ivch_priv *priv = dvo->dev_priv;
413 vr10 = priv->reg_backup[ARRAY_SIZE(backup_addresses) - 1];
415 /* Enable dithering for 18 bpp pipelines */
416 vr10 &= VR10_INTERFACE_DEPTH_MASK;
417 if (vr10 == VR10_INTERFACE_2X18 || vr10 == VR10_INTERFACE_1X18)
418 vr01 = VR01_DITHER_ENABLE;
420 vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE |
421 VR40_HORIZONTAL_INTERP_ENABLE);
423 if (mode->hdisplay != adjusted_mode->crtc_hdisplay ||
424 mode->vdisplay != adjusted_mode->crtc_vdisplay) {
425 uint16_t x_ratio, y_ratio;
427 vr01 |= VR01_PANEL_FIT_ENABLE;
428 vr40 |= VR40_CLOCK_GATING_ENABLE;
429 x_ratio = (((mode->hdisplay - 1) << 16) /
430 (adjusted_mode->crtc_hdisplay - 1)) >> 2;
431 y_ratio = (((mode->vdisplay - 1) << 16) /
432 (adjusted_mode->crtc_vdisplay - 1)) >> 2;
433 ivch_write(dvo, VR42, x_ratio);
434 ivch_write(dvo, VR41, y_ratio);
436 vr01 &= ~VR01_PANEL_FIT_ENABLE;
437 vr40 &= ~VR40_CLOCK_GATING_ENABLE;
439 vr40 &= ~VR40_AUTO_RATIO_ENABLE;
441 ivch_write(dvo, VR01, vr01);
442 ivch_write(dvo, VR40, vr40);
445 static void ivch_dump_regs(struct intel_dvo_device *dvo)
449 ivch_read(dvo, VR00, &val);
450 DRM_DEBUG_KMS("VR00: 0x%04x\n", val);
451 ivch_read(dvo, VR01, &val);
452 DRM_DEBUG_KMS("VR01: 0x%04x\n", val);
453 ivch_read(dvo, VR10, &val);
454 DRM_DEBUG_KMS("VR10: 0x%04x\n", val);
455 ivch_read(dvo, VR30, &val);
456 DRM_DEBUG_KMS("VR30: 0x%04x\n", val);
457 ivch_read(dvo, VR40, &val);
458 DRM_DEBUG_KMS("VR40: 0x%04x\n", val);
461 ivch_read(dvo, VR80, &val);
462 DRM_DEBUG_KMS("VR80: 0x%04x\n", val);
463 ivch_read(dvo, VR81, &val);
464 DRM_DEBUG_KMS("VR81: 0x%04x\n", val);
465 ivch_read(dvo, VR82, &val);
466 DRM_DEBUG_KMS("VR82: 0x%04x\n", val);
467 ivch_read(dvo, VR83, &val);
468 DRM_DEBUG_KMS("VR83: 0x%04x\n", val);
469 ivch_read(dvo, VR84, &val);
470 DRM_DEBUG_KMS("VR84: 0x%04x\n", val);
471 ivch_read(dvo, VR85, &val);
472 DRM_DEBUG_KMS("VR85: 0x%04x\n", val);
473 ivch_read(dvo, VR86, &val);
474 DRM_DEBUG_KMS("VR86: 0x%04x\n", val);
475 ivch_read(dvo, VR87, &val);
476 DRM_DEBUG_KMS("VR87: 0x%04x\n", val);
477 ivch_read(dvo, VR88, &val);
478 DRM_DEBUG_KMS("VR88: 0x%04x\n", val);
480 /* Scratch register 0 - AIM Panel type */
481 ivch_read(dvo, VR8E, &val);
482 DRM_DEBUG_KMS("VR8E: 0x%04x\n", val);
484 /* Scratch register 1 - Status register */
485 ivch_read(dvo, VR8F, &val);
486 DRM_DEBUG_KMS("VR8F: 0x%04x\n", val);
489 static void ivch_destroy(struct intel_dvo_device *dvo)
491 struct ivch_priv *priv = dvo->dev_priv;
495 dvo->dev_priv = NULL;
499 struct intel_dvo_dev_ops ivch_ops = {
502 .get_hw_state = ivch_get_hw_state,
503 .mode_valid = ivch_mode_valid,
504 .mode_set = ivch_mode_set,
505 .detect = ivch_detect,
506 .dump_regs = ivch_dump_regs,
507 .destroy = ivch_destroy,