sys/platform/pc64/isa/clock.c

   1 /*-
   2  * Copyright (c) 1990 The Regents of the University of California.
   3  * Copyright (c) 2008 The DragonFly Project.
   4  * All rights reserved.
   5  *
   6  * This code is derived from software contributed to Berkeley by
   7  * William Jolitz and Don Ahn.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. Neither the name of the University nor the names of its contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31  * SUCH DAMAGE.
  32  *
  33  *      from: @(#)clock.c       7.2 (Berkeley) 5/12/91
  34  * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
  35  */
  36
  37 /*
  38  * Routines to handle clock hardware.
  39  */
  40
  41 /*
  42  * inittodr, settodr and support routines written
  43  * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
  44  *
  45  * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
  46  */
  47
  48 #if 0
  49 #include "opt_clock.h"
  50 #endif
  51
  52 #include <sys/param.h>
  53 #include <sys/systm.h>
  54 #include <sys/eventhandler.h>
  55 #include <sys/time.h>
  56 #include <sys/kernel.h>
  57 #include <sys/bus.h>
  58 #include <sys/sysctl.h>
  59 #include <sys/cons.h>
  60 #include <sys/kbio.h>
  61 #include <sys/systimer.h>
  62 #include <sys/globaldata.h>
  63 #include <sys/machintr.h>
  64 #include <sys/interrupt.h>
  65
  66 #include <sys/thread2.h>
  67
  68 #include <machine/clock.h>
  69 #include <machine/cputypes.h>
  70 #include <machine/frame.h>
  71 #include <machine/ipl.h>
  72 #include <machine/limits.h>
  73 #include <machine/md_var.h>
  74 #include <machine/psl.h>
  75 #include <machine/segments.h>
  76 #include <machine/smp.h>
  77 #include <machine/specialreg.h>
  78 #include <machine/intr_machdep.h>
  79
  80 #include <machine_base/apic/ioapic.h>
  81 #include <machine_base/apic/ioapic_abi.h>
  82 #include <machine_base/icu/icu.h>
  83 #include <bus/isa/isa.h>
  84 #include <bus/isa/rtc.h>
  85 #include <machine_base/isa/timerreg.h>
  86
  87 static void i8254_restore(void);
  88 static void resettodr_on_shutdown(void *arg __unused);
  89
  90 /*
  91  * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
  92  * can use a simple formula for leap years.
  93  */
  94 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
  95 #define DAYSPERYEAR   (31+28+31+30+31+30+31+31+30+31+30+31)
  96
  97 #ifndef TIMER_FREQ
  98 #define TIMER_FREQ   1193182
  99 #endif
 100
 101 static uint8_t i8254_walltimer_sel;
 102 static uint16_t i8254_walltimer_cntr;
 103
 104 int     adjkerntz;              /* local offset from GMT in seconds */
 105 int     disable_rtc_set;        /* disable resettodr() if != 0 */
 106 int     tsc_present;
 107 int     tsc_invariant;
 108 int     tsc_mpsync;
 109 int64_t tsc_frequency;
 110 int     tsc_is_broken;
 111 int     wall_cmos_clock;        /* wall CMOS clock assumed if != 0 */
 112 int     timer0_running;
 113 enum tstate { RELEASED, ACQUIRED };
 114 enum tstate timer0_state;
 115 enum tstate timer1_state;
 116 enum tstate timer2_state;
 117
 118 static  int     beeping = 0;
 119 static  const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
 120 static  u_char  rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
 121 static  u_char  rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
 122 static  int     rtc_loaded;
 123
 124 static int i8254_cputimer_div;
 125
 126 static int i8254_nointr;
 127 static int i8254_intr_disable = 1;
 128 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable);
 129
 130 static struct callout sysbeepstop_ch;
 131
 132 static sysclock_t i8254_cputimer_count(void);
 133 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
 134 static void i8254_cputimer_destruct(struct cputimer *cputimer);
 135
 136 static struct cputimer  i8254_cputimer = {
 137     SLIST_ENTRY_INITIALIZER,
 138     "i8254",
 139     CPUTIMER_PRI_8254,
 140     0,
 141     i8254_cputimer_count,
 142     cputimer_default_fromhz,
 143     cputimer_default_fromus,
 144     i8254_cputimer_construct,
 145     i8254_cputimer_destruct,
 146     TIMER_FREQ,
 147     0, 0, 0
 148 };
 149
 150 static sysclock_t tsc_cputimer_count_mfence(void);
 151 static sysclock_t tsc_cputimer_count_lfence(void);
 152 static void tsc_cputimer_construct(struct cputimer *, sysclock_t);
 153
 154 static struct cputimer  tsc_cputimer = {
 155     SLIST_ENTRY_INITIALIZER,
 156     "TSC",
 157     CPUTIMER_PRI_TSC,
 158     CPUTIMER_TSC,
 159     tsc_cputimer_count_mfence, /* safe bet */
 160     cputimer_default_fromhz,
 161     cputimer_default_fromus,
 162     tsc_cputimer_construct,
 163     cputimer_default_destruct,
 164     0,
 165     0, 0, 0
 166 };
 167
 168 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t);
 169 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *);
 170 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t);
 171
 172 static struct cputimer_intr i8254_cputimer_intr = {
 173     .freq = TIMER_FREQ,
 174     .reload = i8254_intr_reload,
 175     .enable = cputimer_intr_default_enable,
 176     .config = i8254_intr_config,
 177     .restart = cputimer_intr_default_restart,
 178     .pmfixup = cputimer_intr_default_pmfixup,
 179     .initclock = i8254_intr_initclock,
 180     .pcpuhand = NULL,
 181     .next = SLIST_ENTRY_INITIALIZER,
 182     .name = "i8254",
 183     .type = CPUTIMER_INTR_8254,
 184     .prio = CPUTIMER_INTR_PRIO_8254,
 185     .caps = CPUTIMER_INTR_CAP_PS,
 186     .priv = NULL
 187 };
 188
 189 /*
 190  * timer0 clock interrupt.  Timer0 is in one-shot mode and has stopped
 191  * counting as of this interrupt.  We use timer1 in free-running mode (not
 192  * generating any interrupts) as our main counter.  Each cpu has timeouts
 193  * pending.
 194  *
 195  * This code is INTR_MPSAFE and may be called without the BGL held.
 196  */
 197 static void
 198 clkintr(void *dummy, void *frame_arg)
 199 {
 200         static sysclock_t sysclock_count;       /* NOTE! Must be static */
 201         struct globaldata *gd = mycpu;
 202         struct globaldata *gscan;
 203         int n;
 204
 205         /*
 206          * SWSTROBE mode is a one-shot, the timer is no longer running
 207          */
 208         timer0_running = 0;
 209
 210         /*
 211          * XXX the dispatcher needs work.  right now we call systimer_intr()
 212          * directly or via IPI for any cpu with systimers queued, which is
 213          * usually *ALL* of them.  We need to use the LAPIC timer for this.
 214          */
 215         sysclock_count = sys_cputimer->count();
 216         for (n = 0; n < ncpus; ++n) {
 217             gscan = globaldata_find(n);
 218             if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
 219                 continue;
 220             if (gscan != gd) {
 221                 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
 222                                 &sysclock_count, 1);
 223             } else {
 224                 systimer_intr(&sysclock_count, 0, frame_arg);
 225             }
 226         }
 227 }
 228
 229
 230 /*
 231  * NOTE! not MP safe.
 232  */
 233 int
 234 acquire_timer2(int mode)
 235 {
 236         if (timer2_state != RELEASED)
 237                 return (-1);
 238         timer2_state = ACQUIRED;
 239
 240         /*
 241          * This access to the timer registers is as atomic as possible
 242          * because it is a single instruction.  We could do better if we
 243          * knew the rate.
 244          */
 245         outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
 246         return (0);
 247 }
 248
 249 int
 250 release_timer2(void)
 251 {
 252         if (timer2_state != ACQUIRED)
 253                 return (-1);
 254         outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
 255         timer2_state = RELEASED;
 256         return (0);
 257 }
 258
 259 #include "opt_ddb.h"
 260 #ifdef DDB
 261 #include <ddb/ddb.h>
 262
 263 DB_SHOW_COMMAND(rtc, rtc)
 264 {
 265         kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
 266                rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
 267                rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
 268                rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
 269 }
 270 #endif /* DDB */
 271
 272 /*
 273  * Return the current cpu timer count as a 32 bit integer.
 274  */
 275 static
 276 sysclock_t
 277 i8254_cputimer_count(void)
 278 {
 279         static uint16_t cputimer_last;
 280         uint16_t count;
 281         sysclock_t ret;
 282
 283         clock_lock();
 284         outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
 285         count = (uint8_t)inb(i8254_walltimer_cntr);             /* get countdown */
 286         count |= ((uint8_t)inb(i8254_walltimer_cntr) << 8);
 287         count = -count;                                 /* -> countup */
 288         if (count < cputimer_last)                      /* rollover */
 289                 i8254_cputimer.base += 0x00010000;
 290         ret = i8254_cputimer.base | count;
 291         cputimer_last = count;
 292         clock_unlock();
 293         return(ret);
 294 }
 295
 296 /*
 297  * This function is called whenever the system timebase changes, allowing
 298  * us to calculate what is needed to convert a system timebase tick
 299  * into an 8254 tick for the interrupt timer.  If we can convert to a
 300  * simple shift, multiplication, or division, we do so.  Otherwise 64
 301  * bit arithmatic is required every time the interrupt timer is reloaded.
 302  */
 303 static void
 304 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer)
 305 {
 306     int freq;
 307     int div;
 308
 309     /*
 310      * Will a simple divide do the trick?
 311      */
 312     div = (timer->freq + (cti->freq / 2)) / cti->freq;
 313     freq = cti->freq * div;
 314
 315     if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
 316         i8254_cputimer_div = div;
 317     else
 318         i8254_cputimer_div = 0;
 319 }
 320
 321 /*
 322  * Reload for the next timeout.  It is possible for the reload value
 323  * to be 0 or negative, indicating that an immediate timer interrupt
 324  * is desired.  For now make the minimum 2 ticks.
 325  *
 326  * We may have to convert from the system timebase to the 8254 timebase.
 327  */
 328 static void
 329 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
 330 {
 331     uint16_t count;
 332
 333     if (i8254_cputimer_div)
 334         reload /= i8254_cputimer_div;
 335     else
 336         reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
 337
 338     if ((int)reload < 2)
 339         reload = 2;
 340
 341     clock_lock();
 342     if (timer0_running) {
 343         outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);     /* count-down timer */
 344         count = (uint8_t)inb(TIMER_CNTR0);              /* lsb */
 345         count |= ((uint8_t)inb(TIMER_CNTR0) << 8);      /* msb */
 346         if (reload < count) {
 347             outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
 348             outb(TIMER_CNTR0, (uint8_t)reload);         /* lsb */
 349             outb(TIMER_CNTR0, (uint8_t)(reload >> 8));  /* msb */
 350         }
 351     } else {
 352         timer0_running = 1;
 353         if (reload > 0xFFFF)
 354             reload = 0;         /* full count */
 355         outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
 356         outb(TIMER_CNTR0, (uint8_t)reload);             /* lsb */
 357         outb(TIMER_CNTR0, (uint8_t)(reload >> 8));      /* msb */
 358     }
 359     clock_unlock();
 360 }
 361
 362 /*
 363  * DELAY(usec)       - Spin for the specified number of microseconds.
 364  * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
 365  *                     but do a thread switch in the loop
 366  *
 367  * Relies on timer 1 counting down from (cputimer_freq / hz)
 368  * Note: timer had better have been programmed before this is first used!
 369  */
 370 static void
 371 DODELAY(int n, int doswitch)
 372 {
 373         ssysclock_t delta, ticks_left;
 374         sysclock_t prev_tick, tick;
 375
 376 #ifdef DELAYDEBUG
 377         int getit_calls = 1;
 378         int n1;
 379         static int state = 0;
 380
 381         if (state == 0) {
 382                 state = 1;
 383                 for (n1 = 1; n1 <= 10000000; n1 *= 10)
 384                         DELAY(n1);
 385                 state = 2;
 386         }
 387         if (state == 1)
 388                 kprintf("DELAY(%d)...", n);
 389 #endif
 390         /*
 391          * Guard against the timer being uninitialized if we are called
 392          * early for console i/o.
 393          */
 394         if (timer0_state == RELEASED)
 395                 i8254_restore();
 396
 397         /*
 398          * Read the counter first, so that the rest of the setup overhead is
 399          * counted.  Then calculate the number of hardware timer ticks
 400          * required, rounding up to be sure we delay at least the requested
 401          * number of microseconds.
 402          */
 403         prev_tick = sys_cputimer->count();
 404         ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
 405                      1000000;
 406
 407         /*
 408          * Loop until done.
 409          */
 410         while (ticks_left > 0) {
 411                 tick = sys_cputimer->count();
 412 #ifdef DELAYDEBUG
 413                 ++getit_calls;
 414 #endif
 415                 delta = tick - prev_tick;
 416                 prev_tick = tick;
 417                 if (delta < 0)
 418                         delta = 0;
 419                 ticks_left -= delta;
 420                 if (doswitch && ticks_left > 0)
 421                         lwkt_switch();
 422                 cpu_pause();
 423         }
 424 #ifdef DELAYDEBUG
 425         if (state == 1)
 426                 kprintf(" %d calls to getit() at %d usec each\n",
 427                        getit_calls, (n + 5) / getit_calls);
 428 #endif
 429 }
 430
 431 /*
 432  * DELAY() never switches.
 433  */
 434 void
 435 DELAY(int n)
 436 {
 437         DODELAY(n, 0);
 438 }
 439
 440 /*
 441  * Returns non-zero if the specified time period has elapsed.  Call
 442  * first with last_clock set to 0.
 443  */
 444 int
 445 CHECKTIMEOUT(TOTALDELAY *tdd)
 446 {
 447         sysclock_t delta;
 448         int us;
 449
 450         if (tdd->started == 0) {
 451                 if (timer0_state == RELEASED)
 452                         i8254_restore();
 453                 tdd->last_clock = sys_cputimer->count();
 454                 tdd->started = 1;
 455                 return(0);
 456         }
 457         delta = sys_cputimer->count() - tdd->last_clock;
 458         us = (u_int64_t)delta * (u_int64_t)1000000 /
 459              (u_int64_t)sys_cputimer->freq;
 460         tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq /
 461                            1000000;
 462         tdd->us -= us;
 463         return (tdd->us < 0);
 464 }
 465
 466
 467 /*
 468  * DRIVERSLEEP() does not switch if called with a spinlock held or
 469  * from a hard interrupt.
 470  */
 471 void
 472 DRIVERSLEEP(int usec)
 473 {
 474         globaldata_t gd = mycpu;
 475
 476         if (gd->gd_intr_nesting_level || gd->gd_spinlocks) {
 477                 DODELAY(usec, 0);
 478         } else {
 479                 DODELAY(usec, 1);
 480         }
 481 }
 482
 483 static void
 484 sysbeepstop(void *chan)
 485 {
 486         outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
 487         beeping = 0;
 488         release_timer2();
 489 }
 490
 491 int
 492 sysbeep(int pitch, int period)
 493 {
 494         if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
 495                 return(-1);
 496         if (sysbeep_enable == 0)
 497                 return(-1);
 498         /*
 499          * Nobody else is using timer2, we do not need the clock lock
 500          */
 501         outb(TIMER_CNTR2, pitch);
 502         outb(TIMER_CNTR2, (pitch>>8));
 503         if (!beeping) {
 504                 /* enable counter2 output to speaker */
 505                 outb(IO_PPI, inb(IO_PPI) | 3);
 506                 beeping = period;
 507                 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
 508         }
 509         return (0);
 510 }
 511
 512 /*
 513  * RTC support routines
 514  */
 515
 516 int
 517 rtcin(int reg)
 518 {
 519         u_char val;
 520
 521         crit_enter();
 522         outb(IO_RTC, reg);
 523         inb(0x84);
 524         val = inb(IO_RTC + 1);
 525         inb(0x84);
 526         crit_exit();
 527         return (val);
 528 }
 529
 530 static __inline void
 531 writertc(u_char reg, u_char val)
 532 {
 533         crit_enter();
 534         inb(0x84);
 535         outb(IO_RTC, reg);
 536         inb(0x84);
 537         outb(IO_RTC + 1, val);
 538         inb(0x84);              /* XXX work around wrong order in rtcin() */
 539         crit_exit();
 540 }
 541
 542 static __inline int
 543 readrtc(int port)
 544 {
 545         return(bcd2bin(rtcin(port)));
 546 }
 547
 548 static u_int
 549 calibrate_clocks(void)
 550 {
 551         u_int64_t old_tsc;
 552         u_int tot_count;
 553         sysclock_t count, prev_count;
 554         int sec, start_sec, timeout;
 555
 556         if (bootverbose)
 557                 kprintf("Calibrating clock(s) ...\n");
 558         if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
 559                 goto fail;
 560         timeout = 100000000;
 561
 562         /* Read the mc146818A seconds counter. */
 563         for (;;) {
 564                 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
 565                         sec = rtcin(RTC_SEC);
 566                         break;
 567                 }
 568                 if (--timeout == 0)
 569                         goto fail;
 570         }
 571
 572         /* Wait for the mC146818A seconds counter to change. */
 573         start_sec = sec;
 574         for (;;) {
 575                 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
 576                         sec = rtcin(RTC_SEC);
 577                         if (sec != start_sec)
 578                                 break;
 579                 }
 580                 if (--timeout == 0)
 581                         goto fail;
 582         }
 583
 584         /* Start keeping track of the i8254 counter. */
 585         prev_count = sys_cputimer->count();
 586         tot_count = 0;
 587
 588         if (tsc_present)
 589                 old_tsc = rdtsc();
 590         else
 591                 old_tsc = 0;            /* shut up gcc */
 592
 593         /*
 594          * Wait for the mc146818A seconds counter to change.  Read the i8254
 595          * counter for each iteration since this is convenient and only
 596          * costs a few usec of inaccuracy. The timing of the final reads
 597          * of the counters almost matches the timing of the initial reads,
 598          * so the main cause of inaccuracy is the varying latency from
 599          * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
 600          * rtcin(RTC_SEC) that returns a changed seconds count.  The
 601          * maximum inaccuracy from this cause is < 10 usec on 486's.
 602          */
 603         start_sec = sec;
 604         for (;;) {
 605                 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
 606                         sec = rtcin(RTC_SEC);
 607                 count = sys_cputimer->count();
 608                 tot_count += (int)(count - prev_count);
 609                 prev_count = count;
 610                 if (sec != start_sec)
 611                         break;
 612                 if (--timeout == 0)
 613                         goto fail;
 614         }
 615
 616         /*
 617          * Read the cpu cycle counter.  The timing considerations are
 618          * similar to those for the i8254 clock.
 619          */
 620         if (tsc_present) {
 621                 tsc_frequency = rdtsc() - old_tsc;
 622                 if (bootverbose) {
 623                         kprintf("TSC clock: %jd Hz (Method A)\n",
 624                             (intmax_t)tsc_frequency);
 625                 }
 626         }
 627
 628         kprintf("i8254 clock: %u Hz\n", tot_count);
 629         return (tot_count);
 630
 631 fail:
 632         kprintf("failed, using default i8254 clock of %u Hz\n",
 633                 i8254_cputimer.freq);
 634         return (i8254_cputimer.freq);
 635 }
 636
 637 static void
 638 i8254_restore(void)
 639 {
 640         timer0_state = ACQUIRED;
 641
 642         clock_lock();
 643
 644         /*
 645          * Timer0 is our fine-grained variable clock interrupt
 646          */
 647         outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
 648         outb(TIMER_CNTR0, 2);   /* lsb */
 649         outb(TIMER_CNTR0, 0);   /* msb */
 650         clock_unlock();
 651
 652         if (!i8254_nointr) {
 653                 cputimer_intr_register(&i8254_cputimer_intr);
 654                 cputimer_intr_select(&i8254_cputimer_intr, 0);
 655         }
 656
 657         /*
 658          * Timer1 or timer2 is our free-running clock, but only if another
 659          * has not been selected.
 660          */
 661         cputimer_register(&i8254_cputimer);
 662         cputimer_select(&i8254_cputimer, 0);
 663 }
 664
 665 static void
 666 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
 667 {
 668         int which;
 669
 670         /*
 671          * Should we use timer 1 or timer 2 ?
 672          */
 673         which = 0;
 674         TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
 675         if (which != 1 && which != 2)
 676                 which = 2;
 677
 678         switch(which) {
 679         case 1:
 680                 timer->name = "i8254_timer1";
 681                 timer->type = CPUTIMER_8254_SEL1;
 682                 i8254_walltimer_sel = TIMER_SEL1;
 683                 i8254_walltimer_cntr = TIMER_CNTR1;
 684                 timer1_state = ACQUIRED;
 685                 break;
 686         case 2:
 687                 timer->name = "i8254_timer2";
 688                 timer->type = CPUTIMER_8254_SEL2;
 689                 i8254_walltimer_sel = TIMER_SEL2;
 690                 i8254_walltimer_cntr = TIMER_CNTR2;
 691                 timer2_state = ACQUIRED;
 692                 break;
 693         }
 694
 695         timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
 696
 697         clock_lock();
 698         outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
 699         outb(i8254_walltimer_cntr, 0);  /* lsb */
 700         outb(i8254_walltimer_cntr, 0);  /* msb */
 701         outb(IO_PPI, inb(IO_PPI) | 1);  /* bit 0: enable gate, bit 1: spkr */
 702         clock_unlock();
 703 }
 704
 705 static void
 706 i8254_cputimer_destruct(struct cputimer *timer)
 707 {
 708         switch(timer->type) {
 709         case CPUTIMER_8254_SEL1:
 710             timer1_state = RELEASED;
 711             break;
 712         case CPUTIMER_8254_SEL2:
 713             timer2_state = RELEASED;
 714             break;
 715         default:
 716             break;
 717         }
 718         timer->type = 0;
 719 }
 720
 721 static void
 722 rtc_restore(void)
 723 {
 724         /* Restore all of the RTC's "status" (actually, control) registers. */
 725         writertc(RTC_STATUSB, RTCSB_24HR);
 726         writertc(RTC_STATUSA, rtc_statusa);
 727         writertc(RTC_STATUSB, rtc_statusb);
 728 }
 729
 730 /*
 731  * Restore all the timers.
 732  *
 733  * This function is called to resynchronize our core timekeeping after a
 734  * long halt, e.g. from apm_default_resume() and friends.  It is also
 735  * called if after a BIOS call we have detected munging of the 8254.
 736  * It is necessary because cputimer_count() counter's delta may have grown
 737  * too large for nanouptime() and friends to handle, or (in the case of 8254
 738  * munging) might cause the SYSTIMER code to prematurely trigger.
 739  */
 740 void
 741 timer_restore(void)
 742 {
 743         crit_enter();
 744         i8254_restore();                /* restore timer_freq and hz */
 745         rtc_restore();                  /* reenable RTC interrupts */
 746         crit_exit();
 747 }
 748
 749 /*
 750  * Initialize 8254 timer 0 early so that it can be used in DELAY().
 751  */
 752 void
 753 startrtclock(void)
 754 {
 755         u_int delta, freq;
 756
 757         /*
 758          * Can we use the TSC?
 759          *
 760          * NOTE: If running under qemu, probably a good idea to force the
 761          *       TSC because we are not likely to detect it as being
 762          *       invariant or mpsyncd if you don't.  This will greatly
 763          *       reduce SMP contention.
 764          */
 765         if (cpu_feature & CPUID_TSC) {
 766                 tsc_present = 1;
 767                 TUNABLE_INT_FETCH("hw.tsc_cputimer_force", &tsc_invariant);
 768
 769                 if ((cpu_vendor_id == CPU_VENDOR_INTEL ||
 770                      cpu_vendor_id == CPU_VENDOR_AMD) &&
 771                     cpu_exthigh >= 0x80000007) {
 772                         u_int regs[4];
 773
 774                         do_cpuid(0x80000007, regs);
 775                         if (regs[3] & 0x100)
 776                                 tsc_invariant = 1;
 777                 }
 778         } else {
 779                 tsc_present = 0;
 780         }
 781
 782         /*
 783          * Initial RTC state, don't do anything unexpected
 784          */
 785         writertc(RTC_STATUSA, rtc_statusa);
 786         writertc(RTC_STATUSB, RTCSB_24HR);
 787
 788         /*
 789          * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
 790          * generate an interrupt, which we will ignore for now.
 791          *
 792          * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
 793          * (so it counts a full 2^16 and repeats).  We will use this timer
 794          * for our counting.
 795          */
 796         i8254_restore();
 797         freq = calibrate_clocks();
 798 #ifdef CLK_CALIBRATION_LOOP
 799         if (bootverbose) {
 800                 int c;
 801
 802                 cnpoll(TRUE);
 803                 kprintf("Press a key on the console to "
 804                         "abort clock calibration\n");
 805                 while ((c = cncheckc()) == -1 || c == NOKEY)
 806                         calibrate_clocks();
 807                 cnpoll(FALSE);
 808         }
 809 #endif
 810
 811         /*
 812          * Use the calibrated i8254 frequency if it seems reasonable.
 813          * Otherwise use the default, and don't use the calibrated i586
 814          * frequency.
 815          */
 816         delta = freq > i8254_cputimer.freq ?
 817                         freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
 818         if (delta < i8254_cputimer.freq / 100) {
 819 #ifndef CLK_USE_I8254_CALIBRATION
 820                 if (bootverbose)
 821                         kprintf(
 822 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
 823                 freq = i8254_cputimer.freq;
 824 #endif
 825                 /*
 826                  * NOTE:
 827                  * Interrupt timer's freq must be adjusted
 828                  * before we change the cuptimer's frequency.
 829                  */
 830                 i8254_cputimer_intr.freq = freq;
 831                 cputimer_set_frequency(&i8254_cputimer, freq);
 832         } else {
 833                 if (bootverbose)
 834                         kprintf(
 835                     "%d Hz differs from default of %d Hz by more than 1%%\n",
 836                                freq, i8254_cputimer.freq);
 837                 tsc_frequency = 0;
 838         }
 839
 840 #ifndef CLK_USE_TSC_CALIBRATION
 841         if (tsc_frequency != 0) {
 842                 if (bootverbose)
 843                         kprintf(
 844 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
 845                 tsc_frequency = 0;
 846         }
 847 #endif
 848         if (tsc_present && tsc_frequency == 0) {
 849                 /*
 850                  * Calibration of the i586 clock relative to the mc146818A
 851                  * clock failed.  Do a less accurate calibration relative
 852                  * to the i8254 clock.
 853                  */
 854                 u_int64_t old_tsc = rdtsc();
 855
 856                 DELAY(1000000);
 857                 tsc_frequency = rdtsc() - old_tsc;
 858 #ifdef CLK_USE_TSC_CALIBRATION
 859                 if (bootverbose) {
 860                         kprintf("TSC clock: %jd Hz (Method B)\n",
 861                             (intmax_t)tsc_frequency);
 862                 }
 863 #endif
 864         }
 865
 866         if (tsc_present) {
 867                 kprintf("TSC%s clock: %jd Hz\n",
 868                     tsc_invariant ? " invariant" : "",
 869                     (intmax_t)tsc_frequency);
 870         }
 871
 872         EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
 873 }
 874
 875 /*
 876  * Sync the time of day back to the RTC on shutdown, but only if
 877  * we have already loaded it and have not crashed.
 878  */
 879 static void
 880 resettodr_on_shutdown(void *arg __unused)
 881 {
 882         if (rtc_loaded && panicstr == NULL) {
 883                 resettodr();
 884         }
 885 }
 886
 887 /*
 888  * Initialize the time of day register, based on the time base which is, e.g.
 889  * from a filesystem.
 890  */
 891 void
 892 inittodr(time_t base)
 893 {
 894         unsigned long   sec, days;
 895         int             year, month;
 896         int             y, m;
 897         struct timespec ts;
 898
 899         if (base) {
 900                 ts.tv_sec = base;
 901                 ts.tv_nsec = 0;
 902                 set_timeofday(&ts);
 903         }
 904
 905         /* Look if we have a RTC present and the time is valid */
 906         if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
 907                 goto wrong_time;
 908
 909         /* wait for time update to complete */
 910         /* If RTCSA_TUP is zero, we have at least 244us before next update */
 911         crit_enter();
 912         while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
 913                 crit_exit();
 914                 crit_enter();
 915         }
 916
 917         days = 0;
 918 #ifdef USE_RTC_CENTURY
 919         year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
 920 #else
 921         year = readrtc(RTC_YEAR) + 1900;
 922         if (year < 1970)
 923                 year += 100;
 924 #endif
 925         if (year < 1970) {
 926                 crit_exit();
 927                 goto wrong_time;
 928         }
 929         month = readrtc(RTC_MONTH);
 930         for (m = 1; m < month; m++)
 931                 days += daysinmonth[m-1];
 932         if ((month > 2) && LEAPYEAR(year))
 933                 days ++;
 934         days += readrtc(RTC_DAY) - 1;
 935         for (y = 1970; y < year; y++)
 936                 days += DAYSPERYEAR + LEAPYEAR(y);
 937         sec = ((( days * 24 +
 938                   readrtc(RTC_HRS)) * 60 +
 939                   readrtc(RTC_MIN)) * 60 +
 940                   readrtc(RTC_SEC));
 941         /* sec now contains the number of seconds, since Jan 1 1970,
 942            in the local time zone */
 943
 944         sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
 945
 946         y = (int)(time_second - sec);
 947         if (y <= -2 || y >= 2) {
 948                 /* badly off, adjust it */
 949                 ts.tv_sec = sec;
 950                 ts.tv_nsec = 0;
 951                 set_timeofday(&ts);
 952         }
 953         rtc_loaded = 1;
 954         crit_exit();
 955         return;
 956
 957 wrong_time:
 958         kprintf("Invalid time in real time clock.\n");
 959         kprintf("Check and reset the date immediately!\n");
 960 }
 961
 962 /*
 963  * Write system time back to RTC
 964  */
 965 void
 966 resettodr(void)
 967 {
 968         struct timeval tv;
 969         unsigned long tm;
 970         int m;
 971         int y;
 972
 973         if (disable_rtc_set)
 974                 return;
 975
 976         microtime(&tv);
 977         tm = tv.tv_sec;
 978
 979         crit_enter();
 980         /* Disable RTC updates and interrupts. */
 981         writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
 982
 983         /* Calculate local time to put in RTC */
 984
 985         tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
 986
 987         writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60;    /* Write back Seconds */
 988         writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60;    /* Write back Minutes */
 989         writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24;    /* Write back Hours   */
 990
 991         /* We have now the days since 01-01-1970 in tm */
 992         writertc(RTC_WDAY, (tm+4)%7);                   /* Write back Weekday */
 993         for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
 994              tm >= m;
 995              y++,      m = DAYSPERYEAR + LEAPYEAR(y))
 996              tm -= m;
 997
 998         /* Now we have the years in y and the day-of-the-year in tm */
 999         writertc(RTC_YEAR, bin2bcd(y%100));             /* Write back Year    */
1000 #ifdef USE_RTC_CENTURY
1001         writertc(RTC_CENTURY, bin2bcd(y/100));          /* ... and Century    */
1002 #endif
1003         for (m = 0; ; m++) {
1004                 int ml;
1005
1006                 ml = daysinmonth[m];
1007                 if (m == 1 && LEAPYEAR(y))
1008                         ml++;
1009                 if (tm < ml)
1010                         break;
1011                 tm -= ml;
1012         }
1013
1014         writertc(RTC_MONTH, bin2bcd(m + 1));            /* Write back Month   */
1015         writertc(RTC_DAY, bin2bcd(tm + 1));             /* Write back Month Day */
1016
1017         /* Reenable RTC updates and interrupts. */
1018         writertc(RTC_STATUSB, rtc_statusb);
1019         crit_exit();
1020 }
1021
1022 static int
1023 i8254_ioapic_trial(int irq, struct cputimer_intr *cti)
1024 {
1025         sysclock_t base;
1026         long lastcnt;
1027
1028         /*
1029          * Following code assumes the 8254 is the cpu timer,
1030          * so make sure it is.
1031          */
1032         KKASSERT(sys_cputimer == &i8254_cputimer);
1033         KKASSERT(cti == &i8254_cputimer_intr);
1034
1035         lastcnt = get_interrupt_counter(irq, mycpuid);
1036
1037         /*
1038          * Force an 8254 Timer0 interrupt and wait 1/100s for
1039          * it to happen, then see if we got it.
1040          */
1041         kprintf("IOAPIC: testing 8254 interrupt delivery\n");
1042
1043         i8254_intr_reload(cti, 2);
1044         base = sys_cputimer->count();
1045         while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
1046                 ; /* nothing */
1047
1048         if (get_interrupt_counter(irq, mycpuid) - lastcnt == 0)
1049                 return ENOENT;
1050         return 0;
1051 }
1052
1053 /*
1054  * Start both clocks running.  DragonFly note: the stat clock is no longer
1055  * used.  Instead, 8254 based systimers are used for all major clock
1056  * interrupts.
1057  */
1058 static void
1059 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected)
1060 {
1061         void *clkdesc = NULL;
1062         int irq = 0, mixed_mode = 0, error;
1063
1064         KKASSERT(mycpuid == 0);
1065         callout_init_mp(&sysbeepstop_ch);
1066
1067         if (!selected && i8254_intr_disable)
1068                 goto nointr;
1069
1070         /*
1071          * The stat interrupt mask is different without the
1072          * statistics clock.  Also, don't set the interrupt
1073          * flag which would normally cause the RTC to generate
1074          * interrupts.
1075          */
1076         rtc_statusb = RTCSB_24HR;
1077
1078         /* Finish initializing 8254 timer 0. */
1079         if (ioapic_enable) {
1080                 irq = machintr_legacy_intr_find(0, INTR_TRIGGER_EDGE,
1081                         INTR_POLARITY_HIGH);
1082                 if (irq < 0) {
1083 mixed_mode_setup:
1084                         error = ioapic_conf_legacy_extint(0);
1085                         if (!error) {
1086                                 irq = machintr_legacy_intr_find(0,
1087                                     INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
1088                                 if (irq < 0)
1089                                         error = ENOENT;
1090                         }
1091
1092                         if (error) {
1093                                 if (!selected) {
1094                                         kprintf("IOAPIC: setup mixed mode for "
1095                                                 "irq 0 failed: %d\n", error);
1096                                         goto nointr;
1097                                 } else {
1098                                         panic("IOAPIC: setup mixed mode for "
1099                                               "irq 0 failed: %d\n", error);
1100                                 }
1101                         }
1102                         mixed_mode = 1;
1103                 }
1104                 clkdesc = register_int(irq, clkintr, NULL, "clk",
1105                                        NULL,
1106                                        INTR_EXCL | INTR_CLOCK |
1107                                        INTR_NOPOLL | INTR_MPSAFE |
1108                                        INTR_NOENTROPY, 0);
1109         } else {
1110                 register_int(0, clkintr, NULL, "clk", NULL,
1111                              INTR_EXCL | INTR_CLOCK |
1112                              INTR_NOPOLL | INTR_MPSAFE |
1113                              INTR_NOENTROPY, 0);
1114         }
1115
1116         /* Initialize RTC. */
1117         writertc(RTC_STATUSA, rtc_statusa);
1118         writertc(RTC_STATUSB, RTCSB_24HR);
1119
1120         if (ioapic_enable) {
1121                 error = i8254_ioapic_trial(irq, cti);
1122                 if (error) {
1123                         if (mixed_mode) {
1124                                 if (!selected) {
1125                                         kprintf("IOAPIC: mixed mode for irq %d "
1126                                                 "trial failed: %d\n",
1127                                                 irq, error);
1128                                         goto nointr;
1129                                 } else {
1130                                         panic("IOAPIC: mixed mode for irq %d "
1131                                               "trial failed: %d\n", irq, error);
1132                                 }
1133                         } else {
1134                                 kprintf("IOAPIC: warning 8254 is not connected "
1135                                         "to the correct pin, try mixed mode\n");
1136                                 unregister_int(clkdesc, 0);
1137                                 goto mixed_mode_setup;
1138                         }
1139                 }
1140         }
1141         return;
1142
1143 nointr:
1144         i8254_nointr = 1; /* don't try to register again */
1145         cputimer_intr_deregister(cti);
1146 }
1147
1148 void
1149 setstatclockrate(int newhz)
1150 {
1151         if (newhz == RTC_PROFRATE)
1152                 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1153         else
1154                 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1155         writertc(RTC_STATUSA, rtc_statusa);
1156 }
1157
1158 #if 0
1159 static unsigned
1160 tsc_get_timecount(struct timecounter *tc)
1161 {
1162         return (rdtsc());
1163 }
1164 #endif
1165
1166 #ifdef KERN_TIMESTAMP
1167 #define KERN_TIMESTAMP_SIZE 16384
1168 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1169 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1170         sizeof(tsc), "LU", "Kernel timestamps");
1171 void
1172 _TSTMP(u_int32_t x)
1173 {
1174         static int i;
1175
1176         tsc[i] = (u_int32_t)rdtsc();
1177         tsc[i+1] = x;
1178         i = i + 2;
1179         if (i >= KERN_TIMESTAMP_SIZE)
1180                 i = 0;
1181         tsc[i] = 0; /* mark last entry */
1182 }
1183 #endif /* KERN_TIMESTAMP */
1184
1185 /*
1186  *
1187  */
1188
1189 static int
1190 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1191 {
1192     sysclock_t count;
1193     uint64_t tscval;
1194     char buf[32];
1195
1196     crit_enter();
1197     if (sys_cputimer == &i8254_cputimer)
1198         count = sys_cputimer->count();
1199     else
1200         count = 0;
1201     if (tsc_present)
1202         tscval = rdtsc();
1203     else
1204         tscval = 0;
1205     crit_exit();
1206     ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1207     return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1208 }
1209
1210 struct tsc_mpsync_arg {
1211         volatile uint64_t       tsc_target;
1212         volatile int            tsc_mpsync;
1213 };
1214
1215 struct tsc_mpsync_thr {
1216         volatile int            tsc_done_cnt;
1217         volatile int            tsc_mpsync_cnt;
1218 };
1219
1220 static void
1221 tsc_mpsync_test_remote(void *xarg)
1222 {
1223         struct tsc_mpsync_arg *arg = xarg;
1224         uint64_t tsc;
1225
1226         tsc = rdtsc_ordered();
1227         if (tsc < arg->tsc_target)
1228                 arg->tsc_mpsync = 0;
1229 }
1230
1231 static void
1232 tsc_mpsync_test_loop(struct tsc_mpsync_arg *arg)
1233 {
1234         struct globaldata *gd = mycpu;
1235         uint64_t test_end, test_begin;
1236         u_int i;
1237
1238         if (bootverbose) {
1239                 kprintf("cpu%d: TSC testing MP synchronization ...\n",
1240                     gd->gd_cpuid);
1241         }
1242
1243         test_begin = rdtsc_ordered();
1244         /* Run test for 100ms */
1245         test_end = test_begin + (tsc_frequency / 10);
1246
1247         arg->tsc_mpsync = 1;
1248         arg->tsc_target = test_begin;
1249
1250 #define TSC_TEST_TRYMAX         1000000 /* Make sure we could stop */
1251 #define TSC_TEST_TRYMIN         50000
1252
1253         for (i = 0; i < TSC_TEST_TRYMAX; ++i) {
1254                 struct lwkt_cpusync cs;
1255
1256                 crit_enter();
1257                 lwkt_cpusync_init(&cs, gd->gd_other_cpus,
1258                     tsc_mpsync_test_remote, arg);
1259                 lwkt_cpusync_interlock(&cs);
1260                 arg->tsc_target = rdtsc_ordered();
1261                 cpu_mfence();
1262                 lwkt_cpusync_deinterlock(&cs);
1263                 crit_exit();
1264
1265                 if (!arg->tsc_mpsync) {
1266                         kprintf("cpu%d: TSC is not MP synchronized @%u\n",
1267                             gd->gd_cpuid, i);
1268                         break;
1269                 }
1270                 if (arg->tsc_target > test_end && i >= TSC_TEST_TRYMIN)
1271                         break;
1272         }
1273
1274 #undef TSC_TEST_TRYMIN
1275 #undef TSC_TEST_TRYMAX
1276
1277         if (arg->tsc_target == test_begin) {
1278                 kprintf("cpu%d: TSC does not tick?!\n", gd->gd_cpuid);
1279                 /* XXX disable TSC? */
1280                 tsc_invariant = 0;
1281                 arg->tsc_mpsync = 0;
1282                 return;
1283         }
1284
1285         if (arg->tsc_mpsync && bootverbose) {
1286                 kprintf("cpu%d: TSC is MP synchronized after %u tries\n",
1287                     gd->gd_cpuid, i);
1288         }
1289 }
1290
1291 static void
1292 tsc_mpsync_ap_thread(void *xthr)
1293 {
1294         struct tsc_mpsync_thr *thr = xthr;
1295         struct tsc_mpsync_arg arg;
1296
1297         tsc_mpsync_test_loop(&arg);
1298         if (arg.tsc_mpsync) {
1299                 atomic_add_int(&thr->tsc_mpsync_cnt, 1);
1300                 cpu_sfence();
1301         }
1302         atomic_add_int(&thr->tsc_done_cnt, 1);
1303
1304         lwkt_exit();
1305 }
1306
1307 static void
1308 tsc_mpsync_test(void)
1309 {
1310         struct tsc_mpsync_arg arg;
1311
1312         if (!tsc_invariant) {
1313                 /* Not even invariant TSC */
1314                 return;
1315         }
1316
1317         if (ncpus == 1) {
1318                 /* Only one CPU */
1319                 tsc_mpsync = 1;
1320                 return;
1321         }
1322
1323         /*
1324          * Forcing can be used w/qemu to reduce contention
1325          */
1326         TUNABLE_INT_FETCH("hw.tsc_cputimer_force", &tsc_mpsync);
1327         if (tsc_mpsync) {
1328                 kprintf("TSC as cputimer forced\n");
1329                 return;
1330         }
1331
1332         if (cpu_vendor_id != CPU_VENDOR_INTEL) {
1333                 /* XXX only Intel works */
1334                 return;
1335         }
1336
1337         kprintf("TSC testing MP synchronization ...\n");
1338
1339         tsc_mpsync_test_loop(&arg);
1340         if (arg.tsc_mpsync) {
1341                 struct tsc_mpsync_thr thr;
1342                 int cpu;
1343
1344                 /*
1345                  * Test TSC MP synchronization on APs.
1346                  */
1347
1348                 thr.tsc_done_cnt = 1;
1349                 thr.tsc_mpsync_cnt = 1;
1350
1351                 for (cpu = 0; cpu < ncpus; ++cpu) {
1352                         if (cpu == mycpuid)
1353                                 continue;
1354
1355                         lwkt_create(tsc_mpsync_ap_thread, &thr, NULL,
1356                             NULL, 0, cpu, "tsc mpsync %d", cpu);
1357                 }
1358
1359                 while (thr.tsc_done_cnt != ncpus) {
1360                         cpu_pause();
1361                         cpu_lfence();
1362                 }
1363                 if (thr.tsc_mpsync_cnt == ncpus)
1364                         tsc_mpsync = 1;
1365         }
1366
1367         if (tsc_mpsync)
1368                 kprintf("TSC is MP synchronized\n");
1369         else
1370                 kprintf("TSC is not MP synchronized\n");
1371 }
1372 SYSINIT(tsc_mpsync, SI_BOOT2_FINISH_SMP, SI_ORDER_ANY, tsc_mpsync_test, NULL);
1373
1374 #define TSC_CPUTIMER_FREQMAX    128000000       /* 128Mhz */
1375
1376 static int tsc_cputimer_shift;
1377
1378 static void
1379 tsc_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
1380 {
1381         timer->base = 0;
1382         timer->base = oldclock - timer->count();
1383 }
1384
1385 static __inline sysclock_t
1386 tsc_cputimer_count(void)
1387 {
1388         uint64_t tsc;
1389
1390         tsc = rdtsc();
1391         tsc >>= tsc_cputimer_shift;
1392
1393         return (tsc + tsc_cputimer.base);
1394 }
1395
1396 static sysclock_t
1397 tsc_cputimer_count_lfence(void)
1398 {
1399         cpu_lfence();
1400         return tsc_cputimer_count();
1401 }
1402
1403 static sysclock_t
1404 tsc_cputimer_count_mfence(void)
1405 {
1406         cpu_mfence();
1407         return tsc_cputimer_count();
1408 }
1409
1410 static void
1411 tsc_cputimer_register(void)
1412 {
1413         uint64_t freq;
1414         int enable = 1;
1415
1416         if (!tsc_mpsync)
1417                 return;
1418
1419         TUNABLE_INT_FETCH("hw.tsc_cputimer_enable", &enable);
1420         if (!enable)
1421                 return;
1422
1423         freq = tsc_frequency;
1424         while (freq > TSC_CPUTIMER_FREQMAX) {
1425                 freq >>= 1;
1426                 ++tsc_cputimer_shift;
1427         }
1428         kprintf("TSC: cputimer freq %ju, shift %d\n",
1429             (uintmax_t)freq, tsc_cputimer_shift);
1430
1431         tsc_cputimer.freq = freq;
1432
1433         if (cpu_vendor_id == CPU_VENDOR_INTEL)
1434                 tsc_cputimer.count = tsc_cputimer_count_lfence;
1435         else
1436                 tsc_cputimer.count = tsc_cputimer_count_mfence; /* safe bet */
1437
1438         cputimer_register(&tsc_cputimer);
1439         cputimer_select(&tsc_cputimer, 0);
1440 }
1441 SYSINIT(tsc_cputimer_reg, SI_BOOT2_POST_SMP, SI_ORDER_FIRST,
1442         tsc_cputimer_register, NULL);
1443
1444 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1445 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1446             "frequency");
1447 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1448             0, 0, hw_i8254_timestamp, "A", "");
1449
1450 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1451             &tsc_present, 0, "TSC Available");
1452 SYSCTL_INT(_hw, OID_AUTO, tsc_invariant, CTLFLAG_RD,
1453             &tsc_invariant, 0, "Invariant TSC");
1454 SYSCTL_INT(_hw, OID_AUTO, tsc_mpsync, CTLFLAG_RD,
1455             &tsc_mpsync, 0, "TSC is synchronized across CPUs");
1456 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1457             &tsc_frequency, 0, "TSC Frequency");