2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/jme/if_jmereg.h,v 1.1 2008/05/27 01:42:01 yongari Exp $
28 * $DragonFly: src/sys/dev/netif/jme/if_jmereg.h,v 1.3 2008/09/13 02:47:03 sephe Exp $
34 #define JME_REV_JMC250_A1 0x01
35 #define JME_REV_JMC250_A2 0x11
37 /* JMC250 PCI configuration register. */
38 #define JME_PCIR_BAR PCIR_BAR(0)
40 #define JME_PCI_EROM 0x30
42 #define JME_PCI_DBG 0x9C
44 #define JME_PCI_SPI 0xB0
46 #define SPI_ENB 0x00000010
47 #define SPI_SO_STATUS 0x00000008
48 #define SPI_SI_CTRL 0x00000004
49 #define SPI_SCK_CTRL 0x00000002
50 #define SPI_CS_N_CTRL 0x00000001
52 #define JME_PCI_PHYCFG0 0xC0
54 #define JME_PCI_PHYCFG1 0xC4
56 #define JME_PCI_PHYCFG2 0xC8
58 #define JME_PCI_PHYCFG3 0xCC
60 #define JME_PCI_PIPECTL1 0xD0
62 #define JME_PCI_PIPECTL2 0xD4
64 /* PCIe link error/status. */
65 #define JME_PCI_LES 0xD8
67 /* propeietary register 0. */
68 #define JME_PCI_PE0 0xE0
69 #define PE0_SPI_EXIST 0x00200000
70 #define PE0_PME_D0 0x00100000
71 #define PE0_PME_D3H 0x00080000
72 #define PE0_PME_SPI_PAD 0x00040000
73 #define PE0_MASK_ASPM 0x00020000
74 #define PE0_EEPROM_RW_DIS 0x00008000
75 #define PE0_PCI_INTA 0x00001000
76 #define PE0_PCI_INTB 0x00002000
77 #define PE0_PCI_INTC 0x00003000
78 #define PE0_PCI_INTD 0x00004000
79 #define PE0_PCI_SVSSID_WR_ENB 0x00000800
80 #define PE0_MSIX_SIZE_8 0x00000700
81 #define PE0_MSIX_SIZE_7 0x00000600
82 #define PE0_MSIX_SIZE_6 0x00000500
83 #define PE0_MSIX_SIZE_5 0x00000400
84 #define PE0_MSIX_SIZE_4 0x00000300
85 #define PE0_MSIX_SIZE_3 0x00000200
86 #define PE0_MSIX_SIZE_2 0x00000100
87 #define PE0_MSIX_SIZE_1 0x00000000
88 #define PE0_MSIX_SIZE_DEF 0x00000700
89 #define PE0_MSIX_CAP_DIS 0x00000080
90 #define PE0_MSI_PVMC_ENB 0x00000040
91 #define PE0_LCAP_EXIT_LAT_MASK 0x00000038
92 #define PE0_LCAP_EXIT_LAT_DEF 0x00000038
93 #define PE0_PM_AUXC_MASK 0x00000007
94 #define PE0_PM_AUXC_DEF 0x00000007
96 #define JME_PCI_PE1 0xE4
98 #define JME_PCI_PHYTEST 0xF8
100 #define JME_PCI_GPR 0xFC
104 * -----------------------------------------------------------------------
105 * Register Size IO space Memory space
106 * -----------------------------------------------------------------------
107 * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~
108 * BAR1 + 0x7F BAR0 + 0x7F
109 * -----------------------------------------------------------------------
110 * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~
111 * BAR2 + 0x7F BAR0 + 0x47F
112 * -----------------------------------------------------------------------
113 * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~
114 * BAR2 + 0x7F BAR0 + 0x87F
115 * -----------------------------------------------------------------------
116 * To simplify register access fuctions and to get better performance
117 * this driver doesn't support IO space access. It could be implemented
118 * as a function which selects appropriate BARs to access requested
122 /* Tx control and status. */
123 #define JME_TXCSR 0x0000
124 #define TXCSR_QWEIGHT_MASK 0x0F000000
125 #define TXCSR_QWEIGHT_SHIFT 24
126 #define TXCSR_TXQ_SEL_MASK 0x00070000
127 #define TXCSR_TXQ_SEL_SHIFT 16
128 #define TXCSR_TXQ_START 0x00000001
129 #define TXCSR_TXQ_START_SHIFT 8
130 #define TXCSR_FIFO_THRESH_4QW 0x00000000
131 #define TXCSR_FIFO_THRESH_8QW 0x00000040
132 #define TXCSR_FIFO_THRESH_12QW 0x00000080
133 #define TXCSR_FIFO_THRESH_16QW 0x000000C0
134 #define TXCSR_DMA_SIZE_64 0x00000000
135 #define TXCSR_DMA_SIZE_128 0x00000010
136 #define TXCSR_DMA_SIZE_256 0x00000020
137 #define TXCSR_DMA_SIZE_512 0x00000030
138 #define TXCSR_DMA_BURST 0x00000004
139 #define TXCSR_TX_SUSPEND 0x00000002
140 #define TXCSR_TX_ENB 0x00000001
149 #define TXCSR_TXQ_WEIGHT(x) \
150 (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK)
151 #define TXCSR_TXQ_WEIGHT_MIN 0
152 #define TXCSR_TXQ_WEIGHT_MAX 15
153 #define TXCSR_TXQ_N_SEL(x) \
154 (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK)
155 #define TXCSR_TXQ_N_START(x) \
156 (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x)))
158 /* Tx queue descriptor base address. 16bytes alignment required. */
159 #define JME_TXDBA_LO 0x0004
160 #define JME_TXDBA_HI 0x0008
162 /* Tx queue descriptor count. multiple of 16(max = 1024). */
163 #define JME_TXQDC 0x000C
164 #define TXQDC_MASK 0x0000007F0
166 /* Tx queue next descriptor address. */
167 #define JME_TXNDA 0x0010
168 #define TXNDA_ADDR_MASK 0xFFFFFFF0
169 #define TXNDA_DESC_EMPTY 0x00000008
170 #define TXNDA_DESC_VALID 0x00000004
171 #define TXNDA_DESC_WAIT 0x00000002
172 #define TXNDA_DESC_FETCH 0x00000001
174 /* Tx MAC control ans status. */
175 #define JME_TXMAC 0x0014
176 #define TXMAC_IFG2_MASK 0xC0000000
177 #define TXMAC_IFG2_DEFAULT 0x40000000
178 #define TXMAC_IFG1_MASK 0x30000000
179 #define TXMAC_IFG1_DEFAULT 0x20000000
180 #define TXMAC_THRESH_1_PKT 0x00000300
181 #define TXMAC_THRESH_1_2_PKT 0x00000200
182 #define TXMAC_THRESH_1_4_PKT 0x00000100
183 #define TXMAC_THRESH_1_8_PKT 0x00000000
184 #define TXMAC_FRAME_BURST 0x00000080
185 #define TXMAC_CARRIER_EXT 0x00000040
186 #define TXMAC_IFG_ENB 0x00000020
187 #define TXMAC_BACKOFF 0x00000010
188 #define TXMAC_CARRIER_SENSE 0x00000008
189 #define TXMAC_COLL_ENB 0x00000004
190 #define TXMAC_CRC_ENB 0x00000002
191 #define TXMAC_PAD_ENB 0x00000001
193 /* Tx pause frame control. */
194 #define JME_TXPFC 0x0018
195 #define TXPFC_VLAN_TAG_MASK 0xFFFF0000
196 #define TXPFC_VLAN_TAG_SHIFT 16
197 #define TXPFC_VLAN_ENB 0x00008000
198 #define TXPFC_PAUSE_ENB 0x00000001
200 /* Tx timer/retry at half duplex. */
201 #define JME_TXTRHD 0x001C
202 #define TXTRHD_RT_PERIOD_ENB 0x80000000
203 #define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00
204 #define TXTRHD_RT_PERIOD_SHIFT 8
205 #define TXTRHD_RT_LIMIT_ENB 0x00000080
206 #define TXTRHD_RT_LIMIT_MASK 0x0000007F
207 #define TXTRHD_RT_LIMIT_SHIFT 0
208 #define TXTRHD_RT_PERIOD_DEFAULT 8192
209 #define TXTRHD_RT_LIMIT_DEFAULT 8
211 /* Rx control & status. */
212 #define JME_RXCSR 0x0020
213 #define RXCSR_FIFO_FTHRESH_16T 0x00000000
214 #define RXCSR_FIFO_FTHRESH_32T 0x10000000
215 #define RXCSR_FIFO_FTHRESH_64T 0x20000000
216 #define RXCSR_FIFO_FTHRESH_128T 0x30000000
217 #define RXCSR_FIFO_FTHRESH_MASK 0x30000000
218 #define RXCSR_FIFO_THRESH_16QW 0x00000000
219 #define RXCSR_FIFO_THRESH_32QW 0x04000000
220 #define RXCSR_FIFO_THRESH_64QW 0x08000000
221 #define RXCSR_FIFO_THRESH_128QW 0x0C000000
222 #define RXCSR_FIFO_THRESH_MASK 0x0C000000
223 #define RXCSR_DMA_SIZE_16 0x00000000
224 #define RXCSR_DMA_SIZE_32 0x01000000
225 #define RXCSR_DMA_SIZE_64 0x02000000
226 #define RXCSR_DMA_SIZE_128 0x03000000
227 #define RXCSR_RXQ_SEL_MASK 0x00030000
228 #define RXCSR_RXQ_SEL_SHIFT 16
229 #define RXCSR_DESC_RT_GAP_MASK 0x0000F000
230 #define RXCSR_DESC_RT_GAP_SHIFT 12
231 #define RXCSR_DESC_RT_GAP_256 0x00000000
232 #define RXCSR_DESC_RT_GAP_512 0x00001000
233 #define RXCSR_DESC_RT_GAP_1024 0x00002000
234 #define RXCSR_DESC_RT_GAP_2048 0x00003000
235 #define RXCSR_DESC_RT_GAP_4096 0x00004000
236 #define RXCSR_DESC_RT_GAP_8192 0x00005000
237 #define RXCSR_DESC_RT_GAP_16384 0x00006000
238 #define RXCSR_DESC_RT_GAP_32768 0x00007000
239 #define RXCSR_DESC_RT_CNT_MASK 0x00000F00
240 #define RXCSR_DESC_RT_CNT_SHIFT 8
241 #define RXCSR_PASS_WAKEUP_PKT 0x00000040
242 #define RXCSR_PASS_MAGIC_PKT 0x00000020
243 #define RXCSR_PASS_RUNT_PKT 0x00000010
244 #define RXCSR_PASS_BAD_PKT 0x00000008
245 #define RXCSR_RXQ_START 0x00000004
246 #define RXCSR_RX_SUSPEND 0x00000002
247 #define RXCSR_RX_ENB 0x00000001
249 #define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT)
254 #define RXCSR_DESC_RT_CNT(x) \
255 ((((x) / 4) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK)
256 #define RXCSR_DESC_RT_CNT_DEFAULT 32
258 /* Rx queue descriptor base address. 16bytes alignment needed. */
259 #define JME_RXDBA_LO 0x0024
260 #define JME_RXDBA_HI 0x0028
262 /* Rx queue descriptor count. multiple of 16(max = 1024). */
263 #define JME_RXQDC 0x002C
264 #define RXQDC_MASK 0x0000007F0
266 /* Rx queue next descriptor address. */
267 #define JME_RXNDA 0x0030
268 #define RXNDA_ADDR_MASK 0xFFFFFFF0
269 #define RXNDA_DESC_EMPTY 0x00000008
270 #define RXNDA_DESC_VALID 0x00000004
271 #define RXNDA_DESC_WAIT 0x00000002
272 #define RXNDA_DESC_FETCH 0x00000001
274 /* Rx MAC control and status. */
275 #define JME_RXMAC 0x0034
276 #define RXMAC_RSS_UNICAST 0x00000000
277 #define RXMAC_RSS_UNI_MULTICAST 0x00010000
278 #define RXMAC_RSS_UNI_MULTI_BROADCAST 0x00020000
279 #define RXMAC_RSS_ALLFRAME 0x00030000
280 #define RXMAC_PROMISC 0x00000800
281 #define RXMAC_BROADCAST 0x00000400
282 #define RXMAC_MULTICAST 0x00000200
283 #define RXMAC_UNICAST 0x00000100
284 #define RXMAC_ALLMULTI 0x00000080
285 #define RXMAC_MULTICAST_FILTER 0x00000040
286 #define RXMAC_COLL_DET_ENB 0x00000020
287 #define RXMAC_FC_ENB 0x00000008
288 #define RXMAC_VLAN_ENB 0x00000004
289 #define RXMAC_PAD_10BYTES 0x00000002
290 #define RXMAC_CSUM_ENB 0x00000001
292 /* Rx unicast MAC address. */
293 #define JME_PAR0 0x0038
294 #define JME_PAR1 0x003C
296 /* Rx multicast address hash table. */
297 #define JME_MAR0 0x0040
298 #define JME_MAR1 0x0044
300 /* Wakeup frame output data port. */
301 #define JME_WFODP 0x0048
303 /* Wakeup frame output interface. */
304 #define JME_WFOI 0x004C
305 #define WFOI_MASK_0_31 0x00000000
306 #define WFOI_MASK_31_63 0x00000010
307 #define WFOI_MASK_64_95 0x00000020
308 #define WFOI_MASK_96_127 0x00000030
309 #define WFOI_MASK_SEL 0x00000008
310 #define WFOI_CRC_SEL 0x00000000
311 #define WFOI_WAKEUP_FRAME_MASK 0x00000007
312 #define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK)
314 /* Station management interface. */
315 #define JME_SMI 0x0050
316 #define SMI_DATA_MASK 0xFFFF0000
317 #define SMI_DATA_SHIFT 16
318 #define SMI_REG_ADDR_MASK 0x0000F800
319 #define SMI_REG_ADDR_SHIFT 11
320 #define SMI_PHY_ADDR_MASK 0x000007C0
321 #define SMI_PHY_ADDR_SHIFT 6
322 #define SMI_OP_WRITE 0x00000020
323 #define SMI_OP_READ 0x00000000
324 #define SMI_OP_EXECUTE 0x00000010
325 #define SMI_MDIO 0x00000008
326 #define SMI_MDOE 0x00000004
327 #define SMI_MDC 0x00000002
328 #define SMI_MDEN 0x00000001
329 #define SMI_REG_ADDR(x) \
330 (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK)
331 #define SMI_PHY_ADDR(x) \
332 (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK)
334 /* Global host control. */
335 #define JME_GHC 0x0054
336 #define GHC_LOOPBACK 0x80000000
337 #define GHC_RESET 0x40000000
338 #define GHC_FULL_DUPLEX 0x00000040
339 #define GHC_SPEED_UNKNOWN 0x00000000
340 #define GHC_SPEED_10 0x00000010
341 #define GHC_SPEED_100 0x00000020
342 #define GHC_SPEED_1000 0x00000030
343 #define GHC_SPEED_MASK 0x00000030
344 #define GHC_LINK_OFF 0x00000004
345 #define GHC_LINK_ON 0x00000002
346 #define GHC_LINK_STAT_POLLING 0x00000001
348 /* Power management control and status. */
349 #define JME_PMCS 0x0060
350 #define PMCS_WAKEUP_FRAME_7 0x80000000
351 #define PMCS_WAKEUP_FRAME_6 0x40000000
352 #define PMCS_WAKEUP_FRAME_5 0x20000000
353 #define PMCS_WAKEUP_FRAME_4 0x10000000
354 #define PMCS_WAKEUP_FRAME_3 0x08000000
355 #define PMCS_WAKEUP_FRAME_2 0x04000000
356 #define PMCS_WAKEUP_FRAME_1 0x02000000
357 #define PMCS_WAKEUP_FRAME_0 0x01000000
358 #define PMCS_LINK_FAIL 0x00040000
359 #define PMCS_LINK_RISING 0x00020000
360 #define PMCS_MAGIC_FRAME 0x00010000
361 #define PMCS_WAKEUP_FRAME_7_ENB 0x00008000
362 #define PMCS_WAKEUP_FRAME_6_ENB 0x00004000
363 #define PMCS_WAKEUP_FRAME_5_ENB 0x00002000
364 #define PMCS_WAKEUP_FRAME_4_ENB 0x00001000
365 #define PMCS_WAKEUP_FRAME_3_ENB 0x00000800
366 #define PMCS_WAKEUP_FRAME_2_ENB 0x00000400
367 #define PMCS_WAKEUP_FRAME_1_ENB 0x00000200
368 #define PMCS_WAKEUP_FRAME_0_ENB 0x00000100
369 #define PMCS_LINK_FAIL_ENB 0x00000004
370 #define PMCS_LINK_RISING_ENB 0x00000002
371 #define PMCS_MAGIC_FRAME_ENB 0x00000001
372 #define PMCS_WOL_ENB_MASK 0x0000FFFF
374 /* Giga PHY & EEPROM registers. */
375 #define JME_PHY_EEPROM_BASE_ADDR 0x0400
377 #define JME_GIGAR0LO 0x0400
378 #define JME_GIGAR0HI 0x0404
379 #define JME_GIGARALO 0x0408
380 #define JME_GIGARAHI 0x040C
381 #define JME_GIGARBLO 0x0410
382 #define JME_GIGARBHI 0x0414
383 #define JME_GIGARCLO 0x0418
384 #define JME_GIGARCHI 0x041C
385 #define JME_GIGARDLO 0x0420
386 #define JME_GIGARDHI 0x0424
388 /* BIST status and control. */
389 #define JME_GIGACSR 0x0428
390 #define GIGACSR_STATUS 0x40000000
391 #define GIGACSR_CTRL_MASK 0x30000000
392 #define GIGACSR_CTRL_DEFAULT 0x30000000
393 #define GIGACSR_TX_CLK_MASK 0x0F000000
394 #define GIGACSR_RX_CLK_MASK 0x00F00000
395 #define GIGACSR_TX_CLK_INV 0x00080000
396 #define GIGACSR_RX_CLK_INV 0x00040000
397 #define GIGACSR_PHY_RST 0x00010000
398 #define GIGACSR_IRQ_N_O 0x00001000
399 #define GIGACSR_BIST_OK 0x00000200
400 #define GIGACSR_BIST_DONE 0x00000100
401 #define GIGACSR_BIST_LED_ENB 0x00000010
402 #define GIGACSR_BIST_MASK 0x00000003
404 /* PHY Link Status. */
405 #define JME_LNKSTS 0x0430
406 #define LINKSTS_SPEED_10 0x00000000
407 #define LINKSTS_SPEED_100 0x00004000
408 #define LINKSTS_SPEED_1000 0x00008000
409 #define LINKSTS_FULL_DUPLEX 0x00002000
410 #define LINKSTS_PAGE_RCVD 0x00001000
411 #define LINKSTS_SPDDPX_RESOLVED 0x00000800
412 #define LINKSTS_UP 0x00000400
413 #define LINKSTS_ANEG_COMP 0x00000200
414 #define LINKSTS_MDI_CROSSOVR 0x00000040
415 #define LINKSTS_LPAR_PAUSE_ASYM 0x00000002
416 #define LINKSTS_LPAR_PAUSE 0x00000001
418 /* SMB control and status. */
419 #define JME_SMBCSR 0x0440
420 #define SMBCSR_SLAVE_ADDR_MASK 0x7F000000
421 #define SMBCSR_WR_DATA_NACK 0x00040000
422 #define SMBCSR_CMD_NACK 0x00020000
423 #define SMBCSR_RELOAD 0x00010000
424 #define SMBCSR_CMD_ADDR_MASK 0x0000FF00
425 #define SMBCSR_SCL_STAT 0x00000080
426 #define SMBCSR_SDA_STAT 0x00000040
427 #define SMBCSR_EEPROM_PRESENT 0x00000020
428 #define SMBCSR_INIT_LD_DONE 0x00000010
429 #define SMBCSR_HW_BUSY_MASK 0x0000000F
430 #define SMBCSR_HW_IDLE 0x00000000
433 #define JME_SMBINTF 0x0444
434 #define SMBINTF_RD_DATA_MASK 0xFF000000
435 #define SMBINTF_RD_DATA_SHIFT 24
436 #define SMBINTF_WR_DATA_MASK 0x00FF0000
437 #define SMBINTF_WR_DATA_SHIFT 16
438 #define SMBINTF_ADDR_MASK 0x0000FF00
439 #define SMBINTF_ADDR_SHIFT 8
440 #define SMBINTF_RD 0x00000020
441 #define SMBINTF_WR 0x00000000
442 #define SMBINTF_CMD_TRIGGER 0x00000010
443 #define SMBINTF_BUSY 0x00000010
444 #define SMBINTF_FAST_MODE 0x00000008
445 #define SMBINTF_GPIO_SCL 0x00000004
446 #define SMBINTF_GPIO_SDA 0x00000002
447 #define SMBINTF_GPIO_ENB 0x00000001
449 #define JME_EEPROM_SIG0 0x55
450 #define JME_EEPROM_SIG1 0xAA
451 #define JME_EEPROM_DESC_BYTES 3
452 #define JME_EEPROM_DESC_END 0x80
453 #define JME_EEPROM_FUNC_MASK 0x70
454 #define JME_EEPROM_FUNC_SHIFT 4
455 #define JME_EEPROM_PAGE_MASK 0x0F
456 #define JME_EEPROM_PAGE_SHIFT 0
458 #define JME_EEPROM_FUNC0 0
459 /* PCI configuration space. */
460 #define JME_EEPROM_PAGE_BAR0 0
461 /* 128 bytes I/O window. */
462 #define JME_EEPROM_PAGE_BAR1 1
463 /* 256 bytes I/O window. */
464 #define JME_EEPROM_PAGE_BAR2 2
466 #define JME_EEPROM_END 0xFF
468 #define JME_EEPROM_MKDESC(f, p) \
469 ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \
470 (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT))
472 /* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */
473 #define JME_EEPINTF 0x0448
474 #define EEPINTF_DATA_MASK 0xFFFF0000
475 #define EEPINTF_DATA_SHIFT 16
476 #define EEPINTF_ADDR_MASK 0x0000FC00
477 #define EEPINTF_ADDR_SHIFT 10
478 #define EEPRINTF_OP_MASK 0x00000300
479 #define EEPINTF_OP_EXECUTE 0x00000080
480 #define EEPINTF_DATA_OUT 0x00000008
481 #define EEPINTF_DATA_IN 0x00000004
482 #define EEPINTF_CLK 0x00000002
483 #define EEPINTF_SEL 0x00000001
485 /* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */
486 #define JME_EEPCSR 0x044C
487 #define EEPCSR_EEPROM_RELOAD 0x00000002
488 #define EEPCSR_EEPROM_PRESENT 0x00000001
490 /* Misc registers. */
491 #define JME_MISC_BASE_ADDR 0x800
493 /* Timer control and status. */
494 #define JME_TMCSR 0x0800
495 #define TMCSR_SW_INTR 0x80000000
496 #define TMCSR_TIMER_INTR 0x10000000
497 #define TMCSR_TIMER_ENB 0x01000000
498 #define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF
500 /* GPIO control and status. */
501 #define JME_GPIO 0x0804
502 #define GPIO_4_SPI_IN 0x80000000
503 #define GPIO_3_SPI_IN 0x40000000
504 #define GPIO_4_SPI_OUT 0x20000000
505 #define GPIO_4_SPI_OUT_ENB 0x10000000
506 #define GPIO_3_SPI_OUT 0x08000000
507 #define GPIO_3_SPI_OUT_ENB 0x04000000
508 #define GPIO_3_4_LED 0x00000000
509 #define GPIO_3_4_GPIO 0x02000000
510 #define GPIO_2_CLKREQN_IN 0x00100000
511 #define GPIO_2_CLKREQN_OUT 0x00040000
512 #define GPIO_2_CLKREQN_OUT_ENB 0x00020000
513 #define GPIO_1_LED42_IN 0x00001000
514 #define GPIO_1_LED42_OUT 0x00000400
515 #define GPIO_1_LED42_OUT_ENB 0x00000200
516 #define GPIO_1_LED42_ENB 0x00000100
517 #define GPIO_0_SDA_IN 0x00000010
518 #define GPIO_0_SDA_OUT 0x00000004
519 #define GPIO_0_SDA_OUT_ENB 0x00000002
520 #define GPIO_0_SDA_ENB 0x00000001
522 /* General purpose register 0. */
523 #define JME_GPREG0 0x0808
524 #define GPREG0_SH_POST_DW7_DIS 0x80000000
525 #define GPREG0_SH_POST_DW6_DIS 0x40000000
526 #define GPREG0_SH_POST_DW5_DIS 0x20000000
527 #define GPREG0_SH_POST_DW4_DIS 0x10000000
528 #define GPREG0_SH_POST_DW3_DIS 0x08000000
529 #define GPREG0_SH_POST_DW2_DIS 0x04000000
530 #define GPREG0_SH_POST_DW1_DIS 0x02000000
531 #define GPREG0_SH_POST_DW0_DIS 0x01000000
532 #define GPREG0_DMA_RD_REQ_8 0x00000000
533 #define GPREG0_DMA_RD_REQ_6 0x00100000
534 #define GPREG0_DMA_RD_REQ_5 0x00200000
535 #define GPREG0_DMA_RD_REQ_4 0x00300000
536 #define GPREG0_POST_DW0_ENB 0x00040000
537 #define GPREG0_PCC_CLR_DIS 0x00020000
538 #define GPREG0_FORCE_SCL_OUT 0x00010000
539 #define GPREG0_DL_RSTB_DIS 0x00008000
540 #define GPREG0_STICKY_RESET 0x00004000
541 #define GPREG0_DL_RSTB_CFG_DIS 0x00002000
542 #define GPREG0_LINK_CHG_POLL 0x00001000
543 #define GPREG0_LINK_CHG_DIRECT 0x00000000
544 #define GPREG0_MSI_GEN_SEL 0x00000800
545 #define GPREG0_SMB_PAD_PU_DIS 0x00000400
546 #define GPREG0_PCC_UNIT_16US 0x00000000
547 #define GPREG0_PCC_UNIT_256US 0x00000100
548 #define GPREG0_PCC_UNIT_US 0x00000200
549 #define GPREG0_PCC_UNIT_MS 0x00000300
550 #define GPREG0_PCC_UNIT_MASK 0x00000300
551 #define GPREG0_INTR_EVENT_ENB 0x00000080
552 #define GPREG0_PME_ENB 0x00000020
553 #define GPREG0_PHY_ADDR_MASK 0x0000001F
554 #define GPREG0_PHY_ADDR_SHIFT 0
555 #define GPREG0_PHY_ADDR 1
557 /* General purpose register 1. reserved for future use. */
558 #define JME_GPREG1 0x080C
560 /* MSIX entry number of interrupt source. */
561 #define JME_MSINUM_BASE 0x0810
562 #define JME_MSINUM_END 0x081F
563 #define MSINUM_MASK 0x7FFFFFFF
564 #define MSINUM_ENTRY_MASK 7
565 #define MSINUM_REG_INDEX(x) ((x) / 8)
566 #define MSINUM_INTR_SOURCE(x, y) \
567 (((x) & MSINUM_ENTRY_MASK) << (((y) & 7) * 4))
568 #define MSINUM_NUM_INTR_SOURCE 32
570 /* Interrupt event status. */
571 #define JME_INTR_STATUS 0x0820
572 #define INTR_SW 0x80000000
573 #define INTR_TIMER 0x40000000
574 #define INTR_LINKCHG 0x20000000
575 #define INTR_PAUSE 0x10000000
576 #define INTR_MAGIC_PKT 0x08000000
577 #define INTR_WAKEUP_PKT 0x04000000
578 #define INTR_RXQ0_COAL_TO 0x02000000
579 #define INTR_RXQ1_COAL_TO 0x01000000
580 #define INTR_RXQ2_COAL_TO 0x00800000
581 #define INTR_RXQ3_COAL_TO 0x00400000
582 #define INTR_TXQ_COAL_TO 0x00200000
583 #define INTR_RXQ0_COAL 0x00100000
584 #define INTR_RXQ1_COAL 0x00080000
585 #define INTR_RXQ2_COAL 0x00040000
586 #define INTR_RXQ3_COAL 0x00020000
587 #define INTR_TXQ_COAL 0x00010000
588 #define INTR_RXQ3_DESC_EMPTY 0x00008000
589 #define INTR_RXQ2_DESC_EMPTY 0x00004000
590 #define INTR_RXQ1_DESC_EMPTY 0x00002000
591 #define INTR_RXQ0_DESC_EMPTY 0x00001000
592 #define INTR_RXQ3_COMP 0x00000800
593 #define INTR_RXQ2_COMP 0x00000400
594 #define INTR_RXQ1_COMP 0x00000200
595 #define INTR_RXQ0_COMP 0x00000100
596 #define INTR_TXQ7_COMP 0x00000080
597 #define INTR_TXQ6_COMP 0x00000040
598 #define INTR_TXQ5_COMP 0x00000020
599 #define INTR_TXQ4_COMP 0x00000010
600 #define INTR_TXQ3_COMP 0x00000008
601 #define INTR_TXQ2_COMP 0x00000004
602 #define INTR_TXQ1_COMP 0x00000002
603 #define INTR_TXQ0_COMP 0x00000001
605 #define INTR_RXQ_COAL_TO \
606 (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \
607 INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO)
609 #define INTR_RXQ_COAL \
610 (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \
613 #define INTR_RXQ_COMP \
614 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \
617 #define INTR_RXQ_DESC_EMPTY \
618 (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \
619 INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY)
621 #define INTR_RXQ_COMP \
622 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \
625 #define INTR_TXQ_COMP \
626 (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \
627 INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \
628 INTR_TXQ6_COMP | INTR_TXQ7_COMP)
631 (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \
632 INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY)
635 #define N_INTR_TIMER 30
636 #define N_INTR_LINKCHG 29
637 #define N_INTR_PAUSE 28
638 #define N_INTR_MAGIC_PKT 27
639 #define N_INTR_WAKEUP_PKT 26
640 #define N_INTR_RXQ0_COAL_TO 25
641 #define N_INTR_RXQ1_COAL_TO 24
642 #define N_INTR_RXQ2_COAL_TO 23
643 #define N_INTR_RXQ3_COAL_TO 22
644 #define N_INTR_TXQ_COAL_TO 21
645 #define N_INTR_RXQ0_COAL 20
646 #define N_INTR_RXQ1_COAL 19
647 #define N_INTR_RXQ2_COAL 18
648 #define N_INTR_RXQ3_COAL 17
649 #define N_INTR_TXQ_COAL 16
650 #define N_INTR_RXQ3_DESC_EMPTY 15
651 #define N_INTR_RXQ2_DESC_EMPTY 14
652 #define N_INTR_RXQ1_DESC_EMPTY 13
653 #define N_INTR_RXQ0_DESC_EMPTY 12
654 #define N_INTR_RXQ3_COMP 11
655 #define N_INTR_RXQ2_COMP 10
656 #define N_INTR_RXQ1_COMP 9
657 #define N_INTR_RXQ0_COMP 8
658 #define N_INTR_TXQ7_COMP 7
659 #define N_INTR_TXQ6_COMP 6
660 #define N_INTR_TXQ5_COMP 5
661 #define N_INTR_TXQ4_COMP 4
662 #define N_INTR_TXQ3_COMP 3
663 #define N_INTR_TXQ2_COMP 2
664 #define N_INTR_TXQ1_COMP 1
665 #define N_INTR_TXQ0_COMP 0
667 /* Interrupt request status. */
668 #define JME_INTR_REQ_STATUS 0x0824
670 /* Interrupt enable - setting port. */
671 #define JME_INTR_MASK_SET 0x0828
673 /* Interrupt enable - clearing port. */
674 #define JME_INTR_MASK_CLR 0x082C
676 /* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */
677 #define JME_PCCRX0 0x0830
678 #define JME_PCCRX1 0x0834
679 #define JME_PCCRX2 0x0838
680 #define JME_PCCRX3 0x083C
681 #define PCCRX_COAL_TO_MASK 0xFFFF0000
682 #define PCCRX_COAL_TO_SHIFT 16
683 #define PCCRX_COAL_PKT_MASK 0x0000FF00
684 #define PCCRX_COAL_PKT_SHIFT 8
686 #define PCCRX_COAL_TO_MIN 1
687 #define PCCRX_COAL_TO_DEFAULT 100
688 #define PCCRX_COAL_TO_MAX 65535
690 #define PCCRX_COAL_PKT_MIN 1
691 #define PCCRX_COAL_PKT_DEFAULT 2
692 #define PCCRX_COAL_PKT_MAX 255
694 /* Packet completion coalescing control of Tx queue. */
695 #define JME_PCCTX 0x0840
696 #define PCCTX_COAL_TO_MASK 0xFFFF0000
697 #define PCCTX_COAL_TO_SHIFT 16
698 #define PCCTX_COAL_PKT_MASK 0x0000FF00
699 #define PCCTX_COAL_PKT_SHIFT 8
700 #define PCCTX_COAL_TXQ7 0x00000080
701 #define PCCTX_COAL_TXQ6 0x00000040
702 #define PCCTX_COAL_TXQ5 0x00000020
703 #define PCCTX_COAL_TXQ4 0x00000010
704 #define PCCTX_COAL_TXQ3 0x00000008
705 #define PCCTX_COAL_TXQ2 0x00000004
706 #define PCCTX_COAL_TXQ1 0x00000002
707 #define PCCTX_COAL_TXQ0 0x00000001
709 #define PCCTX_COAL_TO_MIN 1
710 #define PCCTX_COAL_TO_DEFAULT 100
711 #define PCCTX_COAL_TO_MAX 65535
713 #define PCCTX_COAL_PKT_MIN 1
714 #define PCCTX_COAL_PKT_DEFAULT 8
715 #define PCCTX_COAL_PKT_MAX 255
717 /* Chip mode and FPGA version. */
718 #define JME_CHIPMODE 0x0844
719 #define CHIPMODE_FPGA_REV_MASK 0xFFFF0000
720 #define CHIPMODE_FPGA_REV_SHIFT 16
721 #define CHIPMODE_NOT_FPGA 0
722 #define CHIPMODE_REV_MASK 0x0000FF00
723 #define CHIPMODE_REV_SHIFT 8
724 #define CHIPMODE_MODE_48P 0x0000000C
725 #define CHIPMODE_MODE_64P 0x00000004
726 #define CHIPMODE_MODE_128P_MAC 0x00000003
727 #define CHIPMODE_MODE_128P_DBG 0x00000002
728 #define CHIPMODE_MODE_128P_PHY 0x00000000
730 /* Shadow status base address high/low. */
731 #define JME_SHBASE_ADDR_HI 0x0848
732 #define JME_SHBASE_ADDR_LO 0x084C
733 #define SHBASE_ADDR_LO_MASK 0xFFFFFFE0
734 #define SHBASE_POST_FORCE 0x00000002
735 #define SHBASE_POST_ENB 0x00000001
738 #define JME_TIMER1 0x0870
739 #define JME_TIMER2 0x0874
740 #define TIMER_ENB 0x01000000
741 #define TIMER_CNT_MASK 0x00FFFFFF
742 #define TIMER_CNT_SHIFT 0
743 #define TIMER_UNIT 1024 /* 1024us */
745 /* Aggresive power mode control. */
746 #define JME_APMC 0x087C
747 #define APMC_PCIE_SDOWN_STAT 0x80000000
748 #define APMC_PCIE_SDOWN_ENB 0x40000000
749 #define APMC_PSEUDO_HOT_PLUG 0x20000000
750 #define APMC_EXT_PLUGIN_ENB 0x04000000
751 #define APMC_EXT_PLUGIN_CTL_MSK 0x03000000
752 #define APMC_DIS_SRAM 0x00000004
753 #define APMC_DIS_CLKPM 0x00000002
754 #define APMC_DIS_CLKTX 0x00000001
756 /* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */
757 #define JME_PCCSRX_BASE 0x0880
758 #define JME_PCCSRX_END 0x088F
759 #define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4))
760 #define PCCSRX_TO_MASK 0xFFFF0000
761 #define PCCSRX_TO_SHIFT 16
762 #define PCCSRX_PKT_CNT_MASK 0x0000FF00
763 #define PCCSRX_PKT_CNT_SHIFT 8
765 /* Packet completion coalesing status of Tx queue. */
766 #define JME_PCCSTX 0x0890
767 #define PCCSTX_TO_MASK 0xFFFF0000
768 #define PCCSTX_TO_SHIFT 16
769 #define PCCSTX_PKT_CNT_MASK 0x0000FF00
770 #define PCCSTX_PKT_CNT_SHIFT 8
772 /* Tx queues empty indicator. */
773 #define JME_TXQEMPTY 0x0894
774 #define TXQEMPTY_TXQ7 0x00000080
775 #define TXQEMPTY_TXQ6 0x00000040
776 #define TXQEMPTY_TXQ5 0x00000020
777 #define TXQEMPTY_TXQ4 0x00000010
778 #define TXQEMPTY_TXQ3 0x00000008
779 #define TXQEMPTY_TXQ2 0x00000004
780 #define TXQEMPTY_TXQ1 0x00000002
781 #define TXQEMPTY_TXQ0 0x00000001
782 #define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y)))
784 /* RSS control registers. */
785 #define JME_RSS_BASE 0x0C00
787 #define JME_RSSC 0x0C00
788 #define RSSC_HASH_LEN_MASK 0x0000E000
789 #define RSSC_HASH_64_ENTRY 0x0000A000
790 #define RSSC_HASH_128_ENTRY 0x0000E000
791 #define RSSC_HASH_NONE 0x00001000
792 #define RSSC_HASH_IPV6 0x00000800
793 #define RSSC_HASH_IPV4 0x00000400
794 #define RSSC_HASH_IPV6_TCP 0x00000200
795 #define RSSC_HASH_IPV4_TCP 0x00000100
796 #define RSSC_NCPU_MASK 0x000000F8
797 #define RSSC_NCPU_SHIFT 3
798 #define RSSC_DIS_RSS 0x00000000
799 #define RSSC_2RXQ_ENB 0x00000001
800 #define RSSS_4RXQ_ENB 0x00000002
803 #define JME_RSSCPU 0x0C04
804 #define RSSCPU_N_SEL(x) ((1 << (x))
806 /* RSS Hash value. */
807 #define JME_RSSHASH 0x0C10
809 #define JME_RSSHASH_STAT 0x0C14
811 #define JME_RSS_RDATA0 0x0C18
813 #define JME_RSS_RDATA1 0x0C1C
815 /* RSS secret key. */
816 #define JME_RSSKEY_BASE 0x0C40
817 #define JME_RSSKEY_LAST 0x0C64
818 #define JME_RSSKEY_END 0x0C67
819 #define HASHKEY_NBYTES 40
820 #define RSSKEY_REG(x) (JME_RSSKEY_LAST - (4 * ((x) / 4)))
821 #define RSSKEY_VALUE(x, y) ((x) << (24 - 8 * ((y) % 4)))
823 /* RSS indirection table entries. */
824 #define JME_RSSTBL_BASE 0x0C80
825 #define JME_RSSTBL_END 0x0CFF
826 #define RSSTBL_NENTRY 128
827 #define RSSTBL_REG(x) (JME_RSSTBL_BASE + ((x) / 4))
828 #define RSSTBL_VALUE(x, y) ((x) << (8 * ((y) % 4)))
831 #define JME_MSIX_BASE_ADDR 0x2000
833 #define JME_MSIX_BASE 0x2000
834 #define JME_MSIX_END 0x207F
835 #define JME_MSIX_NENTRY 8
836 #define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10))
837 #define MSIX_ADDR_HI_OFF 0x00
838 #define MSIX_ADDR_LO_OFF 0x04
839 #define MSIX_ADDR_LO_MASK 0xFFFFFFFC
840 #define MSIX_DATA_OFF 0x08
841 #define MSIX_VECTOR_OFF 0x0C
842 #define MSIX_VECTOR_RSVD 0x80000000
843 #define MSIX_VECTOR_DIS 0x00000001
846 #define JME_MSIX_PBA_BASE_ADDR 0x3000
848 #define JME_MSIX_PBA 0x3000
849 #define MSIX_PBA_RSVD_MASK 0xFFFFFF00
850 #define MSIX_PBA_RSVD_SHIFT 8
851 #define MSIX_PBA_PEND_MASK 0x000000FF
852 #define MSIX_PBA_PEND_SHIFT 0
853 #define MSIX_PBA_PEND_ENTRY7 0x00000080
854 #define MSIX_PBA_PEND_ENTRY6 0x00000040
855 #define MSIX_PBA_PEND_ENTRY5 0x00000020
856 #define MSIX_PBA_PEND_ENTRY4 0x00000010
857 #define MSIX_PBA_PEND_ENTRY3 0x00000008
858 #define MSIX_PBA_PEND_ENTRY2 0x00000004
859 #define MSIX_PBA_PEND_ENTRY1 0x00000002
860 #define MSIX_PBA_PEND_ENTRY0 0x00000001
862 #define JME_PHY_OUI 0x001B8C
863 #define JME_PHY_MODEL 0x21
864 #define JME_PHY_REV 0x01
865 #define JME_PHY_ADDR 1
867 /* JMC250 shadow status block. */
879 /* JMC250 descriptor structures. */
887 #define JME_TD_OWN 0x80000000
888 #define JME_TD_INTR 0x40000000
889 #define JME_TD_64BIT 0x20000000
890 #define JME_TD_TCPCSUM 0x10000000
891 #define JME_TD_UDPCSUM 0x08000000
892 #define JME_TD_IPCSUM 0x04000000
893 #define JME_TD_TSO 0x02000000
894 #define JME_TD_VLAN_TAG 0x01000000
895 #define JME_TD_VLAN_MASK 0x0000FFFF
897 #define JME_TD_MSS_MASK 0xFFFC0000
898 #define JME_TD_MSS_SHIFT 18
899 #define JME_TD_BUF_LEN_MASK 0x0000FFFF
900 #define JME_TD_BUF_LEN_SHIFT 0
902 #define JME_TD_FRAME_LEN_MASK 0x0000FFFF
903 #define JME_TD_FRAME_LEN_SHIFT 0
906 * Only the first Tx descriptor of a packet is updated
907 * after packet transmission.
909 #define JME_TD_TMOUT 0x20000000
910 #define JME_TD_RETRY_EXP 0x10000000
911 #define JME_TD_COLLISION 0x08000000
912 #define JME_TD_UNDERRUN 0x04000000
913 #define JME_TD_EHDR_SIZE_MASK 0x000000FF
914 #define JME_TD_EHDR_SIZE_SHIFT 0
916 #define JME_TD_SEG_CNT_MASK 0xFFFF0000
917 #define JME_TD_SEG_CNT_SHIFT 16
918 #define JME_TD_RETRY_CNT_MASK 0x0000FFFF
919 #define JME_TD_RETRY_CNT_SHIFT 0
921 #define JME_RD_OWN 0x80000000
922 #define JME_RD_INTR 0x40000000
923 #define JME_RD_64BIT 0x20000000
925 #define JME_RD_BUF_LEN_MASK 0x0000FFFF
926 #define JME_RD_BUF_LEN_SHIFT 0
929 * Only the first Rx descriptor of a packet is updated
930 * after packet reception.
932 #define JME_RD_MORE_FRAG 0x20000000
933 #define JME_RD_TCP 0x10000000
934 #define JME_RD_UDP 0x08000000
935 #define JME_RD_IPCSUM 0x04000000
936 #define JME_RD_TCPCSUM 0x02000000
937 #define JME_RD_UDPCSUM 0x01000000
938 #define JME_RD_VLAN_TAG 0x00800000
939 #define JME_RD_IPV4 0x00400000
940 #define JME_RD_IPV6 0x00200000
941 #define JME_RD_PAUSE 0x00100000
942 #define JME_RD_MAGIC 0x00080000
943 #define JME_RD_WAKEUP 0x00040000
944 #define JME_RD_BCAST 0x00030000
945 #define JME_RD_MCAST 0x00020000
946 #define JME_RD_UCAST 0x00010000
947 #define JME_RD_VLAN_MASK 0x0000FFFF
948 #define JME_RD_VLAN_SHIFT 0
950 #define JME_RD_VALID 0x80000000
951 #define JME_RD_CNT_MASK 0x7F000000
952 #define JME_RD_CNT_SHIFT 24
953 #define JME_RD_GIANT 0x00800000
954 #define JME_RD_GMII_ERR 0x00400000
955 #define JME_RD_NBL_RCVD 0x00200000
956 #define JME_RD_COLL 0x00100000
957 #define JME_RD_ABORT 0x00080000
958 #define JME_RD_RUNT 0x00040000
959 #define JME_RD_FIFO_OVRN 0x00020000
960 #define JME_RD_CRC_ERR 0x00010000
961 #define JME_RD_FRAME_LEN_MASK 0x0000FFFF
963 #define JME_RX_ERR_STAT \
964 (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \
965 JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \
966 JME_RD_FIFO_OVRN | JME_RD_CRC_ERR)
968 #define JME_RD_ERR_MASK 0x00FF0000
969 #define JME_RD_ERR_SHIFT 16
970 #define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT)
971 #define JME_RX_ERR_BITS "\20" \
972 "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \
973 "\5COLL\6NBLRCVD\7GMIIERR\10"
975 #define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT)
976 #define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK)
977 #define JME_RX_PAD_BYTES 10
979 #define JME_RD_RSS_HASH_VALUE 0xFFFFFFFF
981 #define JME_RD_RSS_HASH_MASK 0x00003F00
982 #define JME_RD_RSS_HASH_SHIFT 8
983 #define JME_RD_RSS_HASH_NONE 0x00000000
984 #define JME_RD_RSS_HASH_IPV4 0x00000100
985 #define JME_RD_RSS_HASH_IPV4TCP 0x00000200
986 #define JME_RD_RSS_HASH_IPV6 0x00000400
987 #define JME_RD_RSS_HASH_IPV6TCP 0x00001000
988 #define JME_RD_HASH_FN_NONE 0x00000000
989 #define JME_RD_HASH_FN_TOEPLITZ 0x00000001