2 * Low level routines for Second Generation
3 * Advanced Systems Inc. SCSI controllers chips
5 * Copyright (c) 1998, 1999, 2000 Justin Gibbs.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * $FreeBSD: src/sys/dev/advansys/adwlib.c,v 1.6.2.1 2000/04/14 13:32:50 nyan Exp $
33 * $DragonFly: src/sys/dev/disk/advansys/adwlib.c,v 1.4 2005/06/03 16:57:12 eirikn Exp $
37 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
39 * Copyright (c) 1995-1998 Advanced System Products, Inc.
40 * All Rights Reserved.
42 * Redistribution and use in source and binary forms, with or without
43 * modification, are permitted provided that redistributions of source
44 * code retain the above copyright notice and this comment without
48 #include <sys/param.h>
49 #include <sys/systm.h>
51 #include <sys/thread2.h>
53 #include <machine/bus_pio.h>
54 #include <machine/bus_memio.h>
55 #include <machine/bus.h>
56 #include <machine/clock.h>
58 #include <bus/cam/cam.h>
59 #include <bus/cam/cam_ccb.h>
60 #include <bus/cam/cam_sim.h>
61 #include <bus/cam/cam_xpt_sim.h>
62 #include <bus/cam/scsi/scsi_all.h>
66 const struct adw_eeprom adw_asc3550_default_eeprom =
68 ADW_EEPROM_BIOS_ENABLE, /* cfg_lsw */
70 0xFFFF, /* disc_enable */
71 0xFFFF, /* wdtr_able */
72 { 0xFFFF }, /* sdtr_able */
73 0xFFFF, /* start_motor */
74 0xFFFF, /* tagqng_able */
75 0xFFFF, /* bios_scan */
76 0, /* scam_tolerant */
77 7, /* adapter_scsi_id */
78 0, /* bios_boot_delay */
79 3, /* scsi_reset_delay */
83 0xFFE7, /* bios_ctrl */
84 { 0xFFFF }, /* ultra_able */
85 { 0 }, /* reserved2 */
86 ADW_DEF_MAX_HOST_QNG, /* max_host_qng */
87 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
90 { 0, 0, 0 }, /* serial_number */
93 0, 0, 0, 0, 0, 0, 0, 0,
94 0, 0, 0, 0, 0, 0, 0, 0
99 0, /* saved_dvc_err_code */
100 0, /* saved_adv_err_code */
101 0 /* saved_adv_err_addr */
104 const struct adw_eeprom adw_asc38C0800_default_eeprom =
106 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
107 0x0000, /* 01 cfg_msw */
108 0xFFFF, /* 02 disc_enable */
109 0xFFFF, /* 03 wdtr_able */
110 { 0x4444 }, /* 04 sdtr_speed1 */
111 0xFFFF, /* 05 start_motor */
112 0xFFFF, /* 06 tagqng_able */
113 0xFFFF, /* 07 bios_scan */
114 0, /* 08 scam_tolerant */
115 7, /* 09 adapter_scsi_id */
116 0, /* bios_boot_delay */
117 3, /* 10 scsi_reset_delay */
119 0, /* 11 termination_se */
120 0, /* termination_lvd */
121 0xFFE7, /* 12 bios_ctrl */
122 { 0x4444 }, /* 13 sdtr_speed2 */
123 { 0x4444 }, /* 14 sdtr_speed3 */
124 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
125 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
127 { 0x4444 } , /* 17 sdtr_speed4 */
128 { 0, 0, 0 }, /* 18-20 serial_number */
129 0, /* 21 check_sum */
130 { /* 22-29 oem_name[16] */
131 0, 0, 0, 0, 0, 0, 0, 0,
132 0, 0, 0, 0, 0, 0, 0, 0
134 0, /* 30 dvc_err_code */
135 0, /* 31 adv_err_code */
136 0, /* 32 adv_err_addr */
137 0, /* 33 saved_dvc_err_code */
138 0, /* 34 saved_adv_err_code */
139 0, /* 35 saved_adv_err_addr */
140 { /* 36 - 55 reserved */
141 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
142 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
144 0, /* 56 cisptr_lsw */
145 0, /* 57 cisprt_msw */
147 (PCI_ID_ADVANSYS_38C0800_REV1 & PCI_ID_DEV_VENDOR_MASK) >> 32,
150 #define ADW_MC_SDTR_OFFSET_ULTRA2_DT 0
151 #define ADW_MC_SDTR_OFFSET_ULTRA2 1
152 #define ADW_MC_SDTR_OFFSET_ULTRA 2
153 const struct adw_syncrate adw_syncrates[] =
155 /* mc_sdtr period rate */
156 { ADW_MC_SDTR_80, 9, "80.0" },
157 { ADW_MC_SDTR_40, 10, "40.0" },
158 { ADW_MC_SDTR_20, 12, "20.0" },
159 { ADW_MC_SDTR_10, 25, "10.0" },
160 { ADW_MC_SDTR_5, 50, "5.0" },
161 { ADW_MC_SDTR_ASYNC, 0, "async" }
164 const int adw_num_syncrates = sizeof(adw_syncrates) / sizeof(adw_syncrates[0]);
166 static u_int16_t adw_eeprom_read_16(struct adw_softc *adw, int addr);
167 static void adw_eeprom_write_16(struct adw_softc *adw, int addr,
169 static void adw_eeprom_wait(struct adw_softc *adw);
172 adw_find_signature(struct adw_softc *adw)
174 if (adw_inb(adw, ADW_SIGNATURE_BYTE) == ADW_CHIP_ID_BYTE
175 && adw_inw(adw, ADW_SIGNATURE_WORD) == ADW_CHIP_ID_WORD)
184 adw_reset_chip(struct adw_softc *adw)
186 adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_RESET);
188 adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_WR_IO_REG);
191 * Initialize Chip registers.
193 adw_outw(adw, ADW_SCSI_CFG1,
194 adw_inw(adw, ADW_SCSI_CFG1) & ~ADW_SCSI_CFG1_BIG_ENDIAN);
198 * Reset the SCSI bus.
201 adw_reset_bus(struct adw_softc *adw)
203 adw_idle_cmd_status_t status;
206 adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_START, /*param*/0);
207 if (status != ADW_IDLE_CMD_SUCCESS) {
208 xpt_print_path(adw->path);
209 printf("Bus Reset start attempt failed\n");
212 DELAY(ADW_BUS_RESET_HOLD_DELAY_US);
214 adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_END, /*param*/0);
215 if (status != ADW_IDLE_CMD_SUCCESS) {
216 xpt_print_path(adw->path);
217 printf("Bus Reset end attempt failed\n");
224 * Read the specified EEPROM location
227 adw_eeprom_read_16(struct adw_softc *adw, int addr)
229 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_READ | addr);
230 adw_eeprom_wait(adw);
231 return (adw_inw(adw, ADW_EEP_DATA));
235 adw_eeprom_write_16(struct adw_softc *adw, int addr, u_int data)
237 adw_outw(adw, ADW_EEP_DATA, data);
238 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE | addr);
239 adw_eeprom_wait(adw);
243 * Wait for and EEPROM command to complete
246 adw_eeprom_wait(struct adw_softc *adw)
250 for (i = 0; i < ADW_EEP_DELAY_MS; i++) {
251 if ((adw_inw(adw, ADW_EEP_CMD) & ADW_EEP_CMD_DONE) != 0)
255 if (i == ADW_EEP_DELAY_MS)
256 panic("%s: Timedout Reading EEPROM", adw_name(adw));
260 * Read EEPROM configuration into the specified buffer.
262 * Return a checksum based on the EEPROM configuration read.
265 adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *eep_buf)
272 wbuf = (u_int16_t *)eep_buf;
275 for (eep_addr = ADW_EEP_DVC_CFG_BEGIN;
276 eep_addr < ADW_EEP_DVC_CFG_END;
277 eep_addr++, wbuf++) {
278 wval = adw_eeprom_read_16(adw, eep_addr);
283 /* checksum field is not counted in the checksum */
284 *wbuf = adw_eeprom_read_16(adw, eep_addr);
287 /* Driver seeprom variables are not included in the checksum */
288 for (eep_addr = ADW_EEP_DVC_CTL_BEGIN;
289 eep_addr < ADW_EEP_MAX_WORD_ADDR;
291 *wbuf = adw_eeprom_read_16(adw, eep_addr);
297 adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *eep_buf)
303 wbuf = (u_int16_t *)eep_buf;
306 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_ABLE);
307 adw_eeprom_wait(adw);
310 * Write EEPROM until checksum.
312 for (addr = ADW_EEP_DVC_CFG_BEGIN;
313 addr < ADW_EEP_DVC_CFG_END; addr++, wbuf++) {
315 adw_eeprom_write_16(adw, addr, *wbuf);
319 * Write calculated EEPROM checksum
321 adw_eeprom_write_16(adw, addr, chksum);
323 /* skip over buffer's checksum */
329 for (addr = ADW_EEP_DVC_CTL_BEGIN;
330 addr < ADW_EEP_MAX_WORD_ADDR; addr++, wbuf++)
331 adw_eeprom_write_16(adw, addr, *wbuf);
333 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_DISABLE);
334 adw_eeprom_wait(adw);
338 adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1)
340 u_int8_t biosmem[ADW_MC_BIOSLEN];
341 const u_int16_t *word_table;
342 const u_int8_t *byte_codes;
343 const u_int8_t *byte_codes_end;
345 u_int bytes_downloaded;
353 * Save the RISC memory BIOS region before writing the microcode.
354 * The BIOS may already be loaded and using its RISC LRAM region
355 * so its region must be saved and restored.
357 for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
358 biosmem[addr] = adw_lram_read_8(adw, ADW_MC_BIOSMEM + addr);
361 * Save current per TID negotiated values if the BIOS has been
362 * loaded (BIOS signature is present). These will be used if
363 * we cannot get information from the EEPROM.
365 addr = ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM;
366 bios_sig = biosmem[addr]
367 | (biosmem[addr + 1] << 8);
368 if (bios_sig == 0x55AA
369 && (adw->flags & ADW_EEPROM_FAILED) != 0) {
374 addr = ADW_MC_BIOS_VERSION - ADW_MC_BIOSMEM;
375 minor_ver = biosmem[addr + 1] & 0xF;
376 major_ver = (biosmem[addr + 1] >> 4) & 0xF;
377 if ((adw->chip == ADW_CHIP_ASC3550)
379 || (major_ver == 3 && minor_ver == 1))) {
381 * BIOS 3.1 and earlier location of
382 * 'wdtr_able' variable.
385 adw_lram_read_16(adw, ADW_MC_WDTR_ABLE_BIOS_31);
388 adw_lram_read_16(adw, ADW_MC_WDTR_ABLE);
390 sdtr_able = adw_lram_read_16(adw, ADW_MC_SDTR_ABLE);
391 for (tid = 0; tid < ADW_MAX_TID; tid++) {
395 tid_mask = 0x1 << tid;
396 if ((sdtr_able & tid_mask) == 0)
397 mc_sdtr = ADW_MC_SDTR_ASYNC;
398 else if ((adw->features & ADW_DT) != 0)
399 mc_sdtr = ADW_MC_SDTR_80;
400 else if ((adw->features & ADW_ULTRA2) != 0)
401 mc_sdtr = ADW_MC_SDTR_40;
403 mc_sdtr = ADW_MC_SDTR_20;
404 adw_set_user_sdtr(adw, tid, mc_sdtr);
406 adw->user_tagenb = adw_lram_read_16(adw, ADW_MC_TAGQNG_ABLE);
410 * Load the Microcode.
412 * Assume the following compressed format of the microcode buffer:
414 * 253 word (506 byte) table indexed by byte code followed
415 * by the following byte codes:
418 * 00: Emit word 0 in table.
419 * 01: Emit word 1 in table.
421 * FD: Emit word 253 in table.
426 * FE WW WW: (3 byte code)
427 * Word to emit is the next word WW WW.
428 * FF BB WW WW: (4 byte code)
429 * Emit BB count times next word WW WW.
432 bytes_downloaded = 0;
433 word_table = (const u_int16_t *)adw->mcode_data->mcode_buf;
434 byte_codes = (const u_int8_t *)&word_table[253];
435 byte_codes_end = adw->mcode_data->mcode_buf
436 + adw->mcode_data->mcode_size;
437 adw_outw(adw, ADW_RAM_ADDR, 0);
438 while (byte_codes < byte_codes_end) {
439 if (*byte_codes == 0xFF) {
442 value = byte_codes[2]
443 | byte_codes[3] << 8;
444 adw_set_multi_2(adw, ADW_RAM_DATA,
445 value, byte_codes[1]);
446 bytes_downloaded += byte_codes[1];
448 } else if (*byte_codes == 0xFE) {
451 value = byte_codes[1]
452 | byte_codes[2] << 8;
453 adw_outw(adw, ADW_RAM_DATA, value);
457 adw_outw(adw, ADW_RAM_DATA, word_table[*byte_codes]);
462 /* Convert from words to bytes */
463 bytes_downloaded *= 2;
466 * Clear the rest of LRAM.
468 for (addr = bytes_downloaded; addr < adw->memsize; addr += 2)
469 adw_outw(adw, ADW_RAM_DATA, 0);
472 * Verify the microcode checksum.
475 adw_outw(adw, ADW_RAM_ADDR, 0);
476 for (addr = 0; addr < bytes_downloaded; addr += 2)
477 checksum += adw_inw(adw, ADW_RAM_DATA);
479 if (checksum != adw->mcode_data->mcode_chksum) {
480 printf("%s: Firmware load failed!\n", adw_name(adw));
485 * Restore the RISC memory BIOS region.
487 for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
488 adw_lram_write_8(adw, addr + ADW_MC_BIOSLEN, biosmem[addr]);
491 * Calculate and write the microcode code checksum to
492 * the microcode code checksum location.
494 addr = adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR);
495 end_addr = adw_lram_read_16(adw, ADW_MC_CODE_END_ADDR);
497 adw_outw(adw, ADW_RAM_ADDR, addr);
498 for (; addr < end_addr; addr += 2)
499 checksum += adw_inw(adw, ADW_RAM_DATA);
500 adw_lram_write_16(adw, ADW_MC_CODE_CHK_SUM, checksum);
503 * Tell the microcode what kind of chip it's running on.
505 adw_lram_write_16(adw, ADW_MC_CHIP_TYPE, adw->chip);
508 * Leave WDTR and SDTR negotiation disabled until the XPT has
509 * informed us of device capabilities, but do set the desired
510 * user rates in case we receive an SDTR request from the target
511 * before we negotiate. We turn on tagged queuing at the microcode
512 * level for all devices, and modulate this on a per command basis.
514 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED1, adw->user_sdtr[0]);
515 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED2, adw->user_sdtr[1]);
516 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED3, adw->user_sdtr[2]);
517 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED4, adw->user_sdtr[3]);
518 adw_lram_write_16(adw, ADW_MC_DISC_ENABLE, adw->user_discenb);
519 for (tid = 0; tid < ADW_MAX_TID; tid++) {
520 /* Cam limits the maximum number of commands for us */
521 adw_lram_write_8(adw, ADW_MC_NUMBER_OF_MAX_CMD + tid,
524 adw_lram_write_16(adw, ADW_MC_TAGQNG_ABLE, ~0);
527 * Set SCSI_CFG0 Microcode Default Value.
529 * The microcode will set the SCSI_CFG0 register using this value
530 * after it is started.
532 adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG0,
533 ADW_SCSI_CFG0_PARITY_EN|ADW_SCSI_CFG0_SEL_TMO_LONG|
534 ADW_SCSI_CFG0_OUR_ID_EN|adw->initiator_id);
537 * Tell the MC about the memory size that
538 * was setup by the probe code.
540 adw_lram_write_16(adw, ADW_MC_DEFAULT_MEM_CFG,
541 adw_inb(adw, ADW_MEM_CFG) & ADW_MEM_CFG_RAM_SZ_MASK);
544 * Determine SCSI_CFG1 Microcode Default Value.
546 * The microcode will set the SCSI_CFG1 register using this value
547 * after it is started below.
549 scsicfg1 = adw_inw(adw, ADW_SCSI_CFG1);
552 * If the internal narrow cable is reversed all of the SCSI_CTRL
553 * register signals will be set. Check for and return an error if
554 * this condition is found.
556 if ((adw_inw(adw, ADW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
557 printf("%s: Illegal Cable Config!\n", adw_name(adw));
558 printf("%s: Internal cable is reversed!\n", adw_name(adw));
563 * If this is a differential board and a single-ended device
564 * is attached to one of the connectors, return an error.
566 if ((adw->features & ADW_ULTRA) != 0) {
567 if ((scsicfg1 & ADW_SCSI_CFG1_DIFF_MODE) != 0
568 && (scsicfg1 & ADW_SCSI_CFG1_DIFF_SENSE) == 0) {
569 printf("%s: A Single Ended Device is attached to our "
570 "differential bus!\n", adw_name(adw));
574 if ((scsicfg1 & ADW2_SCSI_CFG1_DEV_DETECT_HVD) != 0) {
575 printf("%s: A High Voltage Differential Device "
576 "is attached to this controller.\n",
578 printf("%s: HVD devices are not supported.\n",
585 * Perform automatic termination control if desired.
587 if ((adw->features & ADW_ULTRA2) != 0) {
591 * Ultra2 Chips require termination disabled to
592 * detect cable presence.
594 adw_outw(adw, ADW_SCSI_CFG1,
595 scsicfg1 | ADW2_SCSI_CFG1_DIS_TERM_DRV);
596 cable_det = adw_inw(adw, ADW_SCSI_CFG1);
597 adw_outw(adw, ADW_SCSI_CFG1, scsicfg1);
599 /* SE Termination first if auto-term has been specified */
600 if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) {
603 * For all SE cable configurations, high byte
604 * termination is enabled.
606 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
607 if ((cable_det & ADW_SCSI_CFG1_INT8_MASK) != 0
608 || (cable_det & ADW_SCSI_CFG1_INT16_MASK) != 0) {
610 * If either cable is not present, the
611 * low byte must be terminated as well.
613 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L;
618 if ((term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) == 0
619 && (term_scsicfg1 & ADW2_SCSI_CFG1_DIS_TERM_DRV) == 0) {
621 * If both cables are installed, termination
622 * is disabled. Otherwise it is enabled.
624 if ((cable_det & ADW2_SCSI_CFG1_EXTLVD_MASK) != 0
625 || (cable_det & ADW2_SCSI_CFG1_INTLVD_MASK) != 0) {
627 term_scsicfg1 |= ADW2_SCSI_CFG1_TERM_CTL_LVD;
630 term_scsicfg1 &= ~ADW2_SCSI_CFG1_DIS_TERM_DRV;
632 /* Ultra Controller Termination */
633 if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) {
635 int wide_cable_count;
638 wide_cable_count = 0;
639 if ((scsicfg1 & ADW_SCSI_CFG1_INT16_MASK) == 0) {
643 if ((scsicfg1 & ADW_SCSI_CFG1_INT8_MASK) == 0)
646 /* There is only one external port */
647 if ((scsicfg1 & ADW_SCSI_CFG1_EXT16_MASK) == 0) {
650 } else if ((scsicfg1 & ADW_SCSI_CFG1_EXT8_MASK) == 0)
653 if (cable_count == 3) {
654 printf("%s: Illegal Cable Config!\n",
656 printf("%s: Only Two Ports may be used at "
657 "a time!\n", adw_name(adw));
658 } else if (cable_count <= 1) {
660 * At least two out of three cables missing.
661 * Terminate both bytes.
663 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H
664 | ADW_SCSI_CFG1_TERM_CTL_L;
665 } else if (wide_cable_count <= 1) {
666 /* No two 16bit cables present. High on. */
667 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
672 /* Tell the user about our decission */
673 switch (term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) {
674 case ADW_SCSI_CFG1_TERM_CTL_MASK:
675 printf("High & Low SE Term Enabled, ");
677 case ADW_SCSI_CFG1_TERM_CTL_H:
678 printf("High SE Termination Enabled, ");
680 case ADW_SCSI_CFG1_TERM_CTL_L:
681 printf("Low SE Term Enabled, ");
687 if ((adw->features & ADW_ULTRA2) != 0
688 && (term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) != 0)
689 printf("LVD Term Enabled, ");
692 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
693 * set 'scsicfg1'. The TERM_POL bit does not need to be
694 * referenced, because the hardware internally inverts
695 * the Termination High and Low bits if TERM_POL is set.
697 if ((adw->features & ADW_ULTRA2) != 0) {
698 term_scsicfg1 = ~term_scsicfg1;
699 term_scsicfg1 &= ADW_SCSI_CFG1_TERM_CTL_MASK
700 | ADW2_SCSI_CFG1_TERM_CTL_LVD;
701 scsicfg1 &= ~(ADW_SCSI_CFG1_TERM_CTL_MASK
702 |ADW2_SCSI_CFG1_TERM_CTL_LVD
703 |ADW_SCSI_CFG1_BIG_ENDIAN
704 |ADW_SCSI_CFG1_TERM_POL
705 |ADW2_SCSI_CFG1_DEV_DETECT);
706 scsicfg1 |= term_scsicfg1;
708 term_scsicfg1 = ~term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK;
709 scsicfg1 &= ~ADW_SCSI_CFG1_TERM_CTL_MASK;
710 scsicfg1 |= term_scsicfg1 | ADW_SCSI_CFG1_TERM_CTL_MANUAL;
711 scsicfg1 |= ADW_SCSI_CFG1_FLTR_DISABLE;
715 * Set SCSI_CFG1 Microcode Default Value
717 * The microcode will set the SCSI_CFG1 register using this value
718 * after it is started below.
720 adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG1, scsicfg1);
723 * Only accept selections on our initiator target id.
724 * This may change in target mode scenarios...
726 adw_lram_write_16(adw, ADW_MC_DEFAULT_SEL_MASK,
727 (0x01 << adw->initiator_id));
730 * Tell the microcode where it can find our
731 * Initiator Command Queue (ICQ). It is
732 * currently empty hence the "stopper" address.
734 adw->commandq = adw->free_carriers;
735 adw->free_carriers = carrierbotov(adw, adw->commandq->next_ba);
736 adw->commandq->next_ba = ADW_CQ_STOPPER;
737 adw_lram_write_32(adw, ADW_MC_ICQ, adw->commandq->carr_ba);
740 * Tell the microcode where it can find our
741 * Initiator Response Queue (IRQ). It too
742 * is currently empty.
744 adw->responseq = adw->free_carriers;
745 adw->free_carriers = carrierbotov(adw, adw->responseq->next_ba);
746 adw->responseq->next_ba = ADW_CQ_STOPPER;
747 adw_lram_write_32(adw, ADW_MC_IRQ, adw->responseq->carr_ba);
749 adw_outb(adw, ADW_INTR_ENABLES,
750 ADW_INTR_ENABLE_HOST_INTR|ADW_INTR_ENABLE_GLOBAL_INTR);
752 adw_outw(adw, ADW_PC, adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR));
758 adw_set_user_sdtr(struct adw_softc *adw, u_int tid, u_int mc_sdtr)
760 adw->user_sdtr[ADW_TARGET_GROUP(tid)] &= ~ADW_TARGET_GROUP_MASK(tid);
761 adw->user_sdtr[ADW_TARGET_GROUP(tid)] |=
762 mc_sdtr << ADW_TARGET_GROUP_SHIFT(tid);
766 adw_get_user_sdtr(struct adw_softc *adw, u_int tid)
770 mc_sdtr = adw->user_sdtr[ADW_TARGET_GROUP(tid)];
771 mc_sdtr &= ADW_TARGET_GROUP_MASK(tid);
772 mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
777 adw_set_chip_sdtr(struct adw_softc *adw, u_int tid, u_int sdtr)
779 u_int mc_sdtr_offset;
782 mc_sdtr_offset = ADW_MC_SDTR_SPEED1;
783 mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2;
784 mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset);
785 mc_sdtr &= ~ADW_TARGET_GROUP_MASK(tid);
786 mc_sdtr |= sdtr << ADW_TARGET_GROUP_SHIFT(tid);
787 adw_lram_write_16(adw, mc_sdtr_offset, mc_sdtr);
791 adw_get_chip_sdtr(struct adw_softc *adw, u_int tid)
793 u_int mc_sdtr_offset;
796 mc_sdtr_offset = ADW_MC_SDTR_SPEED1;
797 mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2;
798 mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset);
799 mc_sdtr &= ADW_TARGET_GROUP_MASK(tid);
800 mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
805 adw_find_sdtr(struct adw_softc *adw, u_int period)
810 if ((adw->features & ADW_DT) == 0)
811 i = ADW_MC_SDTR_OFFSET_ULTRA2;
812 if ((adw->features & ADW_ULTRA2) == 0)
813 i = ADW_MC_SDTR_OFFSET_ULTRA;
815 return ADW_MC_SDTR_ASYNC;
817 for (; i < adw_num_syncrates; i++) {
818 if (period <= adw_syncrates[i].period)
819 return (adw_syncrates[i].mc_sdtr);
821 return ADW_MC_SDTR_ASYNC;
825 adw_find_period(struct adw_softc *adw, u_int mc_sdtr)
829 for (i = 0; i < adw_num_syncrates; i++) {
830 if (mc_sdtr == adw_syncrates[i].mc_sdtr)
833 return (adw_syncrates[i].period);
837 adw_hshk_cfg_period_factor(u_int tinfo)
839 tinfo &= ADW_HSHK_CFG_RATE_MASK;
840 tinfo >>= ADW_HSHK_CFG_RATE_SHIFT;
844 else if (tinfo == 0x10)
848 return (((tinfo * 25) + 50) / 4);
852 * Send an idle command to the chip and wait for completion.
854 adw_idle_cmd_status_t
855 adw_idle_cmd_send(struct adw_softc *adw, adw_idle_cmd_t cmd, u_int parameter)
858 adw_idle_cmd_status_t status;
863 * Clear the idle command status which is set by the microcode
864 * to a non-zero value to indicate when the command is completed.
866 adw_lram_write_16(adw, ADW_MC_IDLE_CMD_STATUS, 0);
869 * Write the idle command value after the idle command parameter
870 * has been written to avoid a race condition. If the order is not
871 * followed, the microcode may process the idle command before the
872 * parameters have been written to LRAM.
874 adw_lram_write_32(adw, ADW_MC_IDLE_CMD_PARAMETER, parameter);
875 adw_lram_write_16(adw, ADW_MC_IDLE_CMD, cmd);
878 * Tickle the RISC to tell it to process the idle command.
880 adw_tickle_risc(adw, ADW_TICKLE_B);
882 /* Wait for up to 10 seconds for the command to complete */
885 status = adw_lram_read_16(adw, ADW_MC_IDLE_CMD_STATUS);
892 panic("%s: Idle Command Timed Out!\n", adw_name(adw));