2 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
3 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
4 * Copyright 2007 Advanced Micro Devices, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
31 #include "dev/drm/drmP.h"
32 #include "dev/drm/drm.h"
33 #include "dev/drm/drm_sarea.h"
34 #include "dev/drm/radeon_drm.h"
35 #include "dev/drm/radeon_drv.h"
36 #include "dev/drm/r300_reg.h"
38 #include "dev/drm/radeon_microcode.h"
40 #define RADEON_FIFO_DEBUG 0
42 static int radeon_do_cleanup_cp(struct drm_device * dev);
43 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
45 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
49 if (dev_priv->flags & RADEON_IS_AGP) {
50 val = DRM_READ32(dev_priv->ring_rptr, off);
52 val = *(((volatile u32 *)
53 dev_priv->ring_rptr->handle) +
55 val = le32_to_cpu(val);
60 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
62 if (dev_priv->writeback_works)
63 return radeon_read_ring_rptr(dev_priv, 0);
65 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
66 return RADEON_READ(R600_CP_RB_RPTR);
68 return RADEON_READ(RADEON_CP_RB_RPTR);
72 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
74 if (dev_priv->flags & RADEON_IS_AGP)
75 DRM_WRITE32(dev_priv->ring_rptr, off, val);
77 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
78 (off / sizeof(u32))) = cpu_to_le32(val);
81 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
83 radeon_write_ring_rptr(dev_priv, 0, val);
86 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
88 if (dev_priv->writeback_works) {
89 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
90 return radeon_read_ring_rptr(dev_priv,
91 R600_SCRATCHOFF(index));
93 return radeon_read_ring_rptr(dev_priv,
94 RADEON_SCRATCHOFF(index));
96 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
97 return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
99 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
103 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
108 ret = DRM_READ32(dev_priv->mmio, addr);
110 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
111 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
117 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
120 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
121 ret = RADEON_READ(R520_MC_IND_DATA);
122 RADEON_WRITE(R520_MC_IND_INDEX, 0);
126 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
129 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
130 ret = RADEON_READ(RS480_NB_MC_DATA);
131 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
135 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
138 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
139 ret = RADEON_READ(RS690_MC_DATA);
140 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
144 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
147 RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
148 RS600_MC_IND_CITF_ARB0));
149 ret = RADEON_READ(RS600_MC_DATA);
153 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
155 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
156 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
157 return RS690_READ_MCIND(dev_priv, addr);
158 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
159 return RS600_READ_MCIND(dev_priv, addr);
161 return RS480_READ_MCIND(dev_priv, addr);
164 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
167 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
168 return RADEON_READ(R700_MC_VM_FB_LOCATION);
169 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
170 return RADEON_READ(R600_MC_VM_FB_LOCATION);
171 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
172 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
173 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
174 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
175 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
176 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
177 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
178 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
179 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
181 return RADEON_READ(RADEON_MC_FB_LOCATION);
184 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
186 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
187 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
188 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
189 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
190 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
191 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
192 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
193 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
194 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
195 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
196 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
197 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
198 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
200 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
203 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
205 /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
206 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
207 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
208 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
209 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
210 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
211 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
212 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
213 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
214 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
215 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
216 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
217 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
218 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
219 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
220 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
222 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
225 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
227 u32 agp_base_hi = upper_32_bits(agp_base);
228 u32 agp_base_lo = agp_base & 0xffffffff;
229 u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
231 /* R6xx/R7xx must be aligned to a 4MB boundry */
232 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
233 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
234 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
235 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
236 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
237 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
238 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
239 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
240 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
241 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
242 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
243 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
244 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
245 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
246 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
247 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
248 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
249 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
250 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
251 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
252 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
254 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
255 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
256 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
260 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
263 /* Turn on bus mastering */
264 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
265 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
266 /* rs600/rs690/rs740 */
267 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
268 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
269 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
270 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
271 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
272 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
273 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
274 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
275 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
276 } /* PCIE cards appears to not need this */
279 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
281 drm_radeon_private_t *dev_priv = dev->dev_private;
283 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
284 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
287 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
289 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
290 return RADEON_READ(RADEON_PCIE_DATA);
293 #if RADEON_FIFO_DEBUG
294 static void radeon_status(drm_radeon_private_t * dev_priv)
296 printk("%s:\n", __func__);
297 printk("RBBM_STATUS = 0x%08x\n",
298 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
299 printk("CP_RB_RTPR = 0x%08x\n",
300 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
301 printk("CP_RB_WTPR = 0x%08x\n",
302 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
303 printk("AIC_CNTL = 0x%08x\n",
304 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
305 printk("AIC_STAT = 0x%08x\n",
306 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
307 printk("AIC_PT_BASE = 0x%08x\n",
308 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
309 printk("TLB_ADDR = 0x%08x\n",
310 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
311 printk("TLB_DATA = 0x%08x\n",
312 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
316 /* ================================================================
317 * Engine, FIFO control
320 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
325 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
327 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
328 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
329 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
330 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
332 for (i = 0; i < dev_priv->usec_timeout; i++) {
333 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
334 & RADEON_RB3D_DC_BUSY)) {
340 /* don't flush or purge cache here or lockup */
344 #if RADEON_FIFO_DEBUG
345 DRM_ERROR("failed!\n");
346 radeon_status(dev_priv);
351 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
355 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
357 for (i = 0; i < dev_priv->usec_timeout; i++) {
358 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
359 & RADEON_RBBM_FIFOCNT_MASK);
360 if (slots >= entries)
364 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
365 RADEON_READ(RADEON_RBBM_STATUS),
366 RADEON_READ(R300_VAP_CNTL_STATUS));
368 #if RADEON_FIFO_DEBUG
369 DRM_ERROR("failed!\n");
370 radeon_status(dev_priv);
375 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
379 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
381 ret = radeon_do_wait_for_fifo(dev_priv, 64);
385 for (i = 0; i < dev_priv->usec_timeout; i++) {
386 if (!(RADEON_READ(RADEON_RBBM_STATUS)
387 & RADEON_RBBM_ACTIVE)) {
388 radeon_do_pixcache_flush(dev_priv);
393 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
394 RADEON_READ(RADEON_RBBM_STATUS),
395 RADEON_READ(R300_VAP_CNTL_STATUS));
397 #if RADEON_FIFO_DEBUG
398 DRM_ERROR("failed!\n");
399 radeon_status(dev_priv);
404 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
406 uint32_t gb_tile_config, gb_pipe_sel = 0;
408 /* RS4xx/RS6xx/R4xx/R5xx */
409 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
410 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
411 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
414 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
415 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
416 dev_priv->num_gb_pipes = 2;
419 dev_priv->num_gb_pipes = 1;
422 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
424 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
426 switch (dev_priv->num_gb_pipes) {
427 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
428 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
429 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
431 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
434 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
435 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
436 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
438 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
439 radeon_do_wait_for_idle(dev_priv);
440 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
441 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
442 R300_DC_AUTOFLUSH_ENABLE |
443 R300_DC_DC_DISABLE_IGNORE_PE));
448 /* ================================================================
449 * CP control, initialization
452 /* Load the microcode for the CP */
453 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
460 radeon_do_wait_for_idle(dev_priv);
462 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
463 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
469 DRM_INFO("Loading R100 Microcode\n");
470 cp = R100_cp_microcode;
476 DRM_INFO("Loading R200 Microcode\n");
477 cp = R200_cp_microcode;
485 DRM_INFO("Loading R300 Microcode\n");
486 cp = R300_cp_microcode;
491 DRM_INFO("Loading R400 Microcode\n");
492 cp = R420_cp_microcode;
496 DRM_INFO("Loading RS690/RS740 Microcode\n");
497 cp = RS690_cp_microcode;
500 DRM_INFO("Loading RS600 Microcode\n");
501 cp = RS600_cp_microcode;
509 DRM_INFO("Loading R500 Microcode\n");
510 cp = R520_cp_microcode;
516 for (i = 0; i != 256; i++) {
517 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, cp[i][1]);
518 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, cp[i][0]);
522 /* Flush any pending commands to the CP. This should only be used just
523 * prior to a wait for idle, as it informs the engine that the command
526 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
532 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
533 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
537 /* Wait for the CP to go idle.
539 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
546 RADEON_PURGE_CACHE();
547 RADEON_PURGE_ZCACHE();
548 RADEON_WAIT_UNTIL_IDLE();
553 return radeon_do_wait_for_idle(dev_priv);
556 /* Start the Command Processor.
558 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
563 radeon_do_wait_for_idle(dev_priv);
565 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
567 dev_priv->cp_running = 1;
570 /* isync can only be written through cp on r5xx write it here */
571 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
572 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
573 RADEON_ISYNC_ANY3D_IDLE2D |
574 RADEON_ISYNC_WAIT_IDLEGUI |
575 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
576 RADEON_PURGE_CACHE();
577 RADEON_PURGE_ZCACHE();
578 RADEON_WAIT_UNTIL_IDLE();
582 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
585 /* Reset the Command Processor. This will not flush any pending
586 * commands, so you must wait for the CP command stream to complete
587 * before calling this routine.
589 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
594 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
595 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
596 SET_RING_HEAD(dev_priv, cur_read_ptr);
597 dev_priv->ring.tail = cur_read_ptr;
600 /* Stop the Command Processor. This will not flush any pending
601 * commands, so you must flush the command stream and wait for the CP
602 * to go idle before calling this routine.
604 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
608 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
610 dev_priv->cp_running = 0;
613 /* Reset the engine. This will stop the CP if it is running.
615 static int radeon_do_engine_reset(struct drm_device * dev)
617 drm_radeon_private_t *dev_priv = dev->dev_private;
618 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
621 radeon_do_pixcache_flush(dev_priv);
623 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
624 /* may need something similar for newer chips */
625 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
626 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
628 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
629 RADEON_FORCEON_MCLKA |
630 RADEON_FORCEON_MCLKB |
631 RADEON_FORCEON_YCLKA |
632 RADEON_FORCEON_YCLKB |
634 RADEON_FORCEON_AIC));
637 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
639 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
640 RADEON_SOFT_RESET_CP |
641 RADEON_SOFT_RESET_HI |
642 RADEON_SOFT_RESET_SE |
643 RADEON_SOFT_RESET_RE |
644 RADEON_SOFT_RESET_PP |
645 RADEON_SOFT_RESET_E2 |
646 RADEON_SOFT_RESET_RB));
647 RADEON_READ(RADEON_RBBM_SOFT_RESET);
648 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
649 ~(RADEON_SOFT_RESET_CP |
650 RADEON_SOFT_RESET_HI |
651 RADEON_SOFT_RESET_SE |
652 RADEON_SOFT_RESET_RE |
653 RADEON_SOFT_RESET_PP |
654 RADEON_SOFT_RESET_E2 |
655 RADEON_SOFT_RESET_RB)));
656 RADEON_READ(RADEON_RBBM_SOFT_RESET);
658 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
659 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
660 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
661 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
664 /* setup the raster pipes */
665 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
666 radeon_init_pipes(dev_priv);
668 /* Reset the CP ring */
669 radeon_do_cp_reset(dev_priv);
671 /* The CP is no longer running after an engine reset */
672 dev_priv->cp_running = 0;
674 /* Reset any pending vertex, indirect buffers */
675 radeon_freelist_reset(dev);
680 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
681 drm_radeon_private_t *dev_priv,
682 struct drm_file *file_priv)
684 u32 ring_start, cur_read_ptr;
686 /* Initialize the memory controller. With new memory map, the fb location
687 * is not changed, it should have been properly initialized already. Part
688 * of the problem is that the code below is bogus, assuming the GART is
689 * always appended to the fb which is not necessarily the case
691 if (!dev_priv->new_memmap)
692 radeon_write_fb_location(dev_priv,
693 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
694 | (dev_priv->fb_location >> 16));
697 if (dev_priv->flags & RADEON_IS_AGP) {
698 radeon_write_agp_base(dev_priv, dev->agp->base);
700 radeon_write_agp_location(dev_priv,
701 (((dev_priv->gart_vm_start - 1 +
702 dev_priv->gart_size) & 0xffff0000) |
703 (dev_priv->gart_vm_start >> 16)));
705 ring_start = (dev_priv->cp_ring->offset
707 + dev_priv->gart_vm_start);
710 ring_start = (dev_priv->cp_ring->offset
711 - (unsigned long)dev->sg->virtual
712 + dev_priv->gart_vm_start);
714 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
716 /* Set the write pointer delay */
717 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
719 /* Initialize the ring buffer's read and write pointers */
720 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
721 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
722 SET_RING_HEAD(dev_priv, cur_read_ptr);
723 dev_priv->ring.tail = cur_read_ptr;
726 if (dev_priv->flags & RADEON_IS_AGP) {
727 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
728 dev_priv->ring_rptr->offset
729 - dev->agp->base + dev_priv->gart_vm_start);
733 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
734 dev_priv->ring_rptr->offset
735 - ((unsigned long) dev->sg->virtual)
736 + dev_priv->gart_vm_start);
739 /* Set ring buffer size */
741 RADEON_WRITE(RADEON_CP_RB_CNTL,
742 RADEON_BUF_SWAP_32BIT |
743 (dev_priv->ring.fetch_size_l2ow << 18) |
744 (dev_priv->ring.rptr_update_l2qw << 8) |
745 dev_priv->ring.size_l2qw);
747 RADEON_WRITE(RADEON_CP_RB_CNTL,
748 (dev_priv->ring.fetch_size_l2ow << 18) |
749 (dev_priv->ring.rptr_update_l2qw << 8) |
750 dev_priv->ring.size_l2qw);
754 /* Initialize the scratch register pointer. This will cause
755 * the scratch register values to be written out to memory
756 * whenever they are updated.
758 * We simply put this behind the ring read pointer, this works
759 * with PCI GART as well as (whatever kind of) AGP GART
761 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
762 + RADEON_SCRATCH_REG_OFFSET);
764 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
766 radeon_enable_bm(dev_priv);
768 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
769 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
771 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
772 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
774 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
775 RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
777 /* reset sarea copies of these */
778 if (dev_priv->sarea_priv) {
779 dev_priv->sarea_priv->last_frame = 0;
780 dev_priv->sarea_priv->last_dispatch = 0;
781 dev_priv->sarea_priv->last_clear = 0;
784 radeon_do_wait_for_idle(dev_priv);
786 /* Sync everything up */
787 RADEON_WRITE(RADEON_ISYNC_CNTL,
788 (RADEON_ISYNC_ANY2D_IDLE3D |
789 RADEON_ISYNC_ANY3D_IDLE2D |
790 RADEON_ISYNC_WAIT_IDLEGUI |
791 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
795 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
799 /* Start with assuming that writeback doesn't work */
800 dev_priv->writeback_works = 0;
802 /* Writeback doesn't seem to work everywhere, test it here and possibly
803 * enable it if it appears to work
805 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
807 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
809 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
812 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
813 if (val == 0xdeadbeef)
818 if (tmp < dev_priv->usec_timeout) {
819 dev_priv->writeback_works = 1;
820 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
822 dev_priv->writeback_works = 0;
823 DRM_INFO("writeback test failed\n");
825 if (radeon_no_wb == 1) {
826 dev_priv->writeback_works = 0;
827 DRM_INFO("writeback forced off\n");
830 if (!dev_priv->writeback_works) {
831 /* Disable writeback to avoid unnecessary bus master transfer */
832 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
833 RADEON_RB_NO_UPDATE);
834 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
838 /* Enable or disable IGP GART on the chip */
839 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
844 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
845 dev_priv->gart_vm_start,
846 (long)dev_priv->gart_info.bus_addr,
847 dev_priv->gart_size);
849 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
850 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
851 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
852 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
853 RS690_BLOCK_GFX_D3_EN));
855 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
857 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
858 RS480_VA_SIZE_32MB));
860 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
861 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
866 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
867 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
868 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
870 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
871 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
872 RS480_REQ_TYPE_SNOOP_DIS));
874 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
876 dev_priv->gart_size = 32*1024*1024;
877 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
878 0xffff0000) | (dev_priv->gart_vm_start >> 16));
880 radeon_write_agp_location(dev_priv, temp);
882 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
883 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
884 RS480_VA_SIZE_32MB));
887 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
888 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
893 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
894 RS480_GART_CACHE_INVALIDATE);
897 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
898 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
903 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
905 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
909 /* Enable or disable IGP GART on the chip */
910 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
916 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
917 dev_priv->gart_vm_start,
918 (long)dev_priv->gart_info.bus_addr,
919 dev_priv->gart_size);
921 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
922 RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
924 for (i = 0; i < 19; i++)
925 IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
926 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
927 RS600_SYSTEM_ACCESS_MODE_IN_SYS |
928 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
929 RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
930 RS600_ENABLE_FRAGMENT_PROCESSING |
931 RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
933 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
934 RS600_PAGE_TABLE_TYPE_FLAT));
936 /* disable all other contexts */
937 for (i = 1; i < 8; i++)
938 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
940 /* setup the page table aperture */
941 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
942 dev_priv->gart_info.bus_addr);
943 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
944 dev_priv->gart_vm_start);
945 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
946 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
947 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
949 /* setup the system aperture */
950 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
951 dev_priv->gart_vm_start);
952 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
953 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
955 /* enable page tables */
956 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
957 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
959 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
960 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
962 /* invalidate the cache */
963 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
965 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
966 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
967 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
969 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
970 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
971 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
973 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
974 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
975 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
978 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
979 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
980 temp &= ~RS600_ENABLE_PAGE_TABLES;
981 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
985 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
987 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
990 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
991 dev_priv->gart_vm_start,
992 (long)dev_priv->gart_info.bus_addr,
993 dev_priv->gart_size);
994 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
995 dev_priv->gart_vm_start);
996 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
997 dev_priv->gart_info.bus_addr);
998 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
999 dev_priv->gart_vm_start);
1000 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1001 dev_priv->gart_vm_start +
1002 dev_priv->gart_size - 1);
1004 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1006 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1007 RADEON_PCIE_TX_GART_EN);
1009 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1010 tmp & ~RADEON_PCIE_TX_GART_EN);
1014 /* Enable or disable PCI GART on the chip */
1015 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1019 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1020 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1021 (dev_priv->flags & RADEON_IS_IGPGART)) {
1022 radeon_set_igpgart(dev_priv, on);
1026 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1027 rs600_set_igpgart(dev_priv, on);
1031 if (dev_priv->flags & RADEON_IS_PCIE) {
1032 radeon_set_pciegart(dev_priv, on);
1036 tmp = RADEON_READ(RADEON_AIC_CNTL);
1039 RADEON_WRITE(RADEON_AIC_CNTL,
1040 tmp | RADEON_PCIGART_TRANSLATE_EN);
1042 /* set PCI GART page-table base address
1044 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1046 /* set address range for PCI address translate
1048 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1049 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1050 + dev_priv->gart_size - 1);
1052 /* Turn off AGP aperture -- is this required for PCI GART?
1054 radeon_write_agp_location(dev_priv, 0xffffffc0);
1055 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1057 RADEON_WRITE(RADEON_AIC_CNTL,
1058 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1062 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1064 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1065 struct radeon_virt_surface *vp;
1068 for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1069 if (!dev_priv->virt_surfaces[i].file_priv ||
1070 dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1073 if (i >= 2 * RADEON_MAX_SURFACES)
1075 vp = &dev_priv->virt_surfaces[i];
1077 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1078 struct radeon_surface *sp = &dev_priv->surfaces[i];
1082 vp->surface_index = i;
1083 vp->lower = gart_info->bus_addr;
1084 vp->upper = vp->lower + gart_info->table_size;
1086 vp->file_priv = PCIGART_FILE_PRIV;
1089 sp->lower = vp->lower;
1090 sp->upper = vp->upper;
1093 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1094 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1095 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1102 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1103 struct drm_file *file_priv)
1105 drm_radeon_private_t *dev_priv = dev->dev_private;
1109 /* if we require new memory map but we don't have it fail */
1110 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1111 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1112 radeon_do_cleanup_cp(dev);
1116 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1117 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1118 dev_priv->flags &= ~RADEON_IS_AGP;
1119 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1121 DRM_DEBUG("Restoring AGP flag\n");
1122 dev_priv->flags |= RADEON_IS_AGP;
1125 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1126 DRM_ERROR("PCI GART memory not allocated!\n");
1127 radeon_do_cleanup_cp(dev);
1131 dev_priv->usec_timeout = init->usec_timeout;
1132 if (dev_priv->usec_timeout < 1 ||
1133 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1134 DRM_DEBUG("TIMEOUT problem!\n");
1135 radeon_do_cleanup_cp(dev);
1139 /* Enable vblank on CRTC1 for older X servers
1141 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1143 switch(init->func) {
1144 case RADEON_INIT_R200_CP:
1145 dev_priv->microcode_version = UCODE_R200;
1147 case RADEON_INIT_R300_CP:
1148 dev_priv->microcode_version = UCODE_R300;
1151 dev_priv->microcode_version = UCODE_R100;
1154 dev_priv->do_boxes = 0;
1155 dev_priv->cp_mode = init->cp_mode;
1157 /* We don't support anything other than bus-mastering ring mode,
1158 * but the ring can be in either AGP or PCI space for the ring
1161 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1162 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1163 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1164 radeon_do_cleanup_cp(dev);
1168 switch (init->fb_bpp) {
1170 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1174 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1177 dev_priv->front_offset = init->front_offset;
1178 dev_priv->front_pitch = init->front_pitch;
1179 dev_priv->back_offset = init->back_offset;
1180 dev_priv->back_pitch = init->back_pitch;
1182 switch (init->depth_bpp) {
1184 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1188 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1191 dev_priv->depth_offset = init->depth_offset;
1192 dev_priv->depth_pitch = init->depth_pitch;
1194 /* Hardware state for depth clears. Remove this if/when we no
1195 * longer clear the depth buffer with a 3D rectangle. Hard-code
1196 * all values to prevent unwanted 3D state from slipping through
1197 * and screwing with the clear operation.
1199 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1200 (dev_priv->color_fmt << 10) |
1201 (dev_priv->microcode_version ==
1202 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1204 dev_priv->depth_clear.rb3d_zstencilcntl =
1205 (dev_priv->depth_fmt |
1206 RADEON_Z_TEST_ALWAYS |
1207 RADEON_STENCIL_TEST_ALWAYS |
1208 RADEON_STENCIL_S_FAIL_REPLACE |
1209 RADEON_STENCIL_ZPASS_REPLACE |
1210 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1212 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1213 RADEON_BFACE_SOLID |
1214 RADEON_FFACE_SOLID |
1215 RADEON_FLAT_SHADE_VTX_LAST |
1216 RADEON_DIFFUSE_SHADE_FLAT |
1217 RADEON_ALPHA_SHADE_FLAT |
1218 RADEON_SPECULAR_SHADE_FLAT |
1219 RADEON_FOG_SHADE_FLAT |
1220 RADEON_VTX_PIX_CENTER_OGL |
1221 RADEON_ROUND_MODE_TRUNC |
1222 RADEON_ROUND_PREC_8TH_PIX);
1225 dev_priv->ring_offset = init->ring_offset;
1226 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1227 dev_priv->buffers_offset = init->buffers_offset;
1228 dev_priv->gart_textures_offset = init->gart_textures_offset;
1230 dev_priv->sarea = drm_getsarea(dev);
1231 if (!dev_priv->sarea) {
1232 DRM_ERROR("could not find sarea!\n");
1233 radeon_do_cleanup_cp(dev);
1237 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1238 if (!dev_priv->cp_ring) {
1239 DRM_ERROR("could not find cp ring region!\n");
1240 radeon_do_cleanup_cp(dev);
1243 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1244 if (!dev_priv->ring_rptr) {
1245 DRM_ERROR("could not find ring read pointer!\n");
1246 radeon_do_cleanup_cp(dev);
1249 dev->agp_buffer_token = init->buffers_offset;
1250 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1251 if (!dev->agp_buffer_map) {
1252 DRM_ERROR("could not find dma buffer region!\n");
1253 radeon_do_cleanup_cp(dev);
1257 if (init->gart_textures_offset) {
1258 dev_priv->gart_textures =
1259 drm_core_findmap(dev, init->gart_textures_offset);
1260 if (!dev_priv->gart_textures) {
1261 DRM_ERROR("could not find GART texture region!\n");
1262 radeon_do_cleanup_cp(dev);
1267 dev_priv->sarea_priv =
1268 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1269 init->sarea_priv_offset);
1272 if (dev_priv->flags & RADEON_IS_AGP) {
1273 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1274 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1275 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1276 if (!dev_priv->cp_ring->handle ||
1277 !dev_priv->ring_rptr->handle ||
1278 !dev->agp_buffer_map->handle) {
1279 DRM_ERROR("could not find ioremap agp regions!\n");
1280 radeon_do_cleanup_cp(dev);
1286 dev_priv->cp_ring->handle =
1287 (void *)(unsigned long)dev_priv->cp_ring->offset;
1288 dev_priv->ring_rptr->handle =
1289 (void *)(unsigned long)dev_priv->ring_rptr->offset;
1290 dev->agp_buffer_map->handle =
1291 (void *)(unsigned long)dev->agp_buffer_map->offset;
1293 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1294 dev_priv->cp_ring->handle);
1295 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1296 dev_priv->ring_rptr->handle);
1297 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1298 dev->agp_buffer_map->handle);
1301 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1303 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1304 - dev_priv->fb_location;
1306 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1307 ((dev_priv->front_offset
1308 + dev_priv->fb_location) >> 10));
1310 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1311 ((dev_priv->back_offset
1312 + dev_priv->fb_location) >> 10));
1314 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1315 ((dev_priv->depth_offset
1316 + dev_priv->fb_location) >> 10));
1318 dev_priv->gart_size = init->gart_size;
1320 /* New let's set the memory map ... */
1321 if (dev_priv->new_memmap) {
1324 DRM_INFO("Setting GART location based on new memory map\n");
1326 /* If using AGP, try to locate the AGP aperture at the same
1327 * location in the card and on the bus, though we have to
1331 if (dev_priv->flags & RADEON_IS_AGP) {
1332 base = dev->agp->base;
1333 /* Check if valid */
1334 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1335 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1336 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1342 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1344 base = dev_priv->fb_location + dev_priv->fb_size;
1345 if (base < dev_priv->fb_location ||
1346 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1347 base = dev_priv->fb_location
1348 - dev_priv->gart_size;
1350 dev_priv->gart_vm_start = base & 0xffc00000u;
1351 if (dev_priv->gart_vm_start != base)
1352 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1353 base, dev_priv->gart_vm_start);
1355 DRM_INFO("Setting GART location based on old memory map\n");
1356 dev_priv->gart_vm_start = dev_priv->fb_location +
1357 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1361 if (dev_priv->flags & RADEON_IS_AGP)
1362 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1364 + dev_priv->gart_vm_start);
1367 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1368 - (unsigned long)dev->sg->virtual
1369 + dev_priv->gart_vm_start);
1371 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1372 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1373 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1374 dev_priv->gart_buffers_offset);
1376 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1377 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1378 + init->ring_size / sizeof(u32));
1379 dev_priv->ring.size = init->ring_size;
1380 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1382 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1383 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1385 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1386 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1387 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1389 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1392 if (dev_priv->flags & RADEON_IS_AGP) {
1393 /* Turn off PCI GART */
1394 radeon_set_pcigart(dev_priv, 0);
1401 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1402 /* if we have an offset set from userspace */
1403 if (dev_priv->pcigart_offset_set) {
1404 dev_priv->gart_info.bus_addr =
1405 dev_priv->pcigart_offset + dev_priv->fb_location;
1406 dev_priv->gart_info.mapping.offset =
1407 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1408 dev_priv->gart_info.mapping.size =
1409 dev_priv->gart_info.table_size;
1411 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1412 dev_priv->gart_info.addr =
1413 dev_priv->gart_info.mapping.handle;
1415 if (dev_priv->flags & RADEON_IS_PCIE)
1416 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1418 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1419 dev_priv->gart_info.gart_table_location =
1422 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1423 dev_priv->gart_info.addr,
1424 dev_priv->pcigart_offset);
1426 if (dev_priv->flags & RADEON_IS_IGPGART)
1427 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1429 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1430 dev_priv->gart_info.gart_table_location =
1432 dev_priv->gart_info.addr = NULL;
1433 dev_priv->gart_info.bus_addr = 0;
1434 if (dev_priv->flags & RADEON_IS_PCIE) {
1436 ("Cannot use PCI Express without GART in FB memory\n");
1437 radeon_do_cleanup_cp(dev);
1442 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1443 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1444 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1445 ret = r600_page_table_init(dev);
1447 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1448 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1451 DRM_ERROR("failed to init PCI GART!\n");
1452 radeon_do_cleanup_cp(dev);
1456 ret = radeon_setup_pcigart_surface(dev_priv);
1458 DRM_ERROR("failed to setup GART surface!\n");
1459 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1460 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1462 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1463 radeon_do_cleanup_cp(dev);
1467 /* Turn on PCI GART */
1468 radeon_set_pcigart(dev_priv, 1);
1471 radeon_cp_load_microcode(dev_priv);
1472 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1474 dev_priv->last_buf = 0;
1476 radeon_do_engine_reset(dev);
1477 radeon_test_writeback(dev_priv);
1482 static int radeon_do_cleanup_cp(struct drm_device * dev)
1484 drm_radeon_private_t *dev_priv = dev->dev_private;
1487 /* Make sure interrupts are disabled here because the uninstall ioctl
1488 * may not have been called from userspace and after dev_private
1489 * is freed, it's too late.
1491 if (dev->irq_enabled)
1492 drm_irq_uninstall(dev);
1495 if (dev_priv->flags & RADEON_IS_AGP) {
1496 if (dev_priv->cp_ring != NULL) {
1497 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1498 dev_priv->cp_ring = NULL;
1500 if (dev_priv->ring_rptr != NULL) {
1501 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1502 dev_priv->ring_rptr = NULL;
1504 if (dev->agp_buffer_map != NULL) {
1505 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1506 dev->agp_buffer_map = NULL;
1512 if (dev_priv->gart_info.bus_addr) {
1513 /* Turn off PCI GART */
1514 radeon_set_pcigart(dev_priv, 0);
1515 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1516 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1518 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1519 DRM_ERROR("failed to cleanup PCI GART!\n");
1523 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1525 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1526 dev_priv->gart_info.addr = 0;
1529 /* only clear to the start of flags */
1530 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1535 /* This code will reinit the Radeon CP hardware after a resume from disc.
1536 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1537 * here we make sure that all Radeon hardware initialisation is re-done without
1538 * affecting running applications.
1540 * Charl P. Botha <http://cpbotha.net>
1542 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1544 drm_radeon_private_t *dev_priv = dev->dev_private;
1547 DRM_ERROR("Called with no initialization\n");
1551 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1554 if (dev_priv->flags & RADEON_IS_AGP) {
1555 /* Turn off PCI GART */
1556 radeon_set_pcigart(dev_priv, 0);
1560 /* Turn on PCI GART */
1561 radeon_set_pcigart(dev_priv, 1);
1564 radeon_cp_load_microcode(dev_priv);
1565 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1567 radeon_do_engine_reset(dev);
1568 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1570 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1575 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1577 drm_radeon_private_t *dev_priv = dev->dev_private;
1578 drm_radeon_init_t *init = data;
1580 LOCK_TEST_WITH_RETURN(dev, file_priv);
1582 if (init->func == RADEON_INIT_R300_CP)
1583 r300_init_reg_flags(dev);
1585 switch (init->func) {
1586 case RADEON_INIT_CP:
1587 case RADEON_INIT_R200_CP:
1588 case RADEON_INIT_R300_CP:
1589 return radeon_do_init_cp(dev, init, file_priv);
1590 case RADEON_INIT_R600_CP:
1591 return r600_do_init_cp(dev, init, file_priv);
1592 case RADEON_CLEANUP_CP:
1593 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1594 return r600_do_cleanup_cp(dev);
1596 return radeon_do_cleanup_cp(dev);
1602 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1604 drm_radeon_private_t *dev_priv = dev->dev_private;
1607 LOCK_TEST_WITH_RETURN(dev, file_priv);
1609 if (dev_priv->cp_running) {
1610 DRM_DEBUG("while CP running\n");
1613 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1614 DRM_DEBUG("called with bogus CP mode (%d)\n",
1619 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1620 r600_do_cp_start(dev_priv);
1622 radeon_do_cp_start(dev_priv);
1627 /* Stop the CP. The engine must have been idled before calling this
1630 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1632 drm_radeon_private_t *dev_priv = dev->dev_private;
1633 drm_radeon_cp_stop_t *stop = data;
1637 LOCK_TEST_WITH_RETURN(dev, file_priv);
1639 if (!dev_priv->cp_running)
1642 /* Flush any pending CP commands. This ensures any outstanding
1643 * commands are exectuted by the engine before we turn it off.
1646 radeon_do_cp_flush(dev_priv);
1649 /* If we fail to make the engine go idle, we return an error
1650 * code so that the DRM ioctl wrapper can try again.
1653 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1654 ret = r600_do_cp_idle(dev_priv);
1656 ret = radeon_do_cp_idle(dev_priv);
1661 /* Finally, we can turn off the CP. If the engine isn't idle,
1662 * we will get some dropped triangles as they won't be fully
1663 * rendered before the CP is shut down.
1665 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1666 r600_do_cp_stop(dev_priv);
1668 radeon_do_cp_stop(dev_priv);
1670 /* Reset the engine */
1671 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1672 r600_do_engine_reset(dev);
1674 radeon_do_engine_reset(dev);
1679 void radeon_do_release(struct drm_device * dev)
1681 drm_radeon_private_t *dev_priv = dev->dev_private;
1685 if (dev_priv->cp_running) {
1687 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1688 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1689 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1691 tsleep_interlock((void *)&dev->lock.lock_queue);
1693 ret = tsleep((void *)&dev->lock.lock_queue, PCATCH,
1699 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1700 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1702 tsleep_interlock((void *)&dev->lock.lock_queue);
1704 ret = tsleep((void *)&dev->lock.lock_queue, PCATCH,
1710 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1711 r600_do_cp_stop(dev_priv);
1712 r600_do_engine_reset(dev);
1714 radeon_do_cp_stop(dev_priv);
1715 radeon_do_engine_reset(dev);
1719 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1720 /* Disable *all* interrupts */
1721 if (dev_priv->mmio) /* remove this after permanent addmaps */
1722 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1724 if (dev_priv->mmio) { /* remove all surfaces */
1725 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1726 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1727 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1729 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1735 /* Free memory heap structures */
1736 radeon_mem_takedown(&(dev_priv->gart_heap));
1737 radeon_mem_takedown(&(dev_priv->fb_heap));
1739 /* deallocate kernel resources */
1740 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1741 r600_do_cleanup_cp(dev);
1743 radeon_do_cleanup_cp(dev);
1747 /* Just reset the CP ring. Called as part of an X Server engine reset.
1749 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1751 drm_radeon_private_t *dev_priv = dev->dev_private;
1754 LOCK_TEST_WITH_RETURN(dev, file_priv);
1757 DRM_DEBUG("called before init done\n");
1761 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1762 r600_do_cp_reset(dev_priv);
1764 radeon_do_cp_reset(dev_priv);
1766 /* The CP is no longer running after an engine reset */
1767 dev_priv->cp_running = 0;
1772 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1774 drm_radeon_private_t *dev_priv = dev->dev_private;
1777 LOCK_TEST_WITH_RETURN(dev, file_priv);
1779 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1780 return r600_do_cp_idle(dev_priv);
1782 return radeon_do_cp_idle(dev_priv);
1785 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1787 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1789 drm_radeon_private_t *dev_priv = dev->dev_private;
1792 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1793 return r600_do_resume_cp(dev, file_priv);
1795 return radeon_do_resume_cp(dev, file_priv);
1798 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1800 drm_radeon_private_t *dev_priv = dev->dev_private;
1803 LOCK_TEST_WITH_RETURN(dev, file_priv);
1805 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1806 return r600_do_engine_reset(dev);
1808 return radeon_do_engine_reset(dev);
1811 /* ================================================================
1815 /* KW: Deprecated to say the least:
1817 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1822 /* ================================================================
1823 * Freelist management
1826 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1827 * bufs until freelist code is used. Note this hides a problem with
1828 * the scratch register * (used to keep track of last buffer
1829 * completed) being written to before * the last buffer has actually
1830 * completed rendering.
1832 * KW: It's also a good way to find free buffers quickly.
1834 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1835 * sleep. However, bugs in older versions of radeon_accel.c mean that
1836 * we essentially have to do this, else old clients will break.
1838 * However, it does leave open a potential deadlock where all the
1839 * buffers are held by other clients, which can't release them because
1840 * they can't get the lock.
1843 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1845 struct drm_device_dma *dma = dev->dma;
1846 drm_radeon_private_t *dev_priv = dev->dev_private;
1847 drm_radeon_buf_priv_t *buf_priv;
1848 struct drm_buf *buf;
1852 if (++dev_priv->last_buf >= dma->buf_count)
1853 dev_priv->last_buf = 0;
1855 start = dev_priv->last_buf;
1857 for (t = 0; t < dev_priv->usec_timeout; t++) {
1858 u32 done_age = GET_SCRATCH(dev_priv, 1);
1859 DRM_DEBUG("done_age = %d\n", done_age);
1860 for (i = start; i < dma->buf_count; i++) {
1861 buf = dma->buflist[i];
1862 buf_priv = buf->dev_private;
1863 if (buf->file_priv == NULL || (buf->pending &&
1866 dev_priv->stats.requested_bufs++;
1875 dev_priv->stats.freelist_loops++;
1879 DRM_DEBUG("returning NULL!\n");
1884 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1886 struct drm_device_dma *dma = dev->dma;
1887 drm_radeon_private_t *dev_priv = dev->dev_private;
1888 drm_radeon_buf_priv_t *buf_priv;
1889 struct drm_buf *buf;
1894 done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
1895 if (++dev_priv->last_buf >= dma->buf_count)
1896 dev_priv->last_buf = 0;
1898 start = dev_priv->last_buf;
1899 dev_priv->stats.freelist_loops++;
1901 for (t = 0; t < 2; t++) {
1902 for (i = start; i < dma->buf_count; i++) {
1903 buf = dma->buflist[i];
1904 buf_priv = buf->dev_private;
1905 if (buf->file_priv == 0 || (buf->pending &&
1908 dev_priv->stats.requested_bufs++;
1920 void radeon_freelist_reset(struct drm_device * dev)
1922 struct drm_device_dma *dma = dev->dma;
1923 drm_radeon_private_t *dev_priv = dev->dev_private;
1926 dev_priv->last_buf = 0;
1927 for (i = 0; i < dma->buf_count; i++) {
1928 struct drm_buf *buf = dma->buflist[i];
1929 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1934 /* ================================================================
1935 * CP command submission
1938 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1940 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1942 u32 last_head = GET_RING_HEAD(dev_priv);
1944 for (i = 0; i < dev_priv->usec_timeout; i++) {
1945 u32 head = GET_RING_HEAD(dev_priv);
1947 ring->space = (head - ring->tail) * sizeof(u32);
1948 if (ring->space <= 0)
1949 ring->space += ring->size;
1950 if (ring->space > n)
1953 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1955 if (head != last_head)
1962 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1963 #if RADEON_FIFO_DEBUG
1964 radeon_status(dev_priv);
1965 DRM_ERROR("failed!\n");
1970 static int radeon_cp_get_buffers(struct drm_device *dev,
1971 struct drm_file *file_priv,
1975 struct drm_buf *buf;
1977 for (i = d->granted_count; i < d->request_count; i++) {
1978 buf = radeon_freelist_get(dev);
1980 return -EBUSY; /* NOTE: broken client */
1982 buf->file_priv = file_priv;
1984 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1987 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1988 sizeof(buf->total)))
1996 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1998 struct drm_device_dma *dma = dev->dma;
2000 struct drm_dma *d = data;
2002 LOCK_TEST_WITH_RETURN(dev, file_priv);
2004 /* Please don't send us buffers.
2006 if (d->send_count != 0) {
2007 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2008 DRM_CURRENTPID, d->send_count);
2012 /* We'll send you buffers.
2014 if (d->request_count < 0 || d->request_count > dma->buf_count) {
2015 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2016 DRM_CURRENTPID, d->request_count, dma->buf_count);
2020 d->granted_count = 0;
2022 if (d->request_count) {
2023 ret = radeon_cp_get_buffers(dev, file_priv, d);
2029 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2031 drm_radeon_private_t *dev_priv;
2034 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2035 if (dev_priv == NULL)
2038 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2039 dev->dev_private = (void *)dev_priv;
2040 dev_priv->flags = flags;
2042 switch (flags & RADEON_FAMILY_MASK) {
2055 dev_priv->flags |= RADEON_HAS_HIERZ;
2058 /* all other chips have no hierarchical z buffer */
2062 if (drm_device_is_agp(dev))
2063 dev_priv->flags |= RADEON_IS_AGP;
2064 else if (drm_device_is_pcie(dev))
2065 dev_priv->flags |= RADEON_IS_PCIE;
2067 dev_priv->flags |= RADEON_IS_PCI;
2069 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2070 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2071 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2075 ret = drm_vblank_init(dev, 2);
2077 radeon_driver_unload(dev);
2081 DRM_DEBUG("%s card detected\n",
2082 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2086 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2087 * have to find them.
2089 int radeon_driver_firstopen(struct drm_device *dev)
2092 drm_local_map_t *map;
2093 drm_radeon_private_t *dev_priv = dev->dev_private;
2095 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2097 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2098 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2099 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2100 _DRM_WRITE_COMBINING, &map);
2107 int radeon_driver_unload(struct drm_device *dev)
2109 drm_radeon_private_t *dev_priv = dev->dev_private;
2113 drm_rmmap(dev, dev_priv->mmio);
2115 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2117 dev->dev_private = NULL;
2121 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2127 /* check if the ring is padded out to 16-dword alignment */
2129 tail_aligned = dev_priv->ring.tail & 0xf;
2131 int num_p2 = 16 - tail_aligned;
2133 ring = dev_priv->ring.start;
2134 /* pad with some CP_PACKET2 */
2135 for (i = 0; i < num_p2; i++)
2136 ring[dev_priv->ring.tail + i] = CP_PACKET2();
2138 dev_priv->ring.tail += i;
2140 dev_priv->ring.space -= num_p2 * sizeof(u32);
2143 dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2145 DRM_MEMORYBARRIER();
2146 GET_RING_HEAD( dev_priv );
2148 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2149 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2150 /* read from PCI bus to ensure correct posting */
2151 RADEON_READ(R600_CP_RB_RPTR);
2153 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2154 /* read from PCI bus to ensure correct posting */
2155 RADEON_READ(RADEON_CP_RB_RPTR);