2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91
34 * $FreeBSD: src/sys/dev/ic/ns16550.h,v 1.14 2003/09/16 14:21:17 bde Exp $
35 * $DragonFly: src/sys/dev/serial/ic_layer/ns16550.h,v 1.4 2005/09/01 00:18:24 swildner Exp $
39 * NS8250... UART registers.
42 /* 8250 registers #[0-6]. */
44 #define com_data 0 /* data register (R/W) */
45 #define com_thr com_data /* transmitter holding register (W) */
46 #define com_rhr com_data /* receiver holding register (R) */
48 #define com_ier 1 /* interrupt enable register (W) */
49 #define IER_ERXRDY 0x1
50 #define IER_ETXRDY 0x2
54 #define com_iir 2 /* interrupt identification register (R) */
55 #define com_isr com_iir /* interrupt status register (R) */
57 #define IIR_RXTOUT 0xc
61 #define IIR_NOPEND 0x1
63 #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
65 #define com_lcr 3 /* line control register (R/W) */
66 #define com_lctl com_lcr
67 #define com_cfcr com_lcr /* character format control register (R/W) */
69 #define CFCR_DLAB LCR_DLAB
70 #define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */
71 #define CFCR_EFR_ENABLE LCR_EFR_ENABLE
72 #define CFCR_SBREAK 0x40
73 #define CFCR_PZERO 0x30
74 #define CFCR_PONE 0x20
75 #define CFCR_PEVEN 0x10
76 #define CFCR_PODD 0x00
77 #define CFCR_PENAB 0x08
78 #define CFCR_STOPB 0x04
79 #define CFCR_8BITS 0x03
80 #define CFCR_7BITS 0x02
81 #define CFCR_6BITS 0x01
82 #define CFCR_5BITS 0x00
84 #define com_mcr 4 /* modem control register (R/W) */
85 #define MCR_PRESCALE 0x80 /* only available on 16650 up */
86 #define MCR_LOOPBACK 0x10
87 #define MCR_IENABLE 0x08
92 #define com_lsr 5 /* line status register (R/W) */
93 #define LSR_RCV_FIFO 0x80
95 #define LSR_TXRDY 0x20
100 #define LSR_RXRDY 0x01
101 #define LSR_RCV_MASK 0x1f
103 #define com_msr 6 /* modem status register (R/W) */
108 #define MSR_DDCD 0x08
109 #define MSR_TERI 0x04
110 #define MSR_DDSR 0x02
111 #define MSR_DCTS 0x01
113 /* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */
114 #define com_dll 0 /* divisor latch low (R/W) */
115 #define com_dlbl com_dll
116 #define com_dlm 1 /* divisor latch high (R/W) */
117 #define com_dlbh com_dlm
119 /* 16450 register #7. Not multiplexed. */
120 #define com_scr 7 /* scratch register (R/W) */
122 /* 16550 register #2. Not multiplexed. */
123 #define com_fcr 2 /* FIFO control register (W) */
124 #define com_fifo com_fcr
125 #define FIFO_ENABLE 0x01
126 #define FIFO_RCV_RST 0x02
127 #define FIFO_XMT_RST 0x04
128 #define FIFO_DMA_MODE 0x08
129 #define FIFO_RX_LOW 0x00
130 #define FIFO_RX_MEDL 0x40
131 #define FIFO_RX_MEDH 0x80
132 #define FIFO_RX_HIGH 0xc0
134 /* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */
136 #define com_efr 2 /* enhanced features register (R/W) */
137 #define EFR_AUTOCTS 0x80
138 #define EFR_AUTORTS 0x40
139 #define EFR_EFE 0x10 /* enhanced functions enable */
141 #define com_xon1 4 /* XON 1 character (R/W) */
142 #define com_xon2 5 /* XON 2 character (R/W) */
143 #define com_xoff1 6 /* XOFF 1 character (R/W) */
144 #define com_xoff2 7 /* XOFF 2 character (R/W) */
146 /* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */
147 #define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */
149 /* 16950 register #3. R/W access enabled by ACR[7]. */
150 #define com_rfl 3 /* receiver fifo level (R) */
153 * 16950 register #4. Access enabled by ACR[7]. Also requires
156 #define com_tfl 4 /* transmitter fifo level (R) */
159 * 16950 register #5. Accessible if !LCR_EFR_ENABLE. Read access also
162 #define com_icr 5 /* index control register (R/W) */
165 * 16950 register #7. It is the same as com_scr except it has a different
166 * abbreviation in the manufacturer's data sheet and it also serves as an
167 * index into the Indexed Control register set.
169 #define com_spr com_scr /* scratch pad (and index) register (R/W) */
172 * 16950 indexed control registers #[0-0x13]. Access is via index in SPR,
173 * data in ICR (if ICR is accessible).
176 #define com_acr 0 /* additional control register (R/W) */
177 #define ACR_ASE 0x80 /* ASR/RFL/TFL enable */
178 #define ACR_ICRE 0x40 /* ICR enable */
179 #define ACR_TLE 0x20 /* TTL/RTL enable */
181 #define com_cpr 1 /* clock prescaler register (R/W) */
182 #define com_tcr 2 /* times clock register (R/W) */
183 #define com_ttl 4 /* transmitter trigger level (R/W) */
184 #define com_rtl 5 /* receiver trigger level (R/W) */