2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $
33 * $DragonFly: src/sys/dev/netif/ste/if_ste.c,v 1.27 2005/06/14 14:19:22 joerg Exp $
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/sockio.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
42 #include <sys/socket.h>
43 #include <sys/thread2.h>
46 #include <net/ifq_var.h>
47 #include <net/if_arp.h>
48 #include <net/ethernet.h>
49 #include <net/if_dl.h>
50 #include <net/if_media.h>
51 #include <net/vlan/if_vlan_var.h>
55 #include <vm/vm.h> /* for vtophys */
56 #include <vm/pmap.h> /* for vtophys */
57 #include <machine/bus_memio.h>
58 #include <machine/bus_pio.h>
59 #include <machine/bus.h>
60 #include <machine/resource.h>
64 #include "../mii_layer/mii.h"
65 #include "../mii_layer/miivar.h"
67 #include <bus/pci/pcireg.h>
68 #include <bus/pci/pcivar.h>
70 /* "controller miibus0" required. See GENERIC if you get errors here. */
71 #include "miibus_if.h"
73 #define STE_USEIOSPACE
75 #include "if_stereg.h"
78 * Various supported device vendors/types and their names.
80 static struct ste_type ste_devs[] = {
81 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" },
82 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" },
86 static int ste_probe (device_t);
87 static int ste_attach (device_t);
88 static int ste_detach (device_t);
89 static void ste_init (void *);
90 static void ste_intr (void *);
91 static void ste_rxeof (struct ste_softc *);
92 static void ste_txeoc (struct ste_softc *);
93 static void ste_txeof (struct ste_softc *);
94 static void ste_stats_update (void *);
95 static void ste_stop (struct ste_softc *);
96 static void ste_reset (struct ste_softc *);
97 static int ste_ioctl (struct ifnet *, u_long, caddr_t,
99 static int ste_encap (struct ste_softc *, struct ste_chain *,
101 static void ste_start (struct ifnet *);
102 static void ste_watchdog (struct ifnet *);
103 static void ste_shutdown (device_t);
104 static int ste_newbuf (struct ste_softc *,
105 struct ste_chain_onefrag *,
107 static int ste_ifmedia_upd (struct ifnet *);
108 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *);
110 static void ste_mii_sync (struct ste_softc *);
111 static void ste_mii_send (struct ste_softc *, u_int32_t, int);
112 static int ste_mii_readreg (struct ste_softc *,
113 struct ste_mii_frame *);
114 static int ste_mii_writereg (struct ste_softc *,
115 struct ste_mii_frame *);
116 static int ste_miibus_readreg (device_t, int, int);
117 static int ste_miibus_writereg (device_t, int, int, int);
118 static void ste_miibus_statchg (device_t);
120 static int ste_eeprom_wait (struct ste_softc *);
121 static int ste_read_eeprom (struct ste_softc *, caddr_t, int,
123 static void ste_wait (struct ste_softc *);
124 static void ste_setmulti (struct ste_softc *);
125 static int ste_init_rx_list (struct ste_softc *);
126 static void ste_init_tx_list (struct ste_softc *);
128 #ifdef STE_USEIOSPACE
129 #define STE_RES SYS_RES_IOPORT
130 #define STE_RID STE_PCI_LOIO
132 #define STE_RES SYS_RES_MEMORY
133 #define STE_RID STE_PCI_LOMEM
136 static device_method_t ste_methods[] = {
137 /* Device interface */
138 DEVMETHOD(device_probe, ste_probe),
139 DEVMETHOD(device_attach, ste_attach),
140 DEVMETHOD(device_detach, ste_detach),
141 DEVMETHOD(device_shutdown, ste_shutdown),
144 DEVMETHOD(bus_print_child, bus_generic_print_child),
145 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
148 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
149 DEVMETHOD(miibus_writereg, ste_miibus_writereg),
150 DEVMETHOD(miibus_statchg, ste_miibus_statchg),
155 static driver_t ste_driver = {
158 sizeof(struct ste_softc)
161 static devclass_t ste_devclass;
163 DECLARE_DUMMY_MODULE(if_ste);
164 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0);
165 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
167 #define STE_SETBIT4(sc, reg, x) \
168 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
170 #define STE_CLRBIT4(sc, reg, x) \
171 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
173 #define STE_SETBIT2(sc, reg, x) \
174 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x)
176 #define STE_CLRBIT2(sc, reg, x) \
177 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x)
179 #define STE_SETBIT1(sc, reg, x) \
180 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)
182 #define STE_CLRBIT1(sc, reg, x) \
183 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)
186 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x)
187 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x)
190 * Sync the PHYs by setting data bit and strobing the clock 32 times.
192 static void ste_mii_sync(sc)
193 struct ste_softc *sc;
197 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA);
199 for (i = 0; i < 32; i++) {
200 MII_SET(STE_PHYCTL_MCLK);
202 MII_CLR(STE_PHYCTL_MCLK);
210 * Clock a series of bits through the MII.
212 static void ste_mii_send(sc, bits, cnt)
213 struct ste_softc *sc;
219 MII_CLR(STE_PHYCTL_MCLK);
221 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
223 MII_SET(STE_PHYCTL_MDATA);
225 MII_CLR(STE_PHYCTL_MDATA);
228 MII_CLR(STE_PHYCTL_MCLK);
230 MII_SET(STE_PHYCTL_MCLK);
235 * Read an PHY register through the MII.
237 static int ste_mii_readreg(sc, frame)
238 struct ste_softc *sc;
239 struct ste_mii_frame *frame;
247 * Set up frame for RX.
249 frame->mii_stdelim = STE_MII_STARTDELIM;
250 frame->mii_opcode = STE_MII_READOP;
251 frame->mii_turnaround = 0;
254 CSR_WRITE_2(sc, STE_PHYCTL, 0);
258 MII_SET(STE_PHYCTL_MDIR);
263 * Send command/address info.
265 ste_mii_send(sc, frame->mii_stdelim, 2);
266 ste_mii_send(sc, frame->mii_opcode, 2);
267 ste_mii_send(sc, frame->mii_phyaddr, 5);
268 ste_mii_send(sc, frame->mii_regaddr, 5);
271 MII_CLR(STE_PHYCTL_MDIR);
274 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA));
276 MII_SET(STE_PHYCTL_MCLK);
280 MII_CLR(STE_PHYCTL_MCLK);
282 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
283 MII_SET(STE_PHYCTL_MCLK);
287 * Now try reading data bits. If the ack failed, we still
288 * need to clock through 16 cycles to keep the PHY(s) in sync.
291 for(i = 0; i < 16; i++) {
292 MII_CLR(STE_PHYCTL_MCLK);
294 MII_SET(STE_PHYCTL_MCLK);
300 for (i = 0x8000; i; i >>= 1) {
301 MII_CLR(STE_PHYCTL_MCLK);
304 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)
305 frame->mii_data |= i;
308 MII_SET(STE_PHYCTL_MCLK);
314 MII_CLR(STE_PHYCTL_MCLK);
316 MII_SET(STE_PHYCTL_MCLK);
327 * Write to a PHY register through the MII.
329 static int ste_mii_writereg(sc, frame)
330 struct ste_softc *sc;
331 struct ste_mii_frame *frame;
337 * Set up frame for TX.
340 frame->mii_stdelim = STE_MII_STARTDELIM;
341 frame->mii_opcode = STE_MII_WRITEOP;
342 frame->mii_turnaround = STE_MII_TURNAROUND;
345 * Turn on data output.
347 MII_SET(STE_PHYCTL_MDIR);
351 ste_mii_send(sc, frame->mii_stdelim, 2);
352 ste_mii_send(sc, frame->mii_opcode, 2);
353 ste_mii_send(sc, frame->mii_phyaddr, 5);
354 ste_mii_send(sc, frame->mii_regaddr, 5);
355 ste_mii_send(sc, frame->mii_turnaround, 2);
356 ste_mii_send(sc, frame->mii_data, 16);
359 MII_SET(STE_PHYCTL_MCLK);
361 MII_CLR(STE_PHYCTL_MCLK);
367 MII_CLR(STE_PHYCTL_MDIR);
374 static int ste_miibus_readreg(dev, phy, reg)
378 struct ste_softc *sc;
379 struct ste_mii_frame frame;
381 sc = device_get_softc(dev);
383 if ( sc->ste_one_phy && phy != 0 )
386 bzero((char *)&frame, sizeof(frame));
388 frame.mii_phyaddr = phy;
389 frame.mii_regaddr = reg;
390 ste_mii_readreg(sc, &frame);
392 return(frame.mii_data);
395 static int ste_miibus_writereg(dev, phy, reg, data)
399 struct ste_softc *sc;
400 struct ste_mii_frame frame;
402 sc = device_get_softc(dev);
403 bzero((char *)&frame, sizeof(frame));
405 frame.mii_phyaddr = phy;
406 frame.mii_regaddr = reg;
407 frame.mii_data = data;
409 ste_mii_writereg(sc, &frame);
414 static void ste_miibus_statchg(dev)
417 struct ste_softc *sc;
418 struct mii_data *mii;
421 sc = device_get_softc(dev);
422 mii = device_get_softc(sc->ste_miibus);
424 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
425 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
427 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
430 STE_SETBIT4(sc, STE_ASICCTL,STE_ASICCTL_RX_RESET |
431 STE_ASICCTL_TX_RESET);
432 for (i = 0; i < STE_TIMEOUT; i++) {
433 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
436 if (i == STE_TIMEOUT)
437 if_printf(&sc->arpcom.ac_if, "rx reset never completed\n");
442 static int ste_ifmedia_upd(ifp)
445 struct ste_softc *sc;
446 struct mii_data *mii;
449 mii = device_get_softc(sc->ste_miibus);
451 if (mii->mii_instance) {
452 struct mii_softc *miisc;
453 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
454 miisc = LIST_NEXT(miisc, mii_list))
455 mii_phy_reset(miisc);
462 static void ste_ifmedia_sts(ifp, ifmr)
464 struct ifmediareq *ifmr;
466 struct ste_softc *sc;
467 struct mii_data *mii;
470 mii = device_get_softc(sc->ste_miibus);
473 ifmr->ifm_active = mii->mii_media_active;
474 ifmr->ifm_status = mii->mii_media_status;
479 static void ste_wait(sc)
480 struct ste_softc *sc;
484 for (i = 0; i < STE_TIMEOUT; i++) {
485 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
489 if (i == STE_TIMEOUT)
490 if_printf(&sc->arpcom.ac_if, "command never completed!\n");
496 * The EEPROM is slow: give it time to come ready after issuing
499 static int ste_eeprom_wait(sc)
500 struct ste_softc *sc;
506 for (i = 0; i < 100; i++) {
507 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
514 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n");
522 * Read a sequence of words from the EEPROM. Note that ethernet address
523 * data is stored in the EEPROM in network byte order.
525 static int ste_read_eeprom(sc, dest, off, cnt, swap)
526 struct ste_softc *sc;
533 u_int16_t word = 0, *ptr;
535 if (ste_eeprom_wait(sc))
538 for (i = 0; i < cnt; i++) {
539 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
540 err = ste_eeprom_wait(sc);
543 word = CSR_READ_2(sc, STE_EEPROM_DATA);
544 ptr = (u_int16_t *)(dest + (i * 2));
554 static void ste_setmulti(sc)
555 struct ste_softc *sc;
559 u_int32_t hashes[2] = { 0, 0 };
560 struct ifmultiaddr *ifma;
562 ifp = &sc->arpcom.ac_if;
563 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
564 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
565 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
569 /* first, zot all the existing hash bits */
570 CSR_WRITE_2(sc, STE_MAR0, 0);
571 CSR_WRITE_2(sc, STE_MAR1, 0);
572 CSR_WRITE_2(sc, STE_MAR2, 0);
573 CSR_WRITE_2(sc, STE_MAR3, 0);
575 /* now program new ones */
576 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
577 ifma = ifma->ifma_link.le_next) {
578 if (ifma->ifma_addr->sa_family != AF_LINK)
581 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
582 ETHER_ADDR_LEN) & 0x3f;
584 hashes[0] |= (1 << h);
586 hashes[1] |= (1 << (h - 32));
589 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
590 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
591 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
592 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
593 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
594 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
599 static void ste_intr(xsc)
602 struct ste_softc *sc;
607 ifp = &sc->arpcom.ac_if;
609 /* See if this is really our interrupt. */
610 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH))
614 status = CSR_READ_2(sc, STE_ISR_ACK);
616 if (!(status & STE_INTRS))
619 if (status & STE_ISR_RX_DMADONE)
622 if (status & STE_ISR_TX_DMADONE)
625 if (status & STE_ISR_TX_DONE)
628 if (status & STE_ISR_STATS_OFLOW) {
629 callout_stop(&sc->ste_stat_timer);
630 ste_stats_update(sc);
633 if (status & STE_ISR_LINKEVENT)
634 mii_pollstat(device_get_softc(sc->ste_miibus));
636 if (status & STE_ISR_HOSTERR) {
642 /* Re-enable interrupts */
643 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
645 if (!ifq_is_empty(&ifp->if_snd))
652 * A frame has been uploaded: pass the resulting mbuf chain up to
653 * the higher level protocols.
655 static void ste_rxeof(sc)
656 struct ste_softc *sc;
660 struct ste_chain_onefrag *cur_rx;
661 int total_len = 0, count=0;
664 ifp = &sc->arpcom.ac_if;
666 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)
667 & STE_RXSTAT_DMADONE) {
668 if ((STE_RX_LIST_CNT - count) < 3) {
672 cur_rx = sc->ste_cdata.ste_rx_head;
673 sc->ste_cdata.ste_rx_head = cur_rx->ste_next;
676 * If an error occurs, update stats, clear the
677 * status word and leave the mbuf cluster in place:
678 * it should simply get re-used next time this descriptor
679 * comes up in the ring.
681 if (rxstat & STE_RXSTAT_FRAME_ERR) {
683 cur_rx->ste_ptr->ste_status = 0;
688 * If there error bit was not set, the upload complete
689 * bit should be set which means we have a valid packet.
690 * If not, something truly strange has happened.
692 if (!(rxstat & STE_RXSTAT_DMADONE)) {
693 if_printf(ifp, "bad receive status -- packet dropped");
695 cur_rx->ste_ptr->ste_status = 0;
699 /* No errors; receive the packet. */
700 m = cur_rx->ste_mbuf;
701 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN;
704 * Try to conjure up a new mbuf cluster. If that
705 * fails, it means we have an out of memory condition and
706 * should leave the buffer in place and continue. This will
707 * result in a lost packet, but there's little else we
708 * can do in this situation.
710 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
712 cur_rx->ste_ptr->ste_status = 0;
717 m->m_pkthdr.rcvif = ifp;
718 m->m_pkthdr.len = m->m_len = total_len;
720 (*ifp->if_input)(ifp, m);
722 cur_rx->ste_ptr->ste_status = 0;
729 static void ste_txeoc(sc)
730 struct ste_softc *sc;
735 ifp = &sc->arpcom.ac_if;
737 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) &
738 STE_TXSTATUS_TXDONE) {
739 if (txstat & STE_TXSTATUS_UNDERRUN ||
740 txstat & STE_TXSTATUS_EXCESSCOLLS ||
741 txstat & STE_TXSTATUS_RECLAIMERR) {
743 if_printf(ifp, "transmission error: %x\n", txstat);
748 if (txstat & STE_TXSTATUS_UNDERRUN &&
749 sc->ste_tx_thresh < STE_PACKET_SIZE) {
750 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
751 if_printf(ifp, "tx underrun, increasing tx"
752 " start threshold to %d bytes\n",
755 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
756 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH,
757 (STE_PACKET_SIZE >> 4));
760 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
766 static void ste_txeof(sc)
767 struct ste_softc *sc;
769 struct ste_chain *cur_tx = NULL;
773 ifp = &sc->arpcom.ac_if;
775 idx = sc->ste_cdata.ste_tx_cons;
776 while(idx != sc->ste_cdata.ste_tx_prod) {
777 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
779 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE))
782 if (cur_tx->ste_mbuf != NULL) {
783 m_freem(cur_tx->ste_mbuf);
784 cur_tx->ste_mbuf = NULL;
789 sc->ste_cdata.ste_tx_cnt--;
790 STE_INC(idx, STE_TX_LIST_CNT);
794 sc->ste_cdata.ste_tx_cons = idx;
797 ifp->if_flags &= ~IFF_OACTIVE;
802 static void ste_stats_update(xsc)
805 struct ste_softc *sc;
807 struct mii_data *mii;
812 ifp = &sc->arpcom.ac_if;
813 mii = device_get_softc(sc->ste_miibus);
815 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS)
816 + CSR_READ_1(sc, STE_MULTI_COLLS)
817 + CSR_READ_1(sc, STE_SINGLE_COLLS);
821 if (mii->mii_media_status & IFM_ACTIVE &&
822 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
825 * we don't get a call-back on re-init so do it
826 * otherwise we get stuck in the wrong link state
828 ste_miibus_statchg(sc->ste_dev);
829 if (!ifq_is_empty(&ifp->if_snd))
834 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc);
842 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
843 * IDs against our list and return a device name if we find a match.
845 static int ste_probe(dev)
852 while(t->ste_name != NULL) {
853 if ((pci_get_vendor(dev) == t->ste_vid) &&
854 (pci_get_device(dev) == t->ste_did)) {
855 device_set_desc(dev, t->ste_name);
865 * Attach the interface. Allocate softc structures, do ifmedia
866 * setup and ethernet/BPF attach.
868 static int ste_attach(dev)
871 struct ste_softc *sc;
874 uint8_t eaddr[ETHER_ADDR_LEN];
876 sc = device_get_softc(dev);
880 * Only use one PHY since this chip reports multiple
881 * Note on the DFE-550 the PHY is at 1 on the DFE-580
882 * it is at 0 & 1. It is rev 0x12.
884 if (pci_get_vendor(dev) == DL_VENDORID &&
885 pci_get_device(dev) == DL_DEVICEID_550TX &&
886 pci_get_revid(dev) == 0x12 )
890 * Handle power management nonsense.
892 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
893 u_int32_t iobase, membase, irq;
895 /* Save important PCI config data. */
896 iobase = pci_read_config(dev, STE_PCI_LOIO, 4);
897 membase = pci_read_config(dev, STE_PCI_LOMEM, 4);
898 irq = pci_read_config(dev, STE_PCI_INTLINE, 4);
900 /* Reset the power state. */
901 device_printf(dev, "chip is in D%d power mode "
902 "-- setting to D0\n", pci_get_powerstate(dev));
903 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
905 /* Restore PCI config data. */
906 pci_write_config(dev, STE_PCI_LOIO, iobase, 4);
907 pci_write_config(dev, STE_PCI_LOMEM, membase, 4);
908 pci_write_config(dev, STE_PCI_INTLINE, irq, 4);
912 * Map control/status registers.
914 pci_enable_busmaster(dev);
917 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE);
919 if (sc->ste_res == NULL) {
920 device_printf(dev, "couldn't map ports/memory\n");
925 sc->ste_btag = rman_get_bustag(sc->ste_res);
926 sc->ste_bhandle = rman_get_bushandle(sc->ste_res);
929 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
930 RF_SHAREABLE | RF_ACTIVE);
932 if (sc->ste_irq == NULL) {
933 device_printf(dev, "couldn't map interrupt\n");
938 callout_init(&sc->ste_stat_timer);
940 ifp = &sc->arpcom.ac_if;
941 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
943 /* Reset the adapter. */
947 * Get station address from the EEPROM.
949 if (ste_read_eeprom(sc, eaddr, STE_EEADDR_NODE0, 3, 0)) {
950 device_printf(dev, "failed to read station address\n");
955 /* Allocate the descriptor queues. */
956 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF,
957 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
959 if (sc->ste_ldata == NULL) {
960 device_printf(dev, "no memory for list buffers!\n");
965 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
968 if (mii_phy_probe(dev, &sc->ste_miibus,
969 ste_ifmedia_upd, ste_ifmedia_sts)) {
970 device_printf(dev, "MII without any phy!\n");
976 ifp->if_mtu = ETHERMTU;
977 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
978 ifp->if_ioctl = ste_ioctl;
979 ifp->if_start = ste_start;
980 ifp->if_watchdog = ste_watchdog;
981 ifp->if_init = ste_init;
982 ifp->if_baudrate = 10000000;
983 ifq_set_maxlen(&ifp->if_snd, STE_TX_LIST_CNT - 1);
984 ifq_set_ready(&ifp->if_snd);
986 sc->ste_tx_thresh = STE_TXSTART_THRESH;
989 * Call MI attach routine.
991 ether_ifattach(ifp, eaddr);
994 * Tell the upper layer(s) we support long frames.
996 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
998 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET,
999 ste_intr, sc, &sc->ste_intrhand, NULL);
1001 device_printf(dev, "couldn't set up irq\n");
1002 ether_ifdetach(ifp);
1013 static int ste_detach(dev)
1016 struct ste_softc *sc;
1021 sc = device_get_softc(dev);
1022 ifp = &sc->arpcom.ac_if;
1024 if (device_is_attached(dev)) {
1025 if (bus_child_present(dev))
1027 ether_ifdetach(ifp);
1029 if (sc->ste_miibus != NULL)
1030 device_delete_child(dev, sc->ste_miibus);
1031 bus_generic_detach(dev);
1033 if (sc->ste_intrhand != NULL)
1034 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1038 if (sc->ste_irq != NULL)
1039 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1040 if (sc->ste_res != NULL)
1041 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1042 if (sc->ste_ldata != NULL) {
1043 contigfree(sc->ste_ldata, sizeof(struct ste_list_data),
1050 static int ste_newbuf(sc, c, m)
1051 struct ste_softc *sc;
1052 struct ste_chain_onefrag *c;
1055 struct mbuf *m_new = NULL;
1058 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1061 MCLGET(m_new, MB_DONTWAIT);
1062 if (!(m_new->m_flags & M_EXT)) {
1066 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1069 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1070 m_new->m_data = m_new->m_ext.ext_buf;
1073 m_adj(m_new, ETHER_ALIGN);
1075 c->ste_mbuf = m_new;
1076 c->ste_ptr->ste_status = 0;
1077 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t));
1078 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST;
1083 static int ste_init_rx_list(sc)
1084 struct ste_softc *sc;
1086 struct ste_chain_data *cd;
1087 struct ste_list_data *ld;
1090 cd = &sc->ste_cdata;
1093 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1094 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1095 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS)
1097 if (i == (STE_RX_LIST_CNT - 1)) {
1098 cd->ste_rx_chain[i].ste_next =
1099 &cd->ste_rx_chain[0];
1100 ld->ste_rx_list[i].ste_next =
1101 vtophys(&ld->ste_rx_list[0]);
1103 cd->ste_rx_chain[i].ste_next =
1104 &cd->ste_rx_chain[i + 1];
1105 ld->ste_rx_list[i].ste_next =
1106 vtophys(&ld->ste_rx_list[i + 1]);
1108 ld->ste_rx_list[i].ste_status = 0;
1111 cd->ste_rx_head = &cd->ste_rx_chain[0];
1116 static void ste_init_tx_list(sc)
1117 struct ste_softc *sc;
1119 struct ste_chain_data *cd;
1120 struct ste_list_data *ld;
1123 cd = &sc->ste_cdata;
1125 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1126 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1127 cd->ste_tx_chain[i].ste_ptr->ste_next = 0;
1128 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0;
1129 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]);
1130 if (i == (STE_TX_LIST_CNT - 1))
1131 cd->ste_tx_chain[i].ste_next =
1132 &cd->ste_tx_chain[0];
1134 cd->ste_tx_chain[i].ste_next =
1135 &cd->ste_tx_chain[i + 1];
1137 cd->ste_tx_chain[i].ste_prev =
1138 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1];
1140 cd->ste_tx_chain[i].ste_prev =
1141 &cd->ste_tx_chain[i - 1];
1144 cd->ste_tx_prod = 0;
1145 cd->ste_tx_cons = 0;
1151 static void ste_init(xsc)
1154 struct ste_softc *sc;
1157 struct mii_data *mii;
1162 ifp = &sc->arpcom.ac_if;
1163 mii = device_get_softc(sc->ste_miibus);
1167 /* Init our MAC address */
1168 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1169 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1173 if (ste_init_rx_list(sc) == ENOBUFS) {
1174 if_printf(ifp, "initialization failed: no "
1175 "memory for RX buffers\n");
1181 /* Set RX polling interval */
1182 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1);
1184 /* Init TX descriptors */
1185 ste_init_tx_list(sc);
1187 /* Set the TX freethresh value */
1188 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1190 /* Set the TX start threshold for best performance. */
1191 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1193 /* Set the TX reclaim threshold. */
1194 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1196 /* Set up the RX filter. */
1197 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST);
1199 /* If we want promiscuous mode, set the allframes bit. */
1200 if (ifp->if_flags & IFF_PROMISC) {
1201 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1203 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1206 /* Set capture broadcast bit to accept broadcast frames. */
1207 if (ifp->if_flags & IFF_BROADCAST) {
1208 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1210 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1215 /* Load the address of the RX list. */
1216 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1218 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1219 vtophys(&sc->ste_ldata->ste_rx_list[0]));
1220 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1221 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1223 /* Set TX polling interval (defer until we TX first packet */
1224 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1226 /* Load address of the TX list */
1227 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1229 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1230 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1231 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1233 sc->ste_tx_prev_idx=-1;
1235 /* Enable receiver and transmitter */
1236 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1237 CSR_WRITE_2(sc, STE_MACCTL1, 0);
1238 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1239 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1241 /* Enable stats counters. */
1242 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1244 /* Enable interrupts. */
1245 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1246 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1248 /* Accept VLAN length packets */
1249 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN);
1251 ste_ifmedia_upd(ifp);
1253 ifp->if_flags |= IFF_RUNNING;
1254 ifp->if_flags &= ~IFF_OACTIVE;
1258 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc);
1263 static void ste_stop(sc)
1264 struct ste_softc *sc;
1269 ifp = &sc->arpcom.ac_if;
1271 callout_stop(&sc->ste_stat_timer);
1273 CSR_WRITE_2(sc, STE_IMR, 0);
1274 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE);
1275 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE);
1276 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE);
1277 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1278 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1281 * Try really hard to stop the RX engine or under heavy RX
1282 * data chip will write into de-allocated memory.
1288 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1289 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) {
1290 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf);
1291 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL;
1295 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1296 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) {
1297 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf);
1298 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL;
1302 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1304 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1309 static void ste_reset(sc)
1310 struct ste_softc *sc;
1314 STE_SETBIT4(sc, STE_ASICCTL,
1315 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET|
1316 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET|
1317 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET|
1318 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET|
1319 STE_ASICCTL_EXTRESET_RESET);
1323 for (i = 0; i < STE_TIMEOUT; i++) {
1324 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1328 if (i == STE_TIMEOUT)
1329 if_printf(&sc->arpcom.ac_if, "global reset never completed\n");
1334 static int ste_ioctl(ifp, command, data, cr)
1340 struct ste_softc *sc;
1342 struct mii_data *mii;
1348 ifr = (struct ifreq *)data;
1352 if (ifp->if_flags & IFF_UP) {
1353 if (ifp->if_flags & IFF_RUNNING &&
1354 ifp->if_flags & IFF_PROMISC &&
1355 !(sc->ste_if_flags & IFF_PROMISC)) {
1356 STE_SETBIT1(sc, STE_RX_MODE,
1357 STE_RXMODE_PROMISC);
1358 } else if (ifp->if_flags & IFF_RUNNING &&
1359 !(ifp->if_flags & IFF_PROMISC) &&
1360 sc->ste_if_flags & IFF_PROMISC) {
1361 STE_CLRBIT1(sc, STE_RX_MODE,
1362 STE_RXMODE_PROMISC);
1364 if (!(ifp->if_flags & IFF_RUNNING)) {
1365 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1369 if (ifp->if_flags & IFF_RUNNING)
1372 sc->ste_if_flags = ifp->if_flags;
1382 mii = device_get_softc(sc->ste_miibus);
1383 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1386 error = ether_ioctl(ifp, command, data);
1395 static int ste_encap(sc, c, m_head)
1396 struct ste_softc *sc;
1397 struct ste_chain *c;
1398 struct mbuf *m_head;
1401 struct ste_frag *f = NULL;
1410 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1411 if (m->m_len != 0) {
1412 if (frag == STE_MAXFRAGS)
1414 total_len += m->m_len;
1415 f = &d->ste_frags[frag];
1416 f->ste_addr = vtophys(mtod(m, vm_offset_t));
1417 f->ste_len = m->m_len;
1426 * We ran out of segments. We have to recopy this
1427 * mbuf chain first. Bail out if we can't get the
1428 * new buffers. Code borrowed from if_fxp.c.
1430 MGETHDR(mn, MB_DONTWAIT, MT_DATA);
1435 if (m_head->m_pkthdr.len > MHLEN) {
1436 MCLGET(mn, MB_DONTWAIT);
1437 if ((mn->m_flags & M_EXT) == 0) {
1443 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1445 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len;
1451 c->ste_mbuf = m_head;
1452 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST;
1458 static void ste_start(ifp)
1461 struct ste_softc *sc;
1462 struct mbuf *m_head = NULL;
1463 struct ste_chain *cur_tx = NULL;
1471 if (ifp->if_flags & IFF_OACTIVE)
1474 idx = sc->ste_cdata.ste_tx_prod;
1476 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) {
1478 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) {
1479 ifp->if_flags |= IFF_OACTIVE;
1483 m_head = ifq_dequeue(&ifp->if_snd);
1487 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
1489 if (ste_encap(sc, cur_tx, m_head) != 0)
1492 cur_tx->ste_ptr->ste_next = 0;
1494 if(sc->ste_tx_prev_idx < 0){
1495 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1496 /* Load address of the TX list */
1497 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1500 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
1501 vtophys(&sc->ste_ldata->ste_tx_list[0]));
1503 /* Set TX polling interval to start TX engine */
1504 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
1506 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1509 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1510 sc->ste_cdata.ste_tx_chain[
1511 sc->ste_tx_prev_idx].ste_ptr->ste_next
1515 sc->ste_tx_prev_idx=idx;
1517 BPF_MTAP(ifp, cur_tx->ste_mbuf);
1519 STE_INC(idx, STE_TX_LIST_CNT);
1520 sc->ste_cdata.ste_tx_cnt++;
1522 sc->ste_cdata.ste_tx_prod = idx;
1528 static void ste_watchdog(ifp)
1531 struct ste_softc *sc;
1536 if_printf(ifp, "watchdog timeout\n");
1544 if (!ifq_is_empty(&ifp->if_snd))
1550 static void ste_shutdown(dev)
1553 struct ste_softc *sc;
1555 sc = device_get_softc(dev);