2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <william.paul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $
34 * $DragonFly: src/sys/dev/netif/lge/if_lge.c,v 1.23 2005/05/24 09:52:13 joerg Exp $
38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
39 * documentation not available, but ask me nicely.
41 * Written by Bill Paul <william.paul@windriver.com>
46 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
47 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
48 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
49 * are three supported methods for data transfer between host and
50 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
51 * Propulsion Technology (tm) DMA. The latter mechanism is a form
52 * of double buffer DMA where the packet data is copied to a
53 * pre-allocated DMA buffer who's physical address has been loaded
54 * into a table at device initialization time. The rationale is that
55 * the virtual to physical address translation needed for normal
56 * scatter/gather DMA is more expensive than the data copy needed
57 * for double buffering. This may be true in Windows NT and the like,
58 * but it isn't true for us, at least on the x86 arch. This driver
59 * uses the scatter/gather I/O method for both TX and RX.
61 * The LXT1001 only supports TCP/IP checksum offload on receive.
62 * Also, the VLAN tagging is done using a 16-entry table which allows
63 * the chip to perform hardware filtering based on VLAN tags. Sadly,
64 * our vlan support doesn't currently play well with this kind of
68 * - Jeff James at Intel, for arranging to have the LXT1001 manual
69 * released (at long last)
70 * - Beny Chen at D-Link, for actually sending it to me
71 * - Brad Short and Keith Alexis at SMC, for sending me sample
72 * SMC9462SX and SMC9462TX adapters for testing
73 * - Paul Saab at Y!, for not killing me (though it remains to be seen
74 * if in fact he did me much of a favor)
77 #include <sys/param.h>
78 #include <sys/systm.h>
79 #include <sys/sockio.h>
81 #include <sys/malloc.h>
82 #include <sys/kernel.h>
83 #include <sys/socket.h>
86 #include <net/ifq_var.h>
87 #include <net/if_arp.h>
88 #include <net/ethernet.h>
89 #include <net/if_dl.h>
90 #include <net/if_media.h>
94 #include <vm/vm.h> /* for vtophys */
95 #include <vm/pmap.h> /* for vtophys */
96 #include <machine/bus.h>
97 #include <machine/resource.h>
101 #include <dev/netif/mii_layer/mii.h>
102 #include <dev/netif/mii_layer/miivar.h>
104 #include <bus/pci/pcireg.h>
105 #include <bus/pci/pcivar.h>
107 #define LGE_USEIOSPACE
109 #include "if_lgereg.h"
111 /* "controller miibus0" required. See GENERIC if you get errors here. */
112 #include "miibus_if.h"
115 * Various supported device vendors/types and their names.
117 static struct lge_type lge_devs[] = {
118 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
122 static int lge_probe(device_t);
123 static int lge_attach(device_t);
124 static int lge_detach(device_t);
126 static int lge_alloc_jumbo_mem(struct lge_softc *);
127 static void lge_free_jumbo_mem(struct lge_softc *);
128 static void *lge_jalloc(struct lge_softc *);
129 static void lge_jfree(caddr_t, u_int);
130 static void lge_jref(caddr_t, u_int);
132 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *,
134 static int lge_encap(struct lge_softc *, struct mbuf *, uint32_t *);
135 static void lge_rxeof(struct lge_softc *, int);
136 static void lge_rxeoc(struct lge_softc *);
137 static void lge_txeof(struct lge_softc *);
138 static void lge_intr(void *);
139 static void lge_tick(void *);
140 static void lge_start(struct ifnet *);
141 static int lge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
142 static void lge_init(void *);
143 static void lge_stop(struct lge_softc *);
144 static void lge_watchdog(struct ifnet *);
145 static void lge_shutdown(device_t);
146 static int lge_ifmedia_upd(struct ifnet *);
147 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
149 static void lge_eeprom_getword(struct lge_softc *, int, uint16_t *);
150 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int);
152 static int lge_miibus_readreg(device_t, int, int);
153 static int lge_miibus_writereg(device_t, int, int, int);
154 static void lge_miibus_statchg(device_t);
156 static void lge_setmulti(struct lge_softc *);
157 static void lge_reset(struct lge_softc *);
158 static int lge_list_rx_init(struct lge_softc *);
159 static int lge_list_tx_init(struct lge_softc *);
161 #ifdef LGE_USEIOSPACE
162 #define LGE_RES SYS_RES_IOPORT
163 #define LGE_RID LGE_PCI_LOIO
165 #define LGE_RES SYS_RES_MEMORY
166 #define LGE_RID LGE_PCI_LOMEM
169 static device_method_t lge_methods[] = {
170 /* Device interface */
171 DEVMETHOD(device_probe, lge_probe),
172 DEVMETHOD(device_attach, lge_attach),
173 DEVMETHOD(device_detach, lge_detach),
174 DEVMETHOD(device_shutdown, lge_shutdown),
177 DEVMETHOD(bus_print_child, bus_generic_print_child),
178 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
181 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
182 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
183 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
188 static DEFINE_CLASS_0(lge, lge_driver, lge_methods, sizeof(struct lge_softc));
189 static devclass_t lge_devclass;
191 DECLARE_DUMMY_MODULE(if_lge);
192 DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0);
193 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
195 #define LGE_SETBIT(sc, reg, x) \
196 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
198 #define LGE_CLRBIT(sc, reg, x) \
199 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
202 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | (x))
205 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~(x))
208 * Read a word of data stored in the EEPROM at address 'addr.'
211 lge_eeprom_getword(struct lge_softc *sc, int addr, uint16_t *dest)
216 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
217 LGE_EECTL_SINGLEACCESS | ((addr >> 1) << 8));
219 for (i = 0; i < LGE_TIMEOUT; i++) {
220 if ((CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ) == 0)
224 if (i == LGE_TIMEOUT) {
225 printf("lge%d: EEPROM read timed out\n", sc->lge_unit);
229 val = CSR_READ_4(sc, LGE_EEDATA);
232 *dest = (val >> 16) & 0xFFFF;
234 *dest = val & 0xFFFF;
238 * Read a sequence of words from the EEPROM.
241 lge_read_eeprom(struct lge_softc *sc, caddr_t dest, int off, int cnt)
244 uint16_t word = 0, *ptr;
246 for (i = 0; i < cnt; i++) {
247 lge_eeprom_getword(sc, off + i, &word);
248 ptr = (uint16_t *)(dest + (i * 2));
254 lge_miibus_readreg(device_t dev, int phy, int reg)
256 struct lge_softc *sc = device_get_softc(dev);
260 * If we have a non-PCS PHY, pretend that the internal
261 * autoneg stuff at PHY address 0 isn't there so that
262 * the miibus code will find only the GMII PHY.
264 if (sc->lge_pcs == 0 && phy == 0)
267 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
269 for (i = 0; i < LGE_TIMEOUT; i++) {
270 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0)
274 if (i == LGE_TIMEOUT) {
275 printf("lge%d: PHY read timed out\n", sc->lge_unit);
279 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
283 lge_miibus_writereg(device_t dev, int phy, int reg, int data)
285 struct lge_softc *sc = device_get_softc(dev);
288 CSR_WRITE_4(sc, LGE_GMIICTL,
289 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
291 for (i = 0; i < LGE_TIMEOUT; i++) {
292 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0)
296 if (i == LGE_TIMEOUT) {
297 printf("lge%d: PHY write timed out\n", sc->lge_unit);
305 lge_miibus_statchg(device_t dev)
307 struct lge_softc *sc = device_get_softc(dev);
308 struct mii_data *mii = device_get_softc(sc->lge_miibus);
310 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
311 switch (IFM_SUBTYPE(mii->mii_media_active)) {
314 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
317 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
320 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
324 * Choose something, even if it's wrong. Clearing
325 * all the bits will hose autoneg on the internal
328 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
332 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
333 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
335 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
339 lge_setmulti(struct lge_softc *sc)
341 struct ifnet *ifp = &sc->arpcom.ac_if;
342 struct ifmultiaddr *ifma;
343 uint32_t h = 0, hashes[2] = { 0, 0 };
345 /* Make sure multicast hash table is enabled. */
346 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_MCAST);
348 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
349 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
350 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
354 /* first, zot all the existing hash bits */
355 CSR_WRITE_4(sc, LGE_MAR0, 0);
356 CSR_WRITE_4(sc, LGE_MAR1, 0);
358 /* now program new ones */
359 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
360 if (ifma->ifma_addr->sa_family != AF_LINK)
362 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
363 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
365 hashes[0] |= (1 << h);
367 hashes[1] |= (1 << (h - 32));
370 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
371 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
377 lge_reset(struct lge_softc *sc)
381 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_SOFTRST);
383 for (i = 0; i < LGE_TIMEOUT; i++) {
384 if ((CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST) == 0)
388 if (i == LGE_TIMEOUT)
389 printf("lge%d: reset never completed\n", sc->lge_unit);
391 /* Wait a little while for the chip to get its brains in order. */
396 * Probe for a Level 1 chip. Check the PCI vendor and device
397 * IDs against our list and return a device name if we find a match.
400 lge_probe(device_t dev)
403 uint16_t vendor, product;
405 vendor = pci_get_vendor(dev);
406 product = pci_get_device(dev);
408 for (t = lge_devs; t->lge_name != NULL; t++) {
409 if (vendor == t->lge_vid && product == t->lge_did) {
410 device_set_desc(dev, t->lge_name);
419 * Attach the interface. Allocate softc structures, do ifmedia
420 * setup and ethernet/BPF attach.
423 lge_attach(device_t dev)
425 uint8_t eaddr[ETHER_ADDR_LEN];
427 struct lge_softc *sc;
429 int unit, error = 0, rid, s;
433 sc = device_get_softc(dev);
434 unit = device_get_unit(dev);
435 callout_init(&sc->lge_stat_timer);
438 * Handle power management nonsense.
440 command = pci_read_config(dev, LGE_PCI_CAPID, 4) & 0x000000FF;
441 if (command == 0x01) {
443 command = pci_read_config(dev, LGE_PCI_PWRMGMTCTRL, 4);
444 if (command & LGE_PSTATE_MASK) {
445 uint32_t iobase, membase, irq;
447 /* Save important PCI config data. */
448 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4);
449 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4);
450 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4);
452 /* Reset the power state. */
453 printf("lge%d: chip is in D%d power mode "
454 "-- setting to D0\n", unit, command & LGE_PSTATE_MASK);
455 command &= 0xFFFFFFFC;
456 pci_write_config(dev, LGE_PCI_PWRMGMTCTRL, command, 4);
458 /* Restore PCI config data. */
459 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4);
460 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4);
461 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4);
466 * Map control/status registers.
468 command = pci_read_config(dev, PCIR_COMMAND, 4);
469 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
470 pci_write_config(dev, PCIR_COMMAND, command, 4);
471 command = pci_read_config(dev, PCIR_COMMAND, 4);
473 #ifdef LGE_USEIOSPACE
474 if (!(command & PCIM_CMD_PORTEN)) {
475 printf("lge%d: failed to enable I/O ports!\n", unit);
480 if (!(command & PCIM_CMD_MEMEN)) {
481 printf("lge%d: failed to enable memory mapping!\n", unit);
488 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE);
490 if (sc->lge_res == NULL) {
491 printf("lge%d: couldn't map ports/memory\n", unit);
496 sc->lge_btag = rman_get_bustag(sc->lge_res);
497 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
499 /* Allocate interrupt */
501 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
502 RF_SHAREABLE | RF_ACTIVE);
504 if (sc->lge_irq == NULL) {
505 printf("lge%d: couldn't map interrupt\n", unit);
506 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
511 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET,
512 lge_intr, sc, &sc->lge_intrhand);
515 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
516 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
517 printf("lge%d: couldn't set up irq\n", unit);
521 /* Reset the adapter. */
525 * Get station address from the EEPROM.
527 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1);
528 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1);
529 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1);
533 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
534 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
536 if (sc->lge_ldata == NULL) {
537 printf("lge%d: no memory for list buffers!\n", unit);
538 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
539 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
540 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
544 bzero(sc->lge_ldata, sizeof(struct lge_list_data));
546 /* Try to allocate memory for jumbo buffers. */
547 if (lge_alloc_jumbo_mem(sc)) {
548 printf("lge%d: jumbo buffer allocation failed\n",
550 contigfree(sc->lge_ldata, sizeof(struct lge_list_data),
552 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
553 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
554 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
559 ifp = &sc->arpcom.ac_if;
561 if_initname(ifp, "lge", unit);
562 ifp->if_mtu = ETHERMTU;
563 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
564 ifp->if_ioctl = lge_ioctl;
565 ifp->if_start = lge_start;
566 ifp->if_watchdog = lge_watchdog;
567 ifp->if_init = lge_init;
568 ifp->if_baudrate = 1000000000;
569 ifq_set_maxlen(&ifp->if_snd, LGE_TX_LIST_CNT - 1);
570 ifq_set_ready(&ifp->if_snd);
571 ifp->if_capabilities = IFCAP_RXCSUM;
572 ifp->if_capenable = ifp->if_capabilities;
574 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
582 if (mii_phy_probe(dev, &sc->lge_miibus,
583 lge_ifmedia_upd, lge_ifmedia_sts)) {
584 printf("lge%d: MII without any PHY!\n", sc->lge_unit);
585 contigfree(sc->lge_ldata,
586 sizeof(struct lge_list_data), M_DEVBUF);
587 lge_free_jumbo_mem(sc);
588 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
589 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
590 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
596 * Call MI attach routine.
598 ether_ifattach(ifp, eaddr);
606 lge_detach(device_t dev)
608 struct lge_softc *sc= device_get_softc(dev);
609 struct ifnet *ifp = &sc->arpcom.ac_if;
618 bus_generic_detach(dev);
619 device_delete_child(dev, sc->lge_miibus);
621 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
622 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
623 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
625 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF);
626 lge_free_jumbo_mem(sc);
634 * Initialize the transmit descriptors.
637 lge_list_tx_init(struct lge_softc *sc)
639 struct lge_list_data *ld;
640 struct lge_ring_data *cd;
645 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
646 ld->lge_tx_list[i].lge_mbuf = NULL;
647 ld->lge_tx_list[i].lge_ctl = 0;
650 cd->lge_tx_prod = cd->lge_tx_cons = 0;
657 * Initialize the RX descriptors and allocate mbufs for them. Note that
658 * we arralge the descriptors in a closed ring, so that the last descriptor
659 * points back to the first.
662 lge_list_rx_init(struct lge_softc *sc)
664 struct lge_list_data *ld;
665 struct lge_ring_data *cd;
671 cd->lge_rx_prod = cd->lge_rx_cons = 0;
673 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
675 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
676 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
678 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
682 /* Clear possible 'rx command queue empty' interrupt. */
683 CSR_READ_4(sc, LGE_ISR);
689 * Initialize an RX descriptor and attach an MBUF cluster.
692 lge_newbuf(struct lge_softc *sc, struct lge_rx_desc *c, struct mbuf *m)
694 struct mbuf *m_new = NULL;
698 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
700 printf("lge%d: no memory for rx list "
701 "-- packet dropped!\n", sc->lge_unit);
705 /* Allocate the jumbo buffer */
706 buf = lge_jalloc(sc);
709 printf("lge%d: jumbo allocation failed "
710 "-- packet dropped!\n", sc->lge_unit);
715 /* Attach the buffer to the mbuf */
716 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
717 m_new->m_flags |= M_EXT | M_EXT_OLD;
718 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
719 m_new->m_len = LGE_MCLBYTES;
720 m_new->m_ext.ext_nfree.old = lge_jfree;
721 m_new->m_ext.ext_nref.old = lge_jref;
724 m_new->m_len = m_new->m_pkthdr.len = LGE_MCLBYTES;
725 m_new->m_data = m_new->m_ext.ext_buf;
729 * Adjust alignment so packet payload begins on a
730 * longword boundary. Mandatory for Alpha, useful on
733 m_adj(m_new, ETHER_ALIGN);
736 c->lge_fragptr_hi = 0;
737 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
738 c->lge_fraglen = m_new->m_len;
739 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
743 * Put this buffer in the RX command FIFO. To do this,
744 * we just write the physical address of the descriptor
745 * into the RX descriptor address registers. Note that
746 * there are two registers, one high DWORD and one low
747 * DWORD, which lets us specify a 64-bit address if
748 * desired. We only use a 32-bit address for now.
749 * Writing to the low DWORD register is what actually
750 * causes the command to be issued, so we do that
753 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
754 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
760 lge_alloc_jumbo_mem(struct lge_softc *sc)
762 struct lge_jpool_entry *entry;
766 /* Grab a big chunk o' storage. */
767 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
768 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
770 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
771 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit);
775 SLIST_INIT(&sc->lge_jfree_listhead);
776 SLIST_INIT(&sc->lge_jinuse_listhead);
779 * Now divide it up into 9K pieces and save the addresses
782 ptr = sc->lge_cdata.lge_jumbo_buf;
783 for (i = 0; i < LGE_JSLOTS; i++) {
785 aptr = (uint64_t **)ptr;
786 aptr[0] = (uint64_t *)sc;
787 ptr += sizeof(uint64_t);
788 sc->lge_cdata.lge_jslots[i].lge_buf = ptr;
789 sc->lge_cdata.lge_jslots[i].lge_inuse = 0;
791 entry = malloc(sizeof(struct lge_jpool_entry),
794 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
795 entry, jpool_entries);
802 lge_free_jumbo_mem(struct lge_softc *sc)
804 struct lge_jpool_entry *entry;
807 for (i = 0; i < LGE_JSLOTS; i++) {
808 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
809 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
810 free(entry, M_DEVBUF);
813 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
817 * Allocate a jumbo buffer.
820 lge_jalloc(struct lge_softc *sc)
822 struct lge_jpool_entry *entry;
824 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
828 printf("lge%d: no free jumbo buffers\n", sc->lge_unit);
833 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
834 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
835 sc->lge_cdata.lge_jslots[entry->slot].lge_inuse = 1;
837 return(sc->lge_cdata.lge_jslots[entry->slot].lge_buf);
841 * Adjust usage count on a jumbo buffer. In general this doesn't
842 * get used much because our jumbo buffers don't get passed around
843 * a lot, but it's implemented for correctness.
846 lge_jref(caddr_t buf, u_int size)
848 struct lge_softc *sc;
852 /* Extract the softc struct pointer. */
853 aptr = (uint64_t **)(buf - sizeof(uint64_t));
854 sc = (struct lge_softc *)(aptr[0]);
857 panic("lge_jref: can't find softc pointer!");
859 if (size != LGE_MCLBYTES)
860 panic("lge_jref: adjusting refcount of buf of wrong size!");
862 /* calculate the slot this buffer belongs to */
864 i = ((vm_offset_t)aptr
865 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
867 if ((i < 0) || (i >= LGE_JSLOTS))
868 panic("lge_jref: asked to reference buffer "
869 "that we don't manage!");
870 else if (sc->lge_cdata.lge_jslots[i].lge_inuse == 0)
871 panic("lge_jref: buffer already free!");
873 sc->lge_cdata.lge_jslots[i].lge_inuse++;
877 * Release a jumbo buffer.
880 lge_jfree(caddr_t buf, u_int size)
882 struct lge_softc *sc;
885 struct lge_jpool_entry *entry;
887 /* Extract the softc struct pointer. */
888 aptr = (uint64_t **)(buf - sizeof(uint64_t));
889 sc = (struct lge_softc *)(aptr[0]);
892 panic("lge_jfree: can't find softc pointer!");
894 if (size != LGE_MCLBYTES)
895 panic("lge_jfree: freeing buffer of wrong size!");
897 /* calculate the slot this buffer belongs to */
898 i = ((vm_offset_t)aptr
899 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
901 if ((i < 0) || (i >= LGE_JSLOTS))
902 panic("lge_jfree: asked to free buffer that we don't manage!");
903 else if (sc->lge_cdata.lge_jslots[i].lge_inuse == 0)
904 panic("lge_jfree: buffer already free!");
906 sc->lge_cdata.lge_jslots[i].lge_inuse--;
907 if(sc->lge_cdata.lge_jslots[i].lge_inuse == 0) {
908 entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
910 panic("lge_jfree: buffer not in use!");
912 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead,
914 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
915 entry, jpool_entries);
921 * A frame has been uploaded: pass the resulting mbuf chain up to
922 * the higher level protocols.
925 lge_rxeof(struct lge_softc *sc, int cnt)
927 struct ifnet *ifp = &sc->arpcom.ac_if;
929 struct lge_rx_desc *cur_rx;
930 int c, i, total_len = 0;
931 uint32_t rxsts, rxctl;
934 /* Find out how many frames were processed. */
936 i = sc->lge_cdata.lge_rx_cons;
940 struct mbuf *m0 = NULL;
942 cur_rx = &sc->lge_ldata->lge_rx_list[i];
943 rxctl = cur_rx->lge_ctl;
944 rxsts = cur_rx->lge_sts;
945 m = cur_rx->lge_mbuf;
946 cur_rx->lge_mbuf = NULL;
947 total_len = LGE_RXBYTES(cur_rx);
948 LGE_INC(i, LGE_RX_LIST_CNT);
952 * If an error occurs, update stats, clear the
953 * status word and leave the mbuf cluster in place:
954 * it should simply get re-used next time this descriptor
955 * comes up in the ring.
957 if (rxctl & LGE_RXCTL_ERRMASK) {
959 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
963 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
964 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
965 total_len + ETHER_ALIGN, 0, ifp, NULL);
966 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
968 printf("lge%d: no receive buffers "
969 "available -- packet dropped!\n",
974 m_adj(m0, ETHER_ALIGN);
977 m->m_pkthdr.rcvif = ifp;
978 m->m_pkthdr.len = m->m_len = total_len;
983 /* Do IP checksum checking. */
984 if (rxsts & LGE_RXSTS_ISIP)
985 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
986 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
987 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
988 if ((rxsts & LGE_RXSTS_ISTCP &&
989 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
990 (rxsts & LGE_RXSTS_ISUDP &&
991 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
992 m->m_pkthdr.csum_flags |=
993 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
994 m->m_pkthdr.csum_data = 0xffff;
997 (*ifp->if_input)(ifp, m);
1000 sc->lge_cdata.lge_rx_cons = i;
1004 lge_rxeoc(struct lge_softc *sc)
1006 struct ifnet *ifp = &sc->arpcom.ac_if;
1008 ifp->if_flags &= ~IFF_RUNNING;
1013 * A frame was downloaded to the chip. It's safe for us to clean up
1017 lge_txeof(struct lge_softc *sc)
1019 struct ifnet *ifp = &sc->arpcom.ac_if;
1020 struct lge_tx_desc *cur_tx = NULL;
1021 uint32_t idx, txdone;
1023 /* Clear the timeout timer. */
1027 * Go through our tx list and free mbufs for those
1028 * frames that have been transmitted.
1030 idx = sc->lge_cdata.lge_tx_cons;
1031 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1033 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
1034 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
1037 if (cur_tx->lge_mbuf != NULL) {
1038 m_freem(cur_tx->lge_mbuf);
1039 cur_tx->lge_mbuf = NULL;
1041 cur_tx->lge_ctl = 0;
1044 LGE_INC(idx, LGE_TX_LIST_CNT);
1048 sc->lge_cdata.lge_tx_cons = idx;
1051 ifp->if_flags &= ~IFF_OACTIVE;
1057 struct lge_softc *sc = xsc;
1058 struct mii_data *mii;
1059 struct ifnet *ifp = &sc->arpcom.ac_if;
1064 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1065 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1066 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1067 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1069 if (!sc->lge_link) {
1070 mii = device_get_softc(sc->lge_miibus);
1073 if (mii->mii_media_status & IFM_ACTIVE &&
1074 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1076 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1077 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
1078 printf("lge%d: gigabit link up\n",
1080 if (!ifq_is_empty(&ifp->if_snd))
1081 (*ifp->if_start)(ifp);
1085 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc);
1093 struct lge_softc *sc = arg;
1094 struct ifnet *ifp = &sc->arpcom.ac_if;
1097 /* Supress unwanted interrupts */
1098 if ((ifp->if_flags & IFF_UP) == 0) {
1105 * Reading the ISR register clears all interrupts, and
1106 * clears the 'interrupts enabled' bit in the IMR
1109 status = CSR_READ_4(sc, LGE_ISR);
1111 if ((status & LGE_INTRS) == 0)
1114 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1117 if (status & LGE_ISR_RXDMA_DONE)
1118 lge_rxeof(sc, LGE_RX_DMACNT(status));
1120 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1123 if (status & LGE_ISR_PHY_INTR) {
1125 callout_stop(&sc->lge_stat_timer);
1130 /* Re-enable interrupts. */
1131 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1133 if (!ifq_is_empty(&ifp->if_snd))
1134 (*ifp->if_start)(ifp);
1138 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1139 * pointers to the fragment pointers.
1142 lge_encap(struct lge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1144 struct lge_frag *f = NULL;
1145 struct lge_tx_desc *cur_tx;
1147 int frag = 0, tot_len = 0;
1150 * Start packing the mbufs in this chain into
1151 * the fragment pointers. Stop when we run out
1152 * of fragments or hit the end of the mbuf chain.
1155 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1158 for (m = m_head; m != NULL; m = m->m_next) {
1159 if (m->m_len != 0) {
1160 tot_len += m->m_len;
1161 f = &cur_tx->lge_frags[frag];
1162 f->lge_fraglen = m->m_len;
1163 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1164 f->lge_fragptr_hi = 0;
1172 cur_tx->lge_mbuf = m_head;
1173 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1174 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1176 /* Queue for transmit */
1177 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1183 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1184 * to the mbuf data regions directly in the transmit lists. We also save a
1185 * copy of the pointers since the transmit list fragment pointers are
1186 * physical addresses.
1190 lge_start(struct ifnet *ifp)
1192 struct lge_softc *sc = ifp->if_softc;
1193 struct mbuf *m_head = NULL;
1199 idx = sc->lge_cdata.lge_tx_prod;
1201 if (ifp->if_flags & IFF_OACTIVE)
1204 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1205 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1208 m_head = ifq_poll(&ifp->if_snd);
1212 if (lge_encap(sc, m_head, &idx)) {
1213 ifp->if_flags |= IFF_OACTIVE;
1216 m_head = ifq_dequeue(&ifp->if_snd);
1218 BPF_MTAP(ifp, m_head);
1221 sc->lge_cdata.lge_tx_prod = idx;
1224 * Set a timeout in case the chip goes out to lunch.
1232 struct lge_softc *sc = xsc;
1233 struct ifnet *ifp = &sc->arpcom.ac_if;
1234 struct mii_data *mii;
1237 if (ifp->if_flags & IFF_RUNNING)
1243 * Cancel pending I/O and free all RX/TX buffers.
1248 mii = device_get_softc(sc->lge_miibus);
1250 /* Set MAC address */
1251 CSR_WRITE_4(sc, LGE_PAR0, *(uint32_t *)(&sc->arpcom.ac_enaddr[0]));
1252 CSR_WRITE_4(sc, LGE_PAR1, *(uint32_t *)(&sc->arpcom.ac_enaddr[4]));
1254 /* Init circular RX list. */
1255 if (lge_list_rx_init(sc) == ENOBUFS) {
1256 printf("lge%d: initialization failed: no "
1257 "memory for rx buffers\n", sc->lge_unit);
1264 * Init tx descriptors.
1266 lge_list_tx_init(sc);
1268 /* Set initial value for MODE1 register. */
1269 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST |
1270 LGE_MODE1_TX_CRC | LGE_MODE1_TXPAD |
1271 LGE_MODE1_RX_FLOWCTL | LGE_MODE1_SETRST_CTL0 |
1272 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_SETRST_CTL2);
1274 /* If we want promiscuous mode, set the allframes bit. */
1275 if (ifp->if_flags & IFF_PROMISC) {
1276 CSR_WRITE_4(sc, LGE_MODE1,
1277 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_PROMISC);
1279 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1283 * Set the capture broadcast bit to capture broadcast frames.
1285 if (ifp->if_flags & IFF_BROADCAST) {
1286 CSR_WRITE_4(sc, LGE_MODE1,
1287 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_BCAST);
1289 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1292 /* Packet padding workaround? */
1293 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1295 /* No error frames */
1296 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1298 /* Receive large frames */
1299 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_GIANTS);
1301 /* Workaround: disable RX/TX flow control */
1302 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1303 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1305 /* Make sure to strip CRC from received frames */
1306 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1308 /* Turn off magic packet mode */
1309 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1311 /* Turn off all VLAN stuff */
1312 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX | LGE_MODE1_VLAN_TX |
1313 LGE_MODE1_VLAN_STRIP | LGE_MODE1_VLAN_INSERT);
1315 /* Workarond: FIFO overflow */
1316 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1317 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1320 * Load the multicast filter.
1325 * Enable hardware checksum validation for all received IPv4
1326 * packets, do not reject packets with bad checksums.
1328 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM |
1329 LGE_MODE2_RX_TCPCSUM | LGE_MODE2_RX_UDPCSUM |
1330 LGE_MODE2_RX_ERRCSUM);
1333 * Enable the delivery of PHY interrupts based on
1334 * link/speed/duplex status chalges.
1336 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_GMIIPOLL);
1338 /* Enable receiver and transmitter. */
1339 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1340 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_ENB);
1342 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1343 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_TX_ENB);
1346 * Enable interrupts.
1348 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0 |
1349 LGE_IMR_SETRST_CTL1 | LGE_IMR_INTR_ENB|LGE_INTRS);
1351 lge_ifmedia_upd(ifp);
1353 ifp->if_flags |= IFF_RUNNING;
1354 ifp->if_flags &= ~IFF_OACTIVE;
1358 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc);
1362 * Set media options.
1365 lge_ifmedia_upd(struct ifnet *ifp)
1367 struct lge_softc *sc = ifp->if_softc;
1368 struct mii_data *mii = device_get_softc(sc->lge_miibus);
1371 if (mii->mii_instance) {
1372 struct mii_softc *miisc;
1373 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1374 mii_phy_reset(miisc);
1382 * Report current media status.
1385 lge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1387 struct lge_softc *sc = ifp->if_softc;
1388 struct mii_data *mii;
1390 mii = device_get_softc(sc->lge_miibus);
1392 ifmr->ifm_active = mii->mii_media_active;
1393 ifmr->ifm_status = mii->mii_media_status;
1397 lge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1399 struct lge_softc *sc = ifp->if_softc;
1400 struct ifreq *ifr = (struct ifreq *) data;
1401 struct mii_data *mii;
1409 error = ether_ioctl(ifp, command, data);
1412 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1415 ifp->if_mtu = ifr->ifr_mtu;
1418 if (ifp->if_flags & IFF_UP) {
1419 if (ifp->if_flags & IFF_RUNNING &&
1420 ifp->if_flags & IFF_PROMISC &&
1421 !(sc->lge_if_flags & IFF_PROMISC)) {
1422 CSR_WRITE_4(sc, LGE_MODE1,
1423 LGE_MODE1_SETRST_CTL1|
1424 LGE_MODE1_RX_PROMISC);
1425 } else if (ifp->if_flags & IFF_RUNNING &&
1426 !(ifp->if_flags & IFF_PROMISC) &&
1427 sc->lge_if_flags & IFF_PROMISC) {
1428 CSR_WRITE_4(sc, LGE_MODE1,
1429 LGE_MODE1_RX_PROMISC);
1431 ifp->if_flags &= ~IFF_RUNNING;
1435 if (ifp->if_flags & IFF_RUNNING)
1438 sc->lge_if_flags = ifp->if_flags;
1448 mii = device_get_softc(sc->lge_miibus);
1449 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1462 lge_watchdog(struct ifnet *ifp)
1464 struct lge_softc *sc = ifp->if_softc;
1467 printf("lge%d: watchdog timeout\n", sc->lge_unit);
1471 ifp->if_flags &= ~IFF_RUNNING;
1474 if (!ifq_is_empty(&ifp->if_snd))
1475 (*ifp->if_start)(ifp);
1479 * Stop the adapter and free any mbufs allocated to the
1483 lge_stop(struct lge_softc *sc)
1485 struct ifnet *ifp = &sc->arpcom.ac_if;
1489 callout_stop(&sc->lge_stat_timer);
1490 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1492 /* Disable receiver and transmitter. */
1493 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1497 * Free data in the RX lists.
1499 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1500 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1501 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1502 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1505 bzero(&sc->lge_ldata->lge_rx_list, sizeof(sc->lge_ldata->lge_rx_list));
1508 * Free the TX list buffers.
1510 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1511 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1512 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1513 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1517 bzero(&sc->lge_ldata->lge_tx_list, sizeof(sc->lge_ldata->lge_tx_list));
1519 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1523 * Stop all chip I/O so that the kernel's probe routines don't
1524 * get confused by errant DMAs when rebooting.
1527 lge_shutdown(device_t dev)
1529 struct lge_softc *sc = device_get_softc(dev);