sys/dev/netif/sk/if_sk.c

   1 /*      $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */
   2
   3 /*
   4  * Copyright (c) 1997, 1998, 1999, 2000
   5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Bill Paul.
  18  * 4. Neither the name of the author nor the names of any co-contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  32  * THE POSSIBILITY OF SUCH DAMAGE.
  33  *
  34  * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $
  35  * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.14 2004/04/07 05:45:29 dillon Exp $
  36  *
  37  * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $
  38  */
  39
  40 /*
  41  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
  42  *
  43  * Permission to use, copy, modify, and distribute this software for any
  44  * purpose with or without fee is hereby granted, provided that the above
  45  * copyright notice and this permission notice appear in all copies.
  46  *
  47  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  48  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  49  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  50  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  51  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  52  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  53  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  54  */
  55
  56 /*
  57  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
  58  * the SK-984x series adapters, both single port and dual port.
  59  * References:
  60  *      The XaQti XMAC II datasheet,
  61  *  http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  62  *      The SysKonnect GEnesis manual, http://www.syskonnect.com
  63  *
  64  * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the
  65  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
  66  * convenience to others until Vitesse corrects this problem:
  67  *
  68  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  69  *
  70  * Written by Bill Paul <wpaul@ee.columbia.edu>
  71  * Department of Electrical Engineering
  72  * Columbia University, New York City
  73  */
  74
  75 /*
  76  * The SysKonnect gigabit ethernet adapters consist of two main
  77  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
  78  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
  79  * components and a PHY while the GEnesis controller provides a PCI
  80  * interface with DMA support. Each card may have between 512K and
  81  * 2MB of SRAM on board depending on the configuration.
  82  *
  83  * The SysKonnect GEnesis controller can have either one or two XMAC
  84  * chips connected to it, allowing single or dual port NIC configurations.
  85  * SysKonnect has the distinction of being the only vendor on the market
  86  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
  87  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
  88  * XMAC registers. This driver takes advantage of these features to allow
  89  * both XMACs to operate as independent interfaces.
  90  */
  91
  92 #include <sys/param.h>
  93 #include <sys/systm.h>
  94 #include <sys/sockio.h>
  95 #include <sys/mbuf.h>
  96 #include <sys/malloc.h>
  97 #include <sys/kernel.h>
  98 #include <sys/socket.h>
  99 #include <sys/queue.h>
 100
 101 #include <net/if.h>
 102 #include <net/if_arp.h>
 103 #include <net/ethernet.h>
 104 #include <net/if_dl.h>
 105 #include <net/if_media.h>
 106
 107 #include <net/bpf.h>
 108
 109 #include <vm/vm.h>              /* for vtophys */
 110 #include <vm/pmap.h>            /* for vtophys */
 111 #include <machine/clock.h>      /* for DELAY */
 112 #include <machine/bus_pio.h>
 113 #include <machine/bus_memio.h>
 114 #include <machine/bus.h>
 115 #include <machine/resource.h>
 116 #include <sys/bus.h>
 117 #include <sys/rman.h>
 118
 119 #include "../mii_layer/mii.h"
 120 #include "../mii_layer/miivar.h"
 121 #include "../mii_layer/brgphyreg.h"
 122
 123 #include <bus/pci/pcireg.h>
 124 #include <bus/pci/pcivar.h>
 125
 126 #if 0
 127 #define SK_USEIOSPACE
 128 #endif
 129
 130 #include "if_skreg.h"
 131 #include "xmaciireg.h"
 132 #include "yukonreg.h"
 133
 134 /* "controller miibus0" required.  See GENERIC if you get errors here. */
 135 #include "miibus_if.h"
 136
 137 static struct sk_type sk_devs[] = {
 138         {
 139                 VENDORID_SK,
 140                 DEVICEID_SK_V1,
 141                 "SysKonnect Gigabit Ethernet (V1.0)"
 142         },
 143         {
 144                 VENDORID_SK,
 145                 DEVICEID_SK_V2,
 146                 "SysKonnect Gigabit Ethernet (V2.0)"
 147         },
 148         {
 149                 VENDORID_MARVELL,
 150                 DEVICEID_SK_V2,
 151                 "Marvell Gigabit Ethernet"
 152         },
 153         {
 154                 VENDORID_3COM,
 155                 DEVICEID_3COM_3C940,
 156                 "3Com 3C940 Gigabit Ethernet"
 157         },
 158         { 0, 0, NULL }
 159 };
 160
 161 static int skc_probe            (device_t);
 162 static int skc_attach           (device_t);
 163 static int skc_detach           (device_t);
 164 static void skc_shutdown        (device_t);
 165 static int sk_probe             (device_t);
 166 static int sk_attach            (device_t);
 167 static int sk_detach            (device_t);
 168 static void sk_tick             (void *);
 169 static void sk_intr             (void *);
 170 static void sk_intr_bcom        (struct sk_if_softc *);
 171 static void sk_intr_xmac        (struct sk_if_softc *);
 172 static void sk_intr_yukon       (struct sk_if_softc *);
 173 static void sk_rxeof            (struct sk_if_softc *);
 174 static void sk_txeof            (struct sk_if_softc *);
 175 static int sk_encap             (struct sk_if_softc *, struct mbuf *,
 176                                         u_int32_t *);
 177 static void sk_start            (struct ifnet *);
 178 static int sk_ioctl             (struct ifnet *, u_long, caddr_t,
 179                                         struct ucred *);
 180 static void sk_init             (void *);
 181 static void sk_init_xmac        (struct sk_if_softc *);
 182 static void sk_init_yukon       (struct sk_if_softc *);
 183 static void sk_stop             (struct sk_if_softc *);
 184 static void sk_watchdog         (struct ifnet *);
 185 static int sk_ifmedia_upd       (struct ifnet *);
 186 static void sk_ifmedia_sts      (struct ifnet *, struct ifmediareq *);
 187 static void sk_reset            (struct sk_softc *);
 188 static int sk_newbuf            (struct sk_if_softc *,
 189                                         struct sk_chain *, struct mbuf *);
 190 static int sk_alloc_jumbo_mem   (struct sk_if_softc *);
 191 static void *sk_jalloc          (struct sk_if_softc *);
 192 static void sk_jfree            (caddr_t, u_int);
 193 static void sk_jref             (caddr_t, u_int);
 194 static int sk_init_rx_ring      (struct sk_if_softc *);
 195 static void sk_init_tx_ring     (struct sk_if_softc *);
 196 static u_int32_t sk_win_read_4  (struct sk_softc *, int);
 197 static u_int16_t sk_win_read_2  (struct sk_softc *, int);
 198 static u_int8_t sk_win_read_1   (struct sk_softc *, int);
 199 static void sk_win_write_4      (struct sk_softc *, int, u_int32_t);
 200 static void sk_win_write_2      (struct sk_softc *, int, u_int32_t);
 201 static void sk_win_write_1      (struct sk_softc *, int, u_int32_t);
 202 static u_int8_t sk_vpd_readbyte (struct sk_softc *, int);
 203 static void sk_vpd_read_res     (struct sk_softc *,
 204                                         struct vpd_res *, int);
 205 static void sk_vpd_read         (struct sk_softc *);
 206
 207 static int sk_miibus_readreg    (device_t, int, int);
 208 static int sk_miibus_writereg   (device_t, int, int, int);
 209 static void sk_miibus_statchg   (device_t);
 210
 211 static int sk_xmac_miibus_readreg     (struct sk_if_softc *, int, int);
 212 static int sk_xmac_miibus_writereg    (struct sk_if_softc *, int, int, int);
 213 static void sk_xmac_miibus_statchg    (struct sk_if_softc *);
 214
 215 static int sk_marv_miibus_readreg     (struct sk_if_softc *, int, int);
 216 static int sk_marv_miibus_writereg    (struct sk_if_softc *, int, int, int);
 217 static void sk_marv_miibus_statchg    (struct sk_if_softc *);
 218
 219 static u_int32_t xmac_calchash  (caddr_t);
 220 static u_int32_t gmac_calchash  (caddr_t);
 221 static void sk_setfilt          (struct sk_if_softc *, caddr_t, int);
 222 static void sk_setmulti         (struct sk_if_softc *);
 223 static void sk_setpromisc       (struct sk_if_softc *);
 224
 225 #ifdef SK_USEIOSPACE
 226 #define SK_RES          SYS_RES_IOPORT
 227 #define SK_RID          SK_PCI_LOIO
 228 #else
 229 #define SK_RES          SYS_RES_MEMORY
 230 #define SK_RID          SK_PCI_LOMEM
 231 #endif
 232
 233 /*
 234  * Note that we have newbus methods for both the GEnesis controller
 235  * itself and the XMAC(s). The XMACs are children of the GEnesis, and
 236  * the miibus code is a child of the XMACs. We need to do it this way
 237  * so that the miibus drivers can access the PHY registers on the
 238  * right PHY. It's not quite what I had in mind, but it's the only
 239  * design that achieves the desired effect.
 240  */
 241 static device_method_t skc_methods[] = {
 242         /* Device interface */
 243         DEVMETHOD(device_probe,         skc_probe),
 244         DEVMETHOD(device_attach,        skc_attach),
 245         DEVMETHOD(device_detach,        skc_detach),
 246         DEVMETHOD(device_shutdown,      skc_shutdown),
 247
 248         /* bus interface */
 249         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 250         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 251
 252         { 0, 0 }
 253 };
 254
 255 static driver_t skc_driver = {
 256         "skc",
 257         skc_methods,
 258         sizeof(struct sk_softc)
 259 };
 260
 261 static devclass_t skc_devclass;
 262
 263 static device_method_t sk_methods[] = {
 264         /* Device interface */
 265         DEVMETHOD(device_probe,         sk_probe),
 266         DEVMETHOD(device_attach,        sk_attach),
 267         DEVMETHOD(device_detach,        sk_detach),
 268         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 269
 270         /* bus interface */
 271         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 272         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 273
 274         /* MII interface */
 275         DEVMETHOD(miibus_readreg,       sk_miibus_readreg),
 276         DEVMETHOD(miibus_writereg,      sk_miibus_writereg),
 277         DEVMETHOD(miibus_statchg,       sk_miibus_statchg),
 278
 279         { 0, 0 }
 280 };
 281
 282 static driver_t sk_driver = {
 283         "sk",
 284         sk_methods,
 285         sizeof(struct sk_if_softc)
 286 };
 287
 288 static devclass_t sk_devclass;
 289
 290 DECLARE_DUMMY_MODULE(if_sk);
 291 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0);
 292 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0);
 293 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
 294
 295 #define SK_SETBIT(sc, reg, x)           \
 296         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
 297
 298 #define SK_CLRBIT(sc, reg, x)           \
 299         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
 300
 301 #define SK_WIN_SETBIT_4(sc, reg, x)     \
 302         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
 303
 304 #define SK_WIN_CLRBIT_4(sc, reg, x)     \
 305         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
 306
 307 #define SK_WIN_SETBIT_2(sc, reg, x)     \
 308         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
 309
 310 #define SK_WIN_CLRBIT_2(sc, reg, x)     \
 311         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
 312
 313 static u_int32_t sk_win_read_4(sc, reg)
 314         struct sk_softc         *sc;
 315         int                     reg;
 316 {
 317 #ifdef SK_USEIOSPACE
 318         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 319         return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
 320 #else
 321         return(CSR_READ_4(sc, reg));
 322 #endif
 323 }
 324
 325 static u_int16_t sk_win_read_2(sc, reg)
 326         struct sk_softc         *sc;
 327         int                     reg;
 328 {
 329 #ifdef SK_USEIOSPACE
 330         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 331         return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
 332 #else
 333         return(CSR_READ_2(sc, reg));
 334 #endif
 335 }
 336
 337 static u_int8_t sk_win_read_1(sc, reg)
 338         struct sk_softc         *sc;
 339         int                     reg;
 340 {
 341 #ifdef SK_USEIOSPACE
 342         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 343         return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
 344 #else
 345         return(CSR_READ_1(sc, reg));
 346 #endif
 347 }
 348
 349 static void sk_win_write_4(sc, reg, val)
 350         struct sk_softc         *sc;
 351         int                     reg;
 352         u_int32_t               val;
 353 {
 354 #ifdef SK_USEIOSPACE
 355         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 356         CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
 357 #else
 358         CSR_WRITE_4(sc, reg, val);
 359 #endif
 360         return;
 361 }
 362
 363 static void sk_win_write_2(sc, reg, val)
 364         struct sk_softc         *sc;
 365         int                     reg;
 366         u_int32_t               val;
 367 {
 368 #ifdef SK_USEIOSPACE
 369         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 370         CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
 371 #else
 372         CSR_WRITE_2(sc, reg, val);
 373 #endif
 374         return;
 375 }
 376
 377 static void sk_win_write_1(sc, reg, val)
 378         struct sk_softc         *sc;
 379         int                     reg;
 380         u_int32_t               val;
 381 {
 382 #ifdef SK_USEIOSPACE
 383         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 384         CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
 385 #else
 386         CSR_WRITE_1(sc, reg, val);
 387 #endif
 388         return;
 389 }
 390
 391 /*
 392  * The VPD EEPROM contains Vital Product Data, as suggested in
 393  * the PCI 2.1 specification. The VPD data is separared into areas
 394  * denoted by resource IDs. The SysKonnect VPD contains an ID string
 395  * resource (the name of the adapter), a read-only area resource
 396  * containing various key/data fields and a read/write area which
 397  * can be used to store asset management information or log messages.
 398  * We read the ID string and read-only into buffers attached to
 399  * the controller softc structure for later use. At the moment,
 400  * we only use the ID string during sk_attach().
 401  */
 402 static u_int8_t sk_vpd_readbyte(sc, addr)
 403         struct sk_softc         *sc;
 404         int                     addr;
 405 {
 406         int                     i;
 407
 408         sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr);
 409         for (i = 0; i < SK_TIMEOUT; i++) {
 410                 DELAY(1);
 411                 if (sk_win_read_2(sc,
 412                     SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG)
 413                         break;
 414         }
 415
 416         if (i == SK_TIMEOUT)
 417                 return(0);
 418
 419         return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)));
 420 }
 421
 422 static void sk_vpd_read_res(sc, res, addr)
 423         struct sk_softc         *sc;
 424         struct vpd_res          *res;
 425         int                     addr;
 426 {
 427         int                     i;
 428         u_int8_t                *ptr;
 429
 430         ptr = (u_int8_t *)res;
 431         for (i = 0; i < sizeof(struct vpd_res); i++)
 432                 ptr[i] = sk_vpd_readbyte(sc, i + addr);
 433
 434         return;
 435 }
 436
 437 static void sk_vpd_read(sc)
 438         struct sk_softc         *sc;
 439 {
 440         int                     pos = 0, i;
 441         struct vpd_res          res;
 442
 443         if (sc->sk_vpd_prodname != NULL)
 444                 free(sc->sk_vpd_prodname, M_DEVBUF);
 445         if (sc->sk_vpd_readonly != NULL)
 446                 free(sc->sk_vpd_readonly, M_DEVBUF);
 447         sc->sk_vpd_prodname = NULL;
 448         sc->sk_vpd_readonly = NULL;
 449
 450         sk_vpd_read_res(sc, &res, pos);
 451
 452         if (res.vr_id != VPD_RES_ID) {
 453                 printf("skc%d: bad VPD resource id: expected %x got %x\n",
 454                     sc->sk_unit, VPD_RES_ID, res.vr_id);
 455                 return;
 456         }
 457
 458         pos += sizeof(res);
 459         sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT);
 460         for (i = 0; i < res.vr_len; i++)
 461                 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos);
 462         sc->sk_vpd_prodname[i] = '\0';
 463         pos += i;
 464
 465         sk_vpd_read_res(sc, &res, pos);
 466
 467         if (res.vr_id != VPD_RES_READ) {
 468                 printf("skc%d: bad VPD resource id: expected %x got %x\n",
 469                     sc->sk_unit, VPD_RES_READ, res.vr_id);
 470                 return;
 471         }
 472
 473         pos += sizeof(res);
 474         sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT);
 475         for (i = 0; i < res.vr_len + 1; i++)
 476                 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos);
 477
 478         return;
 479 }
 480
 481 static int sk_miibus_readreg(dev, phy, reg)
 482         device_t                dev;
 483         int                     phy, reg;
 484 {
 485         struct sk_if_softc      *sc_if;
 486
 487         sc_if = device_get_softc(dev);
 488
 489         switch(sc_if->sk_softc->sk_type) {
 490         case SK_GENESIS:
 491                 return(sk_xmac_miibus_readreg(sc_if, phy, reg));
 492         case SK_YUKON:
 493                 return(sk_marv_miibus_readreg(sc_if, phy, reg));
 494         }
 495
 496         return(0);
 497 }
 498
 499 static int sk_miibus_writereg(dev, phy, reg, val)
 500         device_t                dev;
 501         int                     phy, reg, val;
 502 {
 503         struct sk_if_softc      *sc_if;
 504
 505         sc_if = device_get_softc(dev);
 506
 507         switch(sc_if->sk_softc->sk_type) {
 508         case SK_GENESIS:
 509                 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val));
 510         case SK_YUKON:
 511                 return(sk_marv_miibus_writereg(sc_if, phy, reg, val));
 512         }
 513
 514         return(0);
 515 }
 516
 517 static void sk_miibus_statchg(dev)
 518         device_t                dev;
 519 {
 520         struct sk_if_softc      *sc_if;
 521
 522         sc_if = device_get_softc(dev);
 523
 524         switch(sc_if->sk_softc->sk_type) {
 525         case SK_GENESIS:
 526                 sk_xmac_miibus_statchg(sc_if);
 527                 break;
 528         case SK_YUKON:
 529                 sk_marv_miibus_statchg(sc_if);
 530                 break;
 531         }
 532
 533         return;
 534 }
 535
 536 static int sk_xmac_miibus_readreg(sc_if, phy, reg)
 537         struct sk_if_softc      *sc_if;
 538         int                     phy, reg;
 539 {
 540         int                     i;
 541
 542         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
 543                 return(0);
 544
 545         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 546         SK_XM_READ_2(sc_if, XM_PHY_DATA);
 547         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 548                 for (i = 0; i < SK_TIMEOUT; i++) {
 549                         DELAY(1);
 550                         if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
 551                             XM_MMUCMD_PHYDATARDY)
 552                                 break;
 553                 }
 554
 555                 if (i == SK_TIMEOUT) {
 556                         printf("sk%d: phy failed to come ready\n",
 557                             sc_if->sk_unit);
 558                         return(0);
 559                 }
 560         }
 561         DELAY(1);
 562         return(SK_XM_READ_2(sc_if, XM_PHY_DATA));
 563 }
 564
 565 static int sk_xmac_miibus_writereg(sc_if, phy, reg, val)
 566         struct sk_if_softc      *sc_if;
 567         int                     phy, reg, val;
 568 {
 569         int                     i;
 570
 571         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 572         for (i = 0; i < SK_TIMEOUT; i++) {
 573                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 574                         break;
 575         }
 576
 577         if (i == SK_TIMEOUT) {
 578                 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit);
 579                 return(ETIMEDOUT);
 580         }
 581
 582         SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
 583         for (i = 0; i < SK_TIMEOUT; i++) {
 584                 DELAY(1);
 585                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 586                         break;
 587         }
 588
 589         if (i == SK_TIMEOUT)
 590                 printf("sk%d: phy write timed out\n", sc_if->sk_unit);
 591
 592         return(0);
 593 }
 594
 595 static void sk_xmac_miibus_statchg(sc_if)
 596         struct sk_if_softc      *sc_if;
 597 {
 598         struct mii_data         *mii;
 599
 600         mii = device_get_softc(sc_if->sk_miibus);
 601
 602         /*
 603          * If this is a GMII PHY, manually set the XMAC's
 604          * duplex mode accordingly.
 605          */
 606         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 607                 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 608                         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 609                 } else {
 610                         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 611                 }
 612         }
 613
 614         return;
 615 }
 616
 617 static int sk_marv_miibus_readreg(sc_if, phy, reg)
 618         struct sk_if_softc      *sc_if;
 619         int                     phy, reg;
 620 {
 621         u_int16_t               val;
 622         int                     i;
 623
 624         if (phy != 0 ||
 625             (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
 626              sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
 627                 return(0);
 628         }
 629
 630         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 631                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
 632
 633         for (i = 0; i < SK_TIMEOUT; i++) {
 634                 DELAY(1);
 635                 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
 636                 if (val & YU_SMICR_READ_VALID)
 637                         break;
 638         }
 639
 640         if (i == SK_TIMEOUT) {
 641                 printf("sk%d: phy failed to come ready\n",
 642                     sc_if->sk_unit);
 643                 return(0);
 644         }
 645
 646         val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
 647
 648         return(val);
 649 }
 650
 651 static int sk_marv_miibus_writereg(sc_if, phy, reg, val)
 652         struct sk_if_softc      *sc_if;
 653         int                     phy, reg, val;
 654 {
 655         int                     i;
 656
 657         SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
 658         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 659                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
 660
 661         for (i = 0; i < SK_TIMEOUT; i++) {
 662                 DELAY(1);
 663                 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)
 664                         break;
 665         }
 666
 667         return(0);
 668 }
 669
 670 static void sk_marv_miibus_statchg(sc_if)
 671         struct sk_if_softc      *sc_if;
 672 {
 673         return;
 674 }
 675
 676 #define XMAC_POLY               0xEDB88320
 677 #define GMAC_POLY               0x04C11DB7L
 678 #define HASH_BITS               6
 679
 680 static u_int32_t xmac_calchash(addr)
 681         caddr_t                 addr;
 682 {
 683         u_int32_t               idx, bit, data, crc;
 684
 685         /* Compute CRC for the address value. */
 686         crc = 0xFFFFFFFF; /* initial value */
 687
 688         for (idx = 0; idx < 6; idx++) {
 689                 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
 690                         crc = (crc >> 1) ^ (((crc ^ data) & 1) ? XMAC_POLY : 0);
 691         }
 692
 693         return (~crc & ((1 << HASH_BITS) - 1));
 694 }
 695
 696 static u_int32_t gmac_calchash(addr)
 697     caddr_t                     addr;
 698 {
 699     u_int32_t               idx, bit, crc, tmpData, data;
 700
 701     /* Compute CRC for the address value. */
 702     crc = 0xFFFFFFFF; /* initial value */
 703
 704     for (idx = 0; idx < 6; idx++) {
 705         data = *addr++;
 706
 707         /* Change bit order in byte. */
 708         tmpData = data;
 709         for (bit = 0; bit < 8; bit++) {
 710             if (tmpData & 1) {
 711                 data |=  1 << (7 - bit);
 712             }
 713             else {
 714                 data &= ~(1 << (7 - bit));
 715             }
 716
 717             tmpData >>= 1;
 718         }
 719
 720         crc ^= (data << 24);
 721         for (bit = 0; bit < 8; bit++) {
 722             if (crc & 0x80000000) {
 723                 crc = (crc << 1) ^ GMAC_POLY;
 724             } else {
 725                 crc <<= 1;
 726             }
 727         }
 728     }
 729
 730     return (crc & ((1 << HASH_BITS) - 1));
 731 }
 732
 733 static void sk_setfilt(sc_if, addr, slot)
 734         struct sk_if_softc      *sc_if;
 735         caddr_t                 addr;
 736         int                     slot;
 737 {
 738         int                     base;
 739
 740         base = XM_RXFILT_ENTRY(slot);
 741
 742         SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0]));
 743         SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2]));
 744         SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4]));
 745
 746         return;
 747 }
 748
 749 static void sk_setmulti(sc_if)
 750         struct sk_if_softc      *sc_if;
 751 {
 752         struct sk_softc         *sc = sc_if->sk_softc;
 753         struct ifnet            *ifp = &sc_if->arpcom.ac_if;
 754         u_int32_t               hashes[2] = { 0, 0 };
 755         int                     h, i;
 756         struct ifmultiaddr      *ifma;
 757         u_int8_t                dummy[] = { 0, 0, 0, 0, 0 ,0 };
 758
 759
 760         /* First, zot all the existing filters. */
 761         switch(sc->sk_type) {
 762         case SK_GENESIS:
 763                 for (i = 1; i < XM_RXFILT_MAX; i++)
 764                         sk_setfilt(sc_if, (caddr_t)&dummy, i);
 765
 766                 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
 767                 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
 768                 break;
 769         case SK_YUKON:
 770                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
 771                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
 772                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
 773                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
 774                 break;
 775         }
 776
 777         /* Now program new ones. */
 778         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 779                 hashes[0] = 0xFFFFFFFF;
 780                 hashes[1] = 0xFFFFFFFF;
 781         } else {
 782                 i = 1;
 783                 /* First find the tail of the list. */
 784                 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
 785                                         ifma = ifma->ifma_link.le_next) {
 786                         if (ifma->ifma_link.le_next == NULL)
 787                                 break;
 788                 }
 789                 /* Now traverse the list backwards. */
 790                 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
 791                         ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
 792                         if (ifma->ifma_addr->sa_family != AF_LINK)
 793                                 continue;
 794                         /*
 795                          * Program the first XM_RXFILT_MAX multicast groups
 796                          * into the perfect filter. For all others,
 797                          * use the hash table.
 798                          */
 799                         if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) {
 800                                 sk_setfilt(sc_if,
 801                         LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
 802                                 i++;
 803                                 continue;
 804                         }
 805
 806                         switch(sc->sk_type) {
 807                         case SK_GENESIS:
 808                             h = xmac_calchash(
 809                                 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
 810                             if (h < 32)
 811                                 hashes[0] |= (1 << h);
 812                             else
 813                                 hashes[1] |= (1 << (h - 32));
 814                             break;
 815
 816                         case SK_YUKON:
 817                             h = gmac_calchash(
 818                                 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
 819                             if (h < 32)
 820                                 hashes[0] |= (1 << h);
 821                             else
 822                                 hashes[1] |= (1 << (h - 32));
 823                             break;
 824                         }
 825                 }
 826         }
 827
 828         switch(sc->sk_type) {
 829         case SK_GENESIS:
 830                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
 831                                XM_MODE_RX_USE_PERFECT);
 832                 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
 833                 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
 834                 break;
 835         case SK_YUKON:
 836                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
 837                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
 838                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
 839                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
 840                 break;
 841         }
 842
 843         return;
 844 }
 845
 846 static void sk_setpromisc(sc_if)
 847         struct sk_if_softc      *sc_if;
 848 {
 849         struct sk_softc         *sc = sc_if->sk_softc;
 850         struct ifnet            *ifp = &sc_if->arpcom.ac_if;
 851
 852         switch(sc->sk_type) {
 853         case SK_GENESIS:
 854                 if (ifp->if_flags & IFF_PROMISC) {
 855                         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 856                 } else {
 857                         SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 858                 }
 859                 break;
 860         case SK_YUKON:
 861                 if (ifp->if_flags & IFF_PROMISC) {
 862                         SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
 863                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 864                 } else {
 865                         SK_YU_SETBIT_2(sc_if, YUKON_RCR,
 866                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 867                 }
 868                 break;
 869         }
 870
 871         return;
 872 }
 873
 874 static int sk_init_rx_ring(sc_if)
 875         struct sk_if_softc      *sc_if;
 876 {
 877         struct sk_chain_data    *cd = &sc_if->sk_cdata;
 878         struct sk_ring_data     *rd = sc_if->sk_rdata;
 879         int                     i;
 880
 881         bzero((char *)rd->sk_rx_ring,
 882             sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
 883
 884         for (i = 0; i < SK_RX_RING_CNT; i++) {
 885                 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i];
 886                 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS)
 887                         return(ENOBUFS);
 888                 if (i == (SK_RX_RING_CNT - 1)) {
 889                         cd->sk_rx_chain[i].sk_next =
 890                             &cd->sk_rx_chain[0];
 891                         rd->sk_rx_ring[i].sk_next =
 892                             vtophys(&rd->sk_rx_ring[0]);
 893                 } else {
 894                         cd->sk_rx_chain[i].sk_next =
 895                             &cd->sk_rx_chain[i + 1];
 896                         rd->sk_rx_ring[i].sk_next =
 897                             vtophys(&rd->sk_rx_ring[i + 1]);
 898                 }
 899         }
 900
 901         sc_if->sk_cdata.sk_rx_prod = 0;
 902         sc_if->sk_cdata.sk_rx_cons = 0;
 903
 904         return(0);
 905 }
 906
 907 static void sk_init_tx_ring(sc_if)
 908         struct sk_if_softc      *sc_if;
 909 {
 910         struct sk_chain_data    *cd = &sc_if->sk_cdata;
 911         struct sk_ring_data     *rd = sc_if->sk_rdata;
 912         int                     i;
 913
 914         bzero((char *)sc_if->sk_rdata->sk_tx_ring,
 915             sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
 916
 917         for (i = 0; i < SK_TX_RING_CNT; i++) {
 918                 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i];
 919                 if (i == (SK_TX_RING_CNT - 1)) {
 920                         cd->sk_tx_chain[i].sk_next =
 921                             &cd->sk_tx_chain[0];
 922                         rd->sk_tx_ring[i].sk_next =
 923                             vtophys(&rd->sk_tx_ring[0]);
 924                 } else {
 925                         cd->sk_tx_chain[i].sk_next =
 926                             &cd->sk_tx_chain[i + 1];
 927                         rd->sk_tx_ring[i].sk_next =
 928                             vtophys(&rd->sk_tx_ring[i + 1]);
 929                 }
 930         }
 931
 932         sc_if->sk_cdata.sk_tx_prod = 0;
 933         sc_if->sk_cdata.sk_tx_cons = 0;
 934         sc_if->sk_cdata.sk_tx_cnt = 0;
 935
 936         return;
 937 }
 938
 939 static int sk_newbuf(sc_if, c, m)
 940         struct sk_if_softc      *sc_if;
 941         struct sk_chain         *c;
 942         struct mbuf             *m;
 943 {
 944         struct mbuf             *m_new = NULL;
 945         struct sk_rx_desc       *r;
 946
 947         if (m == NULL) {
 948                 caddr_t                 *buf = NULL;
 949
 950                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 951                 if (m_new == NULL)
 952                         return(ENOBUFS);
 953
 954                 /* Allocate the jumbo buffer */
 955                 buf = sk_jalloc(sc_if);
 956                 if (buf == NULL) {
 957                         m_freem(m_new);
 958 #ifdef SK_VERBOSE
 959                         printf("sk%d: jumbo allocation failed "
 960                             "-- packet dropped!\n", sc_if->sk_unit);
 961 #endif
 962                         return(ENOBUFS);
 963                 }
 964
 965                 /* Attach the buffer to the mbuf */
 966                 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
 967                 m_new->m_flags |= M_EXT;
 968                 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
 969                     m_new->m_len = SK_MCLBYTES;
 970                 m_new->m_ext.ext_free = sk_jfree;
 971                 m_new->m_ext.ext_ref = sk_jref;
 972         } else {
 973                 /*
 974                  * We're re-using a previously allocated mbuf;
 975                  * be sure to re-init pointers and lengths to
 976                  * default values.
 977                  */
 978                 m_new = m;
 979                 m_new->m_len = m_new->m_pkthdr.len = SK_MCLBYTES;
 980                 m_new->m_data = m_new->m_ext.ext_buf;
 981         }
 982
 983         /*
 984          * Adjust alignment so packet payload begins on a
 985          * longword boundary. Mandatory for Alpha, useful on
 986          * x86 too.
 987          */
 988         m_adj(m_new, ETHER_ALIGN);
 989
 990         r = c->sk_desc;
 991         c->sk_mbuf = m_new;
 992         r->sk_data_lo = vtophys(mtod(m_new, caddr_t));
 993         r->sk_ctl = m_new->m_len | SK_RXSTAT;
 994
 995         return(0);
 996 }
 997
 998 /*
 999  * Allocate jumbo buffer storage. The SysKonnect adapters support
1000  * "jumbograms" (9K frames), although SysKonnect doesn't currently
1001  * use them in their drivers. In order for us to use them, we need
1002  * large 9K receive buffers, however standard mbuf clusters are only
1003  * 2048 bytes in size. Consequently, we need to allocate and manage
1004  * our own jumbo buffer pool. Fortunately, this does not require an
1005  * excessive amount of additional code.
1006  */
1007 static int sk_alloc_jumbo_mem(sc_if)
1008         struct sk_if_softc      *sc_if;
1009 {
1010         caddr_t                 ptr;
1011         int             i;
1012         struct sk_jpool_entry   *entry;
1013
1014         /* Grab a big chunk o' storage. */
1015         sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF,
1016             M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1017
1018         if (sc_if->sk_cdata.sk_jumbo_buf == NULL) {
1019                 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit);
1020                 return(ENOBUFS);
1021         }
1022
1023         SLIST_INIT(&sc_if->sk_jfree_listhead);
1024         SLIST_INIT(&sc_if->sk_jinuse_listhead);
1025
1026         /*
1027          * Now divide it up into 9K pieces and save the addresses
1028          * in an array. Note that we play an evil trick here by using
1029          * the first few bytes in the buffer to hold the the address
1030          * of the softc structure for this interface. This is because
1031          * sk_jfree() needs it, but it is called by the mbuf management
1032          * code which will not pass it to us explicitly.
1033          */
1034         ptr = sc_if->sk_cdata.sk_jumbo_buf;
1035         for (i = 0; i < SK_JSLOTS; i++) {
1036                 u_int64_t               **aptr;
1037                 aptr = (u_int64_t **)ptr;
1038                 aptr[0] = (u_int64_t *)sc_if;
1039                 ptr += sizeof(u_int64_t);
1040                 sc_if->sk_cdata.sk_jslots[i].sk_buf = ptr;
1041                 sc_if->sk_cdata.sk_jslots[i].sk_inuse = 0;
1042                 ptr += SK_MCLBYTES;
1043                 entry = malloc(sizeof(struct sk_jpool_entry),
1044                     M_DEVBUF, M_WAITOK);
1045                 if (entry == NULL) {
1046                         free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF);
1047                         sc_if->sk_cdata.sk_jumbo_buf = NULL;
1048                         printf("sk%d: no memory for jumbo "
1049                             "buffer queue!\n", sc_if->sk_unit);
1050                         return(ENOBUFS);
1051                 }
1052                 entry->slot = i;
1053                 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
1054                     entry, jpool_entries);
1055         }
1056
1057         return(0);
1058 }
1059
1060 /*
1061  * Allocate a jumbo buffer.
1062  */
1063 static void *sk_jalloc(sc_if)
1064         struct sk_if_softc      *sc_if;
1065 {
1066         struct sk_jpool_entry   *entry;
1067
1068         entry = SLIST_FIRST(&sc_if->sk_jfree_listhead);
1069
1070         if (entry == NULL) {
1071 #ifdef SK_VERBOSE
1072                 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit);
1073 #endif
1074                 return(NULL);
1075         }
1076
1077         SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries);
1078         SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries);
1079         sc_if->sk_cdata.sk_jslots[entry->slot].sk_inuse = 1;
1080         return(sc_if->sk_cdata.sk_jslots[entry->slot].sk_buf);
1081 }
1082
1083 /*
1084  * Adjust usage count on a jumbo buffer. In general this doesn't
1085  * get used much because our jumbo buffers don't get passed around
1086  * a lot, but it's implemented for correctness.
1087  */
1088 static void sk_jref(buf, size)
1089         caddr_t                 buf;
1090         u_int                   size;
1091 {
1092         struct sk_if_softc      *sc_if;
1093         u_int64_t               **aptr;
1094         int             i;
1095
1096         /* Extract the softc struct pointer. */
1097         aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
1098         sc_if = (struct sk_if_softc *)(aptr[0]);
1099
1100         if (sc_if == NULL)
1101                 panic("sk_jref: can't find softc pointer!");
1102
1103         if (size != SK_MCLBYTES)
1104                 panic("sk_jref: adjusting refcount of buf of wrong size!");
1105
1106         /* calculate the slot this buffer belongs to */
1107
1108         i = ((vm_offset_t)aptr
1109              - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN;
1110
1111         if ((i < 0) || (i >= SK_JSLOTS))
1112                 panic("sk_jref: asked to reference buffer "
1113                     "that we don't manage!");
1114         else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0)
1115                 panic("sk_jref: buffer already free!");
1116         else
1117                 sc_if->sk_cdata.sk_jslots[i].sk_inuse++;
1118
1119         return;
1120 }
1121
1122 /*
1123  * Release a jumbo buffer.
1124  */
1125 static void sk_jfree(buf, size)
1126         caddr_t                 buf;
1127         u_int                   size;
1128 {
1129         struct sk_if_softc      *sc_if;
1130         u_int64_t               **aptr;
1131         int                     i;
1132         struct sk_jpool_entry   *entry;
1133
1134         /* Extract the softc struct pointer. */
1135         aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
1136         sc_if = (struct sk_if_softc *)(aptr[0]);
1137
1138         if (sc_if == NULL)
1139                 panic("sk_jfree: can't find softc pointer!");
1140
1141         if (size != SK_MCLBYTES)
1142                 panic("sk_jfree: freeing buffer of wrong size!");
1143
1144         /* calculate the slot this buffer belongs to */
1145
1146         i = ((vm_offset_t)aptr
1147              - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN;
1148
1149         if ((i < 0) || (i >= SK_JSLOTS))
1150                 panic("sk_jfree: asked to free buffer that we don't manage!");
1151         else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0)
1152                 panic("sk_jfree: buffer already free!");
1153         else {
1154                 sc_if->sk_cdata.sk_jslots[i].sk_inuse--;
1155                 if(sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) {
1156                         entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead);
1157                         if (entry == NULL)
1158                                 panic("sk_jfree: buffer not in use!");
1159                         entry->slot = i;
1160                         SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead,
1161                                           jpool_entries);
1162                         SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
1163                                           entry, jpool_entries);
1164                 }
1165         }
1166
1167         return;
1168 }
1169
1170 /*
1171  * Set media options.
1172  */
1173 static int sk_ifmedia_upd(ifp)
1174         struct ifnet            *ifp;
1175 {
1176         struct sk_if_softc      *sc_if = ifp->if_softc;
1177         struct mii_data         *mii;
1178
1179         mii = device_get_softc(sc_if->sk_miibus);
1180         sk_init(sc_if);
1181         mii_mediachg(mii);
1182
1183         return(0);
1184 }
1185
1186 /*
1187  * Report current media status.
1188  */
1189 static void sk_ifmedia_sts(ifp, ifmr)
1190         struct ifnet            *ifp;
1191         struct ifmediareq       *ifmr;
1192 {
1193         struct sk_if_softc      *sc_if;
1194         struct mii_data         *mii;
1195
1196         sc_if = ifp->if_softc;
1197         mii = device_get_softc(sc_if->sk_miibus);
1198
1199         mii_pollstat(mii);
1200         ifmr->ifm_active = mii->mii_media_active;
1201         ifmr->ifm_status = mii->mii_media_status;
1202
1203         return;
1204 }
1205
1206 static int sk_ioctl(ifp, command, data, cr)
1207         struct ifnet            *ifp;
1208         u_long                  command;
1209         caddr_t                 data;
1210         struct ucred            *cr;
1211 {
1212         struct sk_if_softc      *sc_if = ifp->if_softc;
1213         struct ifreq            *ifr = (struct ifreq *) data;
1214         int                     s, error = 0;
1215         struct mii_data         *mii;
1216
1217         s = splimp();
1218
1219         switch(command) {
1220         case SIOCSIFADDR:
1221         case SIOCGIFADDR:
1222                 error = ether_ioctl(ifp, command, data);
1223                 break;
1224         case SIOCSIFMTU:
1225                 if (ifr->ifr_mtu > SK_JUMBO_MTU)
1226                         error = EINVAL;
1227                 else {
1228                         ifp->if_mtu = ifr->ifr_mtu;
1229                         sk_init(sc_if);
1230                 }
1231                 break;
1232         case SIOCSIFFLAGS:
1233                 if (ifp->if_flags & IFF_UP) {
1234                         if (ifp->if_flags & IFF_RUNNING) {
1235                                 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1236                                     & IFF_PROMISC) {
1237                                         sk_setpromisc(sc_if);
1238                                         sk_setmulti(sc_if);
1239                                 }
1240                         } else
1241                                 sk_init(sc_if);
1242                 } else {
1243                         if (ifp->if_flags & IFF_RUNNING)
1244                                 sk_stop(sc_if);
1245                 }
1246                 sc_if->sk_if_flags = ifp->if_flags;
1247                 error = 0;
1248                 break;
1249         case SIOCADDMULTI:
1250         case SIOCDELMULTI:
1251                 sk_setmulti(sc_if);
1252                 error = 0;
1253                 break;
1254         case SIOCGIFMEDIA:
1255         case SIOCSIFMEDIA:
1256                 mii = device_get_softc(sc_if->sk_miibus);
1257                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1258                 break;
1259         default:
1260                 error = EINVAL;
1261                 break;
1262         }
1263
1264         (void)splx(s);
1265
1266         return(error);
1267 }
1268
1269 /*
1270  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1271  * IDs against our list and return a device name if we find a match.
1272  */
1273 static int skc_probe(dev)
1274         device_t                dev;
1275 {
1276         struct sk_softc         *sc;
1277         struct sk_type          *t = sk_devs;
1278
1279         sc = device_get_softc(dev);
1280
1281         while(t->sk_name != NULL) {
1282                 if ((pci_get_vendor(dev) == t->sk_vid) &&
1283                     (pci_get_device(dev) == t->sk_did)) {
1284                         device_set_desc(dev, t->sk_name);
1285                         return(0);
1286                 }
1287                 t++;
1288         }
1289
1290         return(ENXIO);
1291 }
1292
1293 /*
1294  * Force the GEnesis into reset, then bring it out of reset.
1295  */
1296 static void sk_reset(sc)
1297         struct sk_softc         *sc;
1298 {
1299         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1300         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1301         if (sc->sk_type == SK_YUKON)
1302                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1303
1304         DELAY(1000);
1305         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1306         DELAY(2);
1307         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1308         if (sc->sk_type == SK_YUKON)
1309                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1310
1311         if (sc->sk_type == SK_GENESIS) {
1312                 /* Configure packet arbiter */
1313                 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1314                 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1315                 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1316                 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1317                 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1318         }
1319
1320         /* Enable RAM interface */
1321         sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1322
1323         /*
1324          * Configure interrupt moderation. The moderation timer
1325          * defers interrupts specified in the interrupt moderation
1326          * timer mask based on the timeout specified in the interrupt
1327          * moderation timer init register. Each bit in the timer
1328          * register represents 18.825ns, so to specify a timeout in
1329          * microseconds, we have to multiply by 54.
1330          */
1331         sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200));
1332         sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1333             SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1334         sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1335
1336         return;
1337 }
1338
1339 static int sk_probe(dev)
1340         device_t                dev;
1341 {
1342         struct sk_softc         *sc;
1343
1344         sc = device_get_softc(device_get_parent(dev));
1345
1346         /*
1347          * Not much to do here. We always know there will be
1348          * at least one XMAC present, and if there are two,
1349          * skc_attach() will create a second device instance
1350          * for us.
1351          */
1352         switch (sc->sk_type) {
1353         case SK_GENESIS:
1354                 device_set_desc(dev, "XaQti Corp. XMAC II");
1355                 break;
1356         case SK_YUKON:
1357                 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1358                 break;
1359         }
1360
1361         return(0);
1362 }
1363
1364 /*
1365  * Each XMAC chip is attached as a separate logical IP interface.
1366  * Single port cards will have only one logical interface of course.
1367  */
1368 static int sk_attach(dev)
1369         device_t                dev;
1370 {
1371         struct sk_softc         *sc;
1372         struct sk_if_softc      *sc_if;
1373         struct ifnet            *ifp;
1374         int                     i, port;
1375
1376         if (dev == NULL)
1377                 return(EINVAL);
1378
1379         sc_if = device_get_softc(dev);
1380         sc = device_get_softc(device_get_parent(dev));
1381         port = *(int *)device_get_ivars(dev);
1382         free(device_get_ivars(dev), M_DEVBUF);
1383         device_set_ivars(dev, NULL);
1384         sc_if->sk_dev = dev;
1385
1386         bzero((char *)sc_if, sizeof(struct sk_if_softc));
1387
1388         sc_if->sk_dev = dev;
1389         sc_if->sk_unit = device_get_unit(dev);
1390         sc_if->sk_port = port;
1391         sc_if->sk_softc = sc;
1392         sc->sk_if[port] = sc_if;
1393         if (port == SK_PORT_A)
1394                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1395         if (port == SK_PORT_B)
1396                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1397
1398         /*
1399          * Get station address for this interface. Note that
1400          * dual port cards actually come with three station
1401          * addresses: one for each port, plus an extra. The
1402          * extra one is used by the SysKonnect driver software
1403          * as a 'virtual' station address for when both ports
1404          * are operating in failover mode. Currently we don't
1405          * use this extra address.
1406          */
1407         for (i = 0; i < ETHER_ADDR_LEN; i++)
1408                 sc_if->arpcom.ac_enaddr[i] =
1409                     sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1410
1411         printf("sk%d: Ethernet address: %6D\n",
1412             sc_if->sk_unit, sc_if->arpcom.ac_enaddr, ":");
1413
1414         /*
1415          * Set up RAM buffer addresses. The NIC will have a certain
1416          * amount of SRAM on it, somewhere between 512K and 2MB. We
1417          * need to divide this up a) between the transmitter and
1418          * receiver and b) between the two XMACs, if this is a
1419          * dual port NIC. Our algotithm is to divide up the memory
1420          * evenly so that everyone gets a fair share.
1421          */
1422         if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1423                 u_int32_t               chunk, val;
1424
1425                 chunk = sc->sk_ramsize / 2;
1426                 val = sc->sk_rboff / sizeof(u_int64_t);
1427                 sc_if->sk_rx_ramstart = val;
1428                 val += (chunk / sizeof(u_int64_t));
1429                 sc_if->sk_rx_ramend = val - 1;
1430                 sc_if->sk_tx_ramstart = val;
1431                 val += (chunk / sizeof(u_int64_t));
1432                 sc_if->sk_tx_ramend = val - 1;
1433         } else {
1434                 u_int32_t               chunk, val;
1435
1436                 chunk = sc->sk_ramsize / 4;
1437                 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1438                     sizeof(u_int64_t);
1439                 sc_if->sk_rx_ramstart = val;
1440                 val += (chunk / sizeof(u_int64_t));
1441                 sc_if->sk_rx_ramend = val - 1;
1442                 sc_if->sk_tx_ramstart = val;
1443                 val += (chunk / sizeof(u_int64_t));
1444                 sc_if->sk_tx_ramend = val - 1;
1445         }
1446
1447         /* Read and save PHY type and set PHY address */
1448         sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1449         switch(sc_if->sk_phytype) {
1450         case SK_PHYTYPE_XMAC:
1451                 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1452                 break;
1453         case SK_PHYTYPE_BCOM:
1454                 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1455                 break;
1456         case SK_PHYTYPE_MARV_COPPER:
1457                 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1458                 break;
1459         default:
1460                 printf("skc%d: unsupported PHY type: %d\n",
1461                     sc->sk_unit, sc_if->sk_phytype);
1462                 return(ENODEV);
1463         }
1464
1465         /* Allocate the descriptor queues. */
1466         sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF,
1467             M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1468
1469         if (sc_if->sk_rdata == NULL) {
1470                 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit);
1471                 sc->sk_if[port] = NULL;
1472                 return(ENOMEM);
1473         }
1474
1475         bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data));
1476
1477         /* Try to allocate memory for jumbo buffers. */
1478         if (sk_alloc_jumbo_mem(sc_if)) {
1479                 printf("sk%d: jumbo buffer allocation failed\n",
1480                     sc_if->sk_unit);
1481                 contigfree(sc_if->sk_rdata,
1482                     sizeof(struct sk_ring_data), M_DEVBUF);
1483                 sc->sk_if[port] = NULL;
1484                 return(ENOMEM);
1485         }
1486
1487         ifp = &sc_if->arpcom.ac_if;
1488         ifp->if_softc = sc_if;
1489         if_initname(ifp, "sk", sc_if->sk_unit);
1490         ifp->if_mtu = ETHERMTU;
1491         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1492         ifp->if_ioctl = sk_ioctl;
1493         ifp->if_output = ether_output;
1494         ifp->if_start = sk_start;
1495         ifp->if_watchdog = sk_watchdog;
1496         ifp->if_init = sk_init;
1497         ifp->if_baudrate = 1000000000;
1498         ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1;
1499
1500         /*
1501          * Do miibus setup.
1502          */
1503         switch (sc->sk_type) {
1504         case SK_GENESIS:
1505                 sk_init_xmac(sc_if);
1506                 break;
1507         case SK_YUKON:
1508                 sk_init_yukon(sc_if);
1509                 break;
1510         }
1511
1512         if (mii_phy_probe(dev, &sc_if->sk_miibus,
1513             sk_ifmedia_upd, sk_ifmedia_sts)) {
1514                 printf("skc%d: no PHY found!\n", sc_if->sk_unit);
1515                 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM,
1516                     M_DEVBUF);
1517                 contigfree(sc_if->sk_rdata,
1518                     sizeof(struct sk_ring_data), M_DEVBUF);
1519                 return(ENXIO);
1520         }
1521
1522         /*
1523          * Call MI attach routine.
1524          */
1525         ether_ifattach(ifp, sc_if->arpcom.ac_enaddr);
1526         callout_handle_init(&sc_if->sk_tick_ch);
1527
1528         return(0);
1529 }
1530
1531 /*
1532  * Attach the interface. Allocate softc structures, do ifmedia
1533  * setup and ethernet/BPF attach.
1534  */
1535 static int skc_attach(dev)
1536         device_t                dev;
1537 {
1538         int                     s;
1539         u_int32_t               command;
1540         struct sk_softc         *sc;
1541         int                     unit, error = 0, rid, *port;
1542
1543         s = splimp();
1544
1545         sc = device_get_softc(dev);
1546         unit = device_get_unit(dev);
1547         bzero(sc, sizeof(struct sk_softc));
1548         switch (pci_get_device(dev)) {
1549         case DEVICEID_SK_V1:
1550                 sc->sk_type = SK_GENESIS;
1551                 break;
1552         case DEVICEID_SK_V2:
1553         case DEVICEID_3COM_3C940:
1554                 sc->sk_type = SK_YUKON;
1555                 break;
1556         }
1557
1558         /*
1559          * Handle power management nonsense.
1560          */
1561         command = pci_read_config(dev, SK_PCI_CAPID, 4) & 0x000000FF;
1562         if (command == 0x01) {
1563                 command = pci_read_config(dev, SK_PCI_PWRMGMTCTRL, 4);
1564                 if (command & SK_PSTATE_MASK) {
1565                         u_int32_t               iobase, membase, irq;
1566
1567                         /* Save important PCI config data. */
1568                         iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1569                         membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1570                         irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1571
1572                         /* Reset the power state. */
1573                         printf("skc%d: chip is in D%d power mode "
1574                         "-- setting to D0\n", unit, command & SK_PSTATE_MASK);
1575                         command &= 0xFFFFFFFC;
1576                         pci_write_config(dev, SK_PCI_PWRMGMTCTRL, command, 4);
1577
1578                         /* Restore PCI config data. */
1579                         pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1580                         pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1581                         pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
1582                 }
1583         }
1584
1585         /*
1586          * Map control/status registers.
1587          */
1588         command = pci_read_config(dev, PCIR_COMMAND, 4);
1589         command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1590         pci_write_config(dev, PCIR_COMMAND, command, 4);
1591         command = pci_read_config(dev, PCIR_COMMAND, 4);
1592
1593 #ifdef SK_USEIOSPACE
1594         if (!(command & PCIM_CMD_PORTEN)) {
1595                 printf("skc%d: failed to enable I/O ports!\n", unit);
1596                 error = ENXIO;
1597                 goto fail;
1598         }
1599 #else
1600         if (!(command & PCIM_CMD_MEMEN)) {
1601                 printf("skc%d: failed to enable memory mapping!\n", unit);
1602                 error = ENXIO;
1603                 goto fail;
1604         }
1605 #endif
1606
1607         rid = SK_RID;
1608         sc->sk_res = bus_alloc_resource(dev, SK_RES, &rid,
1609             0, ~0, 1, RF_ACTIVE);
1610
1611         if (sc->sk_res == NULL) {
1612                 printf("sk%d: couldn't map ports/memory\n", unit);
1613                 error = ENXIO;
1614                 goto fail;
1615         }
1616
1617         sc->sk_btag = rman_get_bustag(sc->sk_res);
1618         sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1619
1620         /* Allocate interrupt */
1621         rid = 0;
1622         sc->sk_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1623             RF_SHAREABLE | RF_ACTIVE);
1624
1625         if (sc->sk_irq == NULL) {
1626                 printf("skc%d: couldn't map interrupt\n", unit);
1627                 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1628                 error = ENXIO;
1629                 goto fail;
1630         }
1631
1632         error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET,
1633             sk_intr, sc, &sc->sk_intrhand);
1634
1635         if (error) {
1636                 printf("skc%d: couldn't set up irq\n", unit);
1637                 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1638                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1639                 goto fail;
1640         }
1641
1642         /* Reset the adapter. */
1643         sk_reset(sc);
1644
1645         sc->sk_unit = unit;
1646
1647         /* Read and save vital product data from EEPROM. */
1648         sk_vpd_read(sc);
1649
1650         if (sc->sk_type == SK_GENESIS) {
1651                 /* Read and save RAM size and RAMbuffer offset */
1652                 switch(sk_win_read_1(sc, SK_EPROM0)) {
1653                 case SK_RAMSIZE_512K_64:
1654                         sc->sk_ramsize = 0x80000;
1655                         sc->sk_rboff = SK_RBOFF_0;
1656                         break;
1657                 case SK_RAMSIZE_1024K_64:
1658                         sc->sk_ramsize = 0x100000;
1659                         sc->sk_rboff = SK_RBOFF_80000;
1660                         break;
1661                 case SK_RAMSIZE_1024K_128:
1662                         sc->sk_ramsize = 0x100000;
1663                         sc->sk_rboff = SK_RBOFF_0;
1664                         break;
1665                 case SK_RAMSIZE_2048K_128:
1666                         sc->sk_ramsize = 0x200000;
1667                         sc->sk_rboff = SK_RBOFF_0;
1668                         break;
1669                 default:
1670                         printf("skc%d: unknown ram size: %d\n",
1671                             sc->sk_unit, sk_win_read_1(sc, SK_EPROM0));
1672                         bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1673                         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1674                         bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1675                         error = ENXIO;
1676                         goto fail;
1677                         break;
1678                 }
1679         } else {
1680                 sc->sk_ramsize = 0x20000;
1681                 sc->sk_rboff = SK_RBOFF_0;
1682         }
1683
1684         /* Read and save physical media type */
1685         switch(sk_win_read_1(sc, SK_PMDTYPE)) {
1686         case SK_PMD_1000BASESX:
1687                 sc->sk_pmd = IFM_1000_SX;
1688                 break;
1689         case SK_PMD_1000BASELX:
1690                 sc->sk_pmd = IFM_1000_LX;
1691                 break;
1692         case SK_PMD_1000BASECX:
1693                 sc->sk_pmd = IFM_1000_CX;
1694                 break;
1695         case SK_PMD_1000BASETX:
1696                 sc->sk_pmd = IFM_1000_TX;
1697                 break;
1698         default:
1699                 printf("skc%d: unknown media type: 0x%x\n",
1700                     sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE));
1701                 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1702                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1703                 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1704                 error = ENXIO;
1705                 goto fail;
1706         }
1707
1708         /* Announce the product name. */
1709         printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname);
1710         sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1711         port = malloc(sizeof(int), M_DEVBUF, M_WAITOK);
1712         *port = SK_PORT_A;
1713         device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1714
1715         if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1716                 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1717                 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK);
1718                 *port = SK_PORT_B;
1719                 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1720         }
1721
1722         /* Turn on the 'driver is loaded' LED. */
1723         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1724
1725         bus_generic_attach(dev);
1726
1727 fail:
1728         splx(s);
1729         return(error);
1730 }
1731
1732 static int sk_detach(dev)
1733         device_t                dev;
1734 {
1735         struct sk_softc         *sc;
1736         struct sk_if_softc      *sc_if;
1737         struct ifnet            *ifp;
1738         int                     s;
1739
1740         s = splimp();
1741
1742         sc = device_get_softc(device_get_parent(dev));
1743         sc_if = device_get_softc(dev);
1744         ifp = &sc_if->arpcom.ac_if;
1745         sk_stop(sc_if);
1746         ether_ifdetach(ifp);
1747         bus_generic_detach(dev);
1748         if (sc_if->sk_miibus != NULL)
1749                 device_delete_child(dev, sc_if->sk_miibus);
1750         contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF);
1751         contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF);
1752
1753         return(0);
1754 }
1755
1756 static int skc_detach(dev)
1757         device_t                dev;
1758 {
1759         struct sk_softc         *sc;
1760         int                     s;
1761
1762         s = splimp();
1763
1764         sc = device_get_softc(dev);
1765
1766         bus_generic_detach(dev);
1767         if (sc->sk_devs[SK_PORT_A] != NULL)
1768                 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1769         if (sc->sk_devs[SK_PORT_B] != NULL)
1770                 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1771
1772         bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1773         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1774         bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1775
1776         splx(s);
1777
1778         return(0);
1779 }
1780
1781 static int sk_encap(sc_if, m_head, txidx)
1782         struct sk_if_softc      *sc_if;
1783         struct mbuf             *m_head;
1784         u_int32_t               *txidx;
1785 {
1786         struct sk_tx_desc       *f = NULL;
1787         struct mbuf             *m;
1788         u_int32_t               frag, cur, cnt = 0;
1789
1790         m = m_head;
1791         cur = frag = *txidx;
1792
1793         /*
1794          * Start packing the mbufs in this chain into
1795          * the fragment pointers. Stop when we run out
1796          * of fragments or hit the end of the mbuf chain.
1797          */
1798         for (m = m_head; m != NULL; m = m->m_next) {
1799                 if (m->m_len != 0) {
1800                         if ((SK_TX_RING_CNT -
1801                             (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2)
1802                                 return(ENOBUFS);
1803                         f = &sc_if->sk_rdata->sk_tx_ring[frag];
1804                         f->sk_data_lo = vtophys(mtod(m, vm_offset_t));
1805                         f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT;
1806                         if (cnt == 0)
1807                                 f->sk_ctl |= SK_TXCTL_FIRSTFRAG;
1808                         else
1809                                 f->sk_ctl |= SK_TXCTL_OWN;
1810                         cur = frag;
1811                         SK_INC(frag, SK_TX_RING_CNT);
1812                         cnt++;
1813                 }
1814         }
1815
1816         if (m != NULL)
1817                 return(ENOBUFS);
1818
1819         sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |=
1820                 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR;
1821         sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
1822         sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN;
1823         sc_if->sk_cdata.sk_tx_cnt += cnt;
1824
1825         *txidx = frag;
1826
1827         return(0);
1828 }
1829
1830 static void sk_start(ifp)
1831         struct ifnet            *ifp;
1832 {
1833         struct sk_softc         *sc;
1834         struct sk_if_softc      *sc_if;
1835         struct mbuf             *m_head = NULL;
1836         u_int32_t               idx;
1837
1838         sc_if = ifp->if_softc;
1839         sc = sc_if->sk_softc;
1840
1841         idx = sc_if->sk_cdata.sk_tx_prod;
1842
1843         while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
1844                 IF_DEQUEUE(&ifp->if_snd, m_head);
1845                 if (m_head == NULL)
1846                         break;
1847
1848                 /*
1849                  * Pack the data into the transmit ring. If we
1850                  * don't have room, set the OACTIVE flag and wait
1851                  * for the NIC to drain the ring.
1852                  */
1853                 if (sk_encap(sc_if, m_head, &idx)) {
1854                         IF_PREPEND(&ifp->if_snd, m_head);
1855                         ifp->if_flags |= IFF_OACTIVE;
1856                         break;
1857                 }
1858
1859                 /*
1860                  * If there's a BPF listener, bounce a copy of this frame
1861                  * to him.
1862                  */
1863                 if (ifp->if_bpf)
1864                         bpf_mtap(ifp, m_head);
1865         }
1866
1867         /* Transmit */
1868         sc_if->sk_cdata.sk_tx_prod = idx;
1869         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1870
1871         /* Set a timeout in case the chip goes out to lunch. */
1872         ifp->if_timer = 5;
1873
1874         return;
1875 }
1876
1877
1878 static void sk_watchdog(ifp)
1879         struct ifnet            *ifp;
1880 {
1881         struct sk_if_softc      *sc_if;
1882
1883         sc_if = ifp->if_softc;
1884
1885         printf("sk%d: watchdog timeout\n", sc_if->sk_unit);
1886         sk_init(sc_if);
1887
1888         return;
1889 }
1890
1891 static void skc_shutdown(dev)
1892         device_t                dev;
1893 {
1894         struct sk_softc         *sc;
1895
1896         sc = device_get_softc(dev);
1897
1898         /* Turn off the 'driver is loaded' LED. */
1899         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1900
1901         /*
1902          * Reset the GEnesis controller. Doing this should also
1903          * assert the resets on the attached XMAC(s).
1904          */
1905         sk_reset(sc);
1906
1907         return;
1908 }
1909
1910 static void sk_rxeof(sc_if)
1911         struct sk_if_softc      *sc_if;
1912 {
1913         struct ether_header     *eh;
1914         struct mbuf             *m;
1915         struct ifnet            *ifp;
1916         struct sk_chain         *cur_rx;
1917         int                     total_len = 0;
1918         int                     i;
1919         u_int32_t               rxstat;
1920
1921         ifp = &sc_if->arpcom.ac_if;
1922         i = sc_if->sk_cdata.sk_rx_prod;
1923         cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1924
1925         while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) {
1926
1927                 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1928                 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat;
1929                 m = cur_rx->sk_mbuf;
1930                 cur_rx->sk_mbuf = NULL;
1931                 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl);
1932                 SK_INC(i, SK_RX_RING_CNT);
1933
1934                 if (rxstat & XM_RXSTAT_ERRFRAME) {
1935                         ifp->if_ierrors++;
1936                         sk_newbuf(sc_if, cur_rx, m);
1937                         continue;
1938                 }
1939
1940                 /*
1941                  * Try to allocate a new jumbo buffer. If that
1942                  * fails, copy the packet to mbufs and put the
1943                  * jumbo buffer back in the ring so it can be
1944                  * re-used. If allocating mbufs fails, then we
1945                  * have to drop the packet.
1946                  */
1947                 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) {
1948                         struct mbuf             *m0;
1949                         m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1950                             total_len + ETHER_ALIGN, 0, ifp, NULL);
1951                         sk_newbuf(sc_if, cur_rx, m);
1952                         if (m0 == NULL) {
1953                                 printf("sk%d: no receive buffers "
1954                                     "available -- packet dropped!\n",
1955                                     sc_if->sk_unit);
1956                                 ifp->if_ierrors++;
1957                                 continue;
1958                         }
1959                         m_adj(m0, ETHER_ALIGN);
1960                         m = m0;
1961                 } else {
1962                         m->m_pkthdr.rcvif = ifp;
1963                         m->m_pkthdr.len = m->m_len = total_len;
1964                 }
1965
1966                 ifp->if_ipackets++;
1967                 eh = mtod(m, struct ether_header *);
1968
1969                 /* Remove header from mbuf and pass it on. */
1970                 m_adj(m, sizeof(struct ether_header));
1971                 ether_input(ifp, eh, m);
1972         }
1973
1974         sc_if->sk_cdata.sk_rx_prod = i;
1975
1976         return;
1977 }
1978
1979 static void sk_txeof(sc_if)
1980         struct sk_if_softc      *sc_if;
1981 {
1982         struct sk_tx_desc       *cur_tx = NULL;
1983         struct ifnet            *ifp;
1984         u_int32_t               idx;
1985
1986         ifp = &sc_if->arpcom.ac_if;
1987
1988         /*
1989          * Go through our tx ring and free mbufs for those
1990          * frames that have been sent.
1991          */
1992         idx = sc_if->sk_cdata.sk_tx_cons;
1993         while(idx != sc_if->sk_cdata.sk_tx_prod) {
1994                 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
1995                 if (cur_tx->sk_ctl & SK_TXCTL_OWN)
1996                         break;
1997                 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG)
1998                         ifp->if_opackets++;
1999                 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
2000                         m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf);
2001                         sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL;
2002                 }
2003                 sc_if->sk_cdata.sk_tx_cnt--;
2004                 SK_INC(idx, SK_TX_RING_CNT);
2005                 ifp->if_timer = 0;
2006         }
2007
2008         sc_if->sk_cdata.sk_tx_cons = idx;
2009
2010         if (cur_tx != NULL)
2011                 ifp->if_flags &= ~IFF_OACTIVE;
2012
2013         return;
2014 }
2015
2016 static void sk_tick(xsc_if)
2017         void                    *xsc_if;
2018 {
2019         struct sk_if_softc      *sc_if;
2020         struct mii_data         *mii;
2021         struct ifnet            *ifp;
2022         int                     i;
2023
2024         sc_if = xsc_if;
2025         ifp = &sc_if->arpcom.ac_if;
2026         mii = device_get_softc(sc_if->sk_miibus);
2027
2028         if (!(ifp->if_flags & IFF_UP))
2029                 return;
2030
2031         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2032                 sk_intr_bcom(sc_if);
2033                 return;
2034         }
2035
2036         /*
2037          * According to SysKonnect, the correct way to verify that
2038          * the link has come back up is to poll bit 0 of the GPIO
2039          * register three times. This pin has the signal from the
2040          * link_sync pin connected to it; if we read the same link
2041          * state 3 times in a row, we know the link is up.
2042          */
2043         for (i = 0; i < 3; i++) {
2044                 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2045                         break;
2046         }
2047
2048         if (i != 3) {
2049                 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
2050                 return;
2051         }
2052
2053         /* Turn the GP0 interrupt back on. */
2054         SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2055         SK_XM_READ_2(sc_if, XM_ISR);
2056         mii_tick(mii);
2057         mii_pollstat(mii);
2058         untimeout(sk_tick, sc_if, sc_if->sk_tick_ch);
2059
2060         return;
2061 }
2062
2063 static void sk_intr_bcom(sc_if)
2064         struct sk_if_softc      *sc_if;
2065 {
2066         struct sk_softc         *sc;
2067         struct mii_data         *mii;
2068         struct ifnet            *ifp;
2069         int                     status;
2070
2071         sc = sc_if->sk_softc;
2072         mii = device_get_softc(sc_if->sk_miibus);
2073         ifp = &sc_if->arpcom.ac_if;
2074
2075         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2076
2077         /*
2078          * Read the PHY interrupt register to make sure
2079          * we clear any pending interrupts.
2080          */
2081         status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
2082
2083         if (!(ifp->if_flags & IFF_RUNNING)) {
2084                 sk_init_xmac(sc_if);
2085                 return;
2086         }
2087
2088         if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
2089                 int                     lstat;
2090                 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
2091                     BRGPHY_MII_AUXSTS);
2092
2093                 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2094                         mii_mediachg(mii);
2095                         /* Turn off the link LED. */
2096                         SK_IF_WRITE_1(sc_if, 0,
2097                             SK_LINKLED1_CTL, SK_LINKLED_OFF);
2098                         sc_if->sk_link = 0;
2099                 } else if (status & BRGPHY_ISR_LNK_CHG) {
2100                         sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2101                             BRGPHY_MII_IMR, 0xFF00);
2102                         mii_tick(mii);
2103                         sc_if->sk_link = 1;
2104                         /* Turn on the link LED. */
2105                         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2106                             SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
2107                             SK_LINKLED_BLINK_OFF);
2108                         mii_pollstat(mii);
2109                 } else {
2110                         mii_tick(mii);
2111                         sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
2112                 }
2113         }
2114
2115         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2116
2117         return;
2118 }
2119
2120 static void sk_intr_xmac(sc_if)
2121         struct sk_if_softc      *sc_if;
2122 {
2123         struct sk_softc         *sc;
2124         u_int16_t               status;
2125         struct mii_data         *mii;
2126
2127         sc = sc_if->sk_softc;
2128         mii = device_get_softc(sc_if->sk_miibus);
2129         status = SK_XM_READ_2(sc_if, XM_ISR);
2130
2131         /*
2132          * Link has gone down. Start MII tick timeout to
2133          * watch for link resync.
2134          */
2135         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
2136                 if (status & XM_ISR_GP0_SET) {
2137                         SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2138                         sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
2139                 }
2140
2141                 if (status & XM_ISR_AUTONEG_DONE) {
2142                         sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
2143                 }
2144         }
2145
2146         if (status & XM_IMR_TX_UNDERRUN)
2147                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
2148
2149         if (status & XM_IMR_RX_OVERRUN)
2150                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
2151
2152         status = SK_XM_READ_2(sc_if, XM_ISR);
2153
2154         return;
2155 }
2156
2157 static void sk_intr_yukon(sc_if)
2158         struct sk_if_softc      *sc_if;
2159 {
2160         int status;
2161
2162         status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2163
2164         return;
2165 }
2166
2167 static void sk_intr(xsc)
2168         void                    *xsc;
2169 {
2170         struct sk_softc         *sc = xsc;
2171         struct sk_if_softc      *sc_if0 = NULL, *sc_if1 = NULL;
2172         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
2173         u_int32_t               status;
2174
2175         sc_if0 = sc->sk_if[SK_PORT_A];
2176         sc_if1 = sc->sk_if[SK_PORT_B];
2177
2178         if (sc_if0 != NULL)
2179                 ifp0 = &sc_if0->arpcom.ac_if;
2180         if (sc_if1 != NULL)
2181                 ifp1 = &sc_if1->arpcom.ac_if;
2182
2183         for (;;) {
2184                 status = CSR_READ_4(sc, SK_ISSR);
2185                 if (!(status & sc->sk_intrmask))
2186                         break;
2187
2188                 /* Handle receive interrupts first. */
2189                 if (status & SK_ISR_RX1_EOF) {
2190                         sk_rxeof(sc_if0);
2191                         CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
2192                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2193                 }
2194                 if (status & SK_ISR_RX2_EOF) {
2195                         sk_rxeof(sc_if1);
2196                         CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
2197                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2198                 }
2199
2200                 /* Then transmit interrupts. */
2201                 if (status & SK_ISR_TX1_S_EOF) {
2202                         sk_txeof(sc_if0);
2203                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
2204                             SK_TXBMU_CLR_IRQ_EOF);
2205                 }
2206                 if (status & SK_ISR_TX2_S_EOF) {
2207                         sk_txeof(sc_if1);
2208                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
2209                             SK_TXBMU_CLR_IRQ_EOF);
2210                 }
2211
2212                 /* Then MAC interrupts. */
2213                 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) {
2214                         if (sc->sk_type == SK_GENESIS)
2215                                 sk_intr_xmac(sc_if0);
2216                         else
2217                                 sk_intr_yukon(sc_if0);
2218                 }
2219
2220                 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) {
2221                         if (sc->sk_type == SK_GENESIS)
2222                                 sk_intr_xmac(sc_if1);
2223                         else
2224                                 sk_intr_yukon(sc_if0);
2225                 }
2226
2227                 if (status & SK_ISR_EXTERNAL_REG) {
2228                         if (ifp0 != NULL &&
2229                             sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
2230                                 sk_intr_bcom(sc_if0);
2231                         if (ifp1 != NULL &&
2232                             sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
2233                                 sk_intr_bcom(sc_if1);
2234                 }
2235         }
2236
2237         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2238
2239         if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL)
2240                 sk_start(ifp0);
2241         if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL)
2242                 sk_start(ifp1);
2243
2244         return;
2245 }
2246
2247 static void sk_init_xmac(sc_if)
2248         struct sk_if_softc      *sc_if;
2249 {
2250         struct sk_softc         *sc;
2251         struct ifnet            *ifp;
2252         struct sk_bcom_hack     bhack[] = {
2253         { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
2254         { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
2255         { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
2256         { 0, 0 } };
2257
2258         sc = sc_if->sk_softc;
2259         ifp = &sc_if->arpcom.ac_if;
2260
2261         /* Unreset the XMAC. */
2262         SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
2263         DELAY(1000);
2264
2265         /* Reset the XMAC's internal state. */
2266         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2267
2268         /* Save the XMAC II revision */
2269         sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
2270
2271         /*
2272          * Perform additional initialization for external PHYs,
2273          * namely for the 1000baseTX cards that use the XMAC's
2274          * GMII mode.
2275          */
2276         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2277                 int                     i = 0;
2278                 u_int32_t               val;
2279
2280                 /* Take PHY out of reset. */
2281                 val = sk_win_read_4(sc, SK_GPIO);
2282                 if (sc_if->sk_port == SK_PORT_A)
2283                         val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
2284                 else
2285                         val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
2286                 sk_win_write_4(sc, SK_GPIO, val);
2287
2288                 /* Enable GMII mode on the XMAC. */
2289                 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
2290
2291                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2292                     BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
2293                 DELAY(10000);
2294                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2295                     BRGPHY_MII_IMR, 0xFFF0);
2296
2297                 /*
2298                  * Early versions of the BCM5400 apparently have
2299                  * a bug that requires them to have their reserved
2300                  * registers initialized to some magic values. I don't
2301                  * know what the numbers do, I'm just the messenger.
2302                  */
2303                 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
2304                     == 0x6041) {
2305                         while(bhack[i].reg) {
2306                                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2307                                     bhack[i].reg, bhack[i].val);
2308                                 i++;
2309                         }
2310                 }
2311         }
2312
2313         /* Set station address */
2314         SK_XM_WRITE_2(sc_if, XM_PAR0,
2315             *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0]));
2316         SK_XM_WRITE_2(sc_if, XM_PAR1,
2317             *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2]));
2318         SK_XM_WRITE_2(sc_if, XM_PAR2,
2319             *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4]));
2320         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
2321
2322         if (ifp->if_flags & IFF_BROADCAST) {
2323                 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2324         } else {
2325                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2326         }
2327
2328         /* We don't need the FCS appended to the packet. */
2329         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2330
2331         /* We want short frames padded to 60 bytes. */
2332         SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2333
2334         /*
2335          * Enable the reception of all error frames. This is is
2336          * a necessary evil due to the design of the XMAC. The
2337          * XMAC's receive FIFO is only 8K in size, however jumbo
2338          * frames can be up to 9000 bytes in length. When bad
2339          * frame filtering is enabled, the XMAC's RX FIFO operates
2340          * in 'store and forward' mode. For this to work, the
2341          * entire frame has to fit into the FIFO, but that means
2342          * that jumbo frames larger than 8192 bytes will be
2343          * truncated. Disabling all bad frame filtering causes
2344          * the RX FIFO to operate in streaming mode, in which
2345          * case the XMAC will start transfering frames out of the
2346          * RX FIFO as soon as the FIFO threshold is reached.
2347          */
2348         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2349             XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2350             XM_MODE_RX_INRANGELEN);
2351
2352         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2353                 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2354         else
2355                 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2356
2357         /*
2358          * Bump up the transmit threshold. This helps hold off transmit
2359          * underruns when we're blasting traffic from both ports at once.
2360          */
2361         SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2362
2363         /* Set promiscuous mode */
2364         sk_setpromisc(sc_if);
2365
2366         /* Set multicast filter */
2367         sk_setmulti(sc_if);
2368
2369         /* Clear and enable interrupts */
2370         SK_XM_READ_2(sc_if, XM_ISR);
2371         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2372                 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2373         else
2374                 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2375
2376         /* Configure MAC arbiter */
2377         switch(sc_if->sk_xmac_rev) {
2378         case XM_XMAC_REV_B2:
2379                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2380                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2381                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2382                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2383                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2384                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2385                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2386                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2387                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2388                 break;
2389         case XM_XMAC_REV_C1:
2390                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2391                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2392                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2393                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2394                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2395                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2396                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2397                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2398                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2399                 break;
2400         default:
2401                 break;
2402         }
2403         sk_win_write_2(sc, SK_MACARB_CTL,
2404             SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2405
2406         sc_if->sk_link = 1;
2407
2408         return;
2409 }
2410
2411 static void sk_init_yukon(sc_if)
2412         struct sk_if_softc      *sc_if;
2413 {
2414         u_int32_t               phy;
2415         u_int16_t               reg;
2416         int                     i;
2417
2418         /* GMAC and GPHY Reset */
2419         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2420         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2421         DELAY(1000);
2422         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR);
2423         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2424         DELAY(1000);
2425
2426         phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
2427                 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
2428
2429         switch(sc_if->sk_softc->sk_pmd) {
2430         case IFM_1000_SX:
2431         case IFM_1000_LX:
2432                 phy |= SK_GPHY_FIBER;
2433                 break;
2434
2435         case IFM_1000_CX:
2436         case IFM_1000_TX:
2437                 phy |= SK_GPHY_COPPER;
2438                 break;
2439         }
2440
2441         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2442         DELAY(1000);
2443         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2444         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2445                       SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
2446
2447         /* unused read of the interrupt source register */
2448         SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2449
2450         reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2451
2452         /* MIB Counter Clear Mode set */
2453         reg |= YU_PAR_MIB_CLR;
2454         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2455
2456         /* MIB Counter Clear Mode clear */
2457         reg &= ~YU_PAR_MIB_CLR;
2458         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2459
2460         /* receive control reg */
2461         SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
2462
2463         /* transmit parameter register */
2464         SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2465                       YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
2466
2467         /* serial mode register */
2468         SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) |
2469                       YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e));
2470
2471         /* Setup Yukon's address */
2472         for (i = 0; i < 3; i++) {
2473                 /* Write Source Address 1 (unicast filter) */
2474                 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2475                               sc_if->arpcom.ac_enaddr[i * 2] |
2476                               sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
2477         }
2478
2479         for (i = 0; i < 3; i++) {
2480                 reg = sk_win_read_2(sc_if->sk_softc,
2481                                     SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2482                 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2483         }
2484
2485         /* Set promiscuous mode */
2486         sk_setpromisc(sc_if);
2487
2488         /* Set multicast filter */
2489         sk_setmulti(sc_if);
2490
2491         /* enable interrupt mask for counter overflows */
2492         SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2493         SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2494         SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2495
2496         /* Configure RX MAC FIFO */
2497         SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2498         SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON);
2499
2500         /* Configure TX MAC FIFO */
2501         SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2502         SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2503 }
2504
2505 /*
2506  * Note that to properly initialize any part of the GEnesis chip,
2507  * you first have to take it out of reset mode.
2508  */
2509 static void sk_init(xsc)
2510         void                    *xsc;
2511 {
2512         struct sk_if_softc      *sc_if = xsc;
2513         struct sk_softc         *sc;
2514         struct ifnet            *ifp;
2515         struct mii_data         *mii;
2516         int                     s;
2517         u_int16_t               reg;
2518
2519         s = splimp();
2520
2521         ifp = &sc_if->arpcom.ac_if;
2522         sc = sc_if->sk_softc;
2523         mii = device_get_softc(sc_if->sk_miibus);
2524
2525         /* Cancel pending I/O and free all RX/TX buffers. */
2526         sk_stop(sc_if);
2527
2528         if (sc->sk_type == SK_GENESIS) {
2529                 /* Configure LINK_SYNC LED */
2530                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2531                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2532                         SK_LINKLED_LINKSYNC_ON);
2533
2534                 /* Configure RX LED */
2535                 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
2536                         SK_RXLEDCTL_COUNTER_START);
2537
2538                 /* Configure TX LED */
2539                 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2540                         SK_TXLEDCTL_COUNTER_START);
2541         }
2542
2543         /* Configure I2C registers */
2544
2545         /* Configure XMAC(s) */
2546         switch (sc->sk_type) {
2547         case SK_GENESIS:
2548                 sk_init_xmac(sc_if);
2549                 break;
2550         case SK_YUKON:
2551                 sk_init_yukon(sc_if);
2552                 break;
2553         }
2554         mii_mediachg(mii);
2555
2556         if (sc->sk_type == SK_GENESIS) {
2557                 /* Configure MAC FIFOs */
2558                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2559                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2560                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2561
2562                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2563                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2564                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2565         }
2566
2567         /* Configure transmit arbiter(s) */
2568         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2569             SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
2570
2571         /* Configure RAMbuffers */
2572         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2573         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2574         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2575         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2576         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2577         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2578
2579         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2580         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2581         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2582         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2583         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2584         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2585         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2586
2587         /* Configure BMUs */
2588         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2589         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2590             vtophys(&sc_if->sk_rdata->sk_rx_ring[0]));
2591         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
2592
2593         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2594         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2595             vtophys(&sc_if->sk_rdata->sk_tx_ring[0]));
2596         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
2597
2598         /* Init descriptors */
2599         if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2600                 printf("sk%d: initialization failed: no "
2601                     "memory for rx buffers\n", sc_if->sk_unit);
2602                 sk_stop(sc_if);
2603                 (void)splx(s);
2604                 return;
2605         }
2606         sk_init_tx_ring(sc_if);
2607
2608         /* Configure interrupt handling */
2609         CSR_READ_4(sc, SK_ISSR);
2610         if (sc_if->sk_port == SK_PORT_A)
2611                 sc->sk_intrmask |= SK_INTRS1;
2612         else
2613                 sc->sk_intrmask |= SK_INTRS2;
2614
2615         sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2616
2617         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2618
2619         /* Start BMUs. */
2620         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2621
2622         switch(sc->sk_type) {
2623         case SK_GENESIS:
2624                 /* Enable XMACs TX and RX state machines */
2625                 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2626                 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2627                 break;
2628         case SK_YUKON:
2629                 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
2630                 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
2631                 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN);
2632                 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2633         }
2634
2635         ifp->if_flags |= IFF_RUNNING;
2636         ifp->if_flags &= ~IFF_OACTIVE;
2637
2638         splx(s);
2639
2640         return;
2641 }
2642
2643 static void sk_stop(sc_if)
2644         struct sk_if_softc      *sc_if;
2645 {
2646         int                     i;
2647         struct sk_softc         *sc;
2648         struct ifnet            *ifp;
2649
2650         sc = sc_if->sk_softc;
2651         ifp = &sc_if->arpcom.ac_if;
2652
2653         untimeout(sk_tick, sc_if, sc_if->sk_tick_ch);
2654
2655         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2656                 u_int32_t               val;
2657
2658                 /* Put PHY back into reset. */
2659                 val = sk_win_read_4(sc, SK_GPIO);
2660                 if (sc_if->sk_port == SK_PORT_A) {
2661                         val |= SK_GPIO_DIR0;
2662                         val &= ~SK_GPIO_DAT0;
2663                 } else {
2664                         val |= SK_GPIO_DIR2;
2665                         val &= ~SK_GPIO_DAT2;
2666                 }
2667                 sk_win_write_4(sc, SK_GPIO, val);
2668         }
2669
2670         /* Turn off various components of this interface. */
2671         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2672         switch (sc->sk_type) {
2673         case SK_GENESIS:
2674                 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2675                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2676                 break;
2677         case SK_YUKON:
2678                 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2679                 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2680                 break;
2681         }
2682         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2683         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2684         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2685         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2686         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2687         SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2688         SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2689         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2690         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2691
2692         /* Disable interrupts */
2693         if (sc_if->sk_port == SK_PORT_A)
2694                 sc->sk_intrmask &= ~SK_INTRS1;
2695         else
2696                 sc->sk_intrmask &= ~SK_INTRS2;
2697         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2698
2699         SK_XM_READ_2(sc_if, XM_ISR);
2700         SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2701
2702         /* Free RX and TX mbufs still in the queues. */
2703         for (i = 0; i < SK_RX_RING_CNT; i++) {
2704                 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) {
2705                         m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
2706                         sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
2707                 }
2708         }
2709
2710         for (i = 0; i < SK_TX_RING_CNT; i++) {
2711                 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) {
2712                         m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
2713                         sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
2714                 }
2715         }
2716
2717         ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
2718
2719         return;
2720 }