2 * Copyright (c) 2001 Alcove - Nicolas Souchu
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/isa/ppc.c,v 1.26.2.5 2001/10/02 05:21:45 nsouch Exp $
27 * $DragonFly: src/sys/dev/misc/ppc/ppc.c,v 1.11 2005/12/11 01:54:08 swildner Exp $
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/thread2.h>
42 #include <machine/clock.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
45 #include <machine/vmparam.h>
48 #include <bus/isa/isareg.h>
49 #include <bus/isa/isavar.h>
51 #include <bus/ppbus/ppbconf.h>
52 #include <bus/ppbus/ppb_msq.h>
58 #define LOG_PPC(function, ppc, string) \
59 if (bootverbose) printf("%s: %s\n", function, string)
62 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
64 devclass_t ppc_devclass;
66 static int ppc_probe(device_t dev);
67 static int ppc_attach(device_t dev);
68 static int ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val);
70 static void ppc_reset_epp(device_t);
71 static void ppc_ecp_sync(device_t);
72 static void ppcintr(void *arg);
74 static int ppc_exec_microseq(device_t, struct ppb_microseq **);
75 static int ppc_setmode(device_t, int);
77 static int ppc_read(device_t, char *, int, int);
78 static int ppc_write(device_t, char *, int, int);
80 static u_char ppc_io(device_t, int, u_char *, int, u_char);
82 static int ppc_setup_intr(device_t, device_t, struct resource *, int,
83 void (*)(void *), void *, void **, lwkt_serialize_t);
84 static int ppc_teardown_intr(device_t, device_t, struct resource *, void *);
86 static device_method_t ppc_methods[] = {
87 /* device interface */
88 DEVMETHOD(device_probe, ppc_probe),
89 DEVMETHOD(device_attach, ppc_attach),
92 DEVMETHOD(bus_read_ivar, ppc_read_ivar),
93 DEVMETHOD(bus_setup_intr, ppc_setup_intr),
94 DEVMETHOD(bus_teardown_intr, ppc_teardown_intr),
95 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
98 DEVMETHOD(ppbus_io, ppc_io),
99 DEVMETHOD(ppbus_exec_microseq, ppc_exec_microseq),
100 DEVMETHOD(ppbus_reset_epp, ppc_reset_epp),
101 DEVMETHOD(ppbus_setmode, ppc_setmode),
102 DEVMETHOD(ppbus_ecp_sync, ppc_ecp_sync),
103 DEVMETHOD(ppbus_read, ppc_read),
104 DEVMETHOD(ppbus_write, ppc_write),
109 static driver_t ppc_driver = {
112 sizeof(struct ppc_data),
115 static char *ppc_models[] = {
116 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
117 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
118 "SMC FDC37C935", "PC87303", 0
121 /* list of available modes */
122 static char *ppc_avms[] = {
123 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
124 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
125 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
126 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
129 /* list of current executing modes
130 * Note that few modes do not actually exist.
132 static char *ppc_modes[] = {
133 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
134 "EPP", "EPP", "EPP", "ECP",
135 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
136 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
139 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
143 * BIOS printer list - used by BIOS probe.
145 #define BIOS_PPC_PORTS 0x408
146 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
147 #define BIOS_MAX_PPC 4
154 ppc_ecp_sync(device_t dev)
157 struct ppc_data *ppc = DEVTOSOFTC(dev);
159 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
163 if ((r & 0xe0) != PPC_ECR_EPP)
166 for (i = 0; i < 100; i++) {
173 printf("ppc%d: ECP sync failed as data still " \
174 "present in FIFO.\n", ppc->ppc_unit);
182 * Detect parallel port FIFO
185 ppc_detect_fifo(struct ppc_data *ppc)
188 char ctr_sav, ctr, cc;
192 ecr_sav = r_ecr(ppc);
193 ctr_sav = r_ctr(ppc);
195 /* enter ECP configuration mode, no interrupt, no DMA */
198 /* read PWord size - transfers in FIFO mode must be PWord aligned */
199 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
201 /* XXX 16 and 32 bits implementations not supported */
202 if (ppc->ppc_pword != PPC_PWORD_8) {
203 LOG_PPC(__func__, ppc, "PWord not supported");
207 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
209 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
211 /* enter ECP test mode, no interrupt, no DMA */
215 for (i=0; i<1024; i++) {
216 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
222 LOG_PPC(__func__, ppc, "can't flush FIFO");
226 /* enable interrupts, no DMA */
229 /* determine readIntrThreshold
230 * fill the FIFO until serviceIntr is set
232 for (i=0; i<1024; i++) {
233 w_fifo(ppc, (char)i);
234 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
235 /* readThreshold reached */
238 if (r_ecr(ppc) & PPC_FIFO_FULL) {
245 LOG_PPC(__func__, ppc, "can't fill FIFO");
249 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
250 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
251 w_ecr(ppc, 0xd0); /* enable interrupts */
253 /* determine writeIntrThreshold
254 * empty the FIFO until serviceIntr is set
256 for (i=ppc->ppc_fifo; i>0; i--) {
257 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
258 LOG_PPC(__func__, ppc, "invalid data in FIFO");
261 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
262 /* writeIntrThreshold reached */
263 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
265 /* if FIFO empty before the last byte, error */
266 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
267 LOG_PPC(__func__, ppc, "data lost in FIFO");
272 /* FIFO must be empty after the last byte */
273 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
274 LOG_PPC(__func__, ppc, "can't empty the FIFO");
291 ppc_detect_port(struct ppc_data *ppc)
294 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
296 if (r_dtr(ppc) != 0xaa)
303 * EPP timeout, according to the PC87332 manual
304 * Semantics of clearing EPP timeout bit.
305 * PC87332 - reading SPP_STR does it...
306 * SMC - write 1 to EPP timeout bit XXX
307 * Others - (?) write 0 to EPP timeout bit
310 ppc_reset_epp_timeout(struct ppc_data *ppc)
316 w_str(ppc, r & 0xfe);
322 ppc_check_epp_timeout(struct ppc_data *ppc)
324 ppc_reset_epp_timeout(ppc);
326 return (!(r_str(ppc) & TIMEOUT));
330 * Configure current operating mode
333 ppc_generic_setmode(struct ppc_data *ppc, int mode)
337 /* check if mode is available */
338 if (mode && !(ppc->ppc_avm & mode))
341 /* if ECP mode, configure ecr register */
342 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
343 /* return to byte mode (keeping direction bit),
344 * no interrupt, no DMA to be able to change to
347 w_ecr(ppc, PPC_ECR_RESET);
348 ecr = PPC_DISABLE_INTR;
352 else if (mode & PPB_ECP)
353 /* select ECP mode */
355 else if (mode & PPB_PS2)
356 /* select PS2 mode with ECP */
359 /* select COMPATIBLE/NIBBLE mode */
365 ppc->ppc_mode = mode;
371 * The ppc driver is free to choose options like FIFO or DMA
372 * if ECP mode is available.
374 * The 'RAW' option allows the upper drivers to force the ppc mode
375 * even with FIFO, DMA available.
378 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
382 /* check if mode is available */
383 if (mode && !(ppc->ppc_avm & mode))
386 /* if ECP mode, configure ecr register */
387 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
388 /* return to byte mode (keeping direction bit),
389 * no interrupt, no DMA to be able to change to
392 w_ecr(ppc, PPC_ECR_RESET);
393 ecr = PPC_DISABLE_INTR;
396 /* select EPP mode */
398 else if (mode & PPB_ECP)
399 /* select ECP mode */
401 else if (mode & PPB_PS2)
402 /* select PS2 mode with ECP */
405 /* select COMPATIBLE/NIBBLE mode */
411 ppc->ppc_mode = mode;
416 #ifdef PPC_PROBE_CHIPSET
420 * Probe for a Natsemi PC873xx-family part.
422 * References in this function are to the National Semiconductor
423 * PC87332 datasheet TL/C/11930, May 1995 revision.
425 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
426 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
427 static int pc873xx_irqtab[] = {5, 7, 5, 0};
429 static int pc873xx_regstab[] = {
430 PC873_FER, PC873_FAR, PC873_PTR,
431 PC873_FCR, PC873_PCR, PC873_PMC,
432 PC873_TUP, PC873_SID, PC873_PNP0,
433 PC873_PNP1, PC873_LPTBA, -1
436 static char *pc873xx_rnametab[] = {
437 "FER", "FAR", "PTR", "FCR", "PCR",
438 "PMC", "TUP", "SID", "PNP0", "PNP1",
443 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
445 static int index = 0;
447 int ptr, pcr, val, i;
449 while ((idport = pc873xx_basetab[index++])) {
451 /* XXX should check first to see if this location is already claimed */
454 * Pull the 873xx through the power-on ID cycle (2.2,1.).
455 * We can't use this to locate the chip as it may already have
456 * been used by the BIOS.
458 (void)inb(idport); (void)inb(idport);
459 (void)inb(idport); (void)inb(idport);
462 * Read the SID byte. Possible values are :
469 outb(idport, PC873_SID);
470 val = inb(idport + 1);
471 if ((val & 0xf0) == 0x10) {
472 ppc->ppc_model = NS_PC87332;
473 } else if ((val & 0xf8) == 0x70) {
474 ppc->ppc_model = NS_PC87306;
475 } else if ((val & 0xf8) == 0x50) {
476 ppc->ppc_model = NS_PC87334;
477 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
478 documentation, but probing
480 ppc->ppc_model = NS_PC87303;
482 if (bootverbose && (val != 0xff))
483 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
484 continue ; /* not recognised */
487 /* print registers */
490 for (i=0; pc873xx_regstab[i] != -1; i++) {
491 outb(idport, pc873xx_regstab[i]);
492 printf(" %s=0x%x", pc873xx_rnametab[i],
493 inb(idport + 1) & 0xff);
499 * We think we have one. Is it enabled and where we want it to be?
501 outb(idport, PC873_FER);
502 val = inb(idport + 1);
503 if (!(val & PC873_PPENABLE)) {
505 printf("PC873xx parallel port disabled\n");
508 outb(idport, PC873_FAR);
509 val = inb(idport + 1);
510 /* XXX we should create a driver instance for every port found */
511 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
513 /* First try to change the port address to that requested... */
515 switch(ppc->ppc_base) {
533 outb(idport, PC873_FAR);
534 outb(idport + 1, val);
535 outb(idport + 1, val);
537 /* Check for success by reading back the value we supposedly
538 wrote and comparing...*/
540 outb(idport, PC873_FAR);
541 val = inb(idport + 1) & 0x3;
543 /* If we fail, report the failure... */
545 if (pc873xx_porttab[val] != ppc->ppc_base) {
547 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
548 pc873xx_porttab[val], ppc->ppc_base);
553 outb(idport, PC873_PTR);
554 ptr = inb(idport + 1);
556 /* get irq settings */
557 if (ppc->ppc_base == 0x378)
558 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
560 irq = pc873xx_irqtab[val];
563 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
566 * Check if irq settings are correct
568 if (irq != ppc->ppc_irq) {
570 * If the chipset is not locked and base address is 0x378,
571 * we have another chance
573 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
574 if (ppc->ppc_irq == 7) {
575 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
576 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
578 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
579 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
582 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
585 printf("PC873xx sorry, can't change irq setting\n");
589 printf("PC873xx irq settings are correct\n");
592 outb(idport, PC873_PCR);
593 pcr = inb(idport + 1);
595 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
597 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
599 ppc->ppc_avm |= PPB_NIBBLE;
603 if (pcr & PC873_EPPEN) {
604 ppc->ppc_avm |= PPB_EPP;
609 if (pcr & PC873_EPP19)
610 ppc->ppc_epp = EPP_1_9;
612 ppc->ppc_epp = EPP_1_7;
614 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
615 outb(idport, PC873_PTR);
616 ptr = inb(idport + 1);
617 if (ptr & PC873_EPPRDIR)
618 printf(", Regular mode");
620 printf(", Automatic mode");
622 } else if (pcr & PC873_ECPEN) {
623 ppc->ppc_avm |= PPB_ECP;
627 if (pcr & PC873_ECPCLK) { /* XXX */
628 ppc->ppc_avm |= PPB_PS2;
633 outb(idport, PC873_PTR);
634 ptr = inb(idport + 1);
635 if (ptr & PC873_EXTENDED) {
636 ppc->ppc_avm |= PPB_SPP;
643 printf("PC873xx unlocked");
645 if (chipset_mode & PPB_ECP) {
646 if ((chipset_mode & PPB_EPP) && bootverbose)
647 printf(", ECP+EPP not supported");
650 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
651 outb(idport + 1, pcr);
652 outb(idport + 1, pcr);
657 } else if (chipset_mode & PPB_EPP) {
658 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
659 pcr |= (PC873_EPPEN | PC873_EPP19);
660 outb(idport + 1, pcr);
661 outb(idport + 1, pcr);
663 ppc->ppc_epp = EPP_1_9; /* XXX */
668 /* enable automatic direction turnover */
669 if (ppc->ppc_model == NS_PC87332) {
670 outb(idport, PC873_PTR);
671 ptr = inb(idport + 1);
672 ptr &= ~PC873_EPPRDIR;
673 outb(idport + 1, ptr);
674 outb(idport + 1, ptr);
677 printf(", Automatic mode");
680 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
681 outb(idport + 1, pcr);
682 outb(idport + 1, pcr);
684 /* configure extended bit in PTR */
685 outb(idport, PC873_PTR);
686 ptr = inb(idport + 1);
688 if (chipset_mode & PPB_PS2) {
689 ptr |= PC873_EXTENDED;
695 /* default to NIBBLE mode */
696 ptr &= ~PC873_EXTENDED;
701 outb(idport + 1, ptr);
702 outb(idport + 1, ptr);
705 ppc->ppc_avm = chipset_mode;
711 ppc->ppc_type = PPC_TYPE_GENERIC;
712 ppc_generic_setmode(ppc, chipset_mode);
714 return(chipset_mode);
720 * ppc_smc37c66xgt_detect
722 * SMC FDC37C66xGT configuration.
725 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
730 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
732 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
735 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
738 * Detection: enter configuration mode and read CRD register.
742 outb(csr, SMC665_iCODE);
743 outb(csr, SMC665_iCODE);
747 if (inb(cio) == 0x65) {
752 for (i = 0; i < 2; i++) {
754 outb(csr, SMC666_iCODE);
755 outb(csr, SMC666_iCODE);
759 if (inb(cio) == 0x66) {
764 /* Another chance, CSR may be hard-configured to be at 0x370 */
770 * If chipset not found, do not continue.
778 /* read the port's address: bits 0 and 1 of CR1 */
779 r = inb(cio) & SMC_CR1_ADDR;
780 if (port_address[(int)r] != ppc->ppc_base)
783 ppc->ppc_model = type;
786 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
787 * If SPP mode is detected, try to set ECP+EPP mode
792 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit,
796 printf(" CR4=0x%x", inb(cio) & 0xff);
803 /* autodetect mode */
805 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
806 if (type == SMC_37C666GT) {
807 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
809 printf(" configuration hardwired, supposing " \
813 if ((inb(cio) & SMC_CR1_MODE) == 0) {
814 /* already in extended parallel port mode, read CR4 */
816 r = (inb(cio) & SMC_CR4_EMODE);
820 ppc->ppc_avm |= PPB_SPP;
826 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
832 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
838 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
840 printf(" ECP+EPP SPP");
844 /* not an extended port mode */
845 ppc->ppc_avm |= PPB_SPP;
852 ppc->ppc_avm = chipset_mode;
854 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
855 if (type == SMC_37C666GT)
859 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
860 /* do not use ECP when the mode is not forced to */
861 outb(cio, r | SMC_CR1_MODE);
865 /* an extended mode is selected */
866 outb(cio, r & ~SMC_CR1_MODE);
868 /* read CR4 register and reset mode field */
870 r = inb(cio) & ~SMC_CR4_EMODE;
872 if (chipset_mode & PPB_ECP) {
873 if (chipset_mode & PPB_EPP) {
874 outb(cio, r | SMC_ECPEPP);
878 outb(cio, r | SMC_ECP);
884 outb(cio, r | SMC_EPPSPP);
889 ppc->ppc_avm = chipset_mode;
892 /* set FIFO threshold to 16 */
893 if (ppc->ppc_avm & PPB_ECP) {
904 if (ppc->ppc_avm & PPB_EPP) {
910 * Set the EPP protocol...
911 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
913 if (ppc->ppc_epp == EPP_1_9)
914 outb(cio, (r & ~SMC_CR4_EPPTYPE));
916 outb(cio, (r | SMC_CR4_EPPTYPE));
919 /* end config mode */
922 ppc->ppc_type = PPC_TYPE_SMCLIKE;
923 ppc_smclike_setmode(ppc, chipset_mode);
925 return (chipset_mode);
929 * SMC FDC37C935 configuration
930 * Found on many Alpha machines
933 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
938 outb(SMC935_CFG, 0x55); /* enter config mode */
939 outb(SMC935_CFG, 0x55);
942 outb(SMC935_IND, SMC935_ID); /* check device id */
943 if (inb(SMC935_DAT) == 0x2)
947 outb(SMC935_CFG, 0xaa); /* exit config mode */
951 ppc->ppc_model = type;
953 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
954 outb(SMC935_DAT, 3); /* which is logical device 3 */
956 /* set io port base */
957 outb(SMC935_IND, SMC935_PORTHI);
958 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
959 outb(SMC935_IND, SMC935_PORTLO);
960 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
963 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
965 ppc->ppc_avm = chipset_mode;
966 outb(SMC935_IND, SMC935_PPMODE);
967 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
969 /* SPP + EPP or just plain SPP */
970 if (chipset_mode & (PPB_SPP)) {
971 if (chipset_mode & PPB_EPP) {
972 if (ppc->ppc_epp == EPP_1_9) {
973 outb(SMC935_IND, SMC935_PPMODE);
974 outb(SMC935_DAT, SMC935_EPP19SPP);
976 if (ppc->ppc_epp == EPP_1_7) {
977 outb(SMC935_IND, SMC935_PPMODE);
978 outb(SMC935_DAT, SMC935_EPP17SPP);
981 outb(SMC935_IND, SMC935_PPMODE);
982 outb(SMC935_DAT, SMC935_SPP);
986 /* ECP + EPP or just plain ECP */
987 if (chipset_mode & PPB_ECP) {
988 if (chipset_mode & PPB_EPP) {
989 if (ppc->ppc_epp == EPP_1_9) {
990 outb(SMC935_IND, SMC935_PPMODE);
991 outb(SMC935_DAT, SMC935_ECPEPP19);
993 if (ppc->ppc_epp == EPP_1_7) {
994 outb(SMC935_IND, SMC935_PPMODE);
995 outb(SMC935_DAT, SMC935_ECPEPP17);
998 outb(SMC935_IND, SMC935_PPMODE);
999 outb(SMC935_DAT, SMC935_ECP);
1004 outb(SMC935_CFG, 0xaa); /* exit config mode */
1006 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1007 ppc_smclike_setmode(ppc, chipset_mode);
1009 return (chipset_mode);
1013 * Winbond W83877F stuff
1015 * EFER: extended function enable register
1016 * EFIR: extended function index register
1017 * EFDR: extended function data register
1019 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
1020 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
1022 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
1023 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
1024 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
1025 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
1028 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
1031 unsigned char r, hefere, hefras;
1033 for (i = 0; i < 4; i ++) {
1034 /* first try to enable configuration registers */
1035 efer = w83877f_efers[i];
1037 /* write the key to the EFER */
1038 for (j = 0; j < w83877f_keyiter[i]; j ++)
1039 outb (efer, w83877f_keys[i]);
1041 /* then check HEFERE and HEFRAS bits */
1043 hefere = inb(efdr) & WINB_HEFERE;
1046 hefras = inb(efdr) & WINB_HEFRAS;
1050 * 0 1 write 89h to 250h (power-on default)
1051 * 1 0 write 86h twice to 3f0h
1052 * 1 1 write 87h twice to 3f0h
1053 * 0 0 write 88h to 250h
1055 if ((hefere | hefras) == w83877f_hefs[i])
1059 return (-1); /* failed */
1062 /* check base port address - read from CR23 */
1064 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1067 /* read CHIP ID from CR9/bits0-3 */
1070 switch (inb(efdr) & WINB_CHIPID) {
1071 case WINB_W83877F_ID:
1072 ppc->ppc_model = WINB_W83877F;
1075 case WINB_W83877AF_ID:
1076 ppc->ppc_model = WINB_W83877AF;
1080 ppc->ppc_model = WINB_UNKNOWN;
1084 /* dump of registers */
1085 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]);
1086 for (i = 0; i <= 0xd; i ++) {
1088 printf("0x%x ", inb(efdr));
1090 for (i = 0x10; i <= 0x17; i ++) {
1092 printf("0x%x ", inb(efdr));
1095 printf("0x%x ", inb(efdr));
1096 for (i = 0x20; i <= 0x29; i ++) {
1098 printf("0x%x ", inb(efdr));
1101 printf("ppc%d:", ppc->ppc_unit);
1104 ppc->ppc_type = PPC_TYPE_GENERIC;
1106 if (!chipset_mode) {
1107 /* autodetect mode */
1111 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1115 r |= (inb(efdr) & WINB_PRTMODS2);
1120 printf("ppc%d: W83757 compatible mode\n",
1122 return (-1); /* generic or SMC-like */
1129 printf(" not in parallel port mode\n");
1132 case (WINB_PARALLEL | WINB_EPP_SPP):
1133 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1138 case (WINB_PARALLEL | WINB_ECP):
1139 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1144 case (WINB_PARALLEL | WINB_ECP_EPP):
1145 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1146 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1149 printf(" ECP+EPP SPP");
1152 printf("%s: unknown case (0x%x)!\n", __func__, r);
1158 /* select CR9 and set PRTMODS2 bit */
1160 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1162 /* select CR0 and reset PRTMODSx bits */
1164 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1166 if (chipset_mode & PPB_ECP) {
1167 if (chipset_mode & PPB_EPP) {
1168 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1172 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1175 outb(efdr, inb(efdr) | WINB_ECP);
1180 /* select EPP_SPP otherwise */
1181 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1185 ppc->ppc_avm = chipset_mode;
1191 /* exit configuration mode */
1194 switch (ppc->ppc_type) {
1195 case PPC_TYPE_SMCLIKE:
1196 ppc_smclike_setmode(ppc, chipset_mode);
1199 ppc_generic_setmode(ppc, chipset_mode);
1203 return (chipset_mode);
1208 * ppc_generic_detect
1211 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1213 /* default to generic */
1214 ppc->ppc_type = PPC_TYPE_GENERIC;
1217 printf("ppc%d:", ppc->ppc_unit);
1219 /* first, check for ECP */
1220 w_ecr(ppc, PPC_ECR_PS2);
1221 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1222 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1226 /* search for SMC style ECP+EPP mode */
1227 w_ecr(ppc, PPC_ECR_EPP);
1230 /* try to reset EPP timeout bit */
1231 if (ppc_check_epp_timeout(ppc)) {
1232 ppc->ppc_dtm |= PPB_EPP;
1234 if (ppc->ppc_dtm & PPB_ECP) {
1235 /* SMC like chipset found */
1236 ppc->ppc_model = SMC_LIKE;
1237 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1246 /* restore to standard mode */
1247 w_ecr(ppc, PPC_ECR_STD);
1250 /* XXX try to detect NIBBLE and PS2 modes */
1251 ppc->ppc_dtm |= PPB_NIBBLE;
1257 ppc->ppc_avm = chipset_mode;
1259 ppc->ppc_avm = ppc->ppc_dtm;
1264 switch (ppc->ppc_type) {
1265 case PPC_TYPE_SMCLIKE:
1266 ppc_smclike_setmode(ppc, chipset_mode);
1269 ppc_generic_setmode(ppc, chipset_mode);
1273 return (chipset_mode);
1279 * mode is the mode suggested at boot
1282 ppc_detect(struct ppc_data *ppc, int chipset_mode)
1284 #ifdef PPC_PROBE_CHIPSET
1287 /* list of supported chipsets */
1288 int (*chipset_detect[])(struct ppc_data *, int) = {
1290 ppc_smc37c66xgt_detect,
1292 ppc_smc37c935_detect,
1298 /* if can't find the port and mode not forced return error */
1299 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1300 return (EIO); /* failed, port not present */
1302 /* assume centronics compatible mode is supported */
1303 ppc->ppc_avm = PPB_COMPATIBLE;
1305 #ifdef PPC_PROBE_CHIPSET
1306 /* we have to differenciate available chipset modes,
1307 * chipset running modes and IEEE-1284 operating modes
1309 * after detection, the port must support running in compatible mode
1311 if (ppc->ppc_flags & 0x40) {
1313 printf("ppc: chipset forced to generic\n");
1316 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1318 #ifdef PPC_PROBE_CHIPSET
1320 for (i=0; chipset_detect[i] != NULL; i++) {
1321 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1322 ppc->ppc_mode = mode;
1329 /* configure/detect ECP FIFO */
1330 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1331 ppc_detect_fifo(ppc);
1337 * ppc_exec_microseq()
1339 * Execute a microsequence.
1340 * Microsequence mechanism is supposed to handle fast I/O operations.
1343 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1345 struct ppc_data *ppc = DEVTOSOFTC(dev);
1346 struct ppb_microseq *mi;
1356 struct ppb_microseq *stack = 0;
1358 /* microsequence registers are equivalent to PC-like port registers */
1360 #define r_reg(register,ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, register))
1361 #define w_reg(register, ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, register, byte))
1363 #define INCR_PC (mi ++) /* increment program counter */
1367 switch (mi->opcode) {
1369 cc = r_reg(mi->arg[0].i, ppc);
1370 cc &= (char)mi->arg[2].i; /* clear mask */
1371 cc |= (char)mi->arg[1].i; /* assert mask */
1372 w_reg(mi->arg[0].i, ppc, cc);
1376 case MS_OP_RASSERT_P:
1380 if ((len = mi->arg[0].i) == MS_ACCUM) {
1381 accum = ppc->ppc_accum;
1382 for (; accum; accum--)
1383 w_reg(reg, ppc, *ptr++);
1384 ppc->ppc_accum = accum;
1386 for (i=0; i<len; i++)
1387 w_reg(reg, ppc, *ptr++);
1393 case MS_OP_RFETCH_P:
1395 mask = (char)mi->arg[2].i;
1398 if ((len = mi->arg[0].i) == MS_ACCUM) {
1399 accum = ppc->ppc_accum;
1400 for (; accum; accum--)
1401 *ptr++ = r_reg(reg, ppc) & mask;
1402 ppc->ppc_accum = accum;
1404 for (i=0; i<len; i++)
1405 *ptr++ = r_reg(reg, ppc) & mask;
1412 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1420 /* let's suppose the next instr. is the same */
1422 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1423 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1425 if (mi->opcode == MS_OP_DELAY) {
1426 DELAY(mi->arg[0].i);
1434 tsleep(NULL, 0, "ppbdelay",
1435 mi->arg[0].i * (hz/1000));
1441 iter = mi->arg[1].i;
1442 p = (char *)mi->arg[2].p;
1444 /* XXX delay limited to 255 us */
1445 for (i=0; i<iter; i++) {
1446 w_reg(reg, ppc, *p++);
1447 DELAY((unsigned char)*p++);
1453 ppc->ppc_accum = mi->arg[0].i;
1458 if (--ppc->ppc_accum > 0)
1465 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1472 if ((cc & (char)mi->arg[0].i) == 0)
1479 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1487 * If the C call returns !0 then end the microseq.
1488 * The current state of ptr is passed to the C function
1490 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1497 ppc->ppc_ptr = (char *)mi->arg[0].p;
1503 panic("%s: too much calls", __func__);
1506 /* store the state of the actual
1511 /* jump to the new microsequence */
1512 mi = (struct ppb_microseq *)mi->arg[0].p;
1519 /* retrieve microseq and pc state before the call */
1522 /* reset the stack */
1525 /* XXX return code */
1533 /* can't return to ppb level during the execution
1534 * of a submicrosequence */
1536 panic("%s: can't return to ppb level",
1539 /* update pc for ppb level of execution */
1542 /* return to ppb level of execution */
1546 panic("%s: unknown microsequence opcode 0x%x",
1547 __func__, mi->opcode);
1557 device_t dev = (device_t)arg;
1558 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev);
1559 u_char ctr, ecr, str;
1566 printf("![%x/%x/%x]", ctr, ecr, str);
1569 /* don't use ecp mode with IRQENABLE set */
1570 if (ctr & IRQENABLE) {
1574 /* interrupts are generated by nFault signal
1575 * only in ECP mode */
1576 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1577 /* check if ppc driver has programmed the
1578 * nFault interrupt */
1579 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1581 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1582 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1584 /* shall be handled by underlying layers XXX */
1589 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1590 /* disable interrupts (should be done by hardware though) */
1591 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1592 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1595 /* check if DMA completed */
1596 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1601 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1604 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1614 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1616 /* wakeup the waiting process */
1617 wakeup((caddr_t)ppc);
1620 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1622 /* classic interrupt I/O */
1623 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1630 ppc_read(device_t dev, char *buf, int len, int mode)
1636 * Call this function if you want to send data in any advanced mode
1637 * of your parallel port: FIFO, DMA
1639 * If what you want is not possible (no ECP, no DMA...),
1640 * EINVAL is returned
1643 ppc_write(device_t dev, char *buf, int len, int how)
1645 struct ppc_data *ppc = DEVTOSOFTC(dev);
1646 char ecr, ecr_sav, ctr, ctr_sav;
1654 ecr_sav = r_ecr(ppc);
1655 ctr_sav = r_ctr(ppc);
1658 * Send buffer with DMA, FIFO and interrupts
1660 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_registered)) {
1662 if (ppc->ppc_dmachan > 0) {
1664 /* byte mode, no intr, no DMA, dir=0, flush fifo
1666 ecr = PPC_ECR_STD | PPC_DISABLE_INTR;
1669 /* disable nAck interrupts */
1674 ppc->ppc_dmaflags = 0;
1675 ppc->ppc_dmaddr = (caddr_t)buf;
1676 ppc->ppc_dmacnt = (u_int)len;
1678 switch (ppc->ppc_mode) {
1679 case PPB_COMPATIBLE:
1680 /* compatible mode with FIFO, no intr, DMA, dir=0 */
1681 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1684 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1694 /* enter splhigh() not to be preempted
1695 * by the dma interrupt, we may miss
1696 * the wakeup otherwise
1700 ppc->ppc_dmastat = PPC_DMA_INIT;
1702 /* enable interrupts */
1703 ecr &= ~PPC_SERVICE_INTR;
1704 ppc->ppc_irqstat = PPC_IRQ_DMA;
1713 printf("s%d", ppc->ppc_dmacnt);
1715 ppc->ppc_dmastat = PPC_DMA_STARTED;
1717 /* Wait for the DMA completed interrupt. We hope we won't
1718 * miss it, otherwise a signal will be necessary to unlock the
1723 error = tsleep((caddr_t)ppc, PCATCH, "ppcdma", 0);
1725 } while (error == EWOULDBLOCK);
1735 ppc->ppc_dmaflags, ppc->ppc_dmaddr,
1736 ppc->ppc_dmacnt, ppc->ppc_dmachan);
1738 /* no dma, no interrupt, flush the fifo */
1739 w_ecr(ppc, PPC_ECR_RESET);
1741 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1745 /* wait for an empty fifo */
1746 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
1748 for (spin=100; spin; spin--)
1749 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
1754 error = tsleep((caddr_t)ppc, PCATCH, "ppcfifo", hz/100);
1755 if (error != EWOULDBLOCK) {
1759 /* no dma, no interrupt, flush the fifo */
1760 w_ecr(ppc, PPC_ECR_RESET);
1762 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1769 /* no dma, no interrupt, flush the fifo */
1770 w_ecr(ppc, PPC_ECR_RESET);
1773 error = EINVAL; /* XXX we should FIFO and
1780 /* PDRQ must be kept unasserted until nPDACK is
1781 * deasserted for a minimum of 350ns (SMC datasheet)
1783 * Consequence may be a FIFO that never empty
1787 w_ecr(ppc, ecr_sav);
1788 w_ctr(ppc, ctr_sav);
1794 ppc_reset_epp(device_t dev)
1796 struct ppc_data *ppc = DEVTOSOFTC(dev);
1798 ppc_reset_epp_timeout(ppc);
1804 ppc_setmode(device_t dev, int mode)
1806 struct ppc_data *ppc = DEVTOSOFTC(dev);
1808 switch (ppc->ppc_type) {
1809 case PPC_TYPE_SMCLIKE:
1810 return (ppc_smclike_setmode(ppc, mode));
1813 case PPC_TYPE_GENERIC:
1815 return (ppc_generic_setmode(ppc, mode));
1823 static struct isa_pnp_id lpc_ids[] = {
1824 { 0x0004d041, "Standard parallel printer port" }, /* PNP0400 */
1825 { 0x0104d041, "ECP parallel printer port" }, /* PNP0401 */
1830 ppc_probe(device_t dev)
1833 static short next_bios_ppc = 0;
1835 struct ppc_data *ppc;
1840 parent = device_get_parent(dev);
1842 error = ISA_PNP_PROBE(parent, dev, lpc_ids);
1845 else if (error != 0) /* XXX shall be set after detection */
1846 device_set_desc(dev, "Parallel port");
1849 * Allocate the ppc_data structure.
1851 ppc = DEVTOSOFTC(dev);
1852 bzero(ppc, sizeof(struct ppc_data));
1854 ppc->rid_irq = ppc->rid_drq = ppc->rid_ioport = 0;
1855 ppc->res_irq = ppc->res_drq = ppc->res_ioport = 0;
1857 /* retrieve ISA parameters */
1858 error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, NULL);
1862 * If port not specified, use bios list.
1865 if((next_bios_ppc < BIOS_MAX_PPC) &&
1866 (*(BIOS_PORTS+next_bios_ppc) != 0) ) {
1867 port = *(BIOS_PORTS+next_bios_ppc++);
1869 device_printf(dev, "parallel port found at 0x%x\n",
1872 device_printf(dev, "parallel port not found.\n");
1875 bus_set_resource(dev, SYS_RES_IOPORT, 0, port,
1876 IO_LPTSIZE_EXTENDED);
1880 /* IO port is mandatory */
1882 /* Try "extended" IO port range...*/
1883 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1884 &ppc->rid_ioport, 0, ~0,
1885 IO_LPTSIZE_EXTENDED, RF_ACTIVE);
1887 if (ppc->res_ioport != 0) {
1889 device_printf(dev, "using extended I/O port range\n");
1891 /* Failed? If so, then try the "normal" IO port range... */
1892 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1893 &ppc->rid_ioport, 0, ~0,
1896 if (ppc->res_ioport != 0) {
1898 device_printf(dev, "using normal I/O port range\n");
1900 device_printf(dev, "cannot reserve I/O port range\n");
1905 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1907 ppc->bsh = rman_get_bushandle(ppc->res_ioport);
1908 ppc->bst = rman_get_bustag(ppc->res_ioport);
1910 ppc->ppc_flags = device_get_flags(dev);
1912 if (!(ppc->ppc_flags & 0x20)) {
1913 ppc->res_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &ppc->rid_irq,
1914 0ul, ~0ul, 1, RF_SHAREABLE);
1915 ppc->res_drq = bus_alloc_resource(dev, SYS_RES_DRQ, &ppc->rid_drq,
1916 0ul, ~0ul, 1, RF_ACTIVE);
1920 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1922 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1924 ppc->ppc_unit = device_get_unit(dev);
1925 ppc->ppc_model = GENERIC;
1927 ppc->ppc_mode = PPB_COMPATIBLE;
1928 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1930 ppc->ppc_type = PPC_TYPE_GENERIC;
1933 * Try to detect the chipset and its mode.
1935 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1941 if (ppc->res_irq != 0) {
1942 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1945 if (ppc->res_ioport != 0) {
1946 bus_deactivate_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1948 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1951 if (ppc->res_drq != 0) {
1952 bus_deactivate_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1954 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1961 ppc_attach(device_t dev)
1963 struct ppc_data *ppc = DEVTOSOFTC(dev);
1966 device_t parent = device_get_parent(dev);
1968 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1969 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1970 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1971 ppc_epp_protocol[ppc->ppc_epp] : "");
1974 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1975 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1977 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) {
1978 /* acquire the DMA channel forever */ /* XXX */
1979 isa_dma_acquire(ppc->ppc_dmachan);
1980 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */
1983 /* add ppbus as a child of this isa to parallel bridge */
1984 ppbus = device_add_child(dev, "ppbus", -1);
1987 * Probe the ppbus and attach devices found.
1989 device_probe_and_attach(ppbus);
1991 /* register the ppc interrupt handler as default */
1993 /* default to the tty mask for registration */ /* XXX */
1994 if (BUS_SETUP_INTR(parent, dev, ppc->res_irq, 0,
1996 &ppc->intr_cookie, NULL) == 0) {
1997 /* remember the ppcintr is registered */
1998 ppc->ppc_registered = 1;
2006 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
2008 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
2011 bus_space_write_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
2014 bus_space_write_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
2017 bus_space_write_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
2020 bus_space_read_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
2023 bus_space_read_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
2026 bus_space_read_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
2029 return (r_dtr(ppc));
2032 return (r_str(ppc));
2035 return (r_ctr(ppc));
2038 return (r_epp_A(ppc));
2041 return (r_epp_D(ppc));
2044 return (r_ecr(ppc));
2047 return (r_fifo(ppc));
2071 panic("%s: unknown I/O operation", __func__);
2075 return (0); /* not significative */
2079 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
2081 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
2084 case PPC_IVAR_EPP_PROTO:
2085 *val = (u_long)ppc->ppc_epp;
2088 *val = (u_long)ppc->ppc_irq;
2098 * Resource is useless here since ppbus devices' interrupt handlers are
2099 * multiplexed to the same resource initially allocated by ppc
2102 ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags,
2103 void (*ihand)(void *), void *arg,
2104 void **cookiep, lwkt_serialize_t serializer)
2107 struct ppc_data *ppc = DEVTOSOFTC(bus);
2109 if (ppc->ppc_registered) {
2110 /* XXX refuse registration if DMA is in progress */
2112 /* first, unregister the default interrupt handler */
2113 if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus),
2114 bus, ppc->res_irq, ppc->intr_cookie)))
2117 /* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */
2118 /* ppc->res_irq); */
2120 /* DMA/FIFO operation won't be possible anymore */
2121 ppc->ppc_registered = 0;
2124 /* pass registration to the upper layer, ignore the incoming resource */
2125 return (BUS_SETUP_INTR(device_get_parent(bus), child,
2126 r, flags, ihand, arg, cookiep, serializer));
2130 * When no underlying device has a registered interrupt, register the ppc
2134 ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih)
2137 struct ppc_data *ppc = DEVTOSOFTC(bus);
2138 device_t parent = device_get_parent(bus);
2140 /* pass unregistration to the upper layer */
2141 if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih)))
2144 /* default to the tty mask for registration */ /* XXX */
2146 !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq,
2148 &ppc->intr_cookie, NULL))
2150 /* remember the ppcintr is registered */
2151 ppc->ppc_registered = 1;
2157 DRIVER_MODULE(ppc, isa, ppc_driver, ppc_devclass, 0, 0);