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32 ******************************************************************************/
36 * 82542 Gigabit Ethernet Controller
39 #include "e1000_api.h"
41 static s32 e1000_init_phy_params_82542(struct e1000_hw *hw);
42 static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw);
43 static s32 e1000_init_mac_params_82542(struct e1000_hw *hw);
44 static s32 e1000_get_bus_info_82542(struct e1000_hw *hw);
45 static s32 e1000_reset_hw_82542(struct e1000_hw *hw);
46 static s32 e1000_init_hw_82542(struct e1000_hw *hw);
47 static s32 e1000_setup_link_82542(struct e1000_hw *hw);
48 static s32 e1000_led_on_82542(struct e1000_hw *hw);
49 static s32 e1000_led_off_82542(struct e1000_hw *hw);
50 static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index);
51 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw);
54 * e1000_init_phy_params_82542 - Init PHY func ptrs.
55 * @hw: pointer to the HW structure
57 static s32 e1000_init_phy_params_82542(struct e1000_hw *hw)
59 struct e1000_phy_info *phy = &hw->phy;
60 s32 ret_val = E1000_SUCCESS;
62 DEBUGFUNC("e1000_init_phy_params_82542");
64 phy->type = e1000_phy_none;
70 * e1000_init_nvm_params_82542 - Init NVM func ptrs.
71 * @hw: pointer to the HW structure
73 static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw)
75 struct e1000_nvm_info *nvm = &hw->nvm;
77 DEBUGFUNC("e1000_init_nvm_params_82542");
79 nvm->address_bits = 6;
82 nvm->type = e1000_nvm_eeprom_microwire;
85 /* Function Pointers */
86 nvm->ops.read = e1000_read_nvm_microwire;
87 nvm->ops.release = e1000_stop_nvm;
88 nvm->ops.write = e1000_write_nvm_microwire;
89 nvm->ops.update = e1000_update_nvm_checksum_generic;
90 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
96 * e1000_init_mac_params_82542 - Init MAC func ptrs.
97 * @hw: pointer to the HW structure
99 static s32 e1000_init_mac_params_82542(struct e1000_hw *hw)
101 struct e1000_mac_info *mac = &hw->mac;
103 DEBUGFUNC("e1000_init_mac_params_82542");
106 hw->phy.media_type = e1000_media_type_fiber;
108 /* Set mta register count */
109 mac->mta_reg_count = 128;
110 /* Set rar entry count */
111 mac->rar_entry_count = E1000_RAR_ENTRIES;
113 /* Function pointers */
115 /* bus type/speed/width */
116 mac->ops.get_bus_info = e1000_get_bus_info_82542;
118 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
120 mac->ops.reset_hw = e1000_reset_hw_82542;
121 /* hw initialization */
122 mac->ops.init_hw = e1000_init_hw_82542;
124 mac->ops.setup_link = e1000_setup_link_82542;
125 /* phy/fiber/serdes setup */
126 mac->ops.setup_physical_interface = e1000_setup_fiber_serdes_link_generic;
128 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
129 /* multicast address update */
130 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
132 mac->ops.write_vfta = e1000_write_vfta_generic;
134 mac->ops.clear_vfta = e1000_clear_vfta_generic;
136 mac->ops.mta_set = e1000_mta_set_generic;
138 mac->ops.rar_set = e1000_rar_set_82542;
139 /* turn on/off LED */
140 mac->ops.led_on = e1000_led_on_82542;
141 mac->ops.led_off = e1000_led_off_82542;
142 /* clear hardware counters */
143 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542;
145 mac->ops.get_link_up_info = e1000_get_speed_and_duplex_fiber_serdes_generic;
147 return E1000_SUCCESS;
151 * e1000_init_function_pointers_82542 - Init func ptrs.
152 * @hw: pointer to the HW structure
154 * Called to initialize all function pointers and parameters.
156 void e1000_init_function_pointers_82542(struct e1000_hw *hw)
158 DEBUGFUNC("e1000_init_function_pointers_82542");
160 hw->mac.ops.init_params = e1000_init_mac_params_82542;
161 hw->nvm.ops.init_params = e1000_init_nvm_params_82542;
162 hw->phy.ops.init_params = e1000_init_phy_params_82542;
166 * e1000_get_bus_info_82542 - Obtain bus information for adapter
167 * @hw: pointer to the HW structure
169 * This will obtain information about the HW bus for which the
170 * adapter is attached and stores it in the hw structure.
172 static s32 e1000_get_bus_info_82542(struct e1000_hw *hw)
174 DEBUGFUNC("e1000_get_bus_info_82542");
176 hw->bus.type = e1000_bus_type_pci;
177 hw->bus.speed = e1000_bus_speed_unknown;
178 hw->bus.width = e1000_bus_width_unknown;
180 return E1000_SUCCESS;
184 * e1000_reset_hw_82542 - Reset hardware
185 * @hw: pointer to the HW structure
187 * This resets the hardware into a known state.
189 static s32 e1000_reset_hw_82542(struct e1000_hw *hw)
191 struct e1000_bus_info *bus = &hw->bus;
192 s32 ret_val = E1000_SUCCESS;
195 DEBUGFUNC("e1000_reset_hw_82542");
197 if (hw->revision_id == E1000_REVISION_2) {
198 DEBUGOUT("Disabling MWI on 82542 rev 2\n");
199 e1000_pci_clear_mwi(hw);
202 DEBUGOUT("Masking off all interrupts\n");
203 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
205 E1000_WRITE_REG(hw, E1000_RCTL, 0);
206 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
207 E1000_WRITE_FLUSH(hw);
210 * Delay to allow any outstanding PCI transactions to complete before
211 * resetting the device
215 ctrl = E1000_READ_REG(hw, E1000_CTRL);
217 DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n");
218 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
220 hw->nvm.ops.reload(hw);
223 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
224 icr = E1000_READ_REG(hw, E1000_ICR);
226 if (hw->revision_id == E1000_REVISION_2) {
227 if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
228 e1000_pci_set_mwi(hw);
235 * e1000_init_hw_82542 - Initialize hardware
236 * @hw: pointer to the HW structure
238 * This inits the hardware readying it for operation.
240 static s32 e1000_init_hw_82542(struct e1000_hw *hw)
242 struct e1000_mac_info *mac = &hw->mac;
243 struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542;
244 s32 ret_val = E1000_SUCCESS;
248 DEBUGFUNC("e1000_init_hw_82542");
250 /* Disabling VLAN filtering */
251 E1000_WRITE_REG(hw, E1000_VET, 0);
252 mac->ops.clear_vfta(hw);
254 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
255 if (hw->revision_id == E1000_REVISION_2) {
256 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
257 e1000_pci_clear_mwi(hw);
258 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);
259 E1000_WRITE_FLUSH(hw);
263 /* Setup the receive address. */
264 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
266 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
267 if (hw->revision_id == E1000_REVISION_2) {
268 E1000_WRITE_REG(hw, E1000_RCTL, 0);
269 E1000_WRITE_FLUSH(hw);
271 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
272 e1000_pci_set_mwi(hw);
275 /* Zero out the Multicast HASH table */
276 DEBUGOUT("Zeroing the MTA\n");
277 for (i = 0; i < mac->mta_reg_count; i++)
278 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
281 * Set the PCI priority bit correctly in the CTRL register. This
282 * determines if the adapter gives priority to receives, or if it
283 * gives equal priority to transmits and receives.
285 if (dev_spec->dma_fairness) {
286 ctrl = E1000_READ_REG(hw, E1000_CTRL);
287 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
290 /* Setup link and flow control */
291 ret_val = e1000_setup_link_82542(hw);
294 * Clear all of the statistics registers (clear on read). It is
295 * important that we do this after we have tried to establish link
296 * because the symbol error count will increment wildly if there
299 e1000_clear_hw_cntrs_82542(hw);
305 * e1000_setup_link_82542 - Setup flow control and link settings
306 * @hw: pointer to the HW structure
308 * Determines which flow control settings to use, then configures flow
309 * control. Calls the appropriate media-specific link configuration
310 * function. Assuming the adapter has a valid link partner, a valid link
311 * should be established. Assumes the hardware has previously been reset
312 * and the transmitter and receiver are not enabled.
314 static s32 e1000_setup_link_82542(struct e1000_hw *hw)
316 struct e1000_mac_info *mac = &hw->mac;
317 s32 ret_val = E1000_SUCCESS;
319 DEBUGFUNC("e1000_setup_link_82542");
321 ret_val = e1000_set_default_fc_generic(hw);
325 hw->fc.requested_mode &= ~e1000_fc_tx_pause;
327 if (mac->report_tx_early == 1)
328 hw->fc.requested_mode &= ~e1000_fc_rx_pause;
331 * Save off the requested flow control mode for use later. Depending
332 * on the link partner's capabilities, we may or may not use this mode.
334 hw->fc.current_mode = hw->fc.requested_mode;
336 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
337 hw->fc.current_mode);
339 /* Call the necessary subroutine to configure the link. */
340 ret_val = mac->ops.setup_physical_interface(hw);
345 * Initialize the flow control address, type, and PAUSE timer
346 * registers to their default values. This is done even if flow
347 * control is disabled, because it does not hurt anything to
348 * initialize these registers.
350 DEBUGOUT("Initializing Flow Control address, type and timer regs\n");
352 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
353 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
354 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
356 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
358 ret_val = e1000_set_fc_watermarks_generic(hw);
365 * e1000_led_on_82542 - Turn on SW controllable LED
366 * @hw: pointer to the HW structure
368 * Turns the SW defined LED on.
370 static s32 e1000_led_on_82542(struct e1000_hw *hw)
372 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
374 DEBUGFUNC("e1000_led_on_82542");
376 ctrl |= E1000_CTRL_SWDPIN0;
377 ctrl |= E1000_CTRL_SWDPIO0;
378 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
380 return E1000_SUCCESS;
384 * e1000_led_off_82542 - Turn off SW controllable LED
385 * @hw: pointer to the HW structure
387 * Turns the SW defined LED off.
389 static s32 e1000_led_off_82542(struct e1000_hw *hw)
391 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
393 DEBUGFUNC("e1000_led_off_82542");
395 ctrl &= ~E1000_CTRL_SWDPIN0;
396 ctrl |= E1000_CTRL_SWDPIO0;
397 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
399 return E1000_SUCCESS;
403 * e1000_rar_set_82542 - Set receive address register
404 * @hw: pointer to the HW structure
405 * @addr: pointer to the receive address
406 * @index: receive address array register
408 * Sets the receive address array register at index to the address passed
411 static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)
413 u32 rar_low, rar_high;
415 DEBUGFUNC("e1000_rar_set_82542");
418 * HW expects these in little endian so we reverse the byte order
419 * from network order (big endian) to little endian
421 rar_low = ((u32) addr[0] |
422 ((u32) addr[1] << 8) |
423 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
425 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
427 /* If MAC address zero, no need to set the AV bit */
428 if (rar_low || rar_high)
429 rar_high |= E1000_RAH_AV;
431 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
432 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
436 * e1000_translate_register_82542 - Translate the proper register offset
437 * @reg: e1000 register to be read
439 * Registers in 82542 are located in different offsets than other adapters
440 * even though they function in the same manner. This function takes in
441 * the name of the register to read and returns the correct offset for
444 u32 e1000_translate_register_82542(u32 reg)
447 * Some of the 82542 registers are located at different
448 * offsets than they are in newer adapters.
449 * Despite the difference in location, the registers
450 * function in the same manner.
533 * e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters
534 * @hw: pointer to the HW structure
536 * Clears the hardware counters by reading the counter registers.
538 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw)
540 DEBUGFUNC("e1000_clear_hw_cntrs_82542");
542 e1000_clear_hw_cntrs_base_generic(hw);
544 E1000_READ_REG(hw, E1000_PRC64);
545 E1000_READ_REG(hw, E1000_PRC127);
546 E1000_READ_REG(hw, E1000_PRC255);
547 E1000_READ_REG(hw, E1000_PRC511);
548 E1000_READ_REG(hw, E1000_PRC1023);
549 E1000_READ_REG(hw, E1000_PRC1522);
550 E1000_READ_REG(hw, E1000_PTC64);
551 E1000_READ_REG(hw, E1000_PTC127);
552 E1000_READ_REG(hw, E1000_PTC255);
553 E1000_READ_REG(hw, E1000_PTC511);
554 E1000_READ_REG(hw, E1000_PTC1023);
555 E1000_READ_REG(hw, E1000_PTC1522);