2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/i386/isa/rc.c,v 1.53.2.1 2001/02/26 04:23:10 jlemon Exp $
28 * $DragonFly: src/sys/dev/serial/rc/rc.c,v 1.12 2004/09/19 01:55:06 dillon Exp $
33 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
41 #include <sys/param.h>
42 #include <sys/systm.h>
46 #include <sys/dkstat.h>
47 #include <sys/fcntl.h>
48 #include <sys/interrupt.h>
49 #include <sys/kernel.h>
50 #include <machine/clock.h>
51 #include <machine/ipl.h>
53 #include <bus/isa/i386/isa_device.h>
55 #include <i386/isa/ic/cd180.h>
59 static int rcprobe (struct isa_device *);
60 static int rcattach (struct isa_device *);
62 #define rcin(port) RC_IN (nec, port)
63 #define rcout(port,v) RC_OUT (nec, port, v)
65 #define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__)
66 #define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd))
68 #define RC_IBUFSIZE 256
69 #define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
70 #define RC_OBUFSIZE 512
71 #define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4)
72 #define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
73 #define LOTS_OF_EVENTS 64
75 #define RC_FAKEID 0x10
80 #define GET_UNIT(dev) (minor(dev) & 0x3F)
81 #define CALLOUT(dev) (minor(dev) & 0x80)
83 /* For isa routines */
84 struct isa_driver rcdriver = {
85 rcprobe, rcattach, "rc"
88 static d_open_t rcopen;
89 static d_close_t rcclose;
90 static d_ioctl_t rcioctl;
93 static struct cdevsw rc_cdevsw = {
96 /* flags */ D_TTY | D_KQFILTER,
103 /* write */ ttywrite,
107 /* strategy */ nostrategy,
110 /* kqfilter */ ttykqfilter
113 /* Per-board structure */
114 static struct rc_softc {
115 u_int rcb_probed; /* 1 - probed, 2 - attached */
116 u_int rcb_addr; /* Base I/O addr */
117 u_int rcb_unit; /* unit # */
118 u_char rcb_dtr; /* DTR status */
119 struct rc_chans *rcb_baserc; /* base rc ptr */
122 /* Per-channel structure */
123 static struct rc_chans {
124 struct rc_softc *rc_rcb; /* back ptr */
125 u_short rc_flags; /* Misc. flags */
126 int rc_chan; /* Channel # */
127 u_char rc_ier; /* intr. enable reg */
128 u_char rc_msvr; /* modem sig. status */
129 u_char rc_cor2; /* options reg */
130 u_char rc_pendcmd; /* special cmd pending */
131 u_int rc_dtrwait; /* dtr timeout */
132 u_int rc_dcdwaits; /* how many waits DCD in open */
133 u_char rc_hotchar; /* end packed optimize */
134 struct tty *rc_tp; /* tty struct */
135 u_char *rc_iptr; /* Chars input buffer */
136 u_char *rc_hiwat; /* hi-water mark */
137 u_char *rc_bufend; /* end of buffer */
138 u_char *rc_optr; /* ptr in output buf */
139 u_char *rc_obufend; /* end of output buf */
140 struct callout rc_dtr_ch;
141 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */
142 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */
143 } rc_chans[NRC * CD180_NCHAN];
145 static int rc_scheduled_event = 0;
146 static struct callout rc_wakeup_ch;
149 static struct tty rc_tty[NRC * CD180_NCHAN];
150 static const int nrc_tty = NRC * CD180_NCHAN;
153 #define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */
154 #define RC_ACTOUT 0x0002 /* Dial-out port active */
155 #define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */
156 #define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */
157 #define RC_DORXFER 0x0010 /* RXFER event planned */
158 #define RC_DOXXFER 0x0020 /* XXFER event planned */
159 #define RC_MODCHG 0x0040 /* Modem status changed */
160 #define RC_OSUSP 0x0080 /* Output suspended */
161 #define RC_OSBUSY 0x0100 /* start() routine in progress */
162 #define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */
163 #define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */
164 #define RC_SEND_RDY 0x0800 /* ready to send */
166 /* Table for translation of RCSR status bits to internal form */
167 static int rc_rcsrt[16] = {
169 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE,
170 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
171 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE,
172 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
173 TTY_BI|TTY_PE|TTY_FE|TTY_OE
176 /* Static prototypes */
177 static ointhand2_t rcintr;
178 static void rc_hwreset (int, int, unsigned int);
179 static int rc_test (int, int);
180 static void rc_discard_output (struct rc_chans *);
181 static void rc_hardclose (struct rc_chans *);
182 static int rc_modctl (struct rc_chans *, int, int);
183 static void rc_start (struct tty *);
184 static void rc_stop (struct tty *, int rw);
185 static int rc_param (struct tty *, struct termios *);
186 static inthand2_t rcpoll;
187 static void rc_reinit (struct rc_softc *);
189 static void printrcflags();
191 static timeout_t rc_dtrwakeup;
192 static timeout_t rc_wakeup;
193 static void disc_optim (struct tty *tp, struct termios *t, struct rc_chans *);
194 static void rc_wait0 (int nec, int unit, int chan, int line);
196 /**********************************************/
198 /* Quick device probing */
201 struct isa_device *dvp;
203 int irq = ffs(dvp->id_irq) - 1;
204 int nec = dvp->id_iobase;
206 if (dvp->id_unit > NRC)
208 if (!RC_VALIDADDR(nec)) {
209 printf("rc%d: illegal base address %x\n", dvp->id_unit, nec);
212 if (!RC_VALIDIRQ(irq)) {
213 printf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq);
216 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */
217 rcout(CD180_PPRH, 0x11);
218 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11)
220 /* Now, test the board more thoroughly, with diagnostic */
221 if (rc_test(nec, dvp->id_unit))
223 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED;
230 struct isa_device *dvp;
232 int chan, nec = dvp->id_iobase;
233 struct rc_softc *rcb = &rc_softc[dvp->id_unit];
234 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN];
235 static int rc_started = 0;
238 dvp->id_ointr = rcintr;
240 /* Thorooughly test the device */
241 if (rcb->rcb_probed != RC_PROBED)
245 rcb->rcb_baserc = rc;
246 rcb->rcb_unit = dvp->id_unit;
247 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/
248 printf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit,
249 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A');
251 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
252 callout_init(&rc->rc_dtr_ch);
255 rc->rc_iptr = rc->rc_ibuf;
256 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
257 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
258 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0;
259 rc->rc_cor2 = rc->rc_pendcmd = 0;
260 rc->rc_optr = rc->rc_obufend = rc->rc_obuf;
261 rc->rc_dtrwait = 3 * hz;
264 tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)];
266 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0;
267 tp->t_cflag = TTYDEF_CFLAG;
268 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
270 rcb->rcb_probed = RC_ATTACHED;
272 cdevsw_add(&rc_cdevsw, -1, rcb->rcb_unit);
273 register_swi(SWI_TTY, rcpoll, NULL, "rcpoll");
274 callout_init(&rc_wakeup_ch);
281 /* RC interrupt handling */
286 struct rc_softc *rcb = &rc_softc[unit];
289 u_char val, iack, bsr, ucnt, *optr;
290 int good_data, t_state;
292 if (rcb->rcb_probed != RC_ATTACHED) {
293 printf("rc%d: bogus interrupt\n", unit);
298 bsr = ~(rcin(RC_BSR));
300 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
301 printf("rc%d: extra interrupt\n", unit);
302 rcout(CD180_EOIR, 0);
306 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
307 #ifdef RCDEBUG_DETAILED
308 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr,
309 (bsr & RC_BSR_TOUT)?"TOUT ":"",
310 (bsr & RC_BSR_RXINT)?"RXINT ":"",
311 (bsr & RC_BSR_TXINT)?"TXINT ":"",
312 (bsr & RC_BSR_MOINT)?"MOINT":"");
314 if (bsr & RC_BSR_TOUT) {
315 printf("rc%d: hardware failure, reset board\n", unit);
320 if (bsr & RC_BSR_RXINT) {
321 iack = rcin(RC_PILR_RX);
322 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
323 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
324 printf("rc%d: fake rxint: %02x\n", unit, iack);
327 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
328 t_state = rc->rc_tp->t_state;
329 /* Do RTS flow control stuff */
330 if ( (rc->rc_flags & RC_RTSFLOW)
331 || !(t_state & TS_ISOPEN)
333 if ( ( !(t_state & TS_ISOPEN)
334 || (t_state & TS_TBLOCK)
336 && (rc->rc_msvr & MSVR_RTS)
339 rc->rc_msvr &= ~MSVR_RTS);
340 else if (!(rc->rc_msvr & MSVR_RTS))
342 rc->rc_msvr |= MSVR_RTS);
344 ucnt = rcin(CD180_RDCR) & 0xF;
347 if (t_state & TS_ISOPEN) {
348 /* check for input buffer overflow */
349 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
351 ucnt = rc->rc_bufend - rc->rc_iptr;
353 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
354 rc->rc_flags |= RC_WAS_BUFOVFL;
355 rc_scheduled_event++;
359 /* check foor good data */
362 val = rcin(CD180_RDR);
364 optr[INPUT_FLAGS_SHIFT] = 0;
366 rc_scheduled_event++;
367 if (val != 0 && val == rc->rc_hotchar)
371 /* Store also status data */
373 iack = rcin(CD180_RCSR);
374 if (iack & RCSR_Timeout)
376 if ( (iack & RCSR_OE)
377 && !(rc->rc_flags & RC_WAS_SILOVFL)) {
378 rc->rc_flags |= RC_WAS_SILOVFL;
379 rc_scheduled_event++;
381 val = rcin(CD180_RDR);
383 Don't store PE if IGNPAR and BREAK if IGNBRK,
384 this hack allows "raw" tty optimization
385 works even if IGN* is set.
387 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
388 || ((!(iack & (RCSR_PE|RCSR_FE))
389 || !(rc->rc_tp->t_iflag & IGNPAR))
390 && (!(iack & RCSR_Break)
391 || !(rc->rc_tp->t_iflag & IGNBRK)))) {
392 if ( (iack & (RCSR_PE|RCSR_FE))
393 && (t_state & TS_CAN_BYPASS_L_RINT)
396 && (rc->rc_tp->t_iflag & INPCK))))
398 else if (val != 0 && val == rc->rc_hotchar)
401 optr[INPUT_FLAGS_SHIFT] = iack;
403 rc_scheduled_event++;
408 rc->rc_flags |= RC_DORXFER;
411 /* Clear FIFO if necessary */
412 while (resid-- > 0) {
414 iack = rcin(CD180_RCSR);
417 if (iack & RCSR_Timeout)
419 (void) rcin(CD180_RDR);
423 if (bsr & RC_BSR_MOINT) {
424 iack = rcin(RC_PILR_MODEM);
425 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
426 printf("rc%d: fake moint: %02x\n", unit, iack);
429 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
430 iack = rcin(CD180_MCR);
431 rc->rc_msvr = rcin(CD180_MSVR);
434 printrcflags(rc, "moint");
436 if (rc->rc_flags & RC_CTSFLOW) {
437 if (rc->rc_msvr & MSVR_CTS)
438 rc->rc_flags |= RC_SEND_RDY;
440 rc->rc_flags &= ~RC_SEND_RDY;
442 rc->rc_flags |= RC_SEND_RDY;
443 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
444 rc_scheduled_event += LOTS_OF_EVENTS;
445 rc->rc_flags |= RC_MODCHG;
450 if (bsr & RC_BSR_TXINT) {
451 iack = rcin(RC_PILR_TX);
452 if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
453 printf("rc%d: fake txint: %02x\n", unit, iack);
456 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
457 if ( (rc->rc_flags & RC_OSUSP)
458 || !(rc->rc_flags & RC_SEND_RDY)
461 /* Handle breaks and other stuff */
462 if (rc->rc_pendcmd) {
463 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC);
464 rcout(CD180_TDR, CD180_C_ESC);
465 rcout(CD180_TDR, rc->rc_pendcmd);
466 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
471 resid = rc->rc_obufend - optr;
472 if (resid > CD180_NFIFO)
475 rcout(CD180_TDR, *optr++);
478 /* output completed? */
479 if (optr >= rc->rc_obufend) {
480 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy);
482 printf("rc%d/%d: output completed\n", unit, rc->rc_chan);
484 if (!(rc->rc_flags & RC_DOXXFER)) {
485 rc_scheduled_event += LOTS_OF_EVENTS;
486 rc->rc_flags |= RC_DOXXFER;
492 rcout(CD180_EOIR, 0); /* end of interrupt */
494 bsr = ~(rcin(RC_BSR));
498 /* Feed characters to output buffer */
499 static void rc_start(tp)
502 struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
503 int nec = rc->rc_rcb->rcb_addr, s;
505 if (rc->rc_flags & RC_OSBUSY)
508 rc->rc_flags |= RC_OSBUSY;
510 if (tp->t_state & TS_TTSTOP)
511 rc->rc_flags |= RC_OSUSP;
513 rc->rc_flags &= ~RC_OSUSP;
514 /* Do RTS flow control stuff */
515 if ( (rc->rc_flags & RC_RTSFLOW)
516 && (tp->t_state & TS_TBLOCK)
517 && (rc->rc_msvr & MSVR_RTS)
519 rcout(CD180_CAR, rc->rc_chan);
520 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
521 } else if (!(rc->rc_msvr & MSVR_RTS)) {
522 rcout(CD180_CAR, rc->rc_chan);
523 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
526 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
529 printrcflags(rc, "rcstart");
533 printf("rcstart: outq = %d obuf = %d\n",
534 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
536 if (tp->t_state & TS_BUSY)
537 goto out; /* output still in progress ... */
539 if (tp->t_outq.c_cc > 0) {
542 tp->t_state |= TS_BUSY;
543 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
545 rc->rc_optr = rc->rc_obuf;
546 rc->rc_obufend = rc->rc_optr + ocnt;
548 if (!(rc->rc_ier & IER_TxRdy)) {
550 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan);
552 rcout(CD180_CAR, rc->rc_chan);
553 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy);
557 rc->rc_flags &= ~RC_OSBUSY;
561 /* Handle delayed events. */
566 struct rc_softc *rcb;
569 int chan, icnt, nec, unit;
571 if (rc_scheduled_event == 0)
574 for (unit = 0; unit < NRC; unit++) {
575 rcb = &rc_softc[unit];
576 rc = rcb->rcb_baserc;
577 nec = rc->rc_rcb->rcb_addr;
578 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
581 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
582 RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
583 printrcflags(rc, "rcevent");
585 if (rc->rc_flags & RC_WAS_BUFOVFL) {
587 rc->rc_flags &= ~RC_WAS_BUFOVFL;
588 rc_scheduled_event--;
590 printf("rc%d/%d: interrupt-level buffer overflow\n",
593 if (rc->rc_flags & RC_WAS_SILOVFL) {
595 rc->rc_flags &= ~RC_WAS_SILOVFL;
596 rc_scheduled_event--;
598 printf("rc%d/%d: silo overflow\n",
601 if (rc->rc_flags & RC_MODCHG) {
603 rc->rc_flags &= ~RC_MODCHG;
604 rc_scheduled_event -= LOTS_OF_EVENTS;
606 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD));
608 if (rc->rc_flags & RC_DORXFER) {
610 rc->rc_flags &= ~RC_DORXFER;
612 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
613 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
618 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
619 rc->rc_iptr = rc->rc_ibuf;
620 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
621 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
623 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
624 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
626 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
628 if ( (rc->rc_flags & RC_RTSFLOW)
629 && (tp->t_state & TS_ISOPEN)
630 && !(tp->t_state & TS_TBLOCK)
631 && !(rc->rc_msvr & MSVR_RTS)
633 rcout(CD180_CAR, chan);
635 rc->rc_msvr |= MSVR_RTS);
637 rc_scheduled_event -= icnt;
641 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
644 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT)
645 && !(tp->t_state & TS_LOCAL)) {
646 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER
647 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
648 && !(tp->t_state & TS_TBLOCK))
653 if (b_to_q(tptr, icnt, &tp->t_rawq))
654 printf("rc%d/%d: tty-level buffer overflow\n",
657 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
658 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
659 tp->t_state &= ~TS_TTSTOP;
660 tp->t_lflag &= ~FLUSHO;
664 for (; tptr < eptr; tptr++)
665 (*linesw[tp->t_line].l_rint)
667 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp);
671 if (rc->rc_flags & RC_DOXXFER) {
673 rc_scheduled_event -= LOTS_OF_EVENTS;
674 rc->rc_flags &= ~RC_DOXXFER;
675 rc->rc_tp->t_state &= ~TS_BUSY;
677 (*linesw[tp->t_line].l_start)(tp);
680 if (rc_scheduled_event == 0)
683 if (rc_scheduled_event >= LOTS_OF_EVENTS)
692 struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
696 printf("rc%d/%d: rc_stop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan,
697 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
700 rc_discard_output(rc);
703 rc->rc_flags &= ~RC_DORXFER;
705 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
706 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
707 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
710 rc->rc_iptr = rc->rc_ibuf;
712 rc_scheduled_event -= eptr - tptr;
714 if (tp->t_state & TS_TTSTOP)
715 rc->rc_flags |= RC_OSUSP;
717 rc->rc_flags &= ~RC_OSUSP;
722 rcopen(dev, flag, mode, td)
729 int unit, nec, s, error = 0;
731 unit = GET_UNIT(dev);
732 if (unit >= NRC * CD180_NCHAN)
734 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED)
736 rc = &rc_chans[unit];
739 nec = rc->rc_rcb->rcb_addr;
741 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
746 while (rc->rc_flags & RC_DTR_OFF) {
747 error = tsleep(&(rc->rc_dtrwait), PCATCH, "rcdtr", 0);
751 if (tp->t_state & TS_ISOPEN) {
753 if (!(rc->rc_flags & RC_ACTOUT)) {
758 if (rc->rc_flags & RC_ACTOUT) {
759 if (flag & O_NONBLOCK) {
763 error = tsleep(&rc->rc_rcb, PCATCH, "rcbi", 0);
769 if (tp->t_state & TS_XCLUDE &&
775 tp->t_oproc = rc_start;
776 tp->t_param = rc_param;
777 tp->t_stop = rc_stop;
781 tp->t_cflag |= CLOCAL;
783 tp->t_cflag &= ~CLOCAL;
785 error = rc_param(tp, &tp->t_termios);
788 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET);
790 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev))
791 (*linesw[tp->t_line].l_modem)(tp, 1);
793 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev)
794 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
796 error = tsleep(TSA_CARR_ON(tp), PCATCH, "rcdcd", 0);
802 error = (*linesw[tp->t_line].l_open)(dev, tp);
803 disc_optim(tp, &tp->t_termios, rc);
804 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev))
805 rc->rc_flags |= RC_ACTOUT;
809 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN))
816 rcclose(dev, flag, mode, td)
823 int s, unit = GET_UNIT(dev);
825 if (unit >= NRC * CD180_NCHAN)
827 rc = &rc_chans[unit];
830 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
833 (*linesw[tp->t_line].l_close)(tp, flag);
834 disc_optim(tp, &tp->t_termios, rc);
835 rc_stop(tp, FREAD | FWRITE);
842 static void rc_hardclose(rc)
845 int s, nec = rc->rc_rcb->rcb_addr;
846 struct tty *tp = rc->rc_tp;
849 rcout(CD180_CAR, rc->rc_chan);
851 /* Disable rx/tx intrs */
852 rcout(CD180_IER, rc->rc_ier = 0);
853 if ( (tp->t_cflag & HUPCL)
854 || (!(rc->rc_flags & RC_ACTOUT)
855 && !(rc->rc_msvr & MSVR_CD)
856 && !(tp->t_cflag & CLOCAL))
857 || !(tp->t_state & TS_ISOPEN)
859 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
860 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
861 (void) rc_modctl(rc, TIOCM_RTS, DMSET);
862 if (rc->rc_dtrwait) {
863 callout_reset(&rc->rc_dtr_ch, rc->rc_dtrwait,
865 rc->rc_flags |= RC_DTR_OFF;
868 rc->rc_flags &= ~RC_ACTOUT;
869 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */
870 wakeup(TSA_CARR_ON(tp));
874 /* Reset the bastard */
875 static void rc_hwreset(unit, nec, chipid)
879 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */
881 WAITFORCCR(unit, -1);
883 rcout(RC_CTOUT, 0); /* Clear timeout */
884 rcout(CD180_GIVR, chipid);
885 rcout(CD180_GICR, 0);
887 /* Set Prescaler Registers (1 msec) */
888 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
889 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
891 /* Initialize Priority Interrupt Level Registers */
892 rcout(CD180_PILR1, RC_PILR_MODEM);
893 rcout(CD180_PILR2, RC_PILR_TX);
894 rcout(CD180_PILR3, RC_PILR_RX);
900 /* Set channel parameters */
901 static int rc_param(tp, ts)
905 struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
906 int nec = rc->rc_rcb->rcb_addr;
907 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow;
909 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800
910 || ts->c_ispeed < 0 || ts->c_ispeed > 76800
913 if (ts->c_ispeed == 0)
914 ts->c_ispeed = ts->c_ospeed;
915 odivs = RC_BRD(ts->c_ospeed);
916 idivs = RC_BRD(ts->c_ispeed);
921 rcout(CD180_CAR, rc->rc_chan);
923 /* If speed == 0, hangup line */
924 if (ts->c_ospeed == 0) {
925 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
926 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
927 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
930 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
936 rcout(CD180_RBPRL, idivs & 0xFF);
937 rcout(CD180_RBPRH, idivs >> 8);
940 rcout(CD180_TBPRL, odivs & 0xFF);
941 rcout(CD180_TBPRH, odivs >> 8);
944 /* set timeout value */
945 if (ts->c_ispeed > 0) {
946 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
948 if ( !(lflag & ICANON)
949 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
950 && ts->c_cc[VTIME] * 10 > itm)
951 itm = ts->c_cc[VTIME] * 10;
953 rcout(CD180_RTPR, itm <= 255 ? itm : 255);
956 switch (cflag & CSIZE) {
957 case CS5: val = COR1_5BITS; break;
958 case CS6: val = COR1_6BITS; break;
959 case CS7: val = COR1_7BITS; break;
961 case CS8: val = COR1_8BITS; break;
963 if (cflag & PARENB) {
967 if (!(cflag & INPCK))
973 rcout(CD180_COR1, val);
975 /* Set FIFO threshold */
976 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
979 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE
980 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE
986 val |= COR3_SCDE|COR3_FCT;
988 rcout(CD180_COR3, val);
990 /* Initialize on-chip automatic flow control */
992 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
993 if (cflag & CCTS_OFLOW) {
994 rc->rc_flags |= RC_CTSFLOW;
997 rc->rc_flags |= RC_SEND_RDY;
998 if (tp->t_state & TS_TTSTOP)
999 rc->rc_flags |= RC_OSUSP;
1001 rc->rc_flags &= ~RC_OSUSP;
1002 if (cflag & CRTS_IFLOW)
1003 rc->rc_flags |= RC_RTSFLOW;
1005 rc->rc_flags &= ~RC_RTSFLOW;
1008 if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
1009 rcout(CD180_SCHR1, ts->c_cc[VSTART]);
1010 rcout(CD180_SCHR2, ts->c_cc[VSTOP]);
1016 rcout(CD180_COR2, rc->rc_cor2 = val);
1018 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1019 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1021 disc_optim(tp, ts, rc);
1024 val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
1025 if (cflag & CCTS_OFLOW)
1027 rcout(CD180_MCOR1, val);
1029 val = cflag & CLOCAL ? 0 : MCOR2_CDod;
1030 if (cflag & CCTS_OFLOW)
1032 rcout(CD180_MCOR2, val);
1034 /* enable i/o and interrupts */
1035 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1036 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1037 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
1039 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1040 if (cflag & CCTS_OFLOW)
1041 rc->rc_ier |= IER_CTS;
1043 rc->rc_ier |= IER_RxData;
1044 if (tp->t_state & TS_BUSY)
1045 rc->rc_ier |= IER_TxRdy;
1046 if (ts->c_ospeed != 0)
1047 rc_modctl(rc, TIOCM_DTR, DMBIS);
1048 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1049 rc->rc_flags |= RC_SEND_RDY;
1050 rcout(CD180_IER, rc->rc_ier);
1055 /* Re-initialize board after bogus interrupts */
1056 static void rc_reinit(rcb)
1057 struct rc_softc *rcb;
1059 struct rc_chans *rc, *rce;
1062 nec = rcb->rcb_addr;
1063 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID);
1064 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN];
1065 rce = rc + CD180_NCHAN;
1066 for (; rc < rce; rc++)
1067 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios);
1071 rcioctl(dev, cmd, data, flag, td)
1078 struct rc_chans *rc = &rc_chans[GET_UNIT(dev)];
1080 struct tty *tp = rc->rc_tp;
1082 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td);
1083 if (error != ENOIOCTL)
1085 error = ttioctl(tp, cmd, data, flag);
1086 disc_optim(tp, &tp->t_termios, rc);
1087 if (error != ENOIOCTL)
1093 rc->rc_pendcmd = CD180_C_SBRK;
1097 rc->rc_pendcmd = CD180_C_EBRK;
1101 (void) rc_modctl(rc, TIOCM_DTR, DMBIS);
1105 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1109 *(int *) data = rc_modctl(rc, 0, DMGET);
1113 (void) rc_modctl(rc, *(int *) data, DMSET);
1117 (void) rc_modctl(rc, *(int *) data, DMBIC);
1121 (void) rc_modctl(rc, *(int *) data, DMBIS);
1130 rc->rc_dtrwait = *(int *)data * hz / 100;
1134 *(int *)data = rc->rc_dtrwait * 100 / hz;
1146 /* Modem control routines */
1148 static int rc_modctl(rc, bits, cmd)
1149 struct rc_chans *rc;
1152 int nec = rc->rc_rcb->rcb_addr;
1153 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr;
1155 rcout(CD180_CAR, rc->rc_chan);
1159 rcout(RC_DTREG, (bits & TIOCM_DTR) ?
1160 ~(*dtr |= 1 << rc->rc_chan) :
1161 ~(*dtr &= ~(1 << rc->rc_chan)));
1162 msvr = rcin(CD180_MSVR);
1163 if (bits & TIOCM_RTS)
1167 if (bits & TIOCM_DTR)
1171 rcout(CD180_MSVR, msvr);
1175 if (bits & TIOCM_DTR)
1176 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1177 msvr = rcin(CD180_MSVR);
1178 if (bits & TIOCM_RTS)
1180 if (bits & TIOCM_DTR)
1182 rcout(CD180_MSVR, msvr);
1187 msvr = rc->rc_msvr = rcin(CD180_MSVR);
1189 if (msvr & MSVR_RTS)
1191 if (msvr & MSVR_CTS)
1193 if (msvr & MSVR_DSR)
1195 if (msvr & MSVR_DTR)
1199 if (~rcin(RC_RIREG) & (1 << rc->rc_chan))
1204 if (bits & TIOCM_DTR)
1205 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1206 msvr = rcin(CD180_MSVR);
1207 if (bits & TIOCM_RTS)
1209 if (bits & TIOCM_DTR)
1211 rcout(CD180_MSVR, msvr);
1214 rc->rc_msvr = rcin(CD180_MSVR);
1218 /* Test the board. */
1219 int rc_test(nec, unit)
1224 int i = 0, rcnt, old_level;
1225 unsigned int iack, chipid;
1226 unsigned short divs;
1227 static u_char ctest[] = "\377\125\252\045\244\0\377";
1230 printf("rc%d: ", unit); printf s ; printf("\n"); \
1231 (void) splx(old_level); return 1; }
1234 u_char txbuf[CD180_NFIFO]; /* TX buffer */
1235 u_char rxbuf[CD180_NFIFO]; /* RX buffer */
1236 int rxptr; /* RX pointer */
1237 int txptr; /* TX pointer */
1238 } tchans[CD180_NCHAN];
1240 old_level = spltty();
1244 /* First, reset board to inital state */
1245 rc_hwreset(unit, nec, chipid);
1247 divs = RC_BRD(19200);
1249 /* Initialize channels */
1250 for (chan = 0; chan < CD180_NCHAN; chan++) {
1252 /* Select and reset channel */
1253 rcout(CD180_CAR, chan);
1254 CCRCMD(unit, chan, CCR_ResetChan);
1255 WAITFORCCR(unit, chan);
1258 rcout(CD180_RBPRL, divs & 0xFF);
1259 rcout(CD180_RBPRH, divs >> 8);
1260 rcout(CD180_TBPRL, divs & 0xFF);
1261 rcout(CD180_TBPRH, divs >> 8);
1263 /* set timeout value */
1264 rcout(CD180_RTPR, 0);
1266 /* Establish local loopback */
1267 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1268 rcout(CD180_COR2, COR2_LLM);
1269 rcout(CD180_COR3, CD180_NFIFO);
1270 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1271 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN);
1272 WAITFORCCR(unit, chan);
1273 rcout(CD180_MSVR, MSVR_RTS);
1275 /* Fill TXBUF with test data */
1276 for (i = 0; i < CD180_NFIFO; i++) {
1277 tchans[chan].txbuf[i] = ctest[i];
1278 tchans[chan].rxbuf[i] = 0;
1280 tchans[chan].txptr = tchans[chan].rxptr = 0;
1282 /* Now, start transmit */
1283 rcout(CD180_IER, IER_TxMpty|IER_RxData);
1285 /* Pseudo-interrupt poll stuff */
1286 for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1287 i = ~(rcin(RC_BSR));
1288 if (i & RC_BSR_TOUT)
1289 ERR(("BSR timeout bit set\n"))
1290 else if (i & RC_BSR_TXINT) {
1291 iack = rcin(RC_PILR_TX);
1292 if (iack != (GIVR_IT_TDI | chipid))
1293 ERR(("Bad TX intr ack (%02x != %02x)\n",
1294 iack, GIVR_IT_TDI | chipid));
1295 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1296 /* If no more data to transmit, disable TX intr */
1297 if (tchans[chan].txptr >= CD180_NFIFO) {
1298 iack = rcin(CD180_IER);
1299 rcout(CD180_IER, iack & ~IER_TxMpty);
1301 for (iack = tchans[chan].txptr;
1302 iack < CD180_NFIFO; iack++)
1304 tchans[chan].txbuf[iack]);
1305 tchans[chan].txptr = iack;
1307 rcout(CD180_EOIR, 0);
1308 } else if (i & RC_BSR_RXINT) {
1311 iack = rcin(RC_PILR_RX);
1312 if (iack != (GIVR_IT_RGDI | chipid) &&
1313 iack != (GIVR_IT_REI | chipid))
1314 ERR(("Bad RX intr ack (%02x != %02x)\n",
1315 iack, GIVR_IT_RGDI | chipid))
1316 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1317 ucnt = rcin(CD180_RDCR) & 0xF;
1318 while (ucnt-- > 0) {
1319 iack = rcin(CD180_RCSR);
1320 if (iack & RCSR_Timeout)
1323 ERR(("Bad char chan %d (RCSR = %02X)\n",
1325 if (tchans[chan].rxptr > CD180_NFIFO)
1326 ERR(("Got extra chars chan %d\n",
1328 tchans[chan].rxbuf[tchans[chan].rxptr++] =
1331 rcout(CD180_EOIR, 0);
1334 for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1335 if (tchans[chan].rxptr >= CD180_NFIFO)
1337 if (iack == CD180_NCHAN)
1340 for (chan = 0; chan < CD180_NCHAN; chan++) {
1341 /* Select and reset channel */
1342 rcout(CD180_CAR, chan);
1343 CCRCMD(unit, chan, CCR_ResetChan);
1347 ERR(("looses characters during local loopback\n"))
1348 /* Now, check data */
1349 for (chan = 0; chan < CD180_NCHAN; chan++)
1350 for (i = 0; i < CD180_NFIFO; i++)
1351 if (ctest[i] != tchans[chan].rxbuf[i])
1352 ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1353 chan, i, ctest[i], tchans[chan].rxbuf[i]))
1354 (void) splx(old_level);
1359 static void printrcflags(rc, comment)
1360 struct rc_chans *rc;
1363 u_short f = rc->rc_flags;
1364 int nec = rc->rc_rcb->rcb_addr;
1366 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
1367 rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1368 (f & RC_DTR_OFF)?"DTR_OFF " :"",
1369 (f & RC_ACTOUT) ?"ACTOUT " :"",
1370 (f & RC_RTSFLOW)?"RTSFLOW " :"",
1371 (f & RC_CTSFLOW)?"CTSFLOW " :"",
1372 (f & RC_DORXFER)?"DORXFER " :"",
1373 (f & RC_DOXXFER)?"DOXXFER " :"",
1374 (f & RC_MODCHG) ?"MODCHG " :"",
1375 (f & RC_OSUSP) ?"OSUSP " :"",
1376 (f & RC_OSBUSY) ?"OSBUSY " :"",
1377 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1378 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1379 (f & RC_SEND_RDY) ?"SEND_RDY":"");
1381 rcout(CD180_CAR, rc->rc_chan);
1383 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
1384 rc->rc_rcb->rcb_unit, rc->rc_chan,
1389 #endif /* RCDEBUG */
1395 struct rc_chans *rc;
1397 rc = (struct rc_chans *)chan;
1398 rc->rc_flags &= ~RC_DTR_OFF;
1399 wakeup(&rc->rc_dtrwait);
1403 rc_discard_output(rc)
1404 struct rc_chans *rc;
1407 if (rc->rc_flags & RC_DOXXFER) {
1408 rc_scheduled_event -= LOTS_OF_EVENTS;
1409 rc->rc_flags &= ~RC_DOXXFER;
1411 rc->rc_optr = rc->rc_obufend;
1412 rc->rc_tp->t_state &= ~TS_BUSY;
1414 ttwwakeup(rc->rc_tp);
1421 if (rc_scheduled_event != 0) {
1428 callout_reset(&rc_wakeup_ch, 1, rc_wakeup, NULL);
1432 disc_optim(tp, t, rc)
1435 struct rc_chans *rc;
1438 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
1439 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1440 && (!(t->c_iflag & PARMRK)
1441 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
1442 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
1443 && linesw[tp->t_line].l_rint == ttyinput)
1444 tp->t_state |= TS_CAN_BYPASS_L_RINT;
1446 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1447 rc->rc_hotchar = linesw[tp->t_line].l_hotchar;
1451 rc_wait0(nec, unit, chan, line)
1452 int nec, unit, chan, line;
1456 for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--)
1459 printf("rc%d/%d: channel command timeout, rc.c line: %d\n",