2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <william.paul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $
34 * $DragonFly: src/sys/dev/netif/lge/if_lge.c,v 1.14 2004/07/29 08:46:22 dillon Exp $
36 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $
40 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
41 * documentation not available, but ask me nicely.
43 * Written by Bill Paul <william.paul@windriver.com>
48 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
49 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
50 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
51 * are three supported methods for data transfer between host and
52 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
53 * Propulsion Technology (tm) DMA. The latter mechanism is a form
54 * of double buffer DMA where the packet data is copied to a
55 * pre-allocated DMA buffer who's physical address has been loaded
56 * into a table at device initialization time. The rationale is that
57 * the virtual to physical address translation needed for normal
58 * scatter/gather DMA is more expensive than the data copy needed
59 * for double buffering. This may be true in Windows NT and the like,
60 * but it isn't true for us, at least on the x86 arch. This driver
61 * uses the scatter/gather I/O method for both TX and RX.
63 * The LXT1001 only supports TCP/IP checksum offload on receive.
64 * Also, the VLAN tagging is done using a 16-entry table which allows
65 * the chip to perform hardware filtering based on VLAN tags. Sadly,
66 * our vlan support doesn't currently play well with this kind of
70 * - Jeff James at Intel, for arranging to have the LXT1001 manual
71 * released (at long last)
72 * - Beny Chen at D-Link, for actually sending it to me
73 * - Brad Short and Keith Alexis at SMC, for sending me sample
74 * SMC9462SX and SMC9462TX adapters for testing
75 * - Paul Saab at Y!, for not killing me (though it remains to be seen
76 * if in fact he did me much of a favor)
79 #include <sys/param.h>
80 #include <sys/systm.h>
81 #include <sys/sockio.h>
83 #include <sys/malloc.h>
84 #include <sys/kernel.h>
85 #include <sys/socket.h>
88 #include <net/if_arp.h>
89 #include <net/ethernet.h>
90 #include <net/if_dl.h>
91 #include <net/if_media.h>
95 #include <vm/vm.h> /* for vtophys */
96 #include <vm/pmap.h> /* for vtophys */
97 #include <machine/clock.h> /* for DELAY */
98 #include <machine/bus_pio.h>
99 #include <machine/bus_memio.h>
100 #include <machine/bus.h>
101 #include <machine/resource.h>
103 #include <sys/rman.h>
105 #include "../mii_layer/mii.h"
106 #include "../mii_layer/miivar.h"
108 #include <bus/pci/pcireg.h>
109 #include <bus/pci/pcivar.h>
111 #define LGE_USEIOSPACE
113 #include "if_lgereg.h"
115 /* "controller miibus0" required. See GENERIC if you get errors here. */
116 #include "miibus_if.h"
119 * Various supported device vendors/types and their names.
121 static struct lge_type lge_devs[] = {
122 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
126 static int lge_probe (device_t);
127 static int lge_attach (device_t);
128 static int lge_detach (device_t);
130 static int lge_alloc_jumbo_mem (struct lge_softc *);
131 static void lge_free_jumbo_mem (struct lge_softc *);
132 static void *lge_jalloc (struct lge_softc *);
133 static void lge_jfree (caddr_t, u_int);
134 static void lge_jref (caddr_t, u_int);
136 static int lge_newbuf (struct lge_softc *,
137 struct lge_rx_desc *,
139 static int lge_encap (struct lge_softc *,
140 struct mbuf *, u_int32_t *);
141 static void lge_rxeof (struct lge_softc *, int);
142 static void lge_rxeoc (struct lge_softc *);
143 static void lge_txeof (struct lge_softc *);
144 static void lge_intr (void *);
145 static void lge_tick (void *);
146 static void lge_start (struct ifnet *);
147 static int lge_ioctl (struct ifnet *, u_long, caddr_t,
149 static void lge_init (void *);
150 static void lge_stop (struct lge_softc *);
151 static void lge_watchdog (struct ifnet *);
152 static void lge_shutdown (device_t);
153 static int lge_ifmedia_upd (struct ifnet *);
154 static void lge_ifmedia_sts (struct ifnet *, struct ifmediareq *);
156 static void lge_eeprom_getword (struct lge_softc *, int, u_int16_t *);
157 static void lge_read_eeprom (struct lge_softc *, caddr_t, int,
160 static int lge_miibus_readreg (device_t, int, int);
161 static int lge_miibus_writereg (device_t, int, int, int);
162 static void lge_miibus_statchg (device_t);
164 static void lge_setmulti (struct lge_softc *);
165 static u_int32_t lge_crc (struct lge_softc *, caddr_t);
166 static void lge_reset (struct lge_softc *);
167 static int lge_list_rx_init (struct lge_softc *);
168 static int lge_list_tx_init (struct lge_softc *);
170 #ifdef LGE_USEIOSPACE
171 #define LGE_RES SYS_RES_IOPORT
172 #define LGE_RID LGE_PCI_LOIO
174 #define LGE_RES SYS_RES_MEMORY
175 #define LGE_RID LGE_PCI_LOMEM
178 static device_method_t lge_methods[] = {
179 /* Device interface */
180 DEVMETHOD(device_probe, lge_probe),
181 DEVMETHOD(device_attach, lge_attach),
182 DEVMETHOD(device_detach, lge_detach),
183 DEVMETHOD(device_shutdown, lge_shutdown),
186 DEVMETHOD(bus_print_child, bus_generic_print_child),
187 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
190 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
191 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
192 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
197 static driver_t lge_driver = {
200 sizeof(struct lge_softc)
203 static devclass_t lge_devclass;
205 DECLARE_DUMMY_MODULE(if_lge);
206 DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0);
207 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
209 #define LGE_SETBIT(sc, reg, x) \
210 CSR_WRITE_4(sc, reg, \
211 CSR_READ_4(sc, reg) | (x))
213 #define LGE_CLRBIT(sc, reg, x) \
214 CSR_WRITE_4(sc, reg, \
215 CSR_READ_4(sc, reg) & ~(x))
218 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
221 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
224 * Read a word of data stored in the EEPROM at address 'addr.'
226 static void lge_eeprom_getword(sc, addr, dest)
227 struct lge_softc *sc;
234 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
235 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8));
237 for (i = 0; i < LGE_TIMEOUT; i++)
238 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
241 if (i == LGE_TIMEOUT) {
242 printf("lge%d: EEPROM read timed out\n", sc->lge_unit);
246 val = CSR_READ_4(sc, LGE_EEDATA);
249 *dest = (val >> 16) & 0xFFFF;
251 *dest = val & 0xFFFF;
257 * Read a sequence of words from the EEPROM.
259 static void lge_read_eeprom(sc, dest, off, cnt, swap)
260 struct lge_softc *sc;
267 u_int16_t word = 0, *ptr;
269 for (i = 0; i < cnt; i++) {
270 lge_eeprom_getword(sc, off + i, &word);
271 ptr = (u_int16_t *)(dest + (i * 2));
281 static int lge_miibus_readreg(dev, phy, reg)
285 struct lge_softc *sc;
288 sc = device_get_softc(dev);
291 * If we have a non-PCS PHY, pretend that the internal
292 * autoneg stuff at PHY address 0 isn't there so that
293 * the miibus code will find only the GMII PHY.
295 if (sc->lge_pcs == 0 && phy == 0)
298 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
300 for (i = 0; i < LGE_TIMEOUT; i++)
301 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
304 if (i == LGE_TIMEOUT) {
305 printf("lge%d: PHY read timed out\n", sc->lge_unit);
309 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
312 static int lge_miibus_writereg(dev, phy, reg, data)
316 struct lge_softc *sc;
319 sc = device_get_softc(dev);
321 CSR_WRITE_4(sc, LGE_GMIICTL,
322 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
324 for (i = 0; i < LGE_TIMEOUT; i++)
325 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
328 if (i == LGE_TIMEOUT) {
329 printf("lge%d: PHY write timed out\n", sc->lge_unit);
336 static void lge_miibus_statchg(dev)
339 struct lge_softc *sc;
340 struct mii_data *mii;
342 sc = device_get_softc(dev);
343 mii = device_get_softc(sc->lge_miibus);
345 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
346 switch (IFM_SUBTYPE(mii->mii_media_active)) {
349 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
352 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
355 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
359 * Choose something, even if it's wrong. Clearing
360 * all the bits will hose autoneg on the internal
363 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
367 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
368 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
370 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
376 static u_int32_t lge_crc(sc, addr)
377 struct lge_softc *sc;
380 u_int32_t crc, carry;
384 /* Compute CRC for the address value. */
385 crc = 0xFFFFFFFF; /* initial value */
387 for (i = 0; i < 6; i++) {
389 for (j = 0; j < 8; j++) {
390 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
394 crc = (crc ^ 0x04c11db6) | carry;
399 * return the filter bit position
401 return((crc >> 26) & 0x0000003F);
404 static void lge_setmulti(sc)
405 struct lge_softc *sc;
408 struct ifmultiaddr *ifma;
409 u_int32_t h = 0, hashes[2] = { 0, 0 };
411 ifp = &sc->arpcom.ac_if;
413 /* Make sure multicast hash table is enabled. */
414 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
416 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
417 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
418 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
422 /* first, zot all the existing hash bits */
423 CSR_WRITE_4(sc, LGE_MAR0, 0);
424 CSR_WRITE_4(sc, LGE_MAR1, 0);
426 /* now program new ones */
427 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
428 ifma = ifma->ifma_link.le_next) {
429 if (ifma->ifma_addr->sa_family != AF_LINK)
431 h = lge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
433 hashes[0] |= (1 << h);
435 hashes[1] |= (1 << (h - 32));
438 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
439 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
444 static void lge_reset(sc)
445 struct lge_softc *sc;
449 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
451 for (i = 0; i < LGE_TIMEOUT; i++) {
452 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
456 if (i == LGE_TIMEOUT)
457 printf("lge%d: reset never completed\n", sc->lge_unit);
459 /* Wait a little while for the chip to get its brains in order. */
466 * Probe for a Level 1 chip. Check the PCI vendor and device
467 * IDs against our list and return a device name if we find a match.
469 static int lge_probe(dev)
476 while(t->lge_name != NULL) {
477 if ((pci_get_vendor(dev) == t->lge_vid) &&
478 (pci_get_device(dev) == t->lge_did)) {
479 device_set_desc(dev, t->lge_name);
489 * Attach the interface. Allocate softc structures, do ifmedia
490 * setup and ethernet/BPF attach.
492 static int lge_attach(dev)
496 u_char eaddr[ETHER_ADDR_LEN];
498 struct lge_softc *sc;
500 int unit, error = 0, rid;
504 sc = device_get_softc(dev);
505 unit = device_get_unit(dev);
506 bzero(sc, sizeof(struct lge_softc));
509 * Handle power management nonsense.
511 command = pci_read_config(dev, LGE_PCI_CAPID, 4) & 0x000000FF;
512 if (command == 0x01) {
514 command = pci_read_config(dev, LGE_PCI_PWRMGMTCTRL, 4);
515 if (command & LGE_PSTATE_MASK) {
516 u_int32_t iobase, membase, irq;
518 /* Save important PCI config data. */
519 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4);
520 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4);
521 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4);
523 /* Reset the power state. */
524 printf("lge%d: chip is in D%d power mode "
525 "-- setting to D0\n", unit, command & LGE_PSTATE_MASK);
526 command &= 0xFFFFFFFC;
527 pci_write_config(dev, LGE_PCI_PWRMGMTCTRL, command, 4);
529 /* Restore PCI config data. */
530 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4);
531 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4);
532 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4);
537 * Map control/status registers.
539 command = pci_read_config(dev, PCIR_COMMAND, 4);
540 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
541 pci_write_config(dev, PCIR_COMMAND, command, 4);
542 command = pci_read_config(dev, PCIR_COMMAND, 4);
544 #ifdef LGE_USEIOSPACE
545 if (!(command & PCIM_CMD_PORTEN)) {
546 printf("lge%d: failed to enable I/O ports!\n", unit);
551 if (!(command & PCIM_CMD_MEMEN)) {
552 printf("lge%d: failed to enable memory mapping!\n", unit);
559 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid,
560 0, ~0, 1, RF_ACTIVE);
562 if (sc->lge_res == NULL) {
563 printf("lge%d: couldn't map ports/memory\n", unit);
568 sc->lge_btag = rman_get_bustag(sc->lge_res);
569 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
571 /* Allocate interrupt */
573 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
574 RF_SHAREABLE | RF_ACTIVE);
576 if (sc->lge_irq == NULL) {
577 printf("lge%d: couldn't map interrupt\n", unit);
578 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
583 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET,
584 lge_intr, sc, &sc->lge_intrhand);
587 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
588 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
589 printf("lge%d: couldn't set up irq\n", unit);
593 /* Reset the adapter. */
597 * Get station address from the EEPROM.
599 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0);
600 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0);
601 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0);
604 callout_handle_init(&sc->lge_stat_ch);
606 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
607 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
609 if (sc->lge_ldata == NULL) {
610 printf("lge%d: no memory for list buffers!\n", unit);
611 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
612 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
613 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
617 bzero(sc->lge_ldata, sizeof(struct lge_list_data));
619 /* Try to allocate memory for jumbo buffers. */
620 if (lge_alloc_jumbo_mem(sc)) {
621 printf("lge%d: jumbo buffer allocation failed\n",
623 contigfree(sc->lge_ldata,
624 sizeof(struct lge_list_data), M_DEVBUF);
625 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
626 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
627 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
632 ifp = &sc->arpcom.ac_if;
634 if_initname(ifp, "lge", unit);
635 ifp->if_mtu = ETHERMTU;
636 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
637 ifp->if_ioctl = lge_ioctl;
638 ifp->if_start = lge_start;
639 ifp->if_watchdog = lge_watchdog;
640 ifp->if_init = lge_init;
641 ifp->if_baudrate = 1000000000;
642 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1;
643 ifp->if_capabilities = IFCAP_RXCSUM;
644 ifp->if_capenable = ifp->if_capabilities;
646 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
654 if (mii_phy_probe(dev, &sc->lge_miibus,
655 lge_ifmedia_upd, lge_ifmedia_sts)) {
656 printf("lge%d: MII without any PHY!\n", sc->lge_unit);
657 contigfree(sc->lge_ldata,
658 sizeof(struct lge_list_data), M_DEVBUF);
659 lge_free_jumbo_mem(sc);
660 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
661 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
662 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
668 * Call MI attach routine.
670 ether_ifattach(ifp, eaddr);
671 callout_handle_init(&sc->lge_stat_ch);
678 static int lge_detach(dev)
681 struct lge_softc *sc;
687 sc = device_get_softc(dev);
688 ifp = &sc->arpcom.ac_if;
694 bus_generic_detach(dev);
695 device_delete_child(dev, sc->lge_miibus);
697 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
698 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
699 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
701 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF);
702 lge_free_jumbo_mem(sc);
710 * Initialize the transmit descriptors.
712 static int lge_list_tx_init(sc)
713 struct lge_softc *sc;
715 struct lge_list_data *ld;
716 struct lge_ring_data *cd;
721 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
722 ld->lge_tx_list[i].lge_mbuf = NULL;
723 ld->lge_tx_list[i].lge_ctl = 0;
726 cd->lge_tx_prod = cd->lge_tx_cons = 0;
733 * Initialize the RX descriptors and allocate mbufs for them. Note that
734 * we arralge the descriptors in a closed ring, so that the last descriptor
735 * points back to the first.
737 static int lge_list_rx_init(sc)
738 struct lge_softc *sc;
740 struct lge_list_data *ld;
741 struct lge_ring_data *cd;
747 cd->lge_rx_prod = cd->lge_rx_cons = 0;
749 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
751 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
752 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
754 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
758 /* Clear possible 'rx command queue empty' interrupt. */
759 CSR_READ_4(sc, LGE_ISR);
765 * Initialize an RX descriptor and attach an MBUF cluster.
767 static int lge_newbuf(sc, c, m)
768 struct lge_softc *sc;
769 struct lge_rx_desc *c;
772 struct mbuf *m_new = NULL;
776 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
778 printf("lge%d: no memory for rx list "
779 "-- packet dropped!\n", sc->lge_unit);
783 /* Allocate the jumbo buffer */
784 buf = lge_jalloc(sc);
787 printf("lge%d: jumbo allocation failed "
788 "-- packet dropped!\n", sc->lge_unit);
793 /* Attach the buffer to the mbuf */
794 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
795 m_new->m_flags |= M_EXT | M_EXT_OLD;
796 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
797 m_new->m_len = LGE_MCLBYTES;
798 m_new->m_ext.ext_nfree.old = lge_jfree;
799 m_new->m_ext.ext_nref.old = lge_jref;
802 m_new->m_len = m_new->m_pkthdr.len = LGE_MCLBYTES;
803 m_new->m_data = m_new->m_ext.ext_buf;
807 * Adjust alignment so packet payload begins on a
808 * longword boundary. Mandatory for Alpha, useful on
811 m_adj(m_new, ETHER_ALIGN);
814 c->lge_fragptr_hi = 0;
815 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
816 c->lge_fraglen = m_new->m_len;
817 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
821 * Put this buffer in the RX command FIFO. To do this,
822 * we just write the physical address of the descriptor
823 * into the RX descriptor address registers. Note that
824 * there are two registers, one high DWORD and one low
825 * DWORD, which lets us specify a 64-bit address if
826 * desired. We only use a 32-bit address for now.
827 * Writing to the low DWORD register is what actually
828 * causes the command to be issued, so we do that
831 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
832 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
837 static int lge_alloc_jumbo_mem(sc)
838 struct lge_softc *sc;
842 struct lge_jpool_entry *entry;
844 /* Grab a big chunk o' storage. */
845 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
846 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
848 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
849 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit);
853 SLIST_INIT(&sc->lge_jfree_listhead);
854 SLIST_INIT(&sc->lge_jinuse_listhead);
857 * Now divide it up into 9K pieces and save the addresses
860 ptr = sc->lge_cdata.lge_jumbo_buf;
861 for (i = 0; i < LGE_JSLOTS; i++) {
863 aptr = (u_int64_t **)ptr;
864 aptr[0] = (u_int64_t *)sc;
865 ptr += sizeof(u_int64_t);
866 sc->lge_cdata.lge_jslots[i].lge_buf = ptr;
867 sc->lge_cdata.lge_jslots[i].lge_inuse = 0;
869 entry = malloc(sizeof(struct lge_jpool_entry),
872 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
873 entry, jpool_entries);
879 static void lge_free_jumbo_mem(sc)
880 struct lge_softc *sc;
883 struct lge_jpool_entry *entry;
885 for (i = 0; i < LGE_JSLOTS; i++) {
886 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
887 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
888 free(entry, M_DEVBUF);
891 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
897 * Allocate a jumbo buffer.
899 static void *lge_jalloc(sc)
900 struct lge_softc *sc;
902 struct lge_jpool_entry *entry;
904 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
908 printf("lge%d: no free jumbo buffers\n", sc->lge_unit);
913 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
914 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
915 sc->lge_cdata.lge_jslots[entry->slot].lge_inuse = 1;
916 return(sc->lge_cdata.lge_jslots[entry->slot].lge_buf);
920 * Adjust usage count on a jumbo buffer. In general this doesn't
921 * get used much because our jumbo buffers don't get passed around
922 * a lot, but it's implemented for correctness.
924 static void lge_jref(buf, size)
928 struct lge_softc *sc;
932 /* Extract the softc struct pointer. */
933 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
934 sc = (struct lge_softc *)(aptr[0]);
937 panic("lge_jref: can't find softc pointer!");
939 if (size != LGE_MCLBYTES)
940 panic("lge_jref: adjusting refcount of buf of wrong size!");
942 /* calculate the slot this buffer belongs to */
944 i = ((vm_offset_t)aptr
945 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
947 if ((i < 0) || (i >= LGE_JSLOTS))
948 panic("lge_jref: asked to reference buffer "
949 "that we don't manage!");
950 else if (sc->lge_cdata.lge_jslots[i].lge_inuse == 0)
951 panic("lge_jref: buffer already free!");
953 sc->lge_cdata.lge_jslots[i].lge_inuse++;
959 * Release a jumbo buffer.
961 static void lge_jfree(buf, size)
965 struct lge_softc *sc;
968 struct lge_jpool_entry *entry;
970 /* Extract the softc struct pointer. */
971 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
972 sc = (struct lge_softc *)(aptr[0]);
975 panic("lge_jfree: can't find softc pointer!");
977 if (size != LGE_MCLBYTES)
978 panic("lge_jfree: freeing buffer of wrong size!");
980 /* calculate the slot this buffer belongs to */
981 i = ((vm_offset_t)aptr
982 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
984 if ((i < 0) || (i >= LGE_JSLOTS))
985 panic("lge_jfree: asked to free buffer that we don't manage!");
986 else if (sc->lge_cdata.lge_jslots[i].lge_inuse == 0)
987 panic("lge_jfree: buffer already free!");
989 sc->lge_cdata.lge_jslots[i].lge_inuse--;
990 if(sc->lge_cdata.lge_jslots[i].lge_inuse == 0) {
991 entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
993 panic("lge_jfree: buffer not in use!");
995 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead,
997 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
998 entry, jpool_entries);
1006 * A frame has been uploaded: pass the resulting mbuf chain up to
1007 * the higher level protocols.
1009 static void lge_rxeof(sc, cnt)
1010 struct lge_softc *sc;
1015 struct lge_rx_desc *cur_rx;
1016 int c, i, total_len = 0;
1017 u_int32_t rxsts, rxctl;
1019 ifp = &sc->arpcom.ac_if;
1021 /* Find out how many frames were processed. */
1023 i = sc->lge_cdata.lge_rx_cons;
1027 struct mbuf *m0 = NULL;
1029 cur_rx = &sc->lge_ldata->lge_rx_list[i];
1030 rxctl = cur_rx->lge_ctl;
1031 rxsts = cur_rx->lge_sts;
1032 m = cur_rx->lge_mbuf;
1033 cur_rx->lge_mbuf = NULL;
1034 total_len = LGE_RXBYTES(cur_rx);
1035 LGE_INC(i, LGE_RX_LIST_CNT);
1039 * If an error occurs, update stats, clear the
1040 * status word and leave the mbuf cluster in place:
1041 * it should simply get re-used next time this descriptor
1042 * comes up in the ring.
1044 if (rxctl & LGE_RXCTL_ERRMASK) {
1046 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
1050 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
1051 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1052 total_len + ETHER_ALIGN, 0, ifp, NULL);
1053 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
1055 printf("lge%d: no receive buffers "
1056 "available -- packet dropped!\n",
1061 m_adj(m0, ETHER_ALIGN);
1064 m->m_pkthdr.rcvif = ifp;
1065 m->m_pkthdr.len = m->m_len = total_len;
1070 /* Do IP checksum checking. */
1071 if (rxsts & LGE_RXSTS_ISIP)
1072 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1073 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
1074 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1075 if ((rxsts & LGE_RXSTS_ISTCP &&
1076 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
1077 (rxsts & LGE_RXSTS_ISUDP &&
1078 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
1079 m->m_pkthdr.csum_flags |=
1080 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1081 m->m_pkthdr.csum_data = 0xffff;
1084 (*ifp->if_input)(ifp, m);
1087 sc->lge_cdata.lge_rx_cons = i;
1093 struct lge_softc *sc;
1097 ifp = &sc->arpcom.ac_if;
1098 ifp->if_flags &= ~IFF_RUNNING;
1104 * A frame was downloaded to the chip. It's safe for us to clean up
1108 static void lge_txeof(sc)
1109 struct lge_softc *sc;
1111 struct lge_tx_desc *cur_tx = NULL;
1113 u_int32_t idx, txdone;
1115 ifp = &sc->arpcom.ac_if;
1117 /* Clear the timeout timer. */
1121 * Go through our tx list and free mbufs for those
1122 * frames that have been transmitted.
1124 idx = sc->lge_cdata.lge_tx_cons;
1125 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1127 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
1128 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
1131 if (cur_tx->lge_mbuf != NULL) {
1132 m_freem(cur_tx->lge_mbuf);
1133 cur_tx->lge_mbuf = NULL;
1135 cur_tx->lge_ctl = 0;
1138 LGE_INC(idx, LGE_TX_LIST_CNT);
1142 sc->lge_cdata.lge_tx_cons = idx;
1145 ifp->if_flags &= ~IFF_OACTIVE;
1150 static void lge_tick(xsc)
1153 struct lge_softc *sc;
1154 struct mii_data *mii;
1161 ifp = &sc->arpcom.ac_if;
1163 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1164 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1165 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1166 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1168 if (!sc->lge_link) {
1169 mii = device_get_softc(sc->lge_miibus);
1172 if (mii->mii_media_status & IFM_ACTIVE &&
1173 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1175 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1176 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX)
1177 printf("lge%d: gigabit link up\n",
1179 if (ifp->if_snd.ifq_head != NULL)
1184 sc->lge_stat_ch = timeout(lge_tick, sc, hz);
1191 static void lge_intr(arg)
1194 struct lge_softc *sc;
1199 ifp = &sc->arpcom.ac_if;
1201 /* Supress unwanted interrupts */
1202 if (!(ifp->if_flags & IFF_UP)) {
1209 * Reading the ISR register clears all interrupts, and
1210 * clears the 'interrupts enabled' bit in the IMR
1213 status = CSR_READ_4(sc, LGE_ISR);
1215 if ((status & LGE_INTRS) == 0)
1218 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1221 if (status & LGE_ISR_RXDMA_DONE)
1222 lge_rxeof(sc, LGE_RX_DMACNT(status));
1224 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1227 if (status & LGE_ISR_PHY_INTR) {
1229 untimeout(lge_tick, sc, sc->lge_stat_ch);
1234 /* Re-enable interrupts. */
1235 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1237 if (ifp->if_snd.ifq_head != NULL)
1244 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1245 * pointers to the fragment pointers.
1247 static int lge_encap(sc, m_head, txidx)
1248 struct lge_softc *sc;
1249 struct mbuf *m_head;
1252 struct lge_frag *f = NULL;
1253 struct lge_tx_desc *cur_tx;
1255 int frag = 0, tot_len = 0;
1258 * Start packing the mbufs in this chain into
1259 * the fragment pointers. Stop when we run out
1260 * of fragments or hit the end of the mbuf chain.
1263 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1266 for (m = m_head; m != NULL; m = m->m_next) {
1267 if (m->m_len != 0) {
1268 tot_len += m->m_len;
1269 f = &cur_tx->lge_frags[frag];
1270 f->lge_fraglen = m->m_len;
1271 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1272 f->lge_fragptr_hi = 0;
1280 cur_tx->lge_mbuf = m_head;
1281 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1282 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1284 /* Queue for transmit */
1285 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1291 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1292 * to the mbuf data regions directly in the transmit lists. We also save a
1293 * copy of the pointers since the transmit list fragment pointers are
1294 * physical addresses.
1297 static void lge_start(ifp)
1300 struct lge_softc *sc;
1301 struct mbuf *m_head = NULL;
1309 idx = sc->lge_cdata.lge_tx_prod;
1311 if (ifp->if_flags & IFF_OACTIVE)
1314 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1315 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1318 IF_DEQUEUE(&ifp->if_snd, m_head);
1322 if (lge_encap(sc, m_head, &idx)) {
1323 IF_PREPEND(&ifp->if_snd, m_head);
1324 ifp->if_flags |= IFF_OACTIVE;
1329 * If there's a BPF listener, bounce a copy of this frame
1333 bpf_mtap(ifp, m_head);
1336 sc->lge_cdata.lge_tx_prod = idx;
1339 * Set a timeout in case the chip goes out to lunch.
1346 static void lge_init(xsc)
1349 struct lge_softc *sc = xsc;
1350 struct ifnet *ifp = &sc->arpcom.ac_if;
1351 struct mii_data *mii;
1354 if (ifp->if_flags & IFF_RUNNING)
1360 * Cancel pending I/O and free all RX/TX buffers.
1365 mii = device_get_softc(sc->lge_miibus);
1367 /* Set MAC address */
1368 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1369 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1371 /* Init circular RX list. */
1372 if (lge_list_rx_init(sc) == ENOBUFS) {
1373 printf("lge%d: initialization failed: no "
1374 "memory for rx buffers\n", sc->lge_unit);
1381 * Init tx descriptors.
1383 lge_list_tx_init(sc);
1385 /* Set initial value for MODE1 register. */
1386 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1387 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD|
1388 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0|
1389 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2);
1391 /* If we want promiscuous mode, set the allframes bit. */
1392 if (ifp->if_flags & IFF_PROMISC) {
1393 CSR_WRITE_4(sc, LGE_MODE1,
1394 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC);
1396 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1400 * Set the capture broadcast bit to capture broadcast frames.
1402 if (ifp->if_flags & IFF_BROADCAST) {
1403 CSR_WRITE_4(sc, LGE_MODE1,
1404 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST);
1406 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1409 /* Packet padding workaround? */
1410 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1412 /* No error frames */
1413 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1415 /* Receive large frames */
1416 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1418 /* Workaround: disable RX/TX flow control */
1419 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1420 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1422 /* Make sure to strip CRC from received frames */
1423 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1425 /* Turn off magic packet mode */
1426 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1428 /* Turn off all VLAN stuff */
1429 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1430 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
1432 /* Workarond: FIFO overflow */
1433 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1434 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1437 * Load the multicast filter.
1442 * Enable hardware checksum validation for all received IPv4
1443 * packets, do not reject packets with bad checksums.
1445 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM|
1446 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM|
1447 LGE_MODE2_RX_ERRCSUM);
1450 * Enable the delivery of PHY interrupts based on
1451 * link/speed/duplex status chalges.
1453 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1455 /* Enable receiver and transmitter. */
1456 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1457 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1459 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1460 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1463 * Enable interrupts.
1465 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|
1466 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS);
1468 lge_ifmedia_upd(ifp);
1470 ifp->if_flags |= IFF_RUNNING;
1471 ifp->if_flags &= ~IFF_OACTIVE;
1475 sc->lge_stat_ch = timeout(lge_tick, sc, hz);
1481 * Set media options.
1483 static int lge_ifmedia_upd(ifp)
1486 struct lge_softc *sc;
1487 struct mii_data *mii;
1491 mii = device_get_softc(sc->lge_miibus);
1493 if (mii->mii_instance) {
1494 struct mii_softc *miisc;
1495 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1496 miisc = LIST_NEXT(miisc, mii_list))
1497 mii_phy_reset(miisc);
1505 * Report current media status.
1507 static void lge_ifmedia_sts(ifp, ifmr)
1509 struct ifmediareq *ifmr;
1511 struct lge_softc *sc;
1512 struct mii_data *mii;
1516 mii = device_get_softc(sc->lge_miibus);
1518 ifmr->ifm_active = mii->mii_media_active;
1519 ifmr->ifm_status = mii->mii_media_status;
1524 static int lge_ioctl(ifp, command, data, cr)
1530 struct lge_softc *sc = ifp->if_softc;
1531 struct ifreq *ifr = (struct ifreq *) data;
1532 struct mii_data *mii;
1540 error = ether_ioctl(ifp, command, data);
1543 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1546 ifp->if_mtu = ifr->ifr_mtu;
1549 if (ifp->if_flags & IFF_UP) {
1550 if (ifp->if_flags & IFF_RUNNING &&
1551 ifp->if_flags & IFF_PROMISC &&
1552 !(sc->lge_if_flags & IFF_PROMISC)) {
1553 CSR_WRITE_4(sc, LGE_MODE1,
1554 LGE_MODE1_SETRST_CTL1|
1555 LGE_MODE1_RX_PROMISC);
1556 } else if (ifp->if_flags & IFF_RUNNING &&
1557 !(ifp->if_flags & IFF_PROMISC) &&
1558 sc->lge_if_flags & IFF_PROMISC) {
1559 CSR_WRITE_4(sc, LGE_MODE1,
1560 LGE_MODE1_RX_PROMISC);
1562 ifp->if_flags &= ~IFF_RUNNING;
1566 if (ifp->if_flags & IFF_RUNNING)
1569 sc->lge_if_flags = ifp->if_flags;
1579 mii = device_get_softc(sc->lge_miibus);
1580 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1592 static void lge_watchdog(ifp)
1595 struct lge_softc *sc;
1600 printf("lge%d: watchdog timeout\n", sc->lge_unit);
1604 ifp->if_flags &= ~IFF_RUNNING;
1607 if (ifp->if_snd.ifq_head != NULL)
1614 * Stop the adapter and free any mbufs allocated to the
1617 static void lge_stop(sc)
1618 struct lge_softc *sc;
1623 ifp = &sc->arpcom.ac_if;
1625 untimeout(lge_tick, sc, sc->lge_stat_ch);
1626 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1628 /* Disable receiver and transmitter. */
1629 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1633 * Free data in the RX lists.
1635 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1636 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1637 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1638 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1641 bzero((char *)&sc->lge_ldata->lge_rx_list,
1642 sizeof(sc->lge_ldata->lge_rx_list));
1645 * Free the TX list buffers.
1647 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1648 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1649 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1650 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1654 bzero((char *)&sc->lge_ldata->lge_tx_list,
1655 sizeof(sc->lge_ldata->lge_tx_list));
1657 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1663 * Stop all chip I/O so that the kernel's probe routines don't
1664 * get confused by errant DMAs when rebooting.
1666 static void lge_shutdown(dev)
1669 struct lge_softc *sc;
1671 sc = device_get_softc(dev);