2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/pci/pcivar.h,v 1.48 2000/09/28 00:37:32 peter Exp $
27 * $DragonFly: src/sys/bus/pci/pcivar.h,v 1.7 2004/02/16 18:51:01 joerg Exp $
34 #include <sys/queue.h>
36 /* some PCI bus constants */
38 #define PCI_BUSMAX 255 /* highest supported bus number */
39 #define PCI_SLOTMAX 31 /* highest supported slot number */
40 #define PCI_FUNCMAX 7 /* highest supported function number */
41 #define PCI_REGMAX 255 /* highest supported config register addr. */
43 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
44 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
45 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
47 /* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */
50 typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */
52 typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */
55 /* config header information common to all header types */
57 typedef struct pcicfg {
58 struct device *dev; /* device which owns this */
59 void *hdrspec; /* pointer to header type specific data */
61 u_int16_t subvendor; /* card vendor ID */
62 u_int16_t subdevice; /* card device ID, assigned by card vendor */
63 u_int16_t vendor; /* chip vendor ID */
64 u_int16_t device; /* chip device ID, assigned by chip vendor */
66 u_int16_t cmdreg; /* disable/enable chip and PCI options */
67 u_int16_t statreg; /* supported PCI features and error state */
69 u_int8_t baseclass; /* chip PCI class */
70 u_int8_t subclass; /* chip PCI subclass */
71 u_int8_t progif; /* chip PCI programming interface */
72 u_int8_t revid; /* chip revision ID */
74 u_int8_t hdrtype; /* chip config header type */
75 u_int8_t cachelnsz; /* cache line size in 4byte units */
76 u_int8_t intpin; /* PCI interrupt pin */
77 u_int8_t intline; /* interrupt line (IRQ for PC arch) */
79 u_int8_t mingnt; /* min. useful bus grant time in 250ns units */
80 u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */
81 u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */
83 u_int8_t mfdev; /* multi-function device (from hdrtype reg) */
84 u_int8_t nummaps; /* actual number of PCI maps used */
86 u_int8_t bus; /* config space bus address */
87 u_int8_t slot; /* config space slot address */
88 u_int8_t func; /* config space function number */
90 u_int8_t secondarybus; /* bus on secondary side of bridge, if any */
91 u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */
93 u_int16_t pp_cap; /* PCI power management capabilities */
94 u_int8_t pp_status; /* config space address of PCI power status reg */
95 u_int8_t pp_pmcsr; /* config space address of PMCSR reg */
96 u_int8_t pp_data; /* config space address of PCI power data reg */
99 /* additional type 1 device config header information (PCI to PCI bridge) */
102 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
103 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
105 #define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff)
106 #define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff)
109 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff)
110 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff)
113 pci_addr_t pmembase; /* base address of prefetchable memory */
114 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
115 u_int32_t membase; /* base address of memory window */
116 u_int32_t memlimit; /* topmost address of memory window */
117 u_int32_t iobase; /* base address of port window */
118 u_int32_t iolimit; /* topmost address of port window */
119 u_int16_t secstat; /* secondary bus status register */
120 u_int16_t bridgectl; /* bridge control register */
121 u_int8_t seclat; /* CardBus latency timer */
124 /* additional type 2 device config header information (CardBus bridge) */
127 u_int32_t membase0; /* base address of memory window */
128 u_int32_t memlimit0; /* topmost address of memory window */
129 u_int32_t membase1; /* base address of memory window */
130 u_int32_t memlimit1; /* topmost address of memory window */
131 u_int32_t iobase0; /* base address of port window */
132 u_int32_t iolimit0; /* topmost address of port window */
133 u_int32_t iobase1; /* base address of port window */
134 u_int32_t iolimit1; /* topmost address of port window */
135 u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
136 u_int16_t secstat; /* secondary bus status register */
137 u_int16_t bridgectl; /* bridge control register */
138 u_int8_t seclat; /* CardBus latency timer */
141 extern u_int32_t pci_numdevs;
143 /* Only if the prerequisites are present */
144 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
146 STAILQ_ENTRY(pci_devinfo) pci_links;
147 struct resource_list resources;
149 struct pci_conf conf;
153 /* externally visible functions */
155 const char *pci_ata_match(struct device *dev);
156 const char *pci_usb_match(struct device *dev);
157 const char *pci_vga_match(struct device *dev);
158 const char *pci_chip_match(struct device *dev);
160 /* low level PCI config register functions provided by pcibus.c */
162 int pci_cfgread (pcicfgregs *cfg, int reg, int bytes);
163 void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes);
165 vm_offset_t pci_cvt_to_dense (vm_offset_t);
166 vm_offset_t pci_cvt_to_bwx (vm_offset_t);
167 #endif /* __alpha__ */
169 /* low level devlist operations for the 2.2 compatibility code in pci.c */
170 pcicfgregs * pci_devlist_get_parent(pcicfgregs *cfg);
177 * Define pci-specific resource flags for accessing memory via dense
178 * or bwx memory spaces. These flags are ignored on i386.
180 #define PCI_RF_DENSE 0x10000
181 #define PCI_RF_BWX 0x20000
183 enum pci_device_ivars {
198 PCI_IVAR_SECONDARYBUS,
199 PCI_IVAR_SUBORDINATEBUS,
204 * Simplified accessors for pci devices
206 #define PCI_ACCESSOR(A, B, T) \
208 static __inline T pci_get_ ## A(device_t dev) \
211 BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \
215 static __inline void pci_set_ ## A(device_t dev, T t) \
217 uintptr_t v = (uintptr_t) t; \
218 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \
221 PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t)
222 PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t)
223 PCI_ACCESSOR(vendor, VENDOR, u_int16_t)
224 PCI_ACCESSOR(device, DEVICE, u_int16_t)
225 PCI_ACCESSOR(devid, DEVID, u_int32_t)
226 PCI_ACCESSOR(class, CLASS, u_int8_t)
227 PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t)
228 PCI_ACCESSOR(progif, PROGIF, u_int8_t)
229 PCI_ACCESSOR(revid, REVID, u_int8_t)
230 PCI_ACCESSOR(intpin, INTPIN, u_int8_t)
231 PCI_ACCESSOR(irq, IRQ, u_int8_t)
232 PCI_ACCESSOR(bus, BUS, u_int8_t)
233 PCI_ACCESSOR(slot, SLOT, u_int8_t)
234 PCI_ACCESSOR(function, FUNCTION, u_int8_t)
235 PCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t)
236 PCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t)
237 PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
241 static __inline u_int32_t
242 pci_read_config(device_t dev, int reg, int width)
244 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
248 pci_write_config(device_t dev, int reg, u_int32_t val, int width)
250 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
254 * Convenience functions.
256 * These should be used in preference to manually manipulating
257 * configuration space.
260 pci_enable_busmaster(device_t dev)
262 PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev);
266 pci_disable_busmaster(device_t dev)
268 PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev);
272 pci_enable_io(device_t dev, int space)
274 PCI_ENABLE_IO(device_get_parent(dev), dev, space);
278 pci_disable_io(device_t dev, int space)
280 PCI_DISABLE_IO(device_get_parent(dev), dev, space);
284 * PCI power states are as defined by ACPI:
286 * D0 State in which device is on and running. It is receiving full
287 * power from the system and delivering full functionality to the user.
288 * D1 Class-specific low-power state in which device context may or may not
289 * be lost. Buses in D1 cannot do anything to the bus that would force
290 * devices on that bus to loose context.
291 * D2 Class-specific low-power state in which device context may or may
292 * not be lost. Attains greater power savings than D1. Buses in D2
293 * can cause devices on that bus to loose some context. Devices in D2
294 * must be prepared for the bus to be in D2 or higher.
295 * D3 State in which the device is off and not running. Device context is
296 * lost. Power can be removed from the device.
298 #define PCI_POWERSTATE_D0 0
299 #define PCI_POWERSTATE_D1 1
300 #define PCI_POWERSTATE_D2 2
301 #define PCI_POWERSTATE_D3 3
302 #define PCI_POWERSTATE_UNKNOWN -1
305 pci_set_powerstate(device_t dev, int state)
307 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
311 pci_get_powerstate(device_t dev)
313 return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
317 * Ivars for pci bridges.
320 /*typedef enum pci_device_ivars pcib_device_ivars;*/
321 enum pcib_device_ivars {
325 #define PCIB_ACCESSOR(A, B, T) \
327 static __inline T pcib_get_ ## A(device_t dev) \
330 BUS_READ_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, &v); \
334 static __inline void pcib_set_ ## A(device_t dev, T t) \
336 uintptr_t v = (uintptr_t) t; \
337 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, v); \
340 PCIB_ACCESSOR(bus, BUS, u_int32_t)
344 device_t pci_find_bsf(u_int8_t, u_int8_t, u_int8_t);
345 device_t pci_find_device(u_int16_t, u_int16_t);
348 /* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */
350 #if defined(_KERNEL) && !defined(KLD_MODULE)
351 #include "opt_compat_oldpci.h"
355 /* all this is going some day */
357 typedef pcicfgregs *pcici_t;
358 typedef unsigned pcidi_t;
359 typedef void pci_inthand_t(void *arg);
361 #define pci_max_burst_len (3)
363 /* just copied from old PCI code for now ... */
367 const char* (*pd_probe ) (pcici_t tag, pcidi_t type);
368 void (*pd_attach) (pcici_t tag, int unit);
370 int (*pd_shutdown) (int, int);
374 typedef u_short pci_port_t;
376 typedef u_int pci_port_t;
379 u_long pci_conf_read (pcici_t tag, u_long reg);
380 void pci_conf_write (pcici_t tag, u_long reg, u_long data);
381 int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa);
382 int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa);
383 int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg,
384 intrmask_t *maskptr);
385 int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg,
386 intrmask_t *maskptr, u_int flags);
387 int pci_unmap_int (pcici_t tag);
389 pcici_t pci_get_parent_from_tag(pcici_t tag);
390 int pci_get_bus_from_tag(pcici_t tag);
393 int compat_pci_handler (struct module *, int, void *);
394 #define COMPAT_PCI_DRIVER(name, pcidata) \
395 static moduledata_t name##_mod = { \
397 compat_pci_handler, \
400 DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY)
403 #endif /* COMPAT_OLDPCI */
404 #endif /* _PCIVAR_H_ */