2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 1997 KATO Takenori.
5 * Copyright (c) 2001 Tamotsu Hattori.
6 * Copyright (c) 2001 Mitsuru IWASAKI.
9 * This code is derived from software contributed to Berkeley by
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.80.2.15 2003/04/11 17:06:41 jhb Exp $
42 * $DragonFly: src/sys/platform/pc32/i386/identcpu.c,v 1.13 2006/11/07 06:43:24 dillon Exp $
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/sysctl.h>
53 #include <machine/asmacros.h>
54 #include <machine/clock.h>
55 #include <machine/cputypes.h>
56 #include <machine/segments.h>
57 #include <machine/specialreg.h>
58 #include <machine/md_var.h>
60 #include <machine_base/isa/intr_machdep.h>
62 #define IDENTBLUE_CYRIX486 0
63 #define IDENTBLUE_IBMCPU 1
64 #define IDENTBLUE_CYRIXM2 2
66 /* XXX - should be in header file: */
67 void printcpuinfo(void);
68 void finishidentcpu(void);
69 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
70 void enable_K5_wt_alloc(void);
71 void enable_K6_wt_alloc(void);
72 void enable_K6_2_wt_alloc(void);
74 void panicifcpuunsupported(void);
76 static void identifycyrix(void);
77 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
78 static void print_AMD_features(void);
80 static void print_AMD_info(void);
81 static void print_AMD_assoc(int i);
82 static void print_transmeta_info(void);
83 static void setup_tmx86_longrun(void);
85 int cpu_class = CPUCLASS_386;
86 u_int cpu_exthigh; /* Highest arg to extended CPUID */
87 u_int cyrix_did; /* Device ID of Cyrix CPU */
88 char machine[] = MACHINE;
89 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
90 machine, 0, "Machine class");
92 static char cpu_model[128];
93 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
94 cpu_model, 0, "Machine model");
96 static char cpu_brand[48];
98 #define MAX_ADDITIONAL_INFO 16
100 static const char *additional_cpu_info_ary[MAX_ADDITIONAL_INFO];
101 static u_int additional_cpu_info_count;
103 #define MAX_BRAND_INDEX 8
105 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
109 "Intel Pentium III Xeon",
117 static struct cpu_nameclass i386_cpus[] = {
118 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
119 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
120 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
121 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
122 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
123 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
124 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
125 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
126 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
127 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
128 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
129 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
130 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
131 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
132 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
133 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
134 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
137 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
138 int has_f00f_bug = 0; /* Initialized so that it can be patched. */
144 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
149 cpu_class = i386_cpus[cpu].cpu_class;
151 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
153 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
154 /* Check for extended CPUID information and a processor name. */
156 (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
157 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
158 strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
159 strcmp(cpu_vendor, "TransmetaCPU") == 0)) {
160 do_cpuid(0x80000000, regs);
161 if (regs[0] >= 0x80000000) {
162 cpu_exthigh = regs[0];
163 if (cpu_exthigh >= 0x80000004) {
165 for (i = 0x80000002; i < 0x80000005; i++) {
167 memcpy(brand, regs, sizeof(regs));
168 brand += sizeof(regs);
174 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
175 if ((cpu_id & 0xf00) > 0x300) {
180 switch (cpu_id & 0x3000) {
182 strcpy(cpu_model, "Overdrive ");
185 strcpy(cpu_model, "Dual ");
189 switch (cpu_id & 0xf00) {
191 strcat(cpu_model, "i486 ");
192 /* Check the particular flavor of 486 */
193 switch (cpu_id & 0xf0) {
196 strcat(cpu_model, "DX");
199 strcat(cpu_model, "SX");
202 strcat(cpu_model, "DX2");
205 strcat(cpu_model, "SL");
208 strcat(cpu_model, "SX2");
212 "DX2 Write-Back Enhanced");
215 strcat(cpu_model, "DX4");
220 /* Check the particular flavor of 586 */
221 strcat(cpu_model, "Pentium");
222 switch (cpu_id & 0xf0) {
224 strcat(cpu_model, " A-step");
227 strcat(cpu_model, "/P5");
230 strcat(cpu_model, "/P54C");
233 strcat(cpu_model, "/P54T Overdrive");
236 strcat(cpu_model, "/P55C");
239 strcat(cpu_model, "/P54C");
242 strcat(cpu_model, "/P55C (quarter-micron)");
248 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
250 * XXX - If/when Intel fixes the bug, this
251 * should also check the version of the
252 * CPU, not just that it's a Pentium.
258 /* Check the particular flavor of 686 */
259 switch (cpu_id & 0xf0) {
261 strcat(cpu_model, "Pentium Pro A-step");
264 strcat(cpu_model, "Pentium Pro");
270 "Pentium II/Pentium II Xeon/Celeron");
278 "Pentium III/Pentium III Xeon/Celeron");
282 strcat(cpu_model, "Unknown 80686");
287 strcat(cpu_model, "Pentium 4");
291 strcat(cpu_model, "unknown");
296 * If we didn't get a brand name from the extended
297 * CPUID, try to look it up in the brand table.
299 if (cpu_high > 0 && *cpu_brand == '\0') {
300 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
301 if (brand_index <= MAX_BRAND_INDEX &&
302 cpu_brandtable[brand_index] != NULL)
304 cpu_brandtable[brand_index]);
307 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
309 * Values taken from AMD Processor Recognition
310 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
311 * (also describes ``Features'' encodings.
313 strcpy(cpu_model, "AMD ");
314 switch (cpu_id & 0xFF0) {
316 strcat(cpu_model, "Standard Am486DX");
319 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
322 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
325 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
328 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
331 strcat(cpu_model, "Am5x86 Write-Through");
334 strcat(cpu_model, "Am5x86 Write-Back");
337 strcat(cpu_model, "K5 model 0");
341 strcat(cpu_model, "K5 model 1");
344 strcat(cpu_model, "K5 PR166 (model 2)");
347 strcat(cpu_model, "K5 PR200 (model 3)");
350 strcat(cpu_model, "K6");
353 strcat(cpu_model, "K6 266 (model 1)");
356 strcat(cpu_model, "K6-2");
359 strcat(cpu_model, "K6-III");
362 strcat(cpu_model, "Unknown");
365 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
366 if ((cpu_id & 0xf00) == 0x500) {
367 if (((cpu_id & 0x0f0) > 0)
368 && ((cpu_id & 0x0f0) < 0x60)
369 && ((cpu_id & 0x00f) > 3))
370 enable_K5_wt_alloc();
371 else if (((cpu_id & 0x0f0) > 0x80)
372 || (((cpu_id & 0x0f0) == 0x80)
373 && (cpu_id & 0x00f) > 0x07))
374 enable_K6_2_wt_alloc();
375 else if ((cpu_id & 0x0f0) > 0x50)
376 enable_K6_wt_alloc();
379 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
380 strcpy(cpu_model, "Cyrix ");
381 switch (cpu_id & 0xff0) {
383 strcat(cpu_model, "MediaGX");
386 strcat(cpu_model, "6x86");
389 cpu_class = CPUCLASS_586;
390 strcat(cpu_model, "GXm");
393 strcat(cpu_model, "6x86MX");
397 * Even though CPU supports the cpuid
398 * instruction, it can be disabled.
399 * Therefore, this routine supports all Cyrix
402 switch (cyrix_did & 0xf0) {
404 switch (cyrix_did & 0x0f) {
406 strcat(cpu_model, "486SLC");
409 strcat(cpu_model, "486DLC");
412 strcat(cpu_model, "486SLC2");
415 strcat(cpu_model, "486DLC2");
418 strcat(cpu_model, "486SRx");
421 strcat(cpu_model, "486DRx");
424 strcat(cpu_model, "486SRx2");
427 strcat(cpu_model, "486DRx2");
430 strcat(cpu_model, "486SRu");
433 strcat(cpu_model, "486DRu");
436 strcat(cpu_model, "486SRu2");
439 strcat(cpu_model, "486DRu2");
442 strcat(cpu_model, "Unknown");
447 switch (cyrix_did & 0x0f) {
449 strcat(cpu_model, "486S");
452 strcat(cpu_model, "486S2");
455 strcat(cpu_model, "486Se");
458 strcat(cpu_model, "486S2e");
461 strcat(cpu_model, "486DX");
464 strcat(cpu_model, "486DX2");
467 strcat(cpu_model, "486DX4");
470 strcat(cpu_model, "Unknown");
475 if ((cyrix_did & 0x0f) < 8)
476 strcat(cpu_model, "6x86"); /* Where did you get it? */
478 strcat(cpu_model, "5x86");
481 strcat(cpu_model, "6x86");
484 if ((cyrix_did & 0xf000) == 0x3000) {
485 cpu_class = CPUCLASS_586;
486 strcat(cpu_model, "GXm");
488 strcat(cpu_model, "MediaGX");
491 strcat(cpu_model, "6x86MX");
494 switch (cyrix_did & 0x0f) {
496 strcat(cpu_model, "Overdrive CPU");
498 strcpy(cpu_model, "Texas Instruments 486SXL");
501 strcat(cpu_model, "486SLC/DLC");
504 strcat(cpu_model, "Unknown");
509 strcat(cpu_model, "Unknown");
514 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
515 strcpy(cpu_model, "Rise ");
516 switch (cpu_id & 0xff0) {
518 strcat(cpu_model, "mP6");
521 strcat(cpu_model, "Unknown");
523 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
524 switch (cpu_id & 0xff0) {
526 strcpy(cpu_model, "IDT WinChip C6");
530 strcpy(cpu_model, "IDT WinChip 2");
533 strcpy(cpu_model, "VIA C3 Samuel");
537 strcpy(cpu_model, "VIA C3 Ezra");
539 strcpy(cpu_model, "VIA C3 Samuel 2");
542 strcpy(cpu_model, "VIA C3 Ezra-T");
545 strcpy(cpu_model, "VIA C3 Nehemiah");
546 do_cpuid(0xc0000000, regs);
547 if (regs[0] == 0xc0000001) {
548 do_cpuid(0xc0000001, regs);
549 if ((cpu_id & 0xf) >= 3)
550 if ((regs[3] & 0x0c) == 0x0c)
551 strcat(cpu_model, "+RNG");
552 if ((cpu_id & 0xf) >= 8)
553 if ((regs[3] & 0xc0) == 0xc0)
554 strcat(cpu_model, "+ACE");
558 strcpy(cpu_model, "VIA/IDT Unknown");
560 } else if (strcmp(cpu_vendor, "IBM") == 0) {
561 strcpy(cpu_model, "Blue Lightning CPU");
565 * Replace cpu_model with cpu_brand minus leading spaces if
569 while (*brand == ' ')
572 strcpy(cpu_model, brand);
576 printf("%s (", cpu_model);
581 #if defined(I386_CPU)
586 #if defined(I486_CPU)
589 /* bzero = i486_bzero; */
592 #if defined(I586_CPU)
594 printf("%d.%02d-MHz ",
595 (tsc_freq + 4999) / 1000000,
596 ((tsc_freq + 4999) / 10000) % 100);
600 #if defined(I686_CPU)
602 printf("%d.%02d-MHz ",
603 (tsc_freq + 4999) / 1000000,
604 ((tsc_freq + 4999) / 10000) % 100);
609 printf("Unknown"); /* will panic below... */
611 printf("-class CPU)\n");
612 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
614 printf(" Origin = \"%s\"",cpu_vendor);
616 printf(" Id = 0x%x", cpu_id);
618 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
619 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
620 strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
621 strcmp(cpu_vendor, "CentaurHauls") == 0 ||
622 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
623 ((cpu_id & 0xf00) > 0x500))) {
624 printf(" Stepping = %u", cpu_id & 0xf);
625 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
626 printf(" DIR=0x%04x", cyrix_did);
629 * Here we should probably set up flags indicating
630 * whether or not various features are available.
631 * The interesting ones are probably VME, PSE, PAE,
632 * and PGE. The code already assumes without bothering
633 * to check that all CPUs >= Pentium have a TSC and
636 printf("\n Features=0x%b", cpu_feature,
638 "\001FPU" /* Integral FPU */
639 "\002VME" /* Extended VM86 mode support */
640 "\003DE" /* Debugging Extensions (CR4.DE) */
641 "\004PSE" /* 4MByte page tables */
642 "\005TSC" /* Timestamp counter */
643 "\006MSR" /* Machine specific registers */
644 "\007PAE" /* Physical address extension */
645 "\010MCE" /* Machine Check support */
646 "\011CX8" /* CMPEXCH8 instruction */
647 "\012APIC" /* SMP local APIC */
648 "\013oldMTRR" /* Previous implementation of MTRR */
649 "\014SEP" /* Fast System Call */
650 "\015MTRR" /* Memory Type Range Registers */
651 "\016PGE" /* PG_G (global bit) support */
652 "\017MCA" /* Machine Check Architecture */
653 "\020CMOV" /* CMOV instruction */
654 "\021PAT" /* Page attributes table */
655 "\022PSE36" /* 36 bit address space support */
656 "\023PN" /* Processor Serial number */
657 "\024CLFLUSH" /* Has the CLFLUSH instruction */
659 "\026DTS" /* Debug Trace Store */
660 "\027ACPI" /* ACPI support */
661 "\030MMX" /* MMX instructions */
662 "\031FXSR" /* FXSAVE/FXRSTOR */
663 "\032SSE" /* Streaming SIMD Extensions */
664 "\033SSE2" /* Streaming SIMD Extensions #2 */
665 "\034SS" /* Self snoop */
666 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
667 "\036TM" /* Thermal Monitor clock slowdown */
668 "\037IA64" /* CPU can execute IA64 instructions */
669 "\040PBE" /* Pending Break Enable */
673 * If this CPU supports hyperthreading then mention
674 * the number of logical CPU's it contains.
676 if (cpu_feature & CPUID_HTT &&
677 (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
678 printf("\n Hyperthreading: %d logical CPUs",
679 (cpu_procinfo & CPUID_HTT_CORES) >> 16);
681 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
682 cpu_exthigh >= 0x80000001)
683 print_AMD_features();
684 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
685 printf(" DIR=0x%04x", cyrix_did);
686 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
687 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
688 #ifndef CYRIX_CACHE_REALLY_WORKS
689 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
690 printf("\n CPU cache: write-through mode");
693 /* Avoid ugly blank lines: only print newline when we have to. */
694 if (*cpu_vendor || cpu_id)
698 if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
699 strcmp(cpu_vendor, "TransmetaCPU") == 0) {
700 setup_tmx86_longrun();
703 for (i = 0; i < additional_cpu_info_count; ++i) {
704 printf(" %s\n", additional_cpu_info_ary[i]);
710 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
712 else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
713 strcmp(cpu_vendor, "TransmetaCPU") == 0)
714 print_transmeta_info();
718 * XXX - Do PPro CPUID level=2 stuff here?
720 * No, but maybe in a print_Intel_info() function called from here.
726 panicifcpuunsupported(void)
729 #if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
730 #error This kernel is not configured for one of the supported CPUs
733 * Now that we have told the user what they have,
734 * let them know if that machine type isn't configured.
737 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
738 #if !defined(I386_CPU)
741 #if !defined(I486_CPU)
744 #if !defined(I586_CPU)
747 #if !defined(I686_CPU)
750 panic("CPU class not configured");
757 static volatile u_int trap_by_rdmsr;
760 * Special exception 6 handler.
761 * The rdmsr instruction generates invalid opcodes fault on 486-class
762 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
763 * function identblue() when this handler is called. Stacked eip should
770 " .p2align 2,0x90 \n"
771 " .type " __XSTRING(CNAME(bluetrap6)) ",@function \n"
772 __XSTRING(CNAME(bluetrap6)) ": \n"
774 " movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n"
775 " addl $2, (%esp) # I know rdmsr is a 2-bytes instruction. \n"
780 * Special exception 13 handler.
781 * Accessing non-existent MSR generates general protection fault.
783 inthand_t bluetrap13;
787 " .p2align 2,0x90 \n"
788 " .type " __XSTRING(CNAME(bluetrap13)) ",@function \n"
789 __XSTRING(CNAME(bluetrap13)) ": \n"
791 " movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n"
792 " popl %eax # discard errorcode. \n"
793 " addl $2, (%esp) # I know rdmsr is a 2-bytes instruction. \n"
798 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
799 * support cpuid instruction. This function should be called after
800 * loading interrupt descriptor table register.
802 * I don't like this method that handles fault, but I couldn't get
803 * information for any other methods. Does blue giant know?
812 * Cyrix 486-class CPU does not support rdmsr instruction.
813 * The rdmsr instruction generates invalid opcode fault, and exception
814 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
815 * bluetrap6() set the magic number to trap_by_rdmsr.
817 setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
820 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
821 * In this case, rdmsr generates general protection fault, and
822 * exception will be trapped by bluetrap13().
824 setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
826 rdmsr(0x1002); /* Cyrix CPU generates fault. */
828 if (trap_by_rdmsr == 0xa8c1d)
829 return IDENTBLUE_CYRIX486;
830 else if (trap_by_rdmsr == 0xa89c4)
831 return IDENTBLUE_CYRIXM2;
832 return IDENTBLUE_IBMCPU;
837 * identifycyrix() set lower 16 bits of cyrix_did as follows:
839 * F E D C B A 9 8 7 6 5 4 3 2 1 0
840 * +-------+-------+---------------+
841 * | SID | RID | Device ID |
842 * | (DIR 1) | (DIR 0) |
843 * +-------+-------+---------------+
848 int ccr2_test = 0, dir_test = 0;
853 ccr2 = read_cyrix_reg(CCR2);
854 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
855 read_cyrix_reg(CCR2);
856 if (read_cyrix_reg(CCR2) != ccr2)
858 write_cyrix_reg(CCR2, ccr2);
860 ccr3 = read_cyrix_reg(CCR3);
861 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
862 read_cyrix_reg(CCR3);
863 if (read_cyrix_reg(CCR3) != ccr3)
864 dir_test = 1; /* CPU supports DIRs. */
865 write_cyrix_reg(CCR3, ccr3);
868 /* Device ID registers are available. */
869 cyrix_did = read_cyrix_reg(DIR1) << 8;
870 cyrix_did += read_cyrix_reg(DIR0);
871 } else if (ccr2_test)
872 cyrix_did = 0x0010; /* 486S A-step */
874 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
880 * Final stage of CPU identification. -- Should I check TI?
889 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
890 if (cpu == CPU_486) {
892 * These conditions are equivalent to:
893 * - CPU does not support cpuid instruction.
894 * - Cyrix/IBM CPU is detected.
896 isblue = identblue();
897 if (isblue == IDENTBLUE_IBMCPU) {
898 strcpy(cpu_vendor, "IBM");
903 switch (cpu_id & 0xf00) {
906 * Cyrix's datasheet does not describe DIRs.
907 * Therefor, I assume it does not have them
908 * and use the result of the cpuid instruction.
909 * XXX they seem to have it for now at least. -Peter
917 * This routine contains a trick.
918 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
920 switch (cyrix_did & 0x00f0) {
929 if ((cyrix_did & 0x000f) < 8)
942 /* M2 and later CPUs are treated as M2. */
946 * enable cpuid instruction.
948 ccr3 = read_cyrix_reg(CCR3);
949 write_cyrix_reg(CCR3, CCR3_MAPEN0);
950 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
951 write_cyrix_reg(CCR3, ccr3);
954 cpu_high = regs[0]; /* eax */
956 cpu_id = regs[0]; /* eax */
957 cpu_feature = regs[3]; /* edx */
961 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
963 * There are BlueLightning CPUs that do not change
964 * undefined flags by dividing 5 by 2. In this case,
965 * the CPU identification routine in locore.s leaves
966 * cpu_vendor null string and puts CPU_486 into the
969 isblue = identblue();
970 if (isblue == IDENTBLUE_IBMCPU) {
971 strcpy(cpu_vendor, "IBM");
979 print_AMD_assoc(int i)
982 printf(", fully associative\n");
984 printf(", %d-way associative\n", i);
992 if (cpu_exthigh >= 0x80000005) {
995 do_cpuid(0x80000005, regs);
996 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
997 print_AMD_assoc(regs[1] >> 24);
998 printf("Instruction TLB: %d entries", regs[1] & 0xff);
999 print_AMD_assoc((regs[1] >> 8) & 0xff);
1000 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1001 printf(", %d bytes/line", regs[2] & 0xff);
1002 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1003 print_AMD_assoc((regs[2] >> 16) & 0xff);
1004 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1005 printf(", %d bytes/line", regs[3] & 0xff);
1006 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1007 print_AMD_assoc((regs[3] >> 16) & 0xff);
1008 if (cpu_exthigh >= 0x80000006) { /* K6-III, or later */
1009 do_cpuid(0x80000006, regs);
1011 * Report right L2 cache size on Duron rev. A0.
1013 if ((cpu_id & 0xFF0) == 0x630)
1014 printf("L2 internal cache: 64 kbytes");
1016 printf("L2 internal cache: %d kbytes",
1019 printf(", %d bytes/line", regs[2] & 0xff);
1020 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1021 print_AMD_assoc((regs[2] >> 12) & 0x0f);
1024 if (((cpu_id & 0xf00) == 0x500)
1025 && (((cpu_id & 0x0f0) > 0x80)
1026 || (((cpu_id & 0x0f0) == 0x80)
1027 && (cpu_id & 0x00f) > 0x07))) {
1028 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1029 amd_whcr = rdmsr(0xc0000082);
1030 if (!(amd_whcr & (0x3ff << 22))) {
1031 printf("Write Allocate Disable\n");
1033 printf("Write Allocate Enable Limit: %dM bytes\n",
1034 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1035 printf("Write Allocate 15-16M bytes: %s\n",
1036 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1038 } else if (((cpu_id & 0xf00) == 0x500)
1039 && ((cpu_id & 0x0f0) > 0x50)) {
1040 /* K6, K6-2(old core) */
1041 amd_whcr = rdmsr(0xc0000082);
1042 if (!(amd_whcr & (0x7f << 1))) {
1043 printf("Write Allocate Disable\n");
1045 printf("Write Allocate Enable Limit: %dM bytes\n",
1046 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1047 printf("Write Allocate 15-16M bytes: %s\n",
1048 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1049 printf("Hardware Write Allocate Control: %s\n",
1050 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1055 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
1057 print_AMD_features(void)
1062 * Values taken from AMD Processor Recognition
1063 * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
1065 do_cpuid(0x80000001, regs);
1066 printf("\n AMD Features=0x%b", regs[3] &~ cpu_feature,
1068 "\001FPU" /* Integral FPU */
1069 "\002VME" /* Extended VM86 mode support */
1070 "\003DE" /* Debug extensions */
1071 "\004PSE" /* 4MByte page tables */
1072 "\005TSC" /* Timestamp counter */
1073 "\006MSR" /* Machine specific registers */
1074 "\007PAE" /* Physical address extension */
1075 "\010MCE" /* Machine Check support */
1076 "\011CX8" /* CMPEXCH8 instruction */
1077 "\012APIC" /* SMP local APIC */
1079 "\014SYSCALL" /* SYSENTER/SYSEXIT instructions */
1080 "\015MTRR" /* Memory Type Range Registers */
1081 "\016PGE" /* PG_G (global bit) support */
1082 "\017MCA" /* Machine Check Architecture */
1083 "\020ICMOV" /* CMOV instruction */
1084 "\021PAT" /* Page attributes table */
1085 "\022PGE36" /* 36 bit address space support */
1086 "\023RSVD" /* Reserved, unknown */
1087 "\024MP" /* Multiprocessor Capable */
1090 "\027AMIE" /* AMD MMX Instruction Extensions */
1092 "\031FXSAVE" /* FXSAVE/FXRSTOR */
1098 "\037DSP" /* AMD 3DNow! Instruction Extensions */
1105 * Transmeta Crusoe LongRun Support by Tamotsu Hattori.
1108 #define MSR_TMx86_LONGRUN 0x80868010
1109 #define MSR_TMx86_LONGRUN_FLAGS 0x80868011
1111 #define LONGRUN_MODE_MASK(x) ((x) & 0x000000007f)
1112 #define LONGRUN_MODE_RESERVED(x) ((x) & 0xffffff80)
1113 #define LONGRUN_MODE_WRITE(x, y) (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y))
1115 #define LONGRUN_MODE_MINFREQUENCY 0x00
1116 #define LONGRUN_MODE_ECONOMY 0x01
1117 #define LONGRUN_MODE_PERFORMANCE 0x02
1118 #define LONGRUN_MODE_MAXFREQUENCY 0x03
1119 #define LONGRUN_MODE_UNKNOWN 0x04
1120 #define LONGRUN_MODE_MAX 0x04
1127 u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
1128 /* MSR low, MSR high, flags bit0 */
1129 { 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */
1130 { 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */
1131 { 0, 100, 1}, /* LONGRUN_MODE_PERFORMANCE */
1132 { 100, 100, 1}, /* LONGRUN_MODE_MAXFREQUENCY */
1136 tmx86_get_longrun_mode(void)
1138 union msrinfo msrinfo;
1139 u_int low, high, flags, mode;
1143 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1144 low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
1145 high = LONGRUN_MODE_MASK(msrinfo.regs[1]);
1146 flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
1148 for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) {
1149 if (low == longrun_modes[mode][0] &&
1150 high == longrun_modes[mode][1] &&
1151 flags == longrun_modes[mode][2]) {
1155 mode = LONGRUN_MODE_UNKNOWN;
1162 tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
1168 do_cpuid(0x80860007, regs);
1169 *frequency = regs[0];
1171 *percentage = regs[2];
1178 tmx86_set_longrun_mode(u_int mode)
1180 union msrinfo msrinfo;
1182 if (mode >= LONGRUN_MODE_UNKNOWN) {
1188 /* Write LongRun mode values to Model Specific Register. */
1189 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1190 msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0],
1191 longrun_modes[mode][0]);
1192 msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1],
1193 longrun_modes[mode][1]);
1194 wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
1196 /* Write LongRun mode flags to Model Specific Register. */
1197 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
1198 msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
1199 wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
1205 static u_int crusoe_longrun;
1206 static u_int crusoe_frequency;
1207 static u_int crusoe_voltage;
1208 static u_int crusoe_percentage;
1209 static struct sysctl_ctx_list crusoe_sysctl_ctx;
1210 static struct sysctl_oid *crusoe_sysctl_tree;
1213 tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS)
1218 crusoe_longrun = tmx86_get_longrun_mode();
1219 mode = crusoe_longrun;
1220 error = sysctl_handle_int(oidp, &mode, 0, req);
1221 if (error || !req->newptr) {
1224 if (mode >= LONGRUN_MODE_UNKNOWN) {
1228 if (crusoe_longrun != mode) {
1229 crusoe_longrun = mode;
1230 tmx86_set_longrun_mode(crusoe_longrun);
1237 tmx86_status_sysctl(SYSCTL_HANDLER_ARGS)
1242 tmx86_get_longrun_status(&crusoe_frequency,
1243 &crusoe_voltage, &crusoe_percentage);
1244 val = *(u_int *)oidp->oid_arg1;
1245 error = sysctl_handle_int(oidp, &val, 0, req);
1250 setup_tmx86_longrun(void)
1252 static int done = 0;
1258 sysctl_ctx_init(&crusoe_sysctl_ctx);
1259 crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx,
1260 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1261 "crusoe", CTLFLAG_RD, 0,
1262 "Transmeta Crusoe LongRun support");
1263 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1264 OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW,
1265 &crusoe_longrun, 0, tmx86_longrun_sysctl, "I",
1266 "LongRun mode [0-3]");
1267 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1268 OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD,
1269 &crusoe_frequency, 0, tmx86_status_sysctl, "I",
1270 "Current frequency (MHz)");
1271 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1272 OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD,
1273 &crusoe_voltage, 0, tmx86_status_sysctl, "I",
1274 "Current voltage (mV)");
1275 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1276 OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD,
1277 &crusoe_percentage, 0, tmx86_status_sysctl, "I",
1278 "Processing performance (%)");
1282 print_transmeta_info(void)
1284 u_int regs[4], nreg = 0;
1286 do_cpuid(0x80860000, regs);
1288 if (nreg >= 0x80860001) {
1289 do_cpuid(0x80860001, regs);
1290 printf(" Processor revision %u.%u.%u.%u\n",
1291 (regs[1] >> 24) & 0xff,
1292 (regs[1] >> 16) & 0xff,
1293 (regs[1] >> 8) & 0xff,
1296 if (nreg >= 0x80860002) {
1297 do_cpuid(0x80860002, regs);
1298 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
1299 (regs[1] >> 24) & 0xff,
1300 (regs[1] >> 16) & 0xff,
1301 (regs[1] >> 8) & 0xff,
1305 if (nreg >= 0x80860006) {
1307 do_cpuid(0x80860003, (u_int*) &info[0]);
1308 do_cpuid(0x80860004, (u_int*) &info[16]);
1309 do_cpuid(0x80860005, (u_int*) &info[32]);
1310 do_cpuid(0x80860006, (u_int*) &info[48]);
1312 printf(" %s\n", info);
1315 crusoe_longrun = tmx86_get_longrun_mode();
1316 tmx86_get_longrun_status(&crusoe_frequency,
1317 &crusoe_voltage, &crusoe_percentage);
1318 printf(" LongRun mode: %d <%dMHz %dmV %d%%>\n", crusoe_longrun,
1319 crusoe_frequency, crusoe_voltage, crusoe_percentage);
1323 additional_cpu_info(const char *line)
1327 if ((i = additional_cpu_info_count) < MAX_ADDITIONAL_INFO) {
1328 additional_cpu_info_ary[i] = line;
1329 ++additional_cpu_info_count;