2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/export.h>
31 #include <linux/slab.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 static const struct dp_link_dpll gen4_dpll[] = {
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53 static const struct dp_link_dpll pch_dpll[] = {
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60 static const struct dp_link_dpll vlv_dpll[] = {
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
68 * CHV supports eDP 1.4 that have more link rates.
69 * Below only provides the fixed rate but exclude variable rate.
71 static const struct dp_link_dpll chv_dpll[] = {
73 * CHV requires to program fractional division for m2.
74 * m2 is stored in fixed point format using formula below
75 * (m2_int << 22) | m2_fraction
77 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
78 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
79 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
80 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
81 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
86 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
87 * @intel_dp: DP struct
89 * If a CPU or PCH DP output is attached to an eDP panel, this function
90 * will return true, and false otherwise.
92 static bool is_edp(struct intel_dp *intel_dp)
94 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
96 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
99 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
101 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
103 return intel_dig_port->base.base.dev;
106 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
108 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
111 static void intel_dp_link_down(struct intel_dp *intel_dp);
112 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
113 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
116 intel_dp_max_link_bw(struct intel_dp *intel_dp)
118 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
119 struct drm_device *dev = intel_dp->attached_connector->base.dev;
121 switch (max_link_bw) {
122 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
126 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
127 INTEL_INFO(dev)->gen >= 8) &&
128 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
129 max_link_bw = DP_LINK_BW_5_4;
131 max_link_bw = DP_LINK_BW_2_7;
134 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
136 max_link_bw = DP_LINK_BW_1_62;
142 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
144 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
145 struct drm_device *dev = intel_dig_port->base.base.dev;
146 u8 source_max, sink_max;
149 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
150 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
155 return min(source_max, sink_max);
159 * The units on the numbers in the next two are... bizarre. Examples will
160 * make it clearer; this one parallels an example in the eDP spec.
162 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
164 * 270000 * 1 * 8 / 10 == 216000
166 * The actual data capacity of that configuration is 2.16Gbit/s, so the
167 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
168 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
169 * 119000. At 18bpp that's 2142000 kilobits per second.
171 * Thus the strange-looking division by 10 in intel_dp_link_required, to
172 * get the result in decakilobits instead of kilobits.
176 intel_dp_link_required(int pixel_clock, int bpp)
178 return (pixel_clock * bpp + 9) / 10;
182 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
184 return (max_link_clock * max_lanes * 8) / 10;
187 static enum drm_mode_status
188 intel_dp_mode_valid(struct drm_connector *connector,
189 struct drm_display_mode *mode)
191 struct intel_dp *intel_dp = intel_attached_dp(connector);
192 struct intel_connector *intel_connector = to_intel_connector(connector);
193 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
194 int target_clock = mode->clock;
195 int max_rate, mode_rate, max_lanes, max_link_clock;
197 if (is_edp(intel_dp) && fixed_mode) {
198 if (mode->hdisplay > fixed_mode->hdisplay)
201 if (mode->vdisplay > fixed_mode->vdisplay)
204 target_clock = fixed_mode->clock;
207 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
208 max_lanes = intel_dp_max_lane_count(intel_dp);
210 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
211 mode_rate = intel_dp_link_required(target_clock, 18);
213 if (mode_rate > max_rate)
214 return MODE_CLOCK_HIGH;
216 if (mode->clock < 10000)
217 return MODE_CLOCK_LOW;
219 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
220 return MODE_H_ILLEGAL;
226 pack_aux(uint8_t *src, int src_bytes)
233 for (i = 0; i < src_bytes; i++)
234 v |= ((uint32_t) src[i]) << ((3-i) * 8);
239 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
244 for (i = 0; i < dst_bytes; i++)
245 dst[i] = src >> ((3-i) * 8);
248 /* hrawclock is 1/4 the FSB frequency */
250 intel_hrawclk(struct drm_device *dev)
252 struct drm_i915_private *dev_priv = dev->dev_private;
255 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
256 if (IS_VALLEYVIEW(dev))
259 clkcfg = I915_READ(CLKCFG);
260 switch (clkcfg & CLKCFG_FSB_MASK) {
269 case CLKCFG_FSB_1067:
271 case CLKCFG_FSB_1333:
273 /* these two are just a guess; one of them might be right */
274 case CLKCFG_FSB_1600:
275 case CLKCFG_FSB_1600_ALT:
283 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
284 struct intel_dp *intel_dp,
285 struct edp_power_seq *out);
287 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
288 struct intel_dp *intel_dp,
289 struct edp_power_seq *out);
291 static void pps_lock(struct intel_dp *intel_dp)
293 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
294 struct intel_encoder *encoder = &intel_dig_port->base;
295 struct drm_device *dev = encoder->base.dev;
296 struct drm_i915_private *dev_priv = dev->dev_private;
297 enum intel_display_power_domain power_domain;
300 * See vlv_power_sequencer_reset() why we need
301 * a power domain reference here.
303 power_domain = intel_display_port_power_domain(encoder);
304 intel_display_power_get(dev_priv, power_domain);
306 mutex_lock(&dev_priv->pps_mutex);
309 static void pps_unlock(struct intel_dp *intel_dp)
311 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
312 struct intel_encoder *encoder = &intel_dig_port->base;
313 struct drm_device *dev = encoder->base.dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315 enum intel_display_power_domain power_domain;
317 mutex_unlock(&dev_priv->pps_mutex);
319 power_domain = intel_display_port_power_domain(encoder);
320 intel_display_power_put(dev_priv, power_domain);
323 static enum i915_pipe
324 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
326 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
327 struct drm_device *dev = intel_dig_port->base.base.dev;
328 struct drm_i915_private *dev_priv = dev->dev_private;
329 struct intel_encoder *encoder;
330 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
331 struct edp_power_seq power_seq;
333 lockdep_assert_held(&dev_priv->pps_mutex);
335 if (intel_dp->pps_pipe != INVALID_PIPE)
336 return intel_dp->pps_pipe;
339 * We don't have power sequencer currently.
340 * Pick one that's not used by other ports.
342 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
344 struct intel_dp *tmp;
346 if (encoder->type != INTEL_OUTPUT_EDP)
349 tmp = enc_to_intel_dp(&encoder->base);
351 if (tmp->pps_pipe != INVALID_PIPE)
352 pipes &= ~(1 << tmp->pps_pipe);
356 * Didn't find one. This should not happen since there
357 * are two power sequencers and up to two eDP ports.
359 if (WARN_ON(pipes == 0))
362 intel_dp->pps_pipe = ffs(pipes) - 1;
364 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
365 pipe_name(intel_dp->pps_pipe),
366 port_name(intel_dig_port->port));
368 /* init power sequencer on this pipe and port */
369 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
370 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
373 return intel_dp->pps_pipe;
376 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
377 enum i915_pipe pipe);
379 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
382 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
385 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
388 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
391 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
397 static enum i915_pipe
398 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
400 vlv_pipe_check pipe_check)
404 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
405 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
406 PANEL_PORT_SELECT_MASK;
408 if (port_sel != PANEL_PORT_SELECT_VLV(port))
411 if (!pipe_check(dev_priv, pipe))
421 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
423 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
424 struct drm_device *dev = intel_dig_port->base.base.dev;
425 struct drm_i915_private *dev_priv = dev->dev_private;
426 struct edp_power_seq power_seq;
427 enum port port = intel_dig_port->port;
429 lockdep_assert_held(&dev_priv->pps_mutex);
431 /* try to find a pipe with this port selected */
432 /* first pick one where the panel is on */
433 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
435 /* didn't find one? pick one where vdd is on */
436 if (intel_dp->pps_pipe == INVALID_PIPE)
437 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
438 vlv_pipe_has_vdd_on);
439 /* didn't find one? pick one with just the correct port */
440 if (intel_dp->pps_pipe == INVALID_PIPE)
441 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
444 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
445 if (intel_dp->pps_pipe == INVALID_PIPE) {
446 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
451 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
452 port_name(port), pipe_name(intel_dp->pps_pipe));
454 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
455 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
459 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
461 struct drm_device *dev = dev_priv->dev;
462 struct intel_encoder *encoder;
464 if (WARN_ON(!IS_VALLEYVIEW(dev)))
468 * We can't grab pps_mutex here due to deadlock with power_domain
469 * mutex when power_domain functions are called while holding pps_mutex.
470 * That also means that in order to use pps_pipe the code needs to
471 * hold both a power domain reference and pps_mutex, and the power domain
472 * reference get/put must be done while _not_ holding pps_mutex.
473 * pps_{lock,unlock}() do these steps in the correct order, so one
474 * should use them always.
477 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
478 struct intel_dp *intel_dp;
480 if (encoder->type != INTEL_OUTPUT_EDP)
483 intel_dp = enc_to_intel_dp(&encoder->base);
484 intel_dp->pps_pipe = INVALID_PIPE;
488 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
490 struct drm_device *dev = intel_dp_to_dev(intel_dp);
492 if (HAS_PCH_SPLIT(dev))
493 return PCH_PP_CONTROL;
495 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
498 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
500 struct drm_device *dev = intel_dp_to_dev(intel_dp);
502 if (HAS_PCH_SPLIT(dev))
503 return PCH_PP_STATUS;
505 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
508 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
509 This function only applicable when panel PM state is not to be tracked */
511 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
514 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
516 struct drm_device *dev = intel_dp_to_dev(intel_dp);
517 struct drm_i915_private *dev_priv = dev->dev_private;
519 u32 pp_ctrl_reg, pp_div_reg;
521 if (!is_edp(intel_dp) || code != SYS_RESTART)
526 if (IS_VALLEYVIEW(dev)) {
527 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);
529 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
530 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
531 pp_div = I915_READ(pp_div_reg);
532 pp_div &= PP_REFERENCE_DIVIDER_MASK;
534 /* 0x1F write to PP_DIV_REG sets max cycle delay */
535 I915_WRITE(pp_div_reg, pp_div | 0x1F);
536 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
537 msleep(intel_dp->panel_power_cycle_delay);
540 pps_unlock(intel_dp);
546 static bool edp_have_panel_power(struct intel_dp *intel_dp)
548 struct drm_device *dev = intel_dp_to_dev(intel_dp);
549 struct drm_i915_private *dev_priv = dev->dev_private;
551 lockdep_assert_held(&dev_priv->pps_mutex);
553 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
556 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
559 struct drm_i915_private *dev_priv = dev->dev_private;
561 lockdep_assert_held(&dev_priv->pps_mutex);
563 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
567 intel_dp_check_edp(struct intel_dp *intel_dp)
569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
570 struct drm_i915_private *dev_priv = dev->dev_private;
572 if (!is_edp(intel_dp))
575 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
576 WARN(1, "eDP powered off while attempting aux channel communication.\n");
577 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
578 I915_READ(_pp_stat_reg(intel_dp)),
579 I915_READ(_pp_ctrl_reg(intel_dp)));
584 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
587 struct drm_device *dev = intel_dig_port->base.base.dev;
588 struct drm_i915_private *dev_priv = dev->dev_private;
589 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
593 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
595 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
596 msecs_to_jiffies_timeout(10));
598 done = wait_for_atomic(C, 10) == 0;
600 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
607 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
609 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
610 struct drm_device *dev = intel_dig_port->base.base.dev;
613 * The clock divider is based off the hrawclk, and would like to run at
614 * 2MHz. So, take the hrawclk value and divide by 2 and use that
616 return index ? 0 : intel_hrawclk(dev) / 2;
619 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
621 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
622 struct drm_device *dev = intel_dig_port->base.base.dev;
627 if (intel_dig_port->port == PORT_A) {
628 if (IS_GEN6(dev) || IS_GEN7(dev))
629 return 200; /* SNB & IVB eDP input clock at 400Mhz */
631 return 225; /* eDP input clock at 450Mhz */
633 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
637 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
639 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
640 struct drm_device *dev = intel_dig_port->base.base.dev;
641 struct drm_i915_private *dev_priv = dev->dev_private;
643 if (intel_dig_port->port == PORT_A) {
646 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
647 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
648 /* Workaround for non-ULT HSW */
655 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
659 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
661 return index ? 0 : 100;
664 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
667 uint32_t aux_clock_divider)
669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
670 struct drm_device *dev = intel_dig_port->base.base.dev;
671 uint32_t precharge, timeout;
678 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
679 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
681 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
683 return DP_AUX_CH_CTL_SEND_BUSY |
685 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
686 DP_AUX_CH_CTL_TIME_OUT_ERROR |
688 DP_AUX_CH_CTL_RECEIVE_ERROR |
689 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
690 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
691 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
695 intel_dp_aux_ch(struct intel_dp *intel_dp,
696 uint8_t *send, int send_bytes,
697 uint8_t *recv, int recv_size)
699 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
700 struct drm_device *dev = intel_dig_port->base.base.dev;
701 struct drm_i915_private *dev_priv = dev->dev_private;
702 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
703 uint32_t ch_data = ch_ctl + 4;
704 uint32_t aux_clock_divider;
705 int i, ret, recv_bytes;
708 bool has_aux_irq = HAS_AUX_IRQ(dev);
714 * We will be called with VDD already enabled for dpcd/edid/oui reads.
715 * In such cases we want to leave VDD enabled and it's up to upper layers
716 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
719 vdd = edp_panel_vdd_on(intel_dp);
721 /* dp aux is extremely sensitive to irq latency, hence request the
722 * lowest possible wakeup latency and so prevent the cpu from going into
725 pm_qos_update_request(&dev_priv->pm_qos, 0);
727 intel_dp_check_edp(intel_dp);
729 intel_aux_display_runtime_get(dev_priv);
731 /* Try to wait for any previous AUX channel activity */
732 for (try = 0; try < 3; try++) {
733 status = I915_READ_NOTRACE(ch_ctl);
734 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
740 WARN(1, "dp_aux_ch not started status 0x%08x\n",
746 /* Only 5 data registers! */
747 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
752 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
753 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
758 /* Must try at least 3 times according to DP spec */
759 for (try = 0; try < 5; try++) {
760 /* Load the send data into the aux channel data registers */
761 for (i = 0; i < send_bytes; i += 4)
762 I915_WRITE(ch_data + i,
763 pack_aux(send + i, send_bytes - i));
765 /* Send the command and wait for it to complete */
766 I915_WRITE(ch_ctl, send_ctl);
768 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
770 /* Clear done status and any errors */
774 DP_AUX_CH_CTL_TIME_OUT_ERROR |
775 DP_AUX_CH_CTL_RECEIVE_ERROR);
777 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
778 DP_AUX_CH_CTL_RECEIVE_ERROR))
780 if (status & DP_AUX_CH_CTL_DONE)
783 if (status & DP_AUX_CH_CTL_DONE)
787 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
788 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
793 /* Check for timeout or receive error.
794 * Timeouts occur when the sink is not connected
796 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
797 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
802 /* Timeouts occur when the device isn't connected, so they're
803 * "normal" -- don't fill the kernel log with these */
804 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
805 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
810 /* Unload any bytes sent back from the other side */
811 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
812 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
813 if (recv_bytes > recv_size)
814 recv_bytes = recv_size;
816 for (i = 0; i < recv_bytes; i += 4)
817 unpack_aux(I915_READ(ch_data + i),
818 recv + i, recv_bytes - i);
822 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
823 intel_aux_display_runtime_put(dev_priv);
826 edp_panel_vdd_off(intel_dp, false);
828 pps_unlock(intel_dp);
833 #define BARE_ADDRESS_SIZE 3
834 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
836 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
838 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
839 uint8_t txbuf[20], rxbuf[20];
840 size_t txsize, rxsize;
843 txbuf[0] = msg->request << 4;
844 txbuf[1] = msg->address >> 8;
845 txbuf[2] = msg->address & 0xff;
846 txbuf[3] = msg->size - 1;
848 switch (msg->request & ~DP_AUX_I2C_MOT) {
849 case DP_AUX_NATIVE_WRITE:
850 case DP_AUX_I2C_WRITE:
851 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
854 if (WARN_ON(txsize > 20))
857 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
859 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
861 msg->reply = rxbuf[0] >> 4;
863 /* Return payload size. */
868 case DP_AUX_NATIVE_READ:
869 case DP_AUX_I2C_READ:
870 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
871 rxsize = msg->size + 1;
873 if (WARN_ON(rxsize > 20))
876 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
878 msg->reply = rxbuf[0] >> 4;
880 * Assume happy day, and copy the data. The caller is
881 * expected to check msg->reply before touching it.
883 * Return payload size.
886 memcpy(msg->buffer, rxbuf + 1, ret);
899 intel_dp_i2c_aux_ch(struct device *adapter, int mode,
900 uint8_t write_byte, uint8_t *read_byte)
902 struct i2c_algo_dp_aux_data *data = device_get_softc(adapter);
903 struct intel_dp *intel_dp = data->priv;
904 uint16_t address = data->address;
912 intel_edp_panel_vdd_on(intel_dp);
913 intel_dp_check_edp(intel_dp);
914 /* Set up the command byte */
915 if (mode & MODE_I2C_READ)
916 msg[0] = DP_AUX_I2C_READ << 4;
918 msg[0] = DP_AUX_I2C_WRITE << 4;
920 if (!(mode & MODE_I2C_STOP))
921 msg[0] |= DP_AUX_I2C_MOT << 4;
923 msg[1] = address >> 8;
945 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
946 * required to retry at least seven times upon receiving AUX_DEFER
947 * before giving up the AUX transaction.
949 for (retry = 0; retry < 7; retry++) {
950 ret = intel_dp_aux_ch(intel_dp,
954 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
958 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
959 case DP_AUX_NATIVE_REPLY_ACK:
960 /* I2C-over-AUX Reply field is only valid
961 * when paired with AUX ACK.
964 case DP_AUX_NATIVE_REPLY_NACK:
965 DRM_DEBUG_KMS("aux_ch native nack\n");
968 case DP_AUX_NATIVE_REPLY_DEFER:
970 * For now, just give more slack to branch devices. We
971 * could check the DPCD for I2C bit rate capabilities,
972 * and if available, adjust the interval. We could also
973 * be more careful with DP-to-Legacy adapters where a
974 * long legacy cable may force very low I2C bit rates.
976 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
977 DP_DWN_STRM_PORT_PRESENT)
978 usleep_range(500, 600);
980 usleep_range(300, 400);
983 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
989 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
990 case DP_AUX_I2C_REPLY_ACK:
991 if (mode == MODE_I2C_READ) {
992 *read_byte = reply[1];
994 ret = 0; /* reply_bytes - 1 */
996 case DP_AUX_I2C_REPLY_NACK:
997 DRM_DEBUG_KMS("aux_i2c nack\n");
1000 case DP_AUX_I2C_REPLY_DEFER:
1001 DRM_DEBUG_KMS("aux_i2c defer\n");
1005 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
1011 DRM_ERROR("too many retries, giving up\n");
1019 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1021 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1022 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1023 enum port port = intel_dig_port->port;
1024 const char *name = NULL;
1029 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
1033 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
1037 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
1041 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
1049 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
1051 intel_dp->aux.name = name;
1052 intel_dp->aux.dev = dev->dev;
1053 intel_dp->aux.transfer = intel_dp_aux_transfer;
1055 DRM_DEBUG_KMS("i2c_init %s\n", name);
1056 ret = iic_dp_aux_add_bus(connector->base.dev->dev, name,
1057 intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,
1058 &intel_dp->aux.ddc);
1059 WARN(ret, "intel_dp_i2c_init failed with error %d for port %c\n",
1060 ret, port_name(port));
1065 intel_dp_connector_unregister(struct intel_connector *intel_connector)
1067 intel_connector_unregister(intel_connector);
1072 intel_dp_i2c_init(struct intel_dp *intel_dp,
1073 struct intel_connector *intel_connector, const char *name)
1077 DRM_DEBUG_KMS("i2c_init %s\n", name);
1079 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
1080 intel_dp->adapter.owner = THIS_MODULE;
1081 intel_dp->adapter.class = I2C_CLASS_DDC;
1082 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
1083 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
1084 intel_dp->adapter.algo_data = &intel_dp->algo;
1085 intel_dp->adapter.dev.parent = intel_connector->base.dev->dev;
1087 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
1091 ret = sysfs_create_link(&intel_connector->base.kdev->kobj,
1092 &intel_dp->adapter.dev.kobj,
1093 intel_dp->adapter.dev.kobj.name);
1095 ret = iic_dp_aux_add_bus(intel_connector->base.dev->dev, name,
1096 intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,
1097 &intel_dp->adapter);
1104 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
1107 case DP_LINK_BW_1_62:
1108 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1110 case DP_LINK_BW_2_7:
1111 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1113 case DP_LINK_BW_5_4:
1114 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1120 intel_dp_set_clock(struct intel_encoder *encoder,
1121 struct intel_crtc_config *pipe_config, int link_bw)
1123 struct drm_device *dev = encoder->base.dev;
1124 const struct dp_link_dpll *divisor = NULL;
1128 divisor = gen4_dpll;
1129 count = ARRAY_SIZE(gen4_dpll);
1130 } else if (HAS_PCH_SPLIT(dev)) {
1132 count = ARRAY_SIZE(pch_dpll);
1133 } else if (IS_CHERRYVIEW(dev)) {
1135 count = ARRAY_SIZE(chv_dpll);
1136 } else if (IS_VALLEYVIEW(dev)) {
1138 count = ARRAY_SIZE(vlv_dpll);
1141 if (divisor && count) {
1142 for (i = 0; i < count; i++) {
1143 if (link_bw == divisor[i].link_bw) {
1144 pipe_config->dpll = divisor[i].dpll;
1145 pipe_config->clock_set = true;
1153 intel_dp_compute_config(struct intel_encoder *encoder,
1154 struct intel_crtc_config *pipe_config)
1156 struct drm_device *dev = encoder->base.dev;
1157 struct drm_i915_private *dev_priv = dev->dev_private;
1158 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1159 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1160 enum port port = dp_to_dig_port(intel_dp)->port;
1161 struct intel_crtc *intel_crtc = encoder->new_crtc;
1162 struct intel_connector *intel_connector = intel_dp->attached_connector;
1163 int lane_count, clock;
1164 int min_lane_count = 1;
1165 int max_lane_count = intel_dp_max_lane_count(intel_dp);
1166 /* Conveniently, the link BW constants become indices with a shift...*/
1168 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
1170 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
1171 int link_avail, link_clock;
1173 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1174 pipe_config->has_pch_encoder = true;
1176 pipe_config->has_dp_encoder = true;
1177 pipe_config->has_drrs = false;
1178 pipe_config->has_audio = intel_dp->has_audio;
1180 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1181 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1183 if (!HAS_PCH_SPLIT(dev))
1184 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1185 intel_connector->panel.fitting_mode);
1187 intel_pch_panel_fitting(intel_crtc, pipe_config,
1188 intel_connector->panel.fitting_mode);
1191 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1194 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1195 "max bw %02x pixel clock %iKHz\n",
1196 max_lane_count, bws[max_clock],
1197 adjusted_mode->crtc_clock);
1199 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1200 * bpc in between. */
1201 bpp = pipe_config->pipe_bpp;
1202 if (is_edp(intel_dp)) {
1203 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1204 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1205 dev_priv->vbt.edp_bpp);
1206 bpp = dev_priv->vbt.edp_bpp;
1210 * Use the maximum clock and number of lanes the eDP panel
1211 * advertizes being capable of. The panels are generally
1212 * designed to support only a single clock and lane
1213 * configuration, and typically these values correspond to the
1214 * native resolution of the panel.
1216 min_lane_count = max_lane_count;
1217 min_clock = max_clock;
1220 for (; bpp >= 6*3; bpp -= 2*3) {
1221 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1224 for (clock = min_clock; clock <= max_clock; clock++) {
1225 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
1226 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1227 link_avail = intel_dp_max_data_rate(link_clock,
1230 if (mode_rate <= link_avail) {
1240 if (intel_dp->color_range_auto) {
1243 * CEA-861-E - 5.1 Default Encoding Parameters
1244 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1246 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
1247 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1249 intel_dp->color_range = 0;
1252 if (intel_dp->color_range)
1253 pipe_config->limited_color_range = true;
1255 intel_dp->link_bw = bws[clock];
1256 intel_dp->lane_count = lane_count;
1257 pipe_config->pipe_bpp = bpp;
1258 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
1260 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1261 intel_dp->link_bw, intel_dp->lane_count,
1262 pipe_config->port_clock, bpp);
1263 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1264 mode_rate, link_avail);
1266 intel_link_compute_m_n(bpp, lane_count,
1267 adjusted_mode->crtc_clock,
1268 pipe_config->port_clock,
1269 &pipe_config->dp_m_n);
1271 if (intel_connector->panel.downclock_mode != NULL &&
1272 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
1273 pipe_config->has_drrs = true;
1274 intel_link_compute_m_n(bpp, lane_count,
1275 intel_connector->panel.downclock_mode->clock,
1276 pipe_config->port_clock,
1277 &pipe_config->dp_m2_n2);
1280 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1281 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1283 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
1288 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1290 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1291 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1292 struct drm_device *dev = crtc->base.dev;
1293 struct drm_i915_private *dev_priv = dev->dev_private;
1296 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
1297 dpa_ctl = I915_READ(DP_A);
1298 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1300 if (crtc->config.port_clock == 162000) {
1301 /* For a long time we've carried around a ILK-DevA w/a for the
1302 * 160MHz clock. If we're really unlucky, it's still required.
1304 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1305 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1306 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1308 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1309 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1312 I915_WRITE(DP_A, dpa_ctl);
1318 static void intel_dp_prepare(struct intel_encoder *encoder)
1320 struct drm_device *dev = encoder->base.dev;
1321 struct drm_i915_private *dev_priv = dev->dev_private;
1322 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1323 enum port port = dp_to_dig_port(intel_dp)->port;
1324 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1325 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1328 * There are four kinds of DP registers:
1335 * IBX PCH and CPU are the same for almost everything,
1336 * except that the CPU DP PLL is configured in this
1339 * CPT PCH is quite different, having many bits moved
1340 * to the TRANS_DP_CTL register instead. That
1341 * configuration happens (oddly) in ironlake_pch_enable
1344 /* Preserve the BIOS-computed detected bit. This is
1345 * supposed to be read-only.
1347 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1349 /* Handle DP bits in common between all three register formats */
1350 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1351 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1353 if (crtc->config.has_audio) {
1354 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1355 pipe_name(crtc->pipe));
1356 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1357 intel_write_eld(&encoder->base, adjusted_mode);
1360 /* Split out the IBX/CPU vs CPT settings */
1362 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1363 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1364 intel_dp->DP |= DP_SYNC_HS_HIGH;
1365 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1366 intel_dp->DP |= DP_SYNC_VS_HIGH;
1367 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1369 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1370 intel_dp->DP |= DP_ENHANCED_FRAMING;
1372 intel_dp->DP |= crtc->pipe << 29;
1373 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1374 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1375 intel_dp->DP |= intel_dp->color_range;
1377 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1378 intel_dp->DP |= DP_SYNC_HS_HIGH;
1379 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1380 intel_dp->DP |= DP_SYNC_VS_HIGH;
1381 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1383 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1384 intel_dp->DP |= DP_ENHANCED_FRAMING;
1386 if (!IS_CHERRYVIEW(dev)) {
1387 if (crtc->pipe == 1)
1388 intel_dp->DP |= DP_PIPEB_SELECT;
1390 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1393 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1397 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1398 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1400 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1401 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1403 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1404 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1406 static void wait_panel_status(struct intel_dp *intel_dp,
1410 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1411 struct drm_i915_private *dev_priv = dev->dev_private;
1412 u32 pp_stat_reg, pp_ctrl_reg;
1414 lockdep_assert_held(&dev_priv->pps_mutex);
1416 pp_stat_reg = _pp_stat_reg(intel_dp);
1417 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1419 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1421 I915_READ(pp_stat_reg),
1422 I915_READ(pp_ctrl_reg));
1424 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1425 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1426 I915_READ(pp_stat_reg),
1427 I915_READ(pp_ctrl_reg));
1430 DRM_DEBUG_KMS("Wait complete\n");
1433 static void wait_panel_on(struct intel_dp *intel_dp)
1435 DRM_DEBUG_KMS("Wait for panel power on\n");
1436 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1439 static void wait_panel_off(struct intel_dp *intel_dp)
1441 DRM_DEBUG_KMS("Wait for panel power off time\n");
1442 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1445 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1447 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1449 /* When we disable the VDD override bit last we have to do the manual
1451 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1452 intel_dp->panel_power_cycle_delay);
1454 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1457 static void wait_backlight_on(struct intel_dp *intel_dp)
1459 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1460 intel_dp->backlight_on_delay);
1463 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1465 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1466 intel_dp->backlight_off_delay);
1469 /* Read the current pp_control value, unlocking the register if it
1473 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1475 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1476 struct drm_i915_private *dev_priv = dev->dev_private;
1479 lockdep_assert_held(&dev_priv->pps_mutex);
1481 control = I915_READ(_pp_ctrl_reg(intel_dp));
1482 control &= ~PANEL_UNLOCK_MASK;
1483 control |= PANEL_UNLOCK_REGS;
1488 * Must be paired with edp_panel_vdd_off().
1489 * Must hold pps_mutex around the whole on/off sequence.
1490 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1492 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1494 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1495 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1496 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1497 struct drm_i915_private *dev_priv = dev->dev_private;
1498 enum intel_display_power_domain power_domain;
1500 u32 pp_stat_reg, pp_ctrl_reg;
1501 bool need_to_disable = !intel_dp->want_panel_vdd;
1503 lockdep_assert_held(&dev_priv->pps_mutex);
1505 if (!is_edp(intel_dp))
1508 intel_dp->want_panel_vdd = true;
1510 if (edp_have_panel_vdd(intel_dp))
1511 return need_to_disable;
1513 power_domain = intel_display_port_power_domain(intel_encoder);
1514 intel_display_power_get(dev_priv, power_domain);
1516 DRM_DEBUG_KMS("Turning eDP VDD on\n");
1518 if (!edp_have_panel_power(intel_dp))
1519 wait_panel_power_cycle(intel_dp);
1521 pp = ironlake_get_pp_control(intel_dp);
1522 pp |= EDP_FORCE_VDD;
1524 pp_stat_reg = _pp_stat_reg(intel_dp);
1525 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1527 I915_WRITE(pp_ctrl_reg, pp);
1528 POSTING_READ(pp_ctrl_reg);
1529 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1530 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1532 * If the panel wasn't on, delay before accessing aux channel
1534 if (!edp_have_panel_power(intel_dp)) {
1535 DRM_DEBUG_KMS("eDP was not running\n");
1536 msleep(intel_dp->panel_power_up_delay);
1539 return need_to_disable;
1543 * Must be paired with intel_edp_panel_vdd_off() or
1544 * intel_edp_panel_off().
1545 * Nested calls to these functions are not allowed since
1546 * we drop the lock. Caller must use some higher level
1547 * locking to prevent nested calls from other threads.
1549 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1553 if (!is_edp(intel_dp))
1557 vdd = edp_panel_vdd_on(intel_dp);
1558 pps_unlock(intel_dp);
1560 WARN(!vdd, "eDP VDD already requested on\n");
1563 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1565 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1566 struct drm_i915_private *dev_priv = dev->dev_private;
1567 struct intel_digital_port *intel_dig_port =
1568 dp_to_dig_port(intel_dp);
1569 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1570 enum intel_display_power_domain power_domain;
1572 u32 pp_stat_reg, pp_ctrl_reg;
1574 lockdep_assert_held(&dev_priv->pps_mutex);
1576 WARN_ON(intel_dp->want_panel_vdd);
1578 if (!edp_have_panel_vdd(intel_dp))
1581 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1583 pp = ironlake_get_pp_control(intel_dp);
1584 pp &= ~EDP_FORCE_VDD;
1586 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1587 pp_stat_reg = _pp_stat_reg(intel_dp);
1589 I915_WRITE(pp_ctrl_reg, pp);
1590 POSTING_READ(pp_ctrl_reg);
1592 /* Make sure sequencer is idle before allowing subsequent activity */
1593 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1594 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1596 if ((pp & POWER_TARGET_ON) == 0)
1597 intel_dp->last_power_cycle = jiffies;
1599 power_domain = intel_display_port_power_domain(intel_encoder);
1600 intel_display_power_put(dev_priv, power_domain);
1603 static void edp_panel_vdd_work(struct work_struct *__work)
1605 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1606 struct intel_dp, panel_vdd_work);
1609 if (!intel_dp->want_panel_vdd)
1610 edp_panel_vdd_off_sync(intel_dp);
1611 pps_unlock(intel_dp);
1614 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1616 unsigned long delay;
1619 * Queue the timer to fire a long time from now (relative to the power
1620 * down delay) to keep the panel power up across a sequence of
1623 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1624 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1628 * Must be paired with edp_panel_vdd_on().
1629 * Must hold pps_mutex around the whole on/off sequence.
1630 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1632 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1634 struct drm_i915_private *dev_priv =
1635 intel_dp_to_dev(intel_dp)->dev_private;
1637 lockdep_assert_held(&dev_priv->pps_mutex);
1639 if (!is_edp(intel_dp))
1642 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1644 intel_dp->want_panel_vdd = false;
1647 edp_panel_vdd_off_sync(intel_dp);
1649 edp_panel_vdd_schedule_off(intel_dp);
1653 * Must be paired with intel_edp_panel_vdd_on().
1654 * Nested calls to these functions are not allowed since
1655 * we drop the lock. Caller must use some higher level
1656 * locking to prevent nested calls from other threads.
1658 static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1660 if (!is_edp(intel_dp))
1664 edp_panel_vdd_off(intel_dp, sync);
1665 pps_unlock(intel_dp);
1668 void intel_edp_panel_on(struct intel_dp *intel_dp)
1670 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1671 struct drm_i915_private *dev_priv = dev->dev_private;
1675 if (!is_edp(intel_dp))
1678 DRM_DEBUG_KMS("Turn eDP power on\n");
1682 if (edp_have_panel_power(intel_dp)) {
1683 DRM_DEBUG_KMS("eDP power already on\n");
1687 wait_panel_power_cycle(intel_dp);
1689 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1690 pp = ironlake_get_pp_control(intel_dp);
1692 /* ILK workaround: disable reset around power sequence */
1693 pp &= ~PANEL_POWER_RESET;
1694 I915_WRITE(pp_ctrl_reg, pp);
1695 POSTING_READ(pp_ctrl_reg);
1698 pp |= POWER_TARGET_ON;
1700 pp |= PANEL_POWER_RESET;
1702 I915_WRITE(pp_ctrl_reg, pp);
1703 POSTING_READ(pp_ctrl_reg);
1705 wait_panel_on(intel_dp);
1706 intel_dp->last_power_on = jiffies;
1709 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1710 I915_WRITE(pp_ctrl_reg, pp);
1711 POSTING_READ(pp_ctrl_reg);
1715 pps_unlock(intel_dp);
1718 void intel_edp_panel_off(struct intel_dp *intel_dp)
1720 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1721 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1722 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1723 struct drm_i915_private *dev_priv = dev->dev_private;
1724 enum intel_display_power_domain power_domain;
1728 if (!is_edp(intel_dp))
1731 DRM_DEBUG_KMS("Turn eDP power off\n");
1735 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1737 pp = ironlake_get_pp_control(intel_dp);
1738 /* We need to switch off panel power _and_ force vdd, for otherwise some
1739 * panels get very unhappy and cease to work. */
1740 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1743 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1745 intel_dp->want_panel_vdd = false;
1747 I915_WRITE(pp_ctrl_reg, pp);
1748 POSTING_READ(pp_ctrl_reg);
1750 intel_dp->last_power_cycle = jiffies;
1751 wait_panel_off(intel_dp);
1753 /* We got a reference when we enabled the VDD. */
1754 power_domain = intel_display_port_power_domain(intel_encoder);
1755 intel_display_power_put(dev_priv, power_domain);
1757 pps_unlock(intel_dp);
1760 /* Enable backlight in the panel power control. */
1761 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
1763 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1764 struct drm_device *dev = intel_dig_port->base.base.dev;
1765 struct drm_i915_private *dev_priv = dev->dev_private;
1770 * If we enable the backlight right away following a panel power
1771 * on, we may see slight flicker as the panel syncs with the eDP
1772 * link. So delay a bit to make sure the image is solid before
1773 * allowing it to appear.
1775 wait_backlight_on(intel_dp);
1779 pp = ironlake_get_pp_control(intel_dp);
1780 pp |= EDP_BLC_ENABLE;
1782 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1784 I915_WRITE(pp_ctrl_reg, pp);
1785 POSTING_READ(pp_ctrl_reg);
1787 pps_unlock(intel_dp);
1790 /* Enable backlight PWM and backlight PP control. */
1791 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1793 if (!is_edp(intel_dp))
1796 DRM_DEBUG_KMS("\n");
1798 intel_panel_enable_backlight(intel_dp->attached_connector);
1799 _intel_edp_backlight_on(intel_dp);
1802 /* Disable backlight in the panel power control. */
1803 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
1805 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1806 struct drm_i915_private *dev_priv = dev->dev_private;
1810 if (!is_edp(intel_dp))
1815 pp = ironlake_get_pp_control(intel_dp);
1816 pp &= ~EDP_BLC_ENABLE;
1818 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1820 I915_WRITE(pp_ctrl_reg, pp);
1821 POSTING_READ(pp_ctrl_reg);
1823 pps_unlock(intel_dp);
1825 intel_dp->last_backlight_off = jiffies;
1826 edp_wait_backlight_off(intel_dp);
1829 /* Disable backlight PP control and backlight PWM. */
1830 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1832 if (!is_edp(intel_dp))
1835 DRM_DEBUG_KMS("\n");
1837 _intel_edp_backlight_off(intel_dp);
1838 intel_panel_disable_backlight(intel_dp->attached_connector);
1842 * Hook for controlling the panel power control backlight through the bl_power
1843 * sysfs attribute. Take care to handle multiple calls.
1845 static void intel_edp_backlight_power(struct intel_connector *connector,
1848 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1852 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1853 pps_unlock(intel_dp);
1855 if (is_enabled == enable)
1858 DRM_DEBUG_KMS("panel power control backlight %s\n",
1859 enable ? "enable" : "disable");
1862 _intel_edp_backlight_on(intel_dp);
1864 _intel_edp_backlight_off(intel_dp);
1867 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1869 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1870 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1871 struct drm_device *dev = crtc->dev;
1872 struct drm_i915_private *dev_priv = dev->dev_private;
1875 assert_pipe_disabled(dev_priv,
1876 to_intel_crtc(crtc)->pipe);
1878 DRM_DEBUG_KMS("\n");
1879 dpa_ctl = I915_READ(DP_A);
1880 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1881 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1883 /* We don't adjust intel_dp->DP while tearing down the link, to
1884 * facilitate link retraining (e.g. after hotplug). Hence clear all
1885 * enable bits here to ensure that we don't enable too much. */
1886 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1887 intel_dp->DP |= DP_PLL_ENABLE;
1888 I915_WRITE(DP_A, intel_dp->DP);
1893 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1895 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1896 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1897 struct drm_device *dev = crtc->dev;
1898 struct drm_i915_private *dev_priv = dev->dev_private;
1901 assert_pipe_disabled(dev_priv,
1902 to_intel_crtc(crtc)->pipe);
1904 dpa_ctl = I915_READ(DP_A);
1905 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1906 "dp pll off, should be on\n");
1907 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1909 /* We can't rely on the value tracked for the DP register in
1910 * intel_dp->DP because link_down must not change that (otherwise link
1911 * re-training will fail. */
1912 dpa_ctl &= ~DP_PLL_ENABLE;
1913 I915_WRITE(DP_A, dpa_ctl);
1918 /* If the sink supports it, try to set the power state appropriately */
1919 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1923 /* Should have a valid DPCD by this point */
1924 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1927 if (mode != DRM_MODE_DPMS_ON) {
1928 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1932 * When turning on, we need to retry for 1ms to give the sink
1935 for (i = 0; i < 3; i++) {
1936 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1945 DRM_DEBUG_KMS("failed to %s sink power state\n",
1946 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
1949 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1950 enum i915_pipe *pipe)
1952 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1953 enum port port = dp_to_dig_port(intel_dp)->port;
1954 struct drm_device *dev = encoder->base.dev;
1955 struct drm_i915_private *dev_priv = dev->dev_private;
1956 enum intel_display_power_domain power_domain;
1959 power_domain = intel_display_port_power_domain(encoder);
1960 if (!intel_display_power_enabled(dev_priv, power_domain))
1963 tmp = I915_READ(intel_dp->output_reg);
1965 if (!(tmp & DP_PORT_EN))
1968 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1969 *pipe = PORT_TO_PIPE_CPT(tmp);
1970 } else if (IS_CHERRYVIEW(dev)) {
1971 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1972 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1973 *pipe = PORT_TO_PIPE(tmp);
1979 switch (intel_dp->output_reg) {
1981 trans_sel = TRANS_DP_PORT_SEL_B;
1984 trans_sel = TRANS_DP_PORT_SEL_C;
1987 trans_sel = TRANS_DP_PORT_SEL_D;
1993 for_each_pipe(dev_priv, i) {
1994 trans_dp = I915_READ(TRANS_DP_CTL(i));
1995 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
2001 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2002 intel_dp->output_reg);
2008 static void intel_dp_get_config(struct intel_encoder *encoder,
2009 struct intel_crtc_config *pipe_config)
2011 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2013 struct drm_device *dev = encoder->base.dev;
2014 struct drm_i915_private *dev_priv = dev->dev_private;
2015 enum port port = dp_to_dig_port(intel_dp)->port;
2016 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2019 tmp = I915_READ(intel_dp->output_reg);
2020 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
2021 pipe_config->has_audio = true;
2023 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
2024 if (tmp & DP_SYNC_HS_HIGH)
2025 flags |= DRM_MODE_FLAG_PHSYNC;
2027 flags |= DRM_MODE_FLAG_NHSYNC;
2029 if (tmp & DP_SYNC_VS_HIGH)
2030 flags |= DRM_MODE_FLAG_PVSYNC;
2032 flags |= DRM_MODE_FLAG_NVSYNC;
2034 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2035 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2036 flags |= DRM_MODE_FLAG_PHSYNC;
2038 flags |= DRM_MODE_FLAG_NHSYNC;
2040 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2041 flags |= DRM_MODE_FLAG_PVSYNC;
2043 flags |= DRM_MODE_FLAG_NVSYNC;
2046 pipe_config->adjusted_mode.flags |= flags;
2048 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2049 tmp & DP_COLOR_RANGE_16_235)
2050 pipe_config->limited_color_range = true;
2052 pipe_config->has_dp_encoder = true;
2054 intel_dp_get_m_n(crtc, pipe_config);
2056 if (port == PORT_A) {
2057 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2058 pipe_config->port_clock = 162000;
2060 pipe_config->port_clock = 270000;
2063 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2064 &pipe_config->dp_m_n);
2066 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2067 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2069 pipe_config->adjusted_mode.crtc_clock = dotclock;
2071 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2072 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2074 * This is a big fat ugly hack.
2076 * Some machines in UEFI boot mode provide us a VBT that has 18
2077 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2078 * unknown we fail to light up. Yet the same BIOS boots up with
2079 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2080 * max, not what it tells us to use.
2082 * Note: This will still be broken if the eDP panel is not lit
2083 * up by the BIOS, and thus we can't get the mode at module
2086 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2087 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2088 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2092 static bool is_edp_psr(struct intel_dp *intel_dp)
2094 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2097 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
2099 struct drm_i915_private *dev_priv = dev->dev_private;
2104 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2107 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
2108 struct edp_vsc_psr *vsc_psr)
2110 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2111 struct drm_device *dev = dig_port->base.base.dev;
2112 struct drm_i915_private *dev_priv = dev->dev_private;
2113 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
2114 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
2115 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
2116 uint32_t *data = (uint32_t *) vsc_psr;
2119 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2120 the video DIP being updated before program video DIP data buffer
2121 registers for DIP being updated. */
2122 I915_WRITE(ctl_reg, 0);
2123 POSTING_READ(ctl_reg);
2125 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
2126 if (i < sizeof(struct edp_vsc_psr))
2127 I915_WRITE(data_reg + i, *data++);
2129 I915_WRITE(data_reg + i, 0);
2132 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
2133 POSTING_READ(ctl_reg);
2136 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
2138 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2139 struct drm_i915_private *dev_priv = dev->dev_private;
2140 struct edp_vsc_psr psr_vsc;
2142 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2143 memset(&psr_vsc, 0, sizeof(psr_vsc));
2144 psr_vsc.sdp_header.HB0 = 0;
2145 psr_vsc.sdp_header.HB1 = 0x7;
2146 psr_vsc.sdp_header.HB2 = 0x2;
2147 psr_vsc.sdp_header.HB3 = 0x8;
2148 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2150 /* Avoid continuous PSR exit by masking memup and hpd */
2151 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
2152 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2155 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2157 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2158 struct drm_device *dev = dig_port->base.base.dev;
2159 struct drm_i915_private *dev_priv = dev->dev_private;
2160 uint32_t aux_clock_divider;
2161 int precharge = 0x3;
2162 int msg_size = 5; /* Header(4) + Message(1) */
2163 bool only_standby = false;
2165 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2167 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2168 only_standby = true;
2170 /* Enable PSR in sink */
2171 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
2172 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2173 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2175 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2176 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2178 /* Setup AUX registers */
2179 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
2180 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
2181 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2182 DP_AUX_CH_CTL_TIME_OUT_400us |
2183 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2184 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2185 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2188 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2190 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2191 struct drm_device *dev = dig_port->base.base.dev;
2192 struct drm_i915_private *dev_priv = dev->dev_private;
2193 uint32_t max_sleep_time = 0x1f;
2194 uint32_t idle_frames = 1;
2196 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2197 bool only_standby = false;
2199 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2200 only_standby = true;
2202 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2203 val |= EDP_PSR_LINK_STANDBY;
2204 val |= EDP_PSR_TP2_TP3_TIME_0us;
2205 val |= EDP_PSR_TP1_TIME_0us;
2206 val |= EDP_PSR_SKIP_AUX_EXIT;
2207 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2209 val |= EDP_PSR_LINK_DISABLE;
2211 I915_WRITE(EDP_PSR_CTL(dev), val |
2212 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2213 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2214 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2218 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2220 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2221 struct drm_device *dev = dig_port->base.base.dev;
2222 struct drm_i915_private *dev_priv = dev->dev_private;
2223 struct drm_crtc *crtc = dig_port->base.base.crtc;
2224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2227 lockdep_assert_held(&dev_priv->psr.lock);
2229 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2230 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2232 dev_priv->psr.source_ok = false;
2234 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
2235 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
2239 if (!i915.enable_psr) {
2240 DRM_DEBUG_KMS("PSR disable by flag\n");
2244 /* Below limitations aren't valid for Broadwell */
2245 if (IS_BROADWELL(dev))
2248 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2250 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
2254 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2255 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
2260 dev_priv->psr.source_ok = true;
2264 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2266 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2267 struct drm_device *dev = intel_dig_port->base.base.dev;
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2270 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2271 WARN_ON(dev_priv->psr.active);
2273 lockdep_assert_held(&dev_priv->psr.lock);
2276 /* Enable PSR on the panel */
2277 intel_edp_psr_enable_sink(intel_dp);
2279 /* Enable PSR on the host */
2280 intel_edp_psr_enable_source(intel_dp);
2282 dev_priv->psr.active = true;
2285 void intel_edp_psr_enable(struct intel_dp *intel_dp)
2287 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2288 struct drm_i915_private *dev_priv = dev->dev_private;
2290 if (!HAS_PSR(dev)) {
2291 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2295 if (!is_edp_psr(intel_dp)) {
2296 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2300 mutex_lock(&dev_priv->psr.lock);
2301 if (dev_priv->psr.enabled) {
2302 DRM_DEBUG_KMS("PSR already in use\n");
2303 mutex_unlock(&dev_priv->psr.lock);
2307 dev_priv->psr.busy_frontbuffer_bits = 0;
2309 /* Setup PSR once */
2310 intel_edp_psr_setup(intel_dp);
2312 if (intel_edp_psr_match_conditions(intel_dp))
2313 dev_priv->psr.enabled = intel_dp;
2314 mutex_unlock(&dev_priv->psr.lock);
2317 void intel_edp_psr_disable(struct intel_dp *intel_dp)
2319 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2320 struct drm_i915_private *dev_priv = dev->dev_private;
2322 mutex_lock(&dev_priv->psr.lock);
2323 if (!dev_priv->psr.enabled) {
2324 mutex_unlock(&dev_priv->psr.lock);
2328 if (dev_priv->psr.active) {
2329 I915_WRITE(EDP_PSR_CTL(dev),
2330 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2332 /* Wait till PSR is idle */
2333 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2334 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2335 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2337 dev_priv->psr.active = false;
2339 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2342 dev_priv->psr.enabled = NULL;
2343 mutex_unlock(&dev_priv->psr.lock);
2345 cancel_delayed_work_sync(&dev_priv->psr.work);
2348 static void intel_edp_psr_work(struct work_struct *work)
2350 struct drm_i915_private *dev_priv =
2351 container_of(work, typeof(*dev_priv), psr.work.work);
2352 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2354 mutex_lock(&dev_priv->psr.lock);
2355 intel_dp = dev_priv->psr.enabled;
2361 * The delayed work can race with an invalidate hence we need to
2362 * recheck. Since psr_flush first clears this and then reschedules we
2363 * won't ever miss a flush when bailing out here.
2365 if (dev_priv->psr.busy_frontbuffer_bits)
2368 intel_edp_psr_do_enable(intel_dp);
2370 mutex_unlock(&dev_priv->psr.lock);
2373 static void intel_edp_psr_do_exit(struct drm_device *dev)
2375 struct drm_i915_private *dev_priv = dev->dev_private;
2377 if (dev_priv->psr.active) {
2378 u32 val = I915_READ(EDP_PSR_CTL(dev));
2380 WARN_ON(!(val & EDP_PSR_ENABLE));
2382 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2384 dev_priv->psr.active = false;
2389 void intel_edp_psr_invalidate(struct drm_device *dev,
2390 unsigned frontbuffer_bits)
2392 struct drm_i915_private *dev_priv = dev->dev_private;
2393 struct drm_crtc *crtc;
2394 enum i915_pipe pipe;
2396 mutex_lock(&dev_priv->psr.lock);
2397 if (!dev_priv->psr.enabled) {
2398 mutex_unlock(&dev_priv->psr.lock);
2402 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2403 pipe = to_intel_crtc(crtc)->pipe;
2405 intel_edp_psr_do_exit(dev);
2407 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2409 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2410 mutex_unlock(&dev_priv->psr.lock);
2413 void intel_edp_psr_flush(struct drm_device *dev,
2414 unsigned frontbuffer_bits)
2416 struct drm_i915_private *dev_priv = dev->dev_private;
2417 struct drm_crtc *crtc;
2418 enum i915_pipe pipe;
2420 mutex_lock(&dev_priv->psr.lock);
2421 if (!dev_priv->psr.enabled) {
2422 mutex_unlock(&dev_priv->psr.lock);
2426 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2427 pipe = to_intel_crtc(crtc)->pipe;
2428 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2431 * On Haswell sprite plane updates don't result in a psr invalidating
2432 * signal in the hardware. Which means we need to manually fake this in
2433 * software for all flushes, not just when we've seen a preceding
2434 * invalidation through frontbuffer rendering.
2436 if (IS_HASWELL(dev) &&
2437 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2438 intel_edp_psr_do_exit(dev);
2440 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2441 schedule_delayed_work(&dev_priv->psr.work,
2442 msecs_to_jiffies(100));
2443 mutex_unlock(&dev_priv->psr.lock);
2446 void intel_edp_psr_init(struct drm_device *dev)
2448 struct drm_i915_private *dev_priv = dev->dev_private;
2450 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
2451 lockinit(&dev_priv->psr.lock, "i915dpl", 0, LK_CANRECURSE);
2454 static void intel_disable_dp(struct intel_encoder *encoder)
2456 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2457 struct drm_device *dev = encoder->base.dev;
2459 /* Make sure the panel is off before trying to change the mode. But also
2460 * ensure that we have vdd while we switch off the panel. */
2461 intel_edp_panel_vdd_on(intel_dp);
2462 intel_edp_backlight_off(intel_dp);
2463 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2464 intel_edp_panel_off(intel_dp);
2466 /* disable the port before the pipe on g4x */
2467 if (INTEL_INFO(dev)->gen < 5)
2468 intel_dp_link_down(intel_dp);
2471 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2473 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2474 enum port port = dp_to_dig_port(intel_dp)->port;
2476 intel_dp_link_down(intel_dp);
2478 ironlake_edp_pll_off(intel_dp);
2481 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2483 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2485 intel_dp_link_down(intel_dp);
2488 static void chv_post_disable_dp(struct intel_encoder *encoder)
2490 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2491 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2492 struct drm_device *dev = encoder->base.dev;
2493 struct drm_i915_private *dev_priv = dev->dev_private;
2494 struct intel_crtc *intel_crtc =
2495 to_intel_crtc(encoder->base.crtc);
2496 enum dpio_channel ch = vlv_dport_to_channel(dport);
2497 enum i915_pipe pipe = intel_crtc->pipe;
2500 intel_dp_link_down(intel_dp);
2502 mutex_lock(&dev_priv->dpio_lock);
2504 /* Propagate soft reset to data lane reset */
2505 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2506 val |= CHV_PCS_REQ_SOFTRESET_EN;
2507 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2509 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2510 val |= CHV_PCS_REQ_SOFTRESET_EN;
2511 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2513 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2514 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2515 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2517 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2518 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2519 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2521 mutex_unlock(&dev_priv->dpio_lock);
2525 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2527 uint8_t dp_train_pat)
2529 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2530 struct drm_device *dev = intel_dig_port->base.base.dev;
2531 struct drm_i915_private *dev_priv = dev->dev_private;
2532 enum port port = intel_dig_port->port;
2535 uint32_t temp = I915_READ(DP_TP_CTL(port));
2537 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2538 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2540 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2542 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2543 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2544 case DP_TRAINING_PATTERN_DISABLE:
2545 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2548 case DP_TRAINING_PATTERN_1:
2549 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2551 case DP_TRAINING_PATTERN_2:
2552 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2554 case DP_TRAINING_PATTERN_3:
2555 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2558 I915_WRITE(DP_TP_CTL(port), temp);
2560 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2561 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2563 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2564 case DP_TRAINING_PATTERN_DISABLE:
2565 *DP |= DP_LINK_TRAIN_OFF_CPT;
2567 case DP_TRAINING_PATTERN_1:
2568 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2570 case DP_TRAINING_PATTERN_2:
2571 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2573 case DP_TRAINING_PATTERN_3:
2574 DRM_ERROR("DP training pattern 3 not supported\n");
2575 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2580 if (IS_CHERRYVIEW(dev))
2581 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2583 *DP &= ~DP_LINK_TRAIN_MASK;
2585 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2586 case DP_TRAINING_PATTERN_DISABLE:
2587 *DP |= DP_LINK_TRAIN_OFF;
2589 case DP_TRAINING_PATTERN_1:
2590 *DP |= DP_LINK_TRAIN_PAT_1;
2592 case DP_TRAINING_PATTERN_2:
2593 *DP |= DP_LINK_TRAIN_PAT_2;
2595 case DP_TRAINING_PATTERN_3:
2596 if (IS_CHERRYVIEW(dev)) {
2597 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2599 DRM_ERROR("DP training pattern 3 not supported\n");
2600 *DP |= DP_LINK_TRAIN_PAT_2;
2607 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2609 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2610 struct drm_i915_private *dev_priv = dev->dev_private;
2612 intel_dp->DP |= DP_PORT_EN;
2614 /* enable with pattern 1 (as per spec) */
2615 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2616 DP_TRAINING_PATTERN_1);
2618 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2619 POSTING_READ(intel_dp->output_reg);
2622 static void intel_enable_dp(struct intel_encoder *encoder)
2624 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2625 struct drm_device *dev = encoder->base.dev;
2626 struct drm_i915_private *dev_priv = dev->dev_private;
2627 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2629 if (WARN_ON(dp_reg & DP_PORT_EN))
2632 intel_dp_enable_port(intel_dp);
2633 intel_edp_panel_vdd_on(intel_dp);
2634 intel_edp_panel_on(intel_dp);
2635 intel_edp_panel_vdd_off(intel_dp, true);
2636 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2637 intel_dp_start_link_train(intel_dp);
2638 intel_dp_complete_link_train(intel_dp);
2639 intel_dp_stop_link_train(intel_dp);
2642 static void g4x_enable_dp(struct intel_encoder *encoder)
2644 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2646 intel_enable_dp(encoder);
2647 intel_edp_backlight_on(intel_dp);
2650 static void vlv_enable_dp(struct intel_encoder *encoder)
2652 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2654 intel_edp_backlight_on(intel_dp);
2657 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2659 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2660 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2662 intel_dp_prepare(encoder);
2664 /* Only ilk+ has port A */
2665 if (dport->port == PORT_A) {
2666 ironlake_set_pll_cpu_edp(intel_dp);
2667 ironlake_edp_pll_on(intel_dp);
2671 static void vlv_steal_power_sequencer(struct drm_device *dev,
2672 enum i915_pipe pipe)
2674 struct drm_i915_private *dev_priv = dev->dev_private;
2675 struct intel_encoder *encoder;
2677 lockdep_assert_held(&dev_priv->pps_mutex);
2679 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2681 struct intel_dp *intel_dp;
2684 if (encoder->type != INTEL_OUTPUT_EDP)
2687 intel_dp = enc_to_intel_dp(&encoder->base);
2688 port = dp_to_dig_port(intel_dp)->port;
2690 if (intel_dp->pps_pipe != pipe)
2693 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2694 pipe_name(pipe), port_name(port));
2696 /* make sure vdd is off before we steal it */
2697 edp_panel_vdd_off_sync(intel_dp);
2699 intel_dp->pps_pipe = INVALID_PIPE;
2703 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2705 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2706 struct intel_encoder *encoder = &intel_dig_port->base;
2707 struct drm_device *dev = encoder->base.dev;
2708 struct drm_i915_private *dev_priv = dev->dev_private;
2709 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2710 struct edp_power_seq power_seq;
2712 lockdep_assert_held(&dev_priv->pps_mutex);
2714 if (intel_dp->pps_pipe == crtc->pipe)
2718 * If another power sequencer was being used on this
2719 * port previously make sure to turn off vdd there while
2720 * we still have control of it.
2722 if (intel_dp->pps_pipe != INVALID_PIPE)
2723 edp_panel_vdd_off_sync(intel_dp);
2726 * We may be stealing the power
2727 * sequencer from another port.
2729 vlv_steal_power_sequencer(dev, crtc->pipe);
2731 /* now it's all ours */
2732 intel_dp->pps_pipe = crtc->pipe;
2734 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2735 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2737 /* init power sequencer on this pipe and port */
2738 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2739 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2743 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2745 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2746 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2747 struct drm_device *dev = encoder->base.dev;
2748 struct drm_i915_private *dev_priv = dev->dev_private;
2749 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2750 enum dpio_channel port = vlv_dport_to_channel(dport);
2751 int pipe = intel_crtc->pipe;
2754 mutex_lock(&dev_priv->dpio_lock);
2756 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2763 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2764 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2765 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2767 mutex_unlock(&dev_priv->dpio_lock);
2769 if (is_edp(intel_dp)) {
2771 vlv_init_panel_power_sequencer(intel_dp);
2772 pps_unlock(intel_dp);
2775 intel_enable_dp(encoder);
2777 vlv_wait_port_ready(dev_priv, dport);
2780 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2782 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2783 struct drm_device *dev = encoder->base.dev;
2784 struct drm_i915_private *dev_priv = dev->dev_private;
2785 struct intel_crtc *intel_crtc =
2786 to_intel_crtc(encoder->base.crtc);
2787 enum dpio_channel port = vlv_dport_to_channel(dport);
2788 int pipe = intel_crtc->pipe;
2790 intel_dp_prepare(encoder);
2792 /* Program Tx lane resets to default */
2793 mutex_lock(&dev_priv->dpio_lock);
2794 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2795 DPIO_PCS_TX_LANE2_RESET |
2796 DPIO_PCS_TX_LANE1_RESET);
2797 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2798 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2799 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2800 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2801 DPIO_PCS_CLK_SOFT_RESET);
2803 /* Fix up inter-pair skew failure */
2804 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2805 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2806 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2807 mutex_unlock(&dev_priv->dpio_lock);
2810 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2812 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2813 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2814 struct drm_device *dev = encoder->base.dev;
2815 struct drm_i915_private *dev_priv = dev->dev_private;
2816 struct intel_crtc *intel_crtc =
2817 to_intel_crtc(encoder->base.crtc);
2818 enum dpio_channel ch = vlv_dport_to_channel(dport);
2819 int pipe = intel_crtc->pipe;
2823 mutex_lock(&dev_priv->dpio_lock);
2825 /* Deassert soft data lane reset*/
2826 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2827 val |= CHV_PCS_REQ_SOFTRESET_EN;
2828 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2830 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2831 val |= CHV_PCS_REQ_SOFTRESET_EN;
2832 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2834 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2835 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2836 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2838 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2839 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2840 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2842 /* Program Tx lane latency optimal setting*/
2843 for (i = 0; i < 4; i++) {
2844 /* Set the latency optimal bit */
2845 data = (i == 1) ? 0x0 : 0x6;
2846 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2847 data << DPIO_FRC_LATENCY_SHFIT);
2849 /* Set the upar bit */
2850 data = (i == 1) ? 0x0 : 0x1;
2851 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2852 data << DPIO_UPAR_SHIFT);
2855 /* Data lane stagger programming */
2856 /* FIXME: Fix up value only after power analysis */
2858 mutex_unlock(&dev_priv->dpio_lock);
2860 if (is_edp(intel_dp)) {
2862 vlv_init_panel_power_sequencer(intel_dp);
2863 pps_unlock(intel_dp);
2866 intel_enable_dp(encoder);
2868 vlv_wait_port_ready(dev_priv, dport);
2871 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2873 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2874 struct drm_device *dev = encoder->base.dev;
2875 struct drm_i915_private *dev_priv = dev->dev_private;
2876 struct intel_crtc *intel_crtc =
2877 to_intel_crtc(encoder->base.crtc);
2878 enum dpio_channel ch = vlv_dport_to_channel(dport);
2879 enum i915_pipe pipe = intel_crtc->pipe;
2882 mutex_lock(&dev_priv->dpio_lock);
2884 /* program left/right clock distribution */
2885 if (pipe != PIPE_B) {
2886 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2887 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2889 val |= CHV_BUFLEFTENA1_FORCE;
2891 val |= CHV_BUFRIGHTENA1_FORCE;
2892 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2894 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2895 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2897 val |= CHV_BUFLEFTENA2_FORCE;
2899 val |= CHV_BUFRIGHTENA2_FORCE;
2900 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2903 /* program clock channel usage */
2904 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2905 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2907 val &= ~CHV_PCS_USEDCLKCHANNEL;
2909 val |= CHV_PCS_USEDCLKCHANNEL;
2910 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2912 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2913 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2915 val &= ~CHV_PCS_USEDCLKCHANNEL;
2917 val |= CHV_PCS_USEDCLKCHANNEL;
2918 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2921 * This a a bit weird since generally CL
2922 * matches the pipe, but here we need to
2923 * pick the CL based on the port.
2925 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2927 val &= ~CHV_CMN_USEDCLKCHANNEL;
2929 val |= CHV_CMN_USEDCLKCHANNEL;
2930 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2932 mutex_unlock(&dev_priv->dpio_lock);
2936 * Native read with retry for link status and receiver capability reads for
2937 * cases where the sink may still be asleep.
2939 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2940 * supposed to retry 3 times per the spec.
2943 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2944 void *buffer, size_t size)
2950 * Sometime we just get the same incorrect byte repeated
2951 * over the entire buffer. Doing just one throw away read
2952 * initially seems to "solve" it.
2954 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2956 for (i = 0; i < 3; i++) {
2957 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2967 * Fetch AUX CH registers 0x202 - 0x207 which contain
2968 * link status information
2971 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2973 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2976 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2979 /* These are source-specific values. */
2981 intel_dp_voltage_max(struct intel_dp *intel_dp)
2983 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2984 enum port port = dp_to_dig_port(intel_dp)->port;
2986 if (IS_VALLEYVIEW(dev))
2987 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2988 else if (IS_GEN7(dev) && port == PORT_A)
2989 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2990 else if (HAS_PCH_CPT(dev) && port != PORT_A)
2991 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2993 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2997 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2999 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3000 enum port port = dp_to_dig_port(intel_dp)->port;
3002 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3003 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3004 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3005 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3006 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3007 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3008 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3009 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3010 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3012 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3014 } else if (IS_VALLEYVIEW(dev)) {
3015 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3016 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3017 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3018 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3019 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3020 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3021 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3024 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3026 } else if (IS_GEN7(dev) && port == PORT_A) {
3027 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3028 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3029 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3030 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3032 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3034 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3037 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3038 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3039 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3040 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3041 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3042 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3043 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3044 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3046 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3051 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
3053 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3054 struct drm_i915_private *dev_priv = dev->dev_private;
3055 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3056 struct intel_crtc *intel_crtc =
3057 to_intel_crtc(dport->base.base.crtc);
3058 unsigned long demph_reg_value, preemph_reg_value,
3059 uniqtranscale_reg_value;
3060 uint8_t train_set = intel_dp->train_set[0];
3061 enum dpio_channel port = vlv_dport_to_channel(dport);
3062 int pipe = intel_crtc->pipe;
3064 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3065 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3066 preemph_reg_value = 0x0004000;
3067 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3068 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3069 demph_reg_value = 0x2B405555;
3070 uniqtranscale_reg_value = 0x552AB83A;
3072 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3073 demph_reg_value = 0x2B404040;
3074 uniqtranscale_reg_value = 0x5548B83A;
3076 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3077 demph_reg_value = 0x2B245555;
3078 uniqtranscale_reg_value = 0x5560B83A;
3080 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3081 demph_reg_value = 0x2B405555;
3082 uniqtranscale_reg_value = 0x5598DA3A;
3088 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3089 preemph_reg_value = 0x0002000;
3090 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3092 demph_reg_value = 0x2B404040;
3093 uniqtranscale_reg_value = 0x5552B83A;
3095 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3096 demph_reg_value = 0x2B404848;
3097 uniqtranscale_reg_value = 0x5580B83A;
3099 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3100 demph_reg_value = 0x2B404040;
3101 uniqtranscale_reg_value = 0x55ADDA3A;
3107 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3108 preemph_reg_value = 0x0000000;
3109 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3110 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3111 demph_reg_value = 0x2B305555;
3112 uniqtranscale_reg_value = 0x5570B83A;
3114 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3115 demph_reg_value = 0x2B2B4040;
3116 uniqtranscale_reg_value = 0x55ADDA3A;
3122 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3123 preemph_reg_value = 0x0006000;
3124 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3125 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3126 demph_reg_value = 0x1B405555;
3127 uniqtranscale_reg_value = 0x55ADDA3A;
3137 mutex_lock(&dev_priv->dpio_lock);
3138 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3139 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3140 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3141 uniqtranscale_reg_value);
3142 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3143 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3144 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3145 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
3146 mutex_unlock(&dev_priv->dpio_lock);
3151 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3153 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3154 struct drm_i915_private *dev_priv = dev->dev_private;
3155 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3156 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3157 u32 deemph_reg_value, margin_reg_value, val;
3158 uint8_t train_set = intel_dp->train_set[0];
3159 enum dpio_channel ch = vlv_dport_to_channel(dport);
3160 enum i915_pipe pipe = intel_crtc->pipe;
3163 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3164 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3165 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3166 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3167 deemph_reg_value = 128;
3168 margin_reg_value = 52;
3170 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3171 deemph_reg_value = 128;
3172 margin_reg_value = 77;
3174 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3175 deemph_reg_value = 128;
3176 margin_reg_value = 102;
3178 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3179 deemph_reg_value = 128;
3180 margin_reg_value = 154;
3181 /* FIXME extra to set for 1200 */
3187 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3188 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3190 deemph_reg_value = 85;
3191 margin_reg_value = 78;
3193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3194 deemph_reg_value = 85;
3195 margin_reg_value = 116;
3197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3198 deemph_reg_value = 85;
3199 margin_reg_value = 154;
3205 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3206 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3208 deemph_reg_value = 64;
3209 margin_reg_value = 104;
3211 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3212 deemph_reg_value = 64;
3213 margin_reg_value = 154;
3219 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3220 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3221 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3222 deemph_reg_value = 43;
3223 margin_reg_value = 154;
3233 mutex_lock(&dev_priv->dpio_lock);
3235 /* Clear calc init */
3236 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3237 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3238 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3240 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3241 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3242 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3244 /* Program swing deemph */
3245 for (i = 0; i < 4; i++) {
3246 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3247 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3248 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3249 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3252 /* Program swing margin */
3253 for (i = 0; i < 4; i++) {
3254 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3255 val &= ~DPIO_SWING_MARGIN000_MASK;
3256 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3257 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3260 /* Disable unique transition scale */
3261 for (i = 0; i < 4; i++) {
3262 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3263 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3264 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3267 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
3268 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
3269 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
3270 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
3273 * The document said it needs to set bit 27 for ch0 and bit 26
3274 * for ch1. Might be a typo in the doc.
3275 * For now, for this unique transition scale selection, set bit
3276 * 27 for ch0 and ch1.
3278 for (i = 0; i < 4; i++) {
3279 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3280 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3281 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3284 for (i = 0; i < 4; i++) {
3285 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3286 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3287 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3288 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3292 /* Start swing calculation */
3293 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3294 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3295 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3297 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3298 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3299 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3302 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3303 val |= DPIO_LRC_BYPASS;
3304 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3306 mutex_unlock(&dev_priv->dpio_lock);
3312 intel_get_adjust_train(struct intel_dp *intel_dp,
3313 const uint8_t link_status[DP_LINK_STATUS_SIZE])
3318 uint8_t voltage_max;
3319 uint8_t preemph_max;
3321 for (lane = 0; lane < intel_dp->lane_count; lane++) {
3322 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3323 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
3331 voltage_max = intel_dp_voltage_max(intel_dp);
3332 if (v >= voltage_max)
3333 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
3335 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3336 if (p >= preemph_max)
3337 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
3339 for (lane = 0; lane < 4; lane++)
3340 intel_dp->train_set[lane] = v | p;
3344 intel_gen4_signal_levels(uint8_t train_set)
3346 uint32_t signal_levels = 0;
3348 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3349 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3351 signal_levels |= DP_VOLTAGE_0_4;
3353 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3354 signal_levels |= DP_VOLTAGE_0_6;
3356 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3357 signal_levels |= DP_VOLTAGE_0_8;
3359 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3360 signal_levels |= DP_VOLTAGE_1_2;
3363 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3364 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3366 signal_levels |= DP_PRE_EMPHASIS_0;
3368 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3369 signal_levels |= DP_PRE_EMPHASIS_3_5;
3371 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3372 signal_levels |= DP_PRE_EMPHASIS_6;
3374 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3375 signal_levels |= DP_PRE_EMPHASIS_9_5;
3378 return signal_levels;
3381 /* Gen6's DP voltage swing and pre-emphasis control */
3383 intel_gen6_edp_signal_levels(uint8_t train_set)
3385 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3386 DP_TRAIN_PRE_EMPHASIS_MASK);
3387 switch (signal_levels) {
3388 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3389 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3390 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3391 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3392 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3393 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3394 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3395 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3396 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3397 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3398 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3399 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3400 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3401 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3403 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3404 "0x%x\n", signal_levels);
3405 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3409 /* Gen7's DP voltage swing and pre-emphasis control */
3411 intel_gen7_edp_signal_levels(uint8_t train_set)
3413 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3414 DP_TRAIN_PRE_EMPHASIS_MASK);
3415 switch (signal_levels) {
3416 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3417 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3418 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3419 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3420 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3421 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3423 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3424 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3425 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3426 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3428 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3429 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3430 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3431 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3434 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3435 "0x%x\n", signal_levels);
3436 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3440 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3442 intel_hsw_signal_levels(uint8_t train_set)
3444 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3445 DP_TRAIN_PRE_EMPHASIS_MASK);
3446 switch (signal_levels) {
3447 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3448 return DDI_BUF_TRANS_SELECT(0);
3449 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3450 return DDI_BUF_TRANS_SELECT(1);
3451 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3452 return DDI_BUF_TRANS_SELECT(2);
3453 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
3454 return DDI_BUF_TRANS_SELECT(3);
3456 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3457 return DDI_BUF_TRANS_SELECT(4);
3458 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3459 return DDI_BUF_TRANS_SELECT(5);
3460 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3461 return DDI_BUF_TRANS_SELECT(6);
3463 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3464 return DDI_BUF_TRANS_SELECT(7);
3465 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3466 return DDI_BUF_TRANS_SELECT(8);
3468 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3469 "0x%x\n", signal_levels);
3470 return DDI_BUF_TRANS_SELECT(0);
3474 /* Properly updates "DP" with the correct signal levels. */
3476 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3478 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3479 enum port port = intel_dig_port->port;
3480 struct drm_device *dev = intel_dig_port->base.base.dev;
3481 uint32_t signal_levels, mask;
3482 uint8_t train_set = intel_dp->train_set[0];
3484 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3485 signal_levels = intel_hsw_signal_levels(train_set);
3486 mask = DDI_BUF_EMP_MASK;
3487 } else if (IS_CHERRYVIEW(dev)) {
3488 signal_levels = intel_chv_signal_levels(intel_dp);
3490 } else if (IS_VALLEYVIEW(dev)) {
3491 signal_levels = intel_vlv_signal_levels(intel_dp);
3493 } else if (IS_GEN7(dev) && port == PORT_A) {
3494 signal_levels = intel_gen7_edp_signal_levels(train_set);
3495 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3496 } else if (IS_GEN6(dev) && port == PORT_A) {
3497 signal_levels = intel_gen6_edp_signal_levels(train_set);
3498 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3500 signal_levels = intel_gen4_signal_levels(train_set);
3501 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3504 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3506 *DP = (*DP & ~mask) | signal_levels;
3510 intel_dp_set_link_train(struct intel_dp *intel_dp,
3512 uint8_t dp_train_pat)
3514 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3515 struct drm_device *dev = intel_dig_port->base.base.dev;
3516 struct drm_i915_private *dev_priv = dev->dev_private;
3517 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3520 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3522 I915_WRITE(intel_dp->output_reg, *DP);
3523 POSTING_READ(intel_dp->output_reg);
3525 buf[0] = dp_train_pat;
3526 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3527 DP_TRAINING_PATTERN_DISABLE) {
3528 /* don't write DP_TRAINING_LANEx_SET on disable */
3531 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3532 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3533 len = intel_dp->lane_count + 1;
3536 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3543 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3544 uint8_t dp_train_pat)
3546 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3547 intel_dp_set_signal_levels(intel_dp, DP);
3548 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3552 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3553 const uint8_t link_status[DP_LINK_STATUS_SIZE])
3555 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3556 struct drm_device *dev = intel_dig_port->base.base.dev;
3557 struct drm_i915_private *dev_priv = dev->dev_private;
3560 intel_get_adjust_train(intel_dp, link_status);
3561 intel_dp_set_signal_levels(intel_dp, DP);
3563 I915_WRITE(intel_dp->output_reg, *DP);
3564 POSTING_READ(intel_dp->output_reg);
3566 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3567 intel_dp->train_set, intel_dp->lane_count);
3569 return ret == intel_dp->lane_count;
3572 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3574 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3575 struct drm_device *dev = intel_dig_port->base.base.dev;
3576 struct drm_i915_private *dev_priv = dev->dev_private;
3577 enum port port = intel_dig_port->port;
3583 val = I915_READ(DP_TP_CTL(port));
3584 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3585 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3586 I915_WRITE(DP_TP_CTL(port), val);
3589 * On PORT_A we can have only eDP in SST mode. There the only reason
3590 * we need to set idle transmission mode is to work around a HW issue
3591 * where we enable the pipe while not in idle link-training mode.
3592 * In this case there is requirement to wait for a minimum number of
3593 * idle patterns to be sent.
3598 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3600 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3603 /* Enable corresponding port and start training pattern 1 */
3605 intel_dp_start_link_train(struct intel_dp *intel_dp)
3607 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3608 struct drm_device *dev = encoder->dev;
3611 int voltage_tries, loop_tries;
3612 uint32_t DP = intel_dp->DP;
3613 uint8_t link_config[2];
3616 intel_ddi_prepare_link_retrain(encoder);
3618 /* Write the link configuration data */
3619 link_config[0] = intel_dp->link_bw;
3620 link_config[1] = intel_dp->lane_count;
3621 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3622 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3623 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3626 link_config[1] = DP_SET_ANSI_8B10B;
3627 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3631 /* clock recovery */
3632 if (!intel_dp_reset_link_train(intel_dp, &DP,
3633 DP_TRAINING_PATTERN_1 |
3634 DP_LINK_SCRAMBLING_DISABLE)) {
3635 DRM_ERROR("failed to enable link training\n");
3643 uint8_t link_status[DP_LINK_STATUS_SIZE];
3645 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3646 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3647 DRM_ERROR("failed to get link status\n");
3651 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3652 DRM_DEBUG_KMS("clock recovery OK\n");
3656 /* Check to see if we've tried the max voltage */
3657 for (i = 0; i < intel_dp->lane_count; i++)
3658 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3660 if (i == intel_dp->lane_count) {
3662 if (loop_tries == 5) {
3663 DRM_ERROR("too many full retries, give up\n");
3666 intel_dp_reset_link_train(intel_dp, &DP,
3667 DP_TRAINING_PATTERN_1 |
3668 DP_LINK_SCRAMBLING_DISABLE);
3673 /* Check to see if we've tried the same voltage 5 times */
3674 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3676 if (voltage_tries == 5) {
3677 DRM_ERROR("too many voltage retries, give up\n");
3682 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3684 /* Update training set as requested by target */
3685 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3686 DRM_ERROR("failed to update link training\n");
3695 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3697 bool channel_eq = false;
3698 int tries, cr_tries;
3699 uint32_t DP = intel_dp->DP;
3700 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3702 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3703 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3704 training_pattern = DP_TRAINING_PATTERN_3;
3706 /* channel equalization */
3707 if (!intel_dp_set_link_train(intel_dp, &DP,
3709 DP_LINK_SCRAMBLING_DISABLE)) {
3710 DRM_ERROR("failed to start channel equalization\n");
3718 uint8_t link_status[DP_LINK_STATUS_SIZE];
3721 DRM_ERROR("failed to train DP, aborting\n");
3725 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3726 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3727 DRM_ERROR("failed to get link status\n");
3731 /* Make sure clock is still ok */
3732 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3733 intel_dp_start_link_train(intel_dp);
3734 intel_dp_set_link_train(intel_dp, &DP,
3736 DP_LINK_SCRAMBLING_DISABLE);
3741 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3746 /* Try 5 times, then try clock recovery if that fails */
3748 intel_dp_link_down(intel_dp);
3749 intel_dp_start_link_train(intel_dp);
3750 intel_dp_set_link_train(intel_dp, &DP,
3752 DP_LINK_SCRAMBLING_DISABLE);
3758 /* Update training set as requested by target */
3759 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3760 DRM_ERROR("failed to update link training\n");
3766 intel_dp_set_idle_link_train(intel_dp);
3771 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3775 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3777 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3778 DP_TRAINING_PATTERN_DISABLE);
3782 intel_dp_link_down(struct intel_dp *intel_dp)
3784 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3785 enum port port = intel_dig_port->port;
3786 struct drm_device *dev = intel_dig_port->base.base.dev;
3787 struct drm_i915_private *dev_priv = dev->dev_private;
3788 struct intel_crtc *intel_crtc =
3789 to_intel_crtc(intel_dig_port->base.base.crtc);
3790 uint32_t DP = intel_dp->DP;
3792 if (WARN_ON(HAS_DDI(dev)))
3795 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3798 DRM_DEBUG_KMS("\n");
3800 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3801 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3802 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3804 if (IS_CHERRYVIEW(dev))
3805 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3807 DP &= ~DP_LINK_TRAIN_MASK;
3808 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3810 POSTING_READ(intel_dp->output_reg);
3812 if (HAS_PCH_IBX(dev) &&
3813 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3814 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3816 /* Hardware workaround: leaving our transcoder select
3817 * set to transcoder B while it's off will prevent the
3818 * corresponding HDMI output on transcoder A.
3820 * Combine this with another hardware workaround:
3821 * transcoder select bit can only be cleared while the
3824 DP &= ~DP_PIPEB_SELECT;
3825 I915_WRITE(intel_dp->output_reg, DP);
3827 /* Changes to enable or select take place the vblank
3828 * after being written.
3830 if (WARN_ON(crtc == NULL)) {
3831 /* We should never try to disable a port without a crtc
3832 * attached. For paranoia keep the code around for a
3834 POSTING_READ(intel_dp->output_reg);
3837 intel_wait_for_vblank(dev, intel_crtc->pipe);
3840 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3841 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3842 POSTING_READ(intel_dp->output_reg);
3843 msleep(intel_dp->panel_power_down_delay);
3847 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3849 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3850 struct drm_device *dev = dig_port->base.base.dev;
3851 struct drm_i915_private *dev_priv = dev->dev_private;
3853 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3854 sizeof(intel_dp->dpcd)) < 0)
3855 return false; /* aux transfer failed */
3857 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3859 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3860 return false; /* DPCD not present */
3862 /* Check if the panel supports PSR */
3863 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3864 if (is_edp(intel_dp)) {
3865 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3867 sizeof(intel_dp->psr_dpcd));
3868 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3869 dev_priv->psr.sink_support = true;
3870 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3874 /* Training Pattern 3 support, both source and sink */
3875 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3876 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3877 (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
3878 intel_dp->use_tps3 = true;
3879 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3881 intel_dp->use_tps3 = false;
3883 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3884 DP_DWN_STRM_PORT_PRESENT))
3885 return true; /* native DP sink */
3887 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3888 return true; /* no per-port downstream info */
3890 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3891 intel_dp->downstream_ports,
3892 DP_MAX_DOWNSTREAM_PORTS) < 0)
3893 return false; /* downstream port status fetch failed */
3899 intel_dp_probe_oui(struct intel_dp *intel_dp)
3903 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3906 intel_edp_panel_vdd_on(intel_dp);
3908 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3909 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3910 buf[0], buf[1], buf[2]);
3912 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3913 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3914 buf[0], buf[1], buf[2]);
3916 intel_edp_panel_vdd_off(intel_dp, false);
3919 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3921 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3922 struct drm_device *dev = intel_dig_port->base.base.dev;
3923 struct intel_crtc *intel_crtc =
3924 to_intel_crtc(intel_dig_port->base.base.crtc);
3927 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
3930 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3933 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3934 DP_TEST_SINK_START) < 0)
3937 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3938 intel_wait_for_vblank(dev, intel_crtc->pipe);
3939 intel_wait_for_vblank(dev, intel_crtc->pipe);
3941 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3944 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
3949 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3951 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3952 DP_DEVICE_SERVICE_IRQ_VECTOR,
3953 sink_irq_vector, 1) == 1;
3957 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3959 /* NAK by default */
3960 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3964 * According to DP spec
3967 * 2. Configure link according to Receiver Capabilities
3968 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3969 * 4. Check link status on receipt of hot-plug interrupt
3972 intel_dp_check_link_status(struct intel_dp *intel_dp)
3974 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3975 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3977 u8 link_status[DP_LINK_STATUS_SIZE];
3979 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3981 if (!intel_encoder->connectors_active)
3984 if (WARN_ON(!intel_encoder->base.crtc))
3987 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3990 /* Try to read receiver status if the link appears to be up */
3991 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3995 /* Now read the DPCD to see if it's actually running */
3996 if (!intel_dp_get_dpcd(intel_dp)) {
4000 /* Try to read the source of the interrupt */
4001 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4002 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4003 /* Clear interrupt source */
4004 drm_dp_dpcd_writeb(&intel_dp->aux,
4005 DP_DEVICE_SERVICE_IRQ_VECTOR,
4008 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4009 intel_dp_handle_test_request(intel_dp);
4010 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4011 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4014 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4015 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4016 intel_encoder->base.name);
4017 intel_dp_start_link_train(intel_dp);
4018 intel_dp_complete_link_train(intel_dp);
4019 intel_dp_stop_link_train(intel_dp);
4023 /* XXX this is probably wrong for multiple downstream ports */
4024 static enum drm_connector_status
4025 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4027 uint8_t *dpcd = intel_dp->dpcd;
4030 if (!intel_dp_get_dpcd(intel_dp))
4031 return connector_status_disconnected;
4033 /* if there's no downstream port, we're done */
4034 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4035 return connector_status_connected;
4037 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4038 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4039 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4042 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4044 return connector_status_unknown;
4046 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4047 : connector_status_disconnected;
4050 /* If no HPD, poke DDC gently */
4051 if (drm_probe_ddc(intel_dp->aux.ddc))
4052 return connector_status_connected;
4054 /* Well we tried, say unknown for unreliable port types */
4055 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4056 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4057 if (type == DP_DS_PORT_TYPE_VGA ||
4058 type == DP_DS_PORT_TYPE_NON_EDID)
4059 return connector_status_unknown;
4061 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4062 DP_DWN_STRM_PORT_TYPE_MASK;
4063 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4064 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4065 return connector_status_unknown;
4068 /* Anything else is out of spec, warn and ignore */
4069 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4070 return connector_status_disconnected;
4073 static enum drm_connector_status
4074 edp_detect(struct intel_dp *intel_dp)
4076 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4077 enum drm_connector_status status;
4079 status = intel_panel_detect(dev);
4080 if (status == connector_status_unknown)
4081 status = connector_status_connected;
4086 static enum drm_connector_status
4087 ironlake_dp_detect(struct intel_dp *intel_dp)
4089 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4090 struct drm_i915_private *dev_priv = dev->dev_private;
4091 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4093 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4094 return connector_status_disconnected;
4096 return intel_dp_detect_dpcd(intel_dp);
4099 static enum drm_connector_status
4100 g4x_dp_detect(struct intel_dp *intel_dp)
4102 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4103 struct drm_i915_private *dev_priv = dev->dev_private;
4104 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4107 if (IS_VALLEYVIEW(dev)) {
4108 switch (intel_dig_port->port) {
4110 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4113 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4116 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4119 return connector_status_unknown;
4122 switch (intel_dig_port->port) {
4124 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4127 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4130 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4133 return connector_status_unknown;
4137 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
4138 return connector_status_disconnected;
4140 return intel_dp_detect_dpcd(intel_dp);
4143 static struct edid *
4144 intel_dp_get_edid(struct intel_dp *intel_dp)
4146 struct intel_connector *intel_connector = intel_dp->attached_connector;
4148 /* use cached edid if we have one */
4149 if (intel_connector->edid) {
4151 if (IS_ERR(intel_connector->edid))
4154 return drm_edid_duplicate(intel_connector->edid);
4156 return drm_get_edid(&intel_connector->base,
4161 intel_dp_set_edid(struct intel_dp *intel_dp)
4163 struct intel_connector *intel_connector = intel_dp->attached_connector;
4166 edid = intel_dp_get_edid(intel_dp);
4167 intel_connector->detect_edid = edid;
4169 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4170 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4172 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4176 intel_dp_unset_edid(struct intel_dp *intel_dp)
4178 struct intel_connector *intel_connector = intel_dp->attached_connector;
4180 kfree(intel_connector->detect_edid);
4181 intel_connector->detect_edid = NULL;
4183 intel_dp->has_audio = false;
4186 static enum intel_display_power_domain
4187 intel_dp_power_get(struct intel_dp *dp)
4189 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4190 enum intel_display_power_domain power_domain;
4192 power_domain = intel_display_port_power_domain(encoder);
4193 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4195 return power_domain;
4199 intel_dp_power_put(struct intel_dp *dp,
4200 enum intel_display_power_domain power_domain)
4202 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4203 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
4206 static enum drm_connector_status
4207 intel_dp_detect(struct drm_connector *connector, bool force)
4209 struct intel_dp *intel_dp = intel_attached_dp(connector);
4210 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4211 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4212 struct drm_device *dev = connector->dev;
4213 enum drm_connector_status status;
4214 enum intel_display_power_domain power_domain;
4216 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4217 connector->base.id, connector->name);
4218 intel_dp_unset_edid(intel_dp);
4220 if (intel_dp->is_mst) {
4221 /* MST devices are disconnected from a monitor POV */
4222 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4223 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4224 return connector_status_disconnected;
4227 power_domain = intel_dp_power_get(intel_dp);
4229 /* Can't disconnect eDP, but you can close the lid... */
4230 if (is_edp(intel_dp))
4231 status = edp_detect(intel_dp);
4232 else if (HAS_PCH_SPLIT(dev))
4233 status = ironlake_dp_detect(intel_dp);
4235 status = g4x_dp_detect(intel_dp);
4236 if (status != connector_status_connected)
4239 intel_dp_probe_oui(intel_dp);
4242 ret = intel_dp_probe_mst(intel_dp);
4244 /* if we are in MST mode then this connector
4245 won't appear connected or have anything with EDID on it */
4246 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4247 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4248 status = connector_status_disconnected;
4253 intel_dp_set_edid(intel_dp);
4255 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4256 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4257 status = connector_status_connected;
4260 intel_dp_power_put(intel_dp, power_domain);
4265 intel_dp_force(struct drm_connector *connector)
4267 struct intel_dp *intel_dp = intel_attached_dp(connector);
4268 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4269 enum intel_display_power_domain power_domain;
4271 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4272 connector->base.id, connector->name);
4273 intel_dp_unset_edid(intel_dp);
4275 if (connector->status != connector_status_connected)
4278 power_domain = intel_dp_power_get(intel_dp);
4280 intel_dp_set_edid(intel_dp);
4282 intel_dp_power_put(intel_dp, power_domain);
4284 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4285 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4288 static int intel_dp_get_modes(struct drm_connector *connector)
4290 struct intel_connector *intel_connector = to_intel_connector(connector);
4293 edid = intel_connector->detect_edid;
4295 int ret = intel_connector_update_modes(connector, edid);
4300 /* if eDP has no EDID, fall back to fixed mode */
4301 if (is_edp(intel_attached_dp(connector)) &&
4302 intel_connector->panel.fixed_mode) {
4303 struct drm_display_mode *mode;
4305 mode = drm_mode_duplicate(connector->dev,
4306 intel_connector->panel.fixed_mode);
4308 drm_mode_probed_add(connector, mode);
4317 intel_dp_detect_audio(struct drm_connector *connector)
4319 bool has_audio = false;
4322 edid = to_intel_connector(connector)->detect_edid;
4324 has_audio = drm_detect_monitor_audio(edid);
4330 intel_dp_set_property(struct drm_connector *connector,
4331 struct drm_property *property,
4334 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4335 struct intel_connector *intel_connector = to_intel_connector(connector);
4336 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4337 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4340 ret = drm_object_property_set_value(&connector->base, property, val);
4344 if (property == dev_priv->force_audio_property) {
4348 if (i == intel_dp->force_audio)
4351 intel_dp->force_audio = i;
4353 if (i == HDMI_AUDIO_AUTO)
4354 has_audio = intel_dp_detect_audio(connector);
4356 has_audio = (i == HDMI_AUDIO_ON);
4358 if (has_audio == intel_dp->has_audio)
4361 intel_dp->has_audio = has_audio;
4365 if (property == dev_priv->broadcast_rgb_property) {
4366 bool old_auto = intel_dp->color_range_auto;
4367 uint32_t old_range = intel_dp->color_range;
4370 case INTEL_BROADCAST_RGB_AUTO:
4371 intel_dp->color_range_auto = true;
4373 case INTEL_BROADCAST_RGB_FULL:
4374 intel_dp->color_range_auto = false;
4375 intel_dp->color_range = 0;
4377 case INTEL_BROADCAST_RGB_LIMITED:
4378 intel_dp->color_range_auto = false;
4379 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4385 if (old_auto == intel_dp->color_range_auto &&
4386 old_range == intel_dp->color_range)
4392 if (is_edp(intel_dp) &&
4393 property == connector->dev->mode_config.scaling_mode_property) {
4394 if (val == DRM_MODE_SCALE_NONE) {
4395 DRM_DEBUG_KMS("no scaling not supported\n");
4399 if (intel_connector->panel.fitting_mode == val) {
4400 /* the eDP scaling property is not changed */
4403 intel_connector->panel.fitting_mode = val;
4411 if (intel_encoder->base.crtc)
4412 intel_crtc_restore_mode(intel_encoder->base.crtc);
4418 intel_dp_connector_destroy(struct drm_connector *connector)
4420 struct intel_connector *intel_connector = to_intel_connector(connector);
4422 kfree(intel_connector->detect_edid);
4424 if (!IS_ERR_OR_NULL(intel_connector->edid))
4425 kfree(intel_connector->edid);
4427 /* Can't call is_edp() since the encoder may have been destroyed
4429 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4430 intel_panel_fini(&intel_connector->panel);
4432 drm_connector_cleanup(connector);
4436 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4438 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4439 struct intel_dp *intel_dp = &intel_dig_port->dp;
4441 drm_dp_aux_unregister(&intel_dp->aux);
4442 intel_dp_mst_encoder_cleanup(intel_dig_port);
4443 drm_encoder_cleanup(encoder);
4444 if (is_edp(intel_dp)) {
4445 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4447 * vdd might still be enabled do to the delayed vdd off.
4448 * Make sure vdd is actually turned off here.
4451 edp_panel_vdd_off_sync(intel_dp);
4452 pps_unlock(intel_dp);
4455 if (intel_dp->edp_notifier.notifier_call) {
4456 unregister_reboot_notifier(&intel_dp->edp_notifier);
4457 intel_dp->edp_notifier.notifier_call = NULL;
4461 kfree(intel_dig_port);
4464 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4466 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4468 if (!is_edp(intel_dp))
4472 * vdd might still be enabled do to the delayed vdd off.
4473 * Make sure vdd is actually turned off here.
4475 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4477 edp_panel_vdd_off_sync(intel_dp);
4478 pps_unlock(intel_dp);
4481 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4483 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4486 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4487 .dpms = intel_connector_dpms,
4488 .detect = intel_dp_detect,
4489 .force = intel_dp_force,
4490 .fill_modes = drm_helper_probe_single_connector_modes,
4491 .set_property = intel_dp_set_property,
4492 .destroy = intel_dp_connector_destroy,
4495 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4496 .get_modes = intel_dp_get_modes,
4497 .mode_valid = intel_dp_mode_valid,
4498 .best_encoder = intel_best_encoder,
4501 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4502 .reset = intel_dp_encoder_reset,
4503 .destroy = intel_dp_encoder_destroy,
4507 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4509 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4511 intel_dp_check_link_status(intel_dp);
4515 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4517 struct intel_dp *intel_dp = &intel_dig_port->dp;
4518 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4519 struct drm_device *dev = intel_dig_port->base.base.dev;
4520 struct drm_i915_private *dev_priv = dev->dev_private;
4521 enum intel_display_power_domain power_domain;
4524 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4525 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4527 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4529 * vdd off can generate a long pulse on eDP which
4530 * would require vdd on to handle it, and thus we
4531 * would end up in an endless cycle of
4532 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4534 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4535 port_name(intel_dig_port->port));
4539 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4540 port_name(intel_dig_port->port),
4541 long_hpd ? "long" : "short");
4543 power_domain = intel_display_port_power_domain(intel_encoder);
4544 intel_display_power_get(dev_priv, power_domain);
4552 * we'll check the link status via the normal hot plug path later -
4553 * but for short hpds we should check it now
4555 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4556 intel_dp_check_link_status(intel_dp);
4557 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4561 intel_display_power_put(dev_priv, power_domain);
4566 /* Return which DP Port should be selected for Transcoder DP control */
4568 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4570 struct drm_device *dev = crtc->dev;
4571 struct intel_encoder *intel_encoder;
4572 struct intel_dp *intel_dp;
4574 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4575 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4577 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4578 intel_encoder->type == INTEL_OUTPUT_EDP)
4579 return intel_dp->output_reg;
4585 /* check the VBT to see whether the eDP is on DP-D port */
4586 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4588 struct drm_i915_private *dev_priv = dev->dev_private;
4589 union child_device_config *p_child;
4591 static const short port_mapping[] = {
4592 [PORT_B] = PORT_IDPB,
4593 [PORT_C] = PORT_IDPC,
4594 [PORT_D] = PORT_IDPD,
4600 if (!dev_priv->vbt.child_dev_num)
4603 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4604 p_child = dev_priv->vbt.child_dev + i;
4606 if (p_child->common.dvo_port == port_mapping[port] &&
4607 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4608 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4615 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4617 struct intel_connector *intel_connector = to_intel_connector(connector);
4619 intel_attach_force_audio_property(connector);
4620 intel_attach_broadcast_rgb_property(connector);
4621 intel_dp->color_range_auto = true;
4623 if (is_edp(intel_dp)) {
4624 drm_mode_create_scaling_mode_property(connector->dev);
4625 drm_object_attach_property(
4627 connector->dev->mode_config.scaling_mode_property,
4628 DRM_MODE_SCALE_ASPECT);
4629 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4633 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4635 intel_dp->last_power_cycle = jiffies;
4636 intel_dp->last_power_on = jiffies;
4637 intel_dp->last_backlight_off = jiffies;
4641 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4642 struct intel_dp *intel_dp,
4643 struct edp_power_seq *out)
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646 struct edp_power_seq cur, vbt, spec, final;
4647 u32 pp_on, pp_off, pp_div, pp;
4648 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4650 lockdep_assert_held(&dev_priv->pps_mutex);
4652 if (HAS_PCH_SPLIT(dev)) {
4653 pp_ctrl_reg = PCH_PP_CONTROL;
4654 pp_on_reg = PCH_PP_ON_DELAYS;
4655 pp_off_reg = PCH_PP_OFF_DELAYS;
4656 pp_div_reg = PCH_PP_DIVISOR;
4658 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4660 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4661 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4662 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4663 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4666 /* Workaround: Need to write PP_CONTROL with the unlock key as
4667 * the very first thing. */
4668 pp = ironlake_get_pp_control(intel_dp);
4669 I915_WRITE(pp_ctrl_reg, pp);
4671 pp_on = I915_READ(pp_on_reg);
4672 pp_off = I915_READ(pp_off_reg);
4673 pp_div = I915_READ(pp_div_reg);
4675 /* Pull timing values out of registers */
4676 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4677 PANEL_POWER_UP_DELAY_SHIFT;
4679 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4680 PANEL_LIGHT_ON_DELAY_SHIFT;
4682 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4683 PANEL_LIGHT_OFF_DELAY_SHIFT;
4685 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4686 PANEL_POWER_DOWN_DELAY_SHIFT;
4688 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4689 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4691 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4692 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4694 vbt = dev_priv->vbt.edp_pps;
4696 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4697 * our hw here, which are all in 100usec. */
4698 spec.t1_t3 = 210 * 10;
4699 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4700 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4701 spec.t10 = 500 * 10;
4702 /* This one is special and actually in units of 100ms, but zero
4703 * based in the hw (so we need to add 100 ms). But the sw vbt
4704 * table multiplies it with 1000 to make it in units of 100usec,
4706 spec.t11_t12 = (510 + 100) * 10;
4708 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4709 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4711 /* Use the max of the register settings and vbt. If both are
4712 * unset, fall back to the spec limits. */
4713 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4715 max(cur.field, vbt.field))
4716 assign_final(t1_t3);
4720 assign_final(t11_t12);
4723 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4724 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4725 intel_dp->backlight_on_delay = get_delay(t8);
4726 intel_dp->backlight_off_delay = get_delay(t9);
4727 intel_dp->panel_power_down_delay = get_delay(t10);
4728 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4731 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4732 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4733 intel_dp->panel_power_cycle_delay);
4735 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4736 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4743 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4744 struct intel_dp *intel_dp,
4745 struct edp_power_seq *seq)
4747 struct drm_i915_private *dev_priv = dev->dev_private;
4748 u32 pp_on, pp_off, pp_div, port_sel = 0;
4749 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4750 int pp_on_reg, pp_off_reg, pp_div_reg;
4751 enum port port = dp_to_dig_port(intel_dp)->port;
4753 lockdep_assert_held(&dev_priv->pps_mutex);
4755 if (HAS_PCH_SPLIT(dev)) {
4756 pp_on_reg = PCH_PP_ON_DELAYS;
4757 pp_off_reg = PCH_PP_OFF_DELAYS;
4758 pp_div_reg = PCH_PP_DIVISOR;
4760 enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4762 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4763 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4764 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4768 * And finally store the new values in the power sequencer. The
4769 * backlight delays are set to 1 because we do manual waits on them. For
4770 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4771 * we'll end up waiting for the backlight off delay twice: once when we
4772 * do the manual sleep, and once when we disable the panel and wait for
4773 * the PP_STATUS bit to become zero.
4775 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4776 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4777 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4778 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4779 /* Compute the divisor for the pp clock, simply match the Bspec
4781 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4782 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4783 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4785 /* Haswell doesn't have any port selection bits for the panel
4786 * power sequencer any more. */
4787 if (IS_VALLEYVIEW(dev)) {
4788 port_sel = PANEL_PORT_SELECT_VLV(port);
4789 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4791 port_sel = PANEL_PORT_SELECT_DPA;
4793 port_sel = PANEL_PORT_SELECT_DPD;
4798 I915_WRITE(pp_on_reg, pp_on);
4799 I915_WRITE(pp_off_reg, pp_off);
4800 I915_WRITE(pp_div_reg, pp_div);
4802 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4803 I915_READ(pp_on_reg),
4804 I915_READ(pp_off_reg),
4805 I915_READ(pp_div_reg));
4808 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4810 struct drm_i915_private *dev_priv = dev->dev_private;
4811 struct intel_encoder *encoder;
4812 struct intel_dp *intel_dp = NULL;
4813 struct intel_crtc_config *config = NULL;
4814 struct intel_crtc *intel_crtc = NULL;
4815 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4817 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4819 if (refresh_rate <= 0) {
4820 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4824 if (intel_connector == NULL) {
4825 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4830 * FIXME: This needs proper synchronization with psr state. But really
4831 * hard to tell without seeing the user of this function of this code.
4832 * Check locking and ordering once that lands.
4834 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4835 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4839 encoder = intel_attached_encoder(&intel_connector->base);
4840 intel_dp = enc_to_intel_dp(&encoder->base);
4841 intel_crtc = encoder->new_crtc;
4844 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4848 config = &intel_crtc->config;
4850 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4851 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4855 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4856 index = DRRS_LOW_RR;
4858 if (index == intel_dp->drrs_state.refresh_rate_type) {
4860 "DRRS requested for previously set RR...ignoring\n");
4864 if (!intel_crtc->active) {
4865 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4869 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4870 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4871 val = I915_READ(reg);
4872 if (index > DRRS_HIGH_RR) {
4873 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4874 intel_dp_set_m_n(intel_crtc);
4876 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4878 I915_WRITE(reg, val);
4882 * mutex taken to ensure that there is no race between differnt
4883 * drrs calls trying to update refresh rate. This scenario may occur
4884 * in future when idleness detection based DRRS in kernel and
4885 * possible calls from user space to set differnt RR are made.
4888 mutex_lock(&intel_dp->drrs_state.mutex);
4890 intel_dp->drrs_state.refresh_rate_type = index;
4892 mutex_unlock(&intel_dp->drrs_state.mutex);
4894 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4897 static struct drm_display_mode *
4898 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4899 struct intel_connector *intel_connector,
4900 struct drm_display_mode *fixed_mode)
4902 struct drm_connector *connector = &intel_connector->base;
4903 struct intel_dp *intel_dp = &intel_dig_port->dp;
4904 struct drm_device *dev = intel_dig_port->base.base.dev;
4905 struct drm_i915_private *dev_priv = dev->dev_private;
4906 struct drm_display_mode *downclock_mode = NULL;
4908 if (INTEL_INFO(dev)->gen <= 6) {
4909 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4913 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4914 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4918 downclock_mode = intel_find_panel_downclock
4919 (dev, fixed_mode, connector);
4921 if (!downclock_mode) {
4922 DRM_DEBUG_KMS("DRRS not supported\n");
4926 dev_priv->drrs.connector = intel_connector;
4928 lockinit(&intel_dp->drrs_state.mutex, "i915dsm", 0, LK_CANRECURSE);
4930 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4932 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4933 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4934 return downclock_mode;
4937 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4939 struct drm_device *dev = intel_encoder->base.dev;
4940 struct drm_i915_private *dev_priv = dev->dev_private;
4941 struct intel_dp *intel_dp;
4942 enum intel_display_power_domain power_domain;
4944 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4947 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4951 if (!edp_have_panel_vdd(intel_dp))
4954 * The VDD bit needs a power domain reference, so if the bit is
4955 * already enabled when we boot or resume, grab this reference and
4956 * schedule a vdd off, so we don't hold on to the reference
4959 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4960 power_domain = intel_display_port_power_domain(intel_encoder);
4961 intel_display_power_get(dev_priv, power_domain);
4963 edp_panel_vdd_schedule_off(intel_dp);
4965 pps_unlock(intel_dp);
4968 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4969 struct intel_connector *intel_connector,
4970 struct edp_power_seq *power_seq)
4972 struct drm_connector *connector = &intel_connector->base;
4973 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4974 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4975 struct drm_device *dev = intel_encoder->base.dev;
4976 struct drm_i915_private *dev_priv = dev->dev_private;
4977 struct drm_display_mode *fixed_mode = NULL;
4978 struct drm_display_mode *downclock_mode = NULL;
4980 struct drm_display_mode *scan;
4983 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4985 if (!is_edp(intel_dp))
4988 intel_edp_panel_vdd_sanitize(intel_encoder);
4990 /* Cache DPCD and EDID for edp. */
4991 intel_edp_panel_vdd_on(intel_dp);
4992 has_dpcd = intel_dp_get_dpcd(intel_dp);
4993 intel_edp_panel_vdd_off(intel_dp, false);
4996 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4997 dev_priv->no_aux_handshake =
4998 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4999 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5001 /* if this fails, presume the device is a ghost */
5002 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5006 /* We now know it's not a ghost, init power sequence regs. */
5008 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
5009 pps_unlock(intel_dp);
5011 mutex_lock(&dev->mode_config.mutex);
5012 edid = drm_get_edid(connector, intel_dp->aux.ddc);
5014 if (drm_add_edid_modes(connector, edid)) {
5015 drm_mode_connector_update_edid_property(connector,
5017 drm_edid_to_eld(connector, edid);
5020 edid = ERR_PTR(-EINVAL);
5023 edid = ERR_PTR(-ENOENT);
5025 intel_connector->edid = edid;
5027 /* prefer fixed mode from EDID if available */
5028 list_for_each_entry(scan, &connector->probed_modes, head) {
5029 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5030 fixed_mode = drm_mode_duplicate(dev, scan);
5031 downclock_mode = intel_dp_drrs_init(
5033 intel_connector, fixed_mode);
5038 /* fallback to VBT if available for eDP */
5039 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5040 fixed_mode = drm_mode_duplicate(dev,
5041 dev_priv->vbt.lfp_lvds_vbt_mode);
5043 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5045 mutex_unlock(&dev->mode_config.mutex);
5047 if (IS_VALLEYVIEW(dev)) {
5049 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5050 register_reboot_notifier(&intel_dp->edp_notifier);
5054 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5055 intel_connector->panel.backlight_power = intel_edp_backlight_power;
5056 intel_panel_setup_backlight(connector);
5062 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5063 struct intel_connector *intel_connector)
5065 struct drm_connector *connector = &intel_connector->base;
5066 struct intel_dp *intel_dp = &intel_dig_port->dp;
5067 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5068 struct drm_device *dev = intel_encoder->base.dev;
5069 struct drm_i915_private *dev_priv = dev->dev_private;
5070 enum port port = intel_dig_port->port;
5071 struct edp_power_seq power_seq = { 0 };
5074 intel_dp->pps_pipe = INVALID_PIPE;
5076 /* intel_dp vfuncs */
5077 if (IS_VALLEYVIEW(dev))
5078 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5079 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5080 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5081 else if (HAS_PCH_SPLIT(dev))
5082 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5084 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5086 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5088 /* Preserve the current hw state. */
5089 intel_dp->DP = I915_READ(intel_dp->output_reg);
5090 intel_dp->attached_connector = intel_connector;
5092 if (intel_dp_is_edp(dev, port))
5093 type = DRM_MODE_CONNECTOR_eDP;
5095 type = DRM_MODE_CONNECTOR_DisplayPort;
5098 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5099 * for DP the encoder type can be set by the caller to
5100 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5102 if (type == DRM_MODE_CONNECTOR_eDP)
5103 intel_encoder->type = INTEL_OUTPUT_EDP;
5105 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5106 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5109 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5110 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5112 connector->interlace_allowed = true;
5113 connector->doublescan_allowed = 0;
5115 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5116 edp_panel_vdd_work);
5118 intel_connector_attach_encoder(intel_connector, intel_encoder);
5119 drm_connector_register(connector);
5122 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5124 intel_connector->get_hw_state = intel_connector_get_hw_state;
5125 intel_connector->unregister = intel_dp_connector_unregister;
5127 /* Set up the hotplug pin. */
5130 intel_encoder->hpd_pin = HPD_PORT_A;
5133 intel_encoder->hpd_pin = HPD_PORT_B;
5136 intel_encoder->hpd_pin = HPD_PORT_C;
5139 intel_encoder->hpd_pin = HPD_PORT_D;
5145 if (is_edp(intel_dp)) {
5147 if (IS_VALLEYVIEW(dev)) {
5148 vlv_initial_power_sequencer_setup(intel_dp);
5150 intel_dp_init_panel_power_timestamps(intel_dp);
5151 intel_dp_init_panel_power_sequencer(dev, intel_dp,
5154 pps_unlock(intel_dp);
5157 intel_dp_aux_init(intel_dp, intel_connector);
5159 /* init MST on ports that can support it */
5160 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5161 if (port == PORT_B || port == PORT_C || port == PORT_D) {
5162 intel_dp_mst_encoder_init(intel_dig_port,
5163 intel_connector->base.base.id);
5167 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
5168 drm_dp_aux_unregister(&intel_dp->aux);
5169 if (is_edp(intel_dp)) {
5170 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5172 * vdd might still be enabled do to the delayed vdd off.
5173 * Make sure vdd is actually turned off here.
5176 edp_panel_vdd_off_sync(intel_dp);
5177 pps_unlock(intel_dp);
5179 drm_connector_unregister(connector);
5180 drm_connector_cleanup(connector);
5184 intel_dp_add_properties(intel_dp, connector);
5186 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5187 * 0xd. Failure to do so will result in spurious interrupts being
5188 * generated on the port when a cable is not attached.
5190 if (IS_G4X(dev) && !IS_GM45(dev)) {
5191 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5192 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5199 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5201 struct drm_i915_private *dev_priv = dev->dev_private;
5202 struct intel_digital_port *intel_dig_port;
5203 struct intel_encoder *intel_encoder;
5204 struct drm_encoder *encoder;
5205 struct intel_connector *intel_connector;
5207 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5208 if (!intel_dig_port)
5211 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
5212 if (!intel_connector) {
5213 kfree(intel_dig_port);
5217 intel_encoder = &intel_dig_port->base;
5218 encoder = &intel_encoder->base;
5220 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5221 DRM_MODE_ENCODER_TMDS);
5223 intel_encoder->compute_config = intel_dp_compute_config;
5224 intel_encoder->disable = intel_disable_dp;
5225 intel_encoder->get_hw_state = intel_dp_get_hw_state;
5226 intel_encoder->get_config = intel_dp_get_config;
5227 intel_encoder->suspend = intel_dp_encoder_suspend;
5228 if (IS_CHERRYVIEW(dev)) {
5229 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5230 intel_encoder->pre_enable = chv_pre_enable_dp;
5231 intel_encoder->enable = vlv_enable_dp;
5232 intel_encoder->post_disable = chv_post_disable_dp;
5233 } else if (IS_VALLEYVIEW(dev)) {
5234 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5235 intel_encoder->pre_enable = vlv_pre_enable_dp;
5236 intel_encoder->enable = vlv_enable_dp;
5237 intel_encoder->post_disable = vlv_post_disable_dp;
5239 intel_encoder->pre_enable = g4x_pre_enable_dp;
5240 intel_encoder->enable = g4x_enable_dp;
5241 if (INTEL_INFO(dev)->gen >= 5)
5242 intel_encoder->post_disable = ilk_post_disable_dp;
5245 intel_dig_port->port = port;
5246 intel_dig_port->dp.output_reg = output_reg;
5248 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5249 if (IS_CHERRYVIEW(dev)) {
5251 intel_encoder->crtc_mask = 1 << 2;
5253 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5255 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5257 intel_encoder->cloneable = 0;
5258 intel_encoder->hot_plug = intel_dp_hot_plug;
5260 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5261 dev_priv->hpd_irq_port[port] = intel_dig_port;
5263 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5264 drm_encoder_cleanup(encoder);
5265 kfree(intel_dig_port);
5266 kfree(intel_connector);