1 /* $NetBSD: midway.c,v 1.30 1997/09/29 17:40:38 chuck Exp $ */
2 /* (sync'd to midway.c 1.68) */
6 * Copyright (c) 1996 Charles D. Cranor and Washington University.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Charles D. Cranor and
20 * Washington University.
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/en/midway.c,v 1.19.2.1 2003/01/23 21:06:42 sam Exp $
36 * $DragonFly: src/sys/dev/atm/en/midway.c,v 1.13 2004/07/31 07:52:52 dillon Exp $
41 * m i d w a y . c e n i 1 5 5 d r i v e r
43 * author: Chuck Cranor <chuck@ccrc.wustl.edu>
44 * started: spring, 1996 (written from scratch).
46 * notes from the author:
47 * Extra special thanks go to Werner Almesberger, EPFL LRC. Werner's
48 * ENI driver was especially useful in figuring out how this card works.
49 * I would also like to thank Werner for promptly answering email and being
54 #undef EN_DEBUG_RANGE /* check ranges on en_read/en_write's? */
55 #define EN_MBUF_OPT /* try and put more stuff in mbuf? */
59 #define EN_DMA 1 /* use dma? */
61 #define EN_NOTXDMA 0 /* hook to disable tx dma only */
62 #define EN_NORXDMA 0 /* hook to disable rx dma only */
63 #define EN_DDBHOOK 1 /* compile in ddb functions */
64 #if defined(MIDWAY_ADPONLY)
65 #define EN_ENIDMAFIX 0 /* no ENI cards to worry about */
67 #define EN_ENIDMAFIX 1 /* avoid byte DMA on the ENI card (see below) */
71 * note on EN_ENIDMAFIX: the byte aligner on the ENI version of the card
72 * appears to be broken. it works just fine if there is no load... however
73 * when the card is loaded the data get corrupted. to see this, one only
74 * has to use "telnet" over ATM. do the following command in "telnet":
75 * cat /usr/share/misc/termcap
76 * "telnet" seems to generate lots of 1023 byte mbufs (which make great
77 * use of the byte aligner). watch "netstat -s" for checksum errors.
79 * I further tested this by adding a function that compared the transmit
80 * data on the card's SRAM with the data in the mbuf chain _after_ the
81 * "transmit DMA complete" interrupt. using the "telnet" test I got data
82 * mismatches where the byte-aligned data should have been. using ddb
83 * and en_dumpmem() I verified that the DTQs fed into the card were
84 * absolutely correct. thus, we are forced to concluded that the ENI
85 * hardware is buggy. note that the Adaptec version of the card works
86 * just fine with byte DMA.
88 * bottom line: we set EN_ENIDMAFIX to 1 to avoid byte DMAs on the ENI
92 #if defined(DIAGNOSTIC) && !defined(EN_DIAG)
93 #define EN_DIAG /* link in with master DIAG option */
96 #define EN_COUNT(X) (X)++
98 #define EN_COUNT(X) /* nothing */
104 #define STATIC /* nothing */
105 #define INLINE /* nothing */
107 #define STATIC static
108 #define INLINE __inline
109 #endif /* EN_DEBUG */
111 #if defined(__DragonFly__) || defined(__FreeBSD__)
112 #include "use_en.h" /* XXX for midwayvar.h's NEN */
113 #include "opt_inet.h"
114 #include "opt_natm.h"
116 /* enable DDBHOOK when DDB is available */
123 #include <sys/param.h>
124 #include <sys/systm.h>
125 #include <sys/queue.h>
126 #if defined(__NetBSD__) || defined(__OpenBSD__) || defined(__bsdi__)
127 #include <sys/device.h>
129 #include <sys/sockio.h>
130 #include <sys/mbuf.h>
131 #include <sys/socket.h>
132 #include <sys/proc.h>
135 #include <net/if_atm.h>
139 #if defined(INET) || defined(INET6)
140 #include <netinet/in.h>
141 #include <netinet/if_atm.h>
145 #include <netproto/natm/natm.h>
148 #if !defined(__DragonFly__) && !defined(sparc) && !defined(__FreeBSD__)
149 #include <machine/bus.h>
152 #if defined(__NetBSD__) || defined(__OpenBSD__)
153 #include <dev/ic/midwayreg.h>
154 #include <dev/ic/midwayvar.h>
155 #if defined(__alpha__)
156 /* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */
158 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
160 #elif defined(__DragonFly__) || defined(__FreeBSD__)
161 #include <machine/clock.h> /* for DELAY */
162 #include "midwayreg.h"
163 #include "midwayvar.h"
164 #include <vm/pmap.h> /* for vtophys proto */
166 #ifndef IFF_NOTRAILERS
167 #define IFF_NOTRAILERS 0
170 #endif /* __FreeBSD__ */
173 #if defined(__DragonFly__) || defined(__FreeBSD__)
174 #define BPFATTACH(ifp, dlt, hlen) bpfattach((ifp), (dlt), (hlen))
176 #define BPFATTACH(ifp, dlt, hlen) bpfattach(&(ifp)->if_bpf, (ifp), (dlt), (hlen))
177 #define BPF_MTAP(ifp, m) bpf_mtap((ifp)->if_bpf, (m))
185 #define EN_TXHIWAT (64*1024) /* max 64 KB waiting to be DMAd out */
189 #define EN_MINDMA 32 /* don't DMA anything less than this (bytes) */
192 #define RX_NONE 0xffff /* recv VC not in use */
194 #define EN_OBHDR ATM_PH_DRIVER7 /* TBD in first mbuf ! */
195 #define EN_OBTRL ATM_PH_DRIVER8 /* PDU trailier in last mbuf ! */
197 #define ENOTHER_FREE 0x01 /* free rxslot */
198 #define ENOTHER_DRAIN 0x02 /* almost free (drain DRQ dma) */
199 #define ENOTHER_RAW 0x04 /* 'raw' access (aka boodi mode) */
200 #define ENOTHER_SWSL 0x08 /* in software service list */
202 static int en_dma = EN_DMA; /* use DMA (switch off for dbg) */
205 * autoconfig attachments
208 struct cfdriver en_cd = {
217 * params to en_txlaunch() function
221 u_int32_t tbd1; /* TBD 1 */
222 u_int32_t tbd2; /* TBD 2 */
223 u_int32_t pdu1; /* PDU 1 (aal5) */
224 int nodma; /* don't use DMA */
225 int need; /* total space we need (pad out if less data) */
226 int mlen; /* length of mbuf (for dtq) */
227 struct mbuf *t; /* data */
228 u_int32_t aal; /* aal code */
229 u_int32_t atm_vci; /* vci */
230 u_int8_t atm_flags; /* flags */
235 * dma table (index by # of words)
237 * plan A: use WMAYBE (obsolete)
238 * plan B: avoid WMAYBE
242 u_int8_t bcode; /* code */
243 u_int8_t divshift; /* byte divisor */
246 static struct en_dmatab en_dma_planB[] = {
247 { 0, 0 }, /* 0 */ { MIDDMA_WORD, 2}, /* 1 */
248 { MIDDMA_2WORD, 3}, /* 2 */ { MIDDMA_WORD, 2}, /* 3 */
249 { MIDDMA_4WORD, 4}, /* 4 */ { MIDDMA_WORD, 2}, /* 5 */
250 { MIDDMA_2WORD, 3}, /* 6 */ { MIDDMA_WORD, 2}, /* 7 */
251 { MIDDMA_8WORD, 5}, /* 8 */ { MIDDMA_WORD, 2}, /* 9 */
252 { MIDDMA_2WORD, 3}, /* 10 */ { MIDDMA_WORD, 2}, /* 11 */
253 { MIDDMA_4WORD, 4}, /* 12 */ { MIDDMA_WORD, 2}, /* 13 */
254 { MIDDMA_2WORD, 3}, /* 14 */ { MIDDMA_WORD, 2}, /* 15 */
255 { MIDDMA_16WORD, 6}, /* 16 */
258 static struct en_dmatab *en_dmaplan = en_dma_planB;
264 STATIC INLINE int en_b2sz (int) __attribute__ ((unused));
266 int en_dump (int,int);
267 int en_dumpmem (int,int,int);
269 STATIC void en_dmaprobe (struct en_softc *);
270 STATIC int en_dmaprobe_doit (struct en_softc *, u_int8_t *,
272 STATIC INLINE int en_dqneed (struct en_softc *, caddr_t, u_int,
273 u_int) __attribute__ ((unused));
274 STATIC void en_init (struct en_softc *);
275 STATIC int en_ioctl (struct ifnet *, EN_IOCTL_CMDT, caddr_t,
277 STATIC INLINE int en_k2sz (int) __attribute__ ((unused));
278 STATIC void en_loadvc (struct en_softc *, int);
279 STATIC int en_mfix (struct en_softc *, struct mbuf **,
281 STATIC INLINE struct mbuf *en_mget (struct en_softc *, u_int,
282 u_int *) __attribute__ ((unused));
283 STATIC INLINE u_int32_t en_read (struct en_softc *,
284 u_int32_t) __attribute__ ((unused));
285 STATIC int en_rxctl (struct en_softc *, struct atm_pseudoioctl *,
287 STATIC void en_txdma (struct en_softc *, int);
288 STATIC void en_txlaunch (struct en_softc *, int,
290 STATIC void en_service (struct en_softc *);
291 STATIC void en_start (struct ifnet *);
292 STATIC INLINE int en_sz2b (int) __attribute__ ((unused));
293 STATIC INLINE void en_write (struct en_softc *, u_int32_t,
294 u_int32_t) __attribute__ ((unused));
301 * raw read/write macros
304 #define EN_READDAT(SC,R) en_read(SC,R)
305 #define EN_WRITEDAT(SC,R,V) en_write(SC,R,V)
308 * cooked read/write macros
311 #define EN_READ(SC,R) ntohl(en_read(SC,R))
312 #define EN_WRITE(SC,R,V) en_write(SC,R, htonl(V))
314 #define EN_WRAPADD(START,STOP,CUR,VAL) { \
315 (CUR) = (CUR) + (VAL); \
316 if ((CUR) >= (STOP)) \
317 (CUR) = (START) + ((CUR) - (STOP)); \
320 #define WORD_IDX(START, X) (((X) - (START)) / sizeof(u_int32_t))
322 /* we store sc->dtq and sc->drq data in the following format... */
323 #define EN_DQ_MK(SLOT,LEN) (((SLOT) << 20)|(LEN)|(0x80000))
324 /* the 0x80000 ensures we != 0 */
325 #define EN_DQ_SLOT(X) ((X) >> 20)
326 #define EN_DQ_LEN(X) ((X) & 0x3ffff)
328 /* format of DTQ/DRQ word 1 differs between ENI and ADP */
329 #if defined(MIDWAY_ENIONLY)
331 #define MID_MK_TXQ(SC,CNT,CHAN,END,BCODE) \
332 EN_WRITE((SC), (SC)->dtq_us, \
333 MID_MK_TXQ_ENI((CNT), (CHAN), (END), (BCODE)));
335 #define MID_MK_RXQ(SC,CNT,VCI,END,BCODE) \
336 EN_WRITE((SC), (SC)->drq_us, \
337 MID_MK_RXQ_ENI((CNT), (VCI), (END), (BCODE)));
339 #elif defined(MIDWAY_ADPONLY)
341 #define MID_MK_TXQ(SC,CNT,CHAN,END,JK) \
342 EN_WRITE((SC), (SC)->dtq_us, \
343 MID_MK_TXQ_ADP((CNT), (CHAN), (END), (JK)));
345 #define MID_MK_RXQ(SC,CNT,VCI,END,JK) \
346 EN_WRITE((SC), (SC)->drq_us, \
347 MID_MK_RXQ_ADP((CNT), (VCI), (END), (JK)));
351 #define MID_MK_TXQ(SC,CNT,CHAN,END,JK_OR_BCODE) { \
352 if ((SC)->is_adaptec) \
353 EN_WRITE((SC), (SC)->dtq_us, \
354 MID_MK_TXQ_ADP((CNT), (CHAN), (END), (JK_OR_BCODE))); \
356 EN_WRITE((SC), (SC)->dtq_us, \
357 MID_MK_TXQ_ENI((CNT), (CHAN), (END), (JK_OR_BCODE))); \
360 #define MID_MK_RXQ(SC,CNT,VCI,END,JK_OR_BCODE) { \
361 if ((SC)->is_adaptec) \
362 EN_WRITE((SC), (SC)->drq_us, \
363 MID_MK_RXQ_ADP((CNT), (VCI), (END), (JK_OR_BCODE))); \
365 EN_WRITE((SC), (SC)->drq_us, \
366 MID_MK_RXQ_ENI((CNT), (VCI), (END), (JK_OR_BCODE))); \
371 /* add an item to the DTQ */
372 #define EN_DTQADD(SC,CNT,CHAN,JK_OR_BCODE,ADDR,LEN,END) { \
374 (SC)->dtq[MID_DTQ_A2REG((SC)->dtq_us)] = EN_DQ_MK(CHAN,LEN); \
375 MID_MK_TXQ(SC,CNT,CHAN,END,JK_OR_BCODE); \
377 EN_WRITE((SC), (SC)->dtq_us, (ADDR)); \
378 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, (SC)->dtq_us, 4); \
381 EN_WRITE((SC), MID_DMA_WRTX, MID_DTQ_A2REG((SC)->dtq_us)); \
385 #define EN_DRQADD(SC,CNT,VCI,JK_OR_BCODE,ADDR,LEN,SLOT,END) { \
387 (SC)->drq[MID_DRQ_A2REG((SC)->drq_us)] = EN_DQ_MK(SLOT,LEN); \
388 MID_MK_RXQ(SC,CNT,VCI,END,JK_OR_BCODE); \
390 EN_WRITE((SC), (SC)->drq_us, (ADDR)); \
391 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, (SC)->drq_us, 4); \
394 EN_WRITE((SC), MID_DMA_WRRX, MID_DRQ_A2REG((SC)->drq_us)); \
400 * the code is arranged in a specific way:
401 * [1] short/inline functions
402 * [2] autoconfig stuff
404 * [4] reset -> init -> trasmit -> intr -> receive functions
408 /***********************************************************************/
411 * en_read: read a word from the card. this is the only function
412 * that reads from the card.
415 STATIC INLINE u_int32_t en_read(sc, r)
422 #ifdef EN_DEBUG_RANGE
423 if (r > MID_MAXOFF || (r % 4))
424 panic("en_read out of range, r=0x%x", r);
427 return(bus_space_read_4(sc->en_memt, sc->en_base, r));
431 * en_write: write a word to the card. this is the only function that
432 * writes to the card.
435 STATIC INLINE void en_write(sc, r, v)
441 #ifdef EN_DEBUG_RANGE
442 if (r > MID_MAXOFF || (r % 4))
443 panic("en_write out of range, r=0x%x", r);
446 bus_space_write_4(sc->en_memt, sc->en_base, r, v);
450 * en_k2sz: convert KBytes to a size parameter (a log2)
453 STATIC INLINE int en_k2sz(k)
467 default: panic("en_k2sz");
471 #define en_log2(X) en_k2sz(X)
475 * en_b2sz: convert a DMA burst code to its byte size
478 STATIC INLINE int en_b2sz(b)
484 case MIDDMA_WORD: return(1*4);
486 case MIDDMA_2WORD: return(2*4);
488 case MIDDMA_4WORD: return(4*4);
490 case MIDDMA_8WORD: return(8*4);
491 case MIDDMA_16WMAYBE:
492 case MIDDMA_16WORD: return(16*4);
493 default: panic("en_b2sz");
500 * en_sz2b: convert a burst size (bytes) to DMA burst code
503 STATIC INLINE int en_sz2b(sz)
509 case 1*4: return(MIDDMA_WORD);
510 case 2*4: return(MIDDMA_2WORD);
511 case 4*4: return(MIDDMA_4WORD);
512 case 8*4: return(MIDDMA_8WORD);
513 case 16*4: return(MIDDMA_16WORD);
514 default: panic("en_sz2b");
521 * en_dqneed: calculate number of DTQ/DRQ's needed for a buffer
524 STATIC INLINE int en_dqneed(sc, data, len, tx)
531 int result, needalign, sz;
533 #if !defined(MIDWAY_ENIONLY)
534 #if !defined(MIDWAY_ADPONLY)
536 #endif /* !MIDWAY_ADPONLY */
537 return(1); /* adaptec can DMA anything in one go */
540 #if !defined(MIDWAY_ADPONLY)
542 if (len < EN_MINDMA) {
543 if (!tx) /* XXX: conservative */
544 return(1); /* will copy/DMA_JK */
547 if (tx) { /* byte burst? */
548 needalign = (((uintptr_t) (void *) data) % sizeof(u_int32_t));
551 sz = min(len, sizeof(u_int32_t) - needalign);
557 if (sc->alburst && len) {
558 needalign = (((uintptr_t) (void *) data) & sc->bestburstmask);
560 result++; /* alburst */
561 sz = min(len, sc->bestburstlen - needalign);
566 if (len >= sc->bestburstlen) {
567 sz = len / sc->bestburstlen;
568 sz = sz * sc->bestburstlen;
570 result++; /* best shot */
574 result++; /* clean up */
575 if (tx && (len % sizeof(u_int32_t)) != 0)
576 result++; /* byte cleanup */
580 #endif /* !MIDWAY_ADPONLY */
585 * en_mget: get an mbuf chain that can hold totlen bytes and return it
586 * (for recv) [based on am7990_get from if_le and ieget from if_ie]
587 * after this call the sum of all the m_len's in the chain will be totlen.
590 STATIC INLINE struct mbuf *en_mget(sc, totlen, drqneed)
593 u_int totlen, *drqneed;
597 struct mbuf *top, **mp;
600 MGETHDR(m, MB_DONTWAIT, MT_DATA);
603 m->m_pkthdr.rcvif = &sc->enif;
604 m->m_pkthdr.len = totlen;
609 /* if (top != NULL) then we've already got 1 mbuf on the chain */
612 MGET(m, MB_DONTWAIT, MT_DATA);
615 return(NULL); /* out of mbufs */
619 if (totlen >= MINCLSIZE) {
620 MCLGET(m, MB_DONTWAIT);
621 if ((m->m_flags & M_EXT) == 0) {
624 return(NULL); /* out of mbuf clusters */
628 m->m_len = min(totlen, m->m_len);
633 *drqneed += en_dqneed(sc, m->m_data, m->m_len, 0);
639 /***********************************************************************/
650 struct ifnet *ifp = &sc->enif;
652 u_int32_t reg, lcv, check, ptr, sav, midvloc;
655 * probe card to determine memory size. the stupid ENI card always
656 * reports to PCI that it needs 4MB of space (2MB regs and 2MB RAM).
657 * if it has less than 2MB RAM the addresses wrap in the RAM address space.
658 * (i.e. on a 512KB card addresses 0x3ffffc, 0x37fffc, and 0x2ffffc
659 * are aliases for 0x27fffc [note that RAM starts at offset 0x200000]).
664 EN_WRITE(sc, MID_RESID, 0x0); /* reset card before touching RAM */
665 for (lcv = MID_PROBEOFF; lcv <= MID_MAXOFF ; lcv += MID_PROBSIZE) {
666 EN_WRITE(sc, lcv, lcv); /* data[address] = address */
667 for (check = MID_PROBEOFF ; check < lcv ; check += MID_PROBSIZE) {
668 reg = EN_READ(sc, check);
669 if (reg != check) { /* found an alias! */
670 goto done_probe; /* and quit */
675 lcv -= MID_PROBSIZE; /* take one step back */
676 sc->en_obmemsz = (lcv + 4) - MID_RAMOFF;
679 * determine the largest DMA burst supported
690 EN_WRITE(sc, MID_RESID, 0x0); /* reset */
691 for (lcv = MID_RAMOFF ; lcv < MID_RAMOFF + sc->en_obmemsz ; lcv += 4)
692 EN_WRITE(sc, lcv, 0); /* zero memory */
694 reg = EN_READ(sc, MID_RESID);
696 printf("%s: ATM midway v%d, board IDs %d.%d, %s%s%s, %ldKB on-board RAM\n",
697 sc->sc_dev.dv_xname, MID_VER(reg), MID_MID(reg), MID_DID(reg),
698 (MID_IS_SABRE(reg)) ? "sabre controller, " : "",
699 (MID_IS_SUNI(reg)) ? "SUNI" : "Utopia",
700 (!MID_IS_SUNI(reg) && MID_IS_UPIPE(reg)) ? " (pipelined)" : "",
701 (long)(sc->en_obmemsz / 1024));
703 if (sc->is_adaptec) {
704 if (sc->bestburstlen == 64 && sc->alburst == 0)
705 printf("%s: passed 64 byte DMA test\n", sc->sc_dev.dv_xname);
707 printf("%s: FAILED DMA TEST: burst=%d, alburst=%d\n",
708 sc->sc_dev.dv_xname, sc->bestburstlen, sc->alburst);
710 printf("%s: maximum DMA burst length = %d bytes%s\n", sc->sc_dev.dv_xname,
711 sc->bestburstlen, (sc->alburst) ? " (must align)" : "");
715 * link into network subsystem and prepare card
718 #if defined(__NetBSD__) || defined(__OpenBSD__)
719 bcopy(sc->sc_dev.dv_xname, sc->enif.if_xname, IFNAMSIZ);
721 sc->enif.if_softc = sc;
722 ifp->if_flags = IFF_SIMPLEX|IFF_NOTRAILERS;
723 ifp->if_ioctl = en_ioctl;
724 ifp->if_output = atm_output;
725 ifp->if_start = en_start;
731 for (lcv = 0 ; lcv < MID_N_VC ; lcv++) {
732 sc->rxvc2slot[lcv] = RX_NONE;
733 sc->txspeed[lcv] = 0; /* full */
734 sc->txvc2slot[lcv] = 0; /* full speed == slot 0 */
737 sz = sc->en_obmemsz - (MID_BUFOFF - MID_RAMOFF);
738 ptr = sav = MID_BUFOFF;
739 ptr = roundup(ptr, EN_TXSZ * 1024); /* align */
740 sz = sz - (ptr - sav);
741 if (EN_TXSZ*1024 * EN_NTX > sz) {
742 printf("%s: EN_NTX/EN_TXSZ too big\n", sc->sc_dev.dv_xname);
745 for (lcv = 0 ; lcv < EN_NTX ; lcv++) {
746 sc->txslot[lcv].mbsize = 0;
747 sc->txslot[lcv].start = ptr;
748 ptr += (EN_TXSZ * 1024);
749 sz -= (EN_TXSZ * 1024);
750 sc->txslot[lcv].stop = ptr;
751 sc->txslot[lcv].nref = 0;
752 bzero(&sc->txslot[lcv].indma, sizeof(sc->txslot[lcv].indma));
753 bzero(&sc->txslot[lcv].q, sizeof(sc->txslot[lcv].q));
755 printf("%s: tx%d: start 0x%x, stop 0x%x\n", sc->sc_dev.dv_xname, lcv,
756 sc->txslot[lcv].start, sc->txslot[lcv].stop);
761 ptr = roundup(ptr, EN_RXSZ * 1024); /* align */
762 sz = sz - (ptr - sav);
763 sc->en_nrx = sz / (EN_RXSZ * 1024);
764 if (sc->en_nrx <= 0) {
765 printf("%s: EN_NTX/EN_TXSZ/EN_RXSZ too big\n", sc->sc_dev.dv_xname);
770 * ensure that there is always one VC slot on the service list free
771 * so that we can tell the difference between a full and empty list.
773 if (sc->en_nrx >= MID_N_VC)
774 sc->en_nrx = MID_N_VC - 1;
776 for (lcv = 0 ; lcv < sc->en_nrx ; lcv++) {
777 sc->rxslot[lcv].rxhand = NULL;
778 sc->rxslot[lcv].oth_flags = ENOTHER_FREE;
779 bzero(&sc->rxslot[lcv].indma, sizeof(sc->rxslot[lcv].indma));
780 bzero(&sc->rxslot[lcv].q, sizeof(sc->rxslot[lcv].q));
781 midvloc = sc->rxslot[lcv].start = ptr;
782 ptr += (EN_RXSZ * 1024);
783 sz -= (EN_RXSZ * 1024);
784 sc->rxslot[lcv].stop = ptr;
785 midvloc = midvloc - MID_RAMOFF;
786 midvloc = (midvloc & ~((EN_RXSZ*1024) - 1)) >> 2; /* mask, cvt to words */
787 midvloc = midvloc >> MIDV_LOCTOPSHFT; /* we only want the top 11 bits */
788 midvloc = (midvloc & MIDV_LOCMASK) << MIDV_LOCSHIFT;
789 sc->rxslot[lcv].mode = midvloc |
790 (en_k2sz(EN_RXSZ) << MIDV_SZSHIFT) | MIDV_TRASH;
793 printf("%s: rx%d: start 0x%x, stop 0x%x, mode 0x%x\n", sc->sc_dev.dv_xname,
794 lcv, sc->rxslot[lcv].start, sc->rxslot[lcv].stop, sc->rxslot[lcv].mode);
799 sc->vtrash = sc->otrash = sc->mfix = sc->txmbovr = sc->dmaovr = 0;
800 sc->txoutspace = sc->txdtqout = sc->launch = sc->lheader = sc->ltail = 0;
801 sc->hwpull = sc->swadd = sc->rxqnotus = sc->rxqus = sc->rxoutboth = 0;
802 sc->rxdrqout = sc->ttrash = sc->rxmbufout = sc->mfixfail = 0;
803 sc->headbyte = sc->tailbyte = sc->tailflush = 0;
805 sc->need_drqs = sc->need_dtqs = 0;
807 printf("%s: %d %dKB receive buffers, %d %dKB transmit buffers allocated\n",
808 sc->sc_dev.dv_xname, sc->en_nrx, EN_RXSZ, EN_NTX, EN_TXSZ);
810 printf("%s: End Station Identifier (mac address) %6D\n",
811 sc->sc_dev.dv_xname, sc->macaddr, ":");
821 * en_dmaprobe: helper function for en_attach.
823 * see how the card handles DMA by running a few DMA tests. we need
824 * to figure out the largest number of bytes we can DMA in one burst
825 * ("bestburstlen"), and if the starting address for a burst needs to
826 * be aligned on any sort of boundary or not ("alburst").
829 * sparc1: bestburstlen=4, alburst=0 (ick, broken DMA!)
830 * sparc2: bestburstlen=64, alburst=1
831 * p166: bestburstlen=64, alburst=0
834 #if 1 /* __FreeBSD__ */
835 #define NBURSTS 3 /* number of bursts to use for dmaprobe */
836 #define BOUNDARY 1024 /* test misaligned dma crossing the bounday.
837 should be n * 64. at least 64*(NBURSTS+1).
838 dell P6 with EDO DRAM has 1K bounday problem */
841 STATIC void en_dmaprobe(sc)
847 /* be careful. kernel stack is only 8K */
848 u_int8_t buffer[BOUNDARY * 2 + 64 * (NBURSTS + 1)];
850 u_int32_t srcbuf[64], dstbuf[64];
853 int bestalgn, bestnotalgn, lcv, try;
858 /* setup src and dst buf at the end of the boundary */
859 sp = (u_int8_t *)roundup((uintptr_t)(void *)buffer, 64);
860 while (((uintptr_t)(void *)sp & (BOUNDARY - 1)) != (BOUNDARY - 64))
865 * we can't dma across page boundary so that, if buf is at a page
866 * boundary, move it to the next page. but still either src or dst
867 * will be at the boundary, which should be ok.
869 if ((((uintptr_t)(void *)sp + 64) & PAGE_MASK) == 0)
871 if ((((uintptr_t)(void *)dp + 64) & PAGE_MASK) == 0)
874 sp = (u_int8_t *) srcbuf;
875 while ((((unsigned long) sp) % MIDDMA_MAXBURST) != 0)
877 dp = (u_int8_t *) dstbuf;
878 while ((((unsigned long) dp) % MIDDMA_MAXBURST) != 0)
880 #endif /* !NBURSTS */
882 bestalgn = bestnotalgn = en_dmaprobe_doit(sc, sp, dp, 0);
884 for (lcv = 4 ; lcv < MIDDMA_MAXBURST ; lcv += 4) {
885 try = en_dmaprobe_doit(sc, sp+lcv, dp+lcv, 0);
887 if (try < bestnotalgn) {
892 if (try < bestnotalgn)
897 if (bestalgn != bestnotalgn) /* need bursts aligned */
900 sc->bestburstlen = bestalgn;
901 sc->bestburstshift = en_log2(bestalgn);
902 sc->bestburstmask = sc->bestburstlen - 1; /* must be power of 2 */
903 sc->bestburstcode = en_sz2b(bestalgn);
905 #if 1 /* __FreeBSD__ */
907 * correct pci chipsets should be able to handle misaligned-64-byte DMA.
908 * but there are too many broken chipsets around. we try to work around
909 * by finding the best workable dma size, but still some broken machines
910 * exhibit the problem later. so warn it here.
912 if (bestalgn != 64 || sc->alburst != 0) {
913 printf("%s: WARNING: DMA test detects a broken PCI chipset!\n",
914 sc->sc_dev.dv_xname);
915 printf(" trying to work around the problem... but if this doesn't\n");
916 printf(" work for you, you'd better switch to a newer motherboard.\n");
924 * en_dmaprobe_doit: do actual testing
928 en_dmaprobe_doit(sc, sp, dp, wmtry)
935 int lcv, retval = 4, cnt, count;
936 u_int32_t reg, bcode, midvloc;
939 * set up a 1k buffer at MID_BUFOFF
944 EN_WRITE(sc, MID_RESID, 0x0); /* reset card before touching RAM */
946 midvloc = ((MID_BUFOFF - MID_RAMOFF) / sizeof(u_int32_t)) >> MIDV_LOCTOPSHFT;
947 EN_WRITE(sc, MIDX_PLACE(0), MIDX_MKPLACE(en_k2sz(1), midvloc));
948 EN_WRITE(sc, MID_VC(0), (midvloc << MIDV_LOCSHIFT)
949 | (en_k2sz(1) << MIDV_SZSHIFT) | MIDV_TRASH);
950 EN_WRITE(sc, MID_DST_RP(0), 0);
951 EN_WRITE(sc, MID_WP_ST_CNT(0), 0);
954 for (lcv = 0 ; lcv < 64*NBURSTS; lcv++) /* set up sample data */
956 for (lcv = 0 ; lcv < 68 ; lcv++) /* set up sample data */
959 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* enable DMA (only) */
961 sc->drq_chip = MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX));
962 sc->dtq_chip = MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX));
965 * try it now . . . DMA it out, then DMA it back in and compare
967 * note: in order to get the dma stuff to reverse directions it wants
968 * the "end" flag set! since we are not dma'ing valid data we may
969 * get an ident mismatch interrupt (which we will ignore).
971 * note: we've got two different tests rolled up in the same loop
973 * then we are doing a wmaybe test and wmtry is a byte count
974 * else we are doing a burst test
977 for (lcv = 8 ; lcv <= MIDDMA_MAXBURST ; lcv = lcv * 2) {
980 printf("DMA test lcv=%d, sp=0x%x, dp=0x%x, wmtry=%d\n",
984 /* zero SRAM and dest buffer */
985 for (cnt = 0 ; cnt < 1024; cnt += 4)
986 EN_WRITE(sc, MID_BUFOFF+cnt, 0); /* zero memory */
988 for (cnt = 0 ; cnt < 64*NBURSTS; cnt++)
990 for (cnt = 0 ; cnt < 68 ; cnt++)
995 count = (sc->bestburstlen - sizeof(u_int32_t)) / sizeof(u_int32_t);
996 bcode = en_dmaplan[count].bcode;
997 count = wmtry >> en_dmaplan[count].divshift;
999 bcode = en_sz2b(lcv);
1003 /* build lcv-byte-DMA x NBURSTS */
1005 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ADP(lcv*NBURSTS, 0, MID_DMA_END, 0));
1007 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ENI(count*NBURSTS, 0, MID_DMA_END, bcode));
1008 EN_WRITE(sc, sc->dtq_chip+4, vtophys(sp));
1009 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, sc->dtq_chip, 8);
1010 EN_WRITE(sc, MID_DMA_WRTX, MID_DTQ_A2REG(sc->dtq_chip));
1012 while (EN_READ(sc, MID_DMA_RDTX) != MID_DTQ_A2REG(sc->dtq_chip)) {
1016 printf("%s: unexpected timeout in tx DMA test\n", sc->sc_dev.dv_xname);
1018 printf(" alignment=0x%x, burst size=%d, dma addr reg=0x%x\n",
1019 (u_long)sp & 63, lcv, EN_READ(sc, MID_DMA_ADDR));
1021 return(retval); /* timeout, give up */
1024 #else /* !NBURSTS */
1026 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ADP(lcv, 0, MID_DMA_END, 0));
1028 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ENI(count, 0, MID_DMA_END, bcode));
1029 EN_WRITE(sc, sc->dtq_chip+4, vtophys(sp));
1030 EN_WRITE(sc, MID_DMA_WRTX, MID_DTQ_A2REG(sc->dtq_chip+8));
1032 while (EN_READ(sc, MID_DMA_RDTX) == MID_DTQ_A2REG(sc->dtq_chip)) {
1036 printf("%s: unexpected timeout in tx DMA test\n", sc->sc_dev.dv_xname);
1037 return(retval); /* timeout, give up */
1040 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, sc->dtq_chip, 8);
1041 #endif /* !NBURSTS */
1042 reg = EN_READ(sc, MID_INTACK);
1043 if ((reg & MID_INT_DMA_TX) != MID_INT_DMA_TX) {
1044 printf("%s: unexpected status in tx DMA test: 0x%x\n",
1045 sc->sc_dev.dv_xname, reg);
1048 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* re-enable DMA (only) */
1050 /* "return to sender..." address is known ... */
1053 /* build lcv-byte-DMA x NBURSTS */
1055 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ADP(lcv*NBURSTS, 0, MID_DMA_END, 0));
1057 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ENI(count*NBURSTS, 0, MID_DMA_END, bcode));
1058 EN_WRITE(sc, sc->drq_chip+4, vtophys(dp));
1059 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, sc->drq_chip, 8);
1060 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip));
1062 while (EN_READ(sc, MID_DMA_RDRX) != MID_DRQ_A2REG(sc->drq_chip)) {
1066 printf("%s: unexpected timeout in rx DMA test\n", sc->sc_dev.dv_xname);
1067 return(retval); /* timeout, give up */
1070 #else /* !NBURSTS */
1072 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ADP(lcv, 0, MID_DMA_END, 0));
1074 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ENI(count, 0, MID_DMA_END, bcode));
1075 EN_WRITE(sc, sc->drq_chip+4, vtophys(dp));
1076 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip+8));
1078 while (EN_READ(sc, MID_DMA_RDRX) == MID_DRQ_A2REG(sc->drq_chip)) {
1082 printf("%s: unexpected timeout in rx DMA test\n", sc->sc_dev.dv_xname);
1083 return(retval); /* timeout, give up */
1086 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, sc->drq_chip, 8);
1087 #endif /* !NBURSTS */
1088 reg = EN_READ(sc, MID_INTACK);
1089 if ((reg & MID_INT_DMA_RX) != MID_INT_DMA_RX) {
1090 printf("%s: unexpected status in rx DMA test: 0x%x\n",
1091 sc->sc_dev.dv_xname, reg);
1094 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* re-enable DMA (only) */
1097 return(bcmp(sp, dp, wmtry)); /* wmtry always exits here, no looping */
1101 if (bcmp(sp, dp, lcv * NBURSTS)) {
1102 /* printf("DMA test failed! lcv=%d, sp=0x%x, dp=0x%x\n", lcv, sp, dp); */
1103 return(retval); /* failed, use last value */
1106 if (bcmp(sp, dp, lcv))
1107 return(retval); /* failed, use last value */
1113 return(retval); /* studly 64 byte DMA present! oh baby!! */
1116 /***********************************************************************/
1119 * en_ioctl: handle ioctl requests
1121 * NOTE: if you add an ioctl to set txspeed, you should choose a new
1122 * TX channel/slot. Choose the one with the lowest sc->txslot[slot].nref
1123 * value, subtract one from sc->txslot[0].nref, add one to the
1124 * sc->txslot[slot].nref, set sc->txvc2slot[vci] = slot, and then set
1128 STATIC int en_ioctl(ifp, cmd, data, cr)
1136 struct en_softc *sc = (struct en_softc *) ifp->if_softc;
1137 struct ifaddr *ifa = (struct ifaddr *) data;
1138 struct ifreq *ifr = (struct ifreq *) data;
1139 struct atm_pseudoioctl *api = (struct atm_pseudoioctl *)data;
1141 struct atm_rawioctl *ario = (struct atm_rawioctl *)data;
1149 case SIOCATMENA: /* enable circuit for recv */
1150 error = en_rxctl(sc, api, 1);
1153 case SIOCATMDIS: /* disable circuit for recv */
1154 error = en_rxctl(sc, api, 0);
1159 if ((slot = sc->rxvc2slot[ario->npcb->npcb_vci]) == RX_NONE) {
1163 if (ario->rawvalue > EN_RXSZ*1024)
1164 ario->rawvalue = EN_RXSZ*1024;
1165 if (ario->rawvalue) {
1166 sc->rxslot[slot].oth_flags |= ENOTHER_RAW;
1167 sc->rxslot[slot].raw_threshold = ario->rawvalue;
1169 sc->rxslot[slot].oth_flags &= (~ENOTHER_RAW);
1170 sc->rxslot[slot].raw_threshold = 0;
1173 printf("%s: rxvci%d: turn %s raw (boodi) mode\n",
1174 sc->sc_dev.dv_xname, ario->npcb->npcb_vci,
1175 (ario->rawvalue) ? "on" : "off");
1180 ifp->if_flags |= IFF_UP;
1181 #if defined(INET) || defined(INET6)
1182 if (ifa->ifa_addr->sa_family == AF_INET
1183 || ifa->ifa_addr->sa_family == AF_INET6) {
1186 ifa->ifa_rtrequest = atm_rtrequest; /* ??? */
1190 /* what to do if not INET? */
1203 #if defined(SIOCSIFMTU) /* ??? copied from if_de */
1204 #if !defined(ifr_mtu)
1205 #define ifr_mtu ifr_metric
1209 * Set the interface MTU.
1212 if (ifr->ifr_mtu > ATMMTU) {
1217 ifp->if_mtu = ifr->ifr_mtu;
1218 /* XXXCDC: do we really need to reset on MTU size change? */
1222 #endif /* SIOCSIFMTU */
1234 * en_rxctl: turn on and off VCs for recv.
1237 STATIC int en_rxctl(sc, pi, on)
1239 struct en_softc *sc;
1240 struct atm_pseudoioctl *pi;
1244 u_int s, vci, flags, slot;
1245 u_int32_t oldmode, newmode;
1247 vci = ATM_PH_VCI(&pi->aph);
1248 flags = ATM_PH_FLAGS(&pi->aph);
1251 printf("%s: %s vpi=%d, vci=%d, flags=%d\n", sc->sc_dev.dv_xname,
1252 (on) ? "enable" : "disable", ATM_PH_VPI(&pi->aph), vci, flags);
1255 if (ATM_PH_VPI(&pi->aph) || vci >= MID_N_VC)
1263 if (sc->rxvc2slot[vci] != RX_NONE)
1265 for (slot = 0 ; slot < sc->en_nrx ; slot++)
1266 if (sc->rxslot[slot].oth_flags & ENOTHER_FREE)
1268 if (slot == sc->en_nrx)
1270 sc->rxvc2slot[vci] = slot;
1271 sc->rxslot[slot].rxhand = NULL;
1272 oldmode = sc->rxslot[slot].mode;
1273 newmode = (flags & ATM_PH_AAL5) ? MIDV_AAL5 : MIDV_NOAAL;
1274 sc->rxslot[slot].mode = MIDV_SETMODE(oldmode, newmode);
1275 sc->rxslot[slot].atm_vci = vci;
1276 sc->rxslot[slot].atm_flags = flags;
1277 sc->rxslot[slot].oth_flags = 0;
1278 sc->rxslot[slot].rxhand = pi->rxhand;
1279 if (sc->rxslot[slot].indma.ifq_head || sc->rxslot[slot].q.ifq_head)
1280 panic("en_rxctl: left over mbufs on enable");
1281 sc->txspeed[vci] = 0; /* full speed to start */
1282 sc->txvc2slot[vci] = 0; /* init value */
1283 sc->txslot[0].nref++; /* bump reference count */
1284 en_loadvc(sc, vci); /* does debug printf for us */
1292 if (sc->rxvc2slot[vci] == RX_NONE)
1294 slot = sc->rxvc2slot[vci];
1295 if ((sc->rxslot[slot].oth_flags & (ENOTHER_FREE|ENOTHER_DRAIN)) != 0)
1297 s = splimp(); /* block out enintr() */
1298 oldmode = EN_READ(sc, MID_VC(vci));
1299 newmode = MIDV_SETMODE(oldmode, MIDV_TRASH) & ~MIDV_INSERVICE;
1300 EN_WRITE(sc, MID_VC(vci), (newmode | (oldmode & MIDV_INSERVICE)));
1301 /* halt in tracks, be careful to preserve inserivce bit */
1303 sc->rxslot[slot].rxhand = NULL;
1304 sc->rxslot[slot].mode = newmode;
1306 sc->txslot[sc->txvc2slot[vci]].nref--;
1307 sc->txspeed[vci] = 0;
1308 sc->txvc2slot[vci] = 0;
1310 /* if stuff is still going on we are going to have to drain it out */
1311 if (sc->rxslot[slot].indma.ifq_head ||
1312 sc->rxslot[slot].q.ifq_head ||
1313 (sc->rxslot[slot].oth_flags & ENOTHER_SWSL) != 0) {
1314 sc->rxslot[slot].oth_flags |= ENOTHER_DRAIN;
1316 sc->rxslot[slot].oth_flags = ENOTHER_FREE;
1317 sc->rxslot[slot].atm_vci = RX_NONE;
1318 sc->rxvc2slot[vci] = RX_NONE;
1320 splx(s); /* enable enintr() */
1322 printf("%s: rx%d: VCI %d is now %s\n", sc->sc_dev.dv_xname, slot, vci,
1323 (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) ? "draining" : "free");
1328 /***********************************************************************/
1331 * en_reset: reset the board, throw away work in progress.
1332 * must en_init to recover.
1337 struct en_softc *sc;
1344 printf("%s: reset\n", sc->sc_dev.dv_xname);
1347 if (sc->en_busreset)
1348 sc->en_busreset(sc);
1349 EN_WRITE(sc, MID_RESID, 0x0); /* reset hardware */
1352 * recv: dump any mbufs we are dma'ing into, if DRAINing, then a reset
1356 for (lcv = 0 ; lcv < MID_N_VC ; lcv++) {
1357 if (sc->rxvc2slot[lcv] == RX_NONE)
1359 slot = sc->rxvc2slot[lcv];
1361 IF_DEQUEUE(&sc->rxslot[slot].indma, m);
1363 break; /* >>> exit 'while(1)' here <<< */
1367 IF_DEQUEUE(&sc->rxslot[slot].q, m);
1369 break; /* >>> exit 'while(1)' here <<< */
1372 sc->rxslot[slot].oth_flags &= ~ENOTHER_SWSL;
1373 if (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) {
1374 sc->rxslot[slot].oth_flags = ENOTHER_FREE;
1375 sc->rxvc2slot[lcv] = RX_NONE;
1377 printf("%s: rx%d: VCI %d is now free\n", sc->sc_dev.dv_xname, slot, lcv);
1383 * xmit: dump everything
1386 for (lcv = 0 ; lcv < EN_NTX ; lcv++) {
1388 IF_DEQUEUE(&sc->txslot[lcv].indma, m);
1390 break; /* >>> exit 'while(1)' here <<< */
1394 IF_DEQUEUE(&sc->txslot[lcv].q, m);
1396 break; /* >>> exit 'while(1)' here <<< */
1400 sc->txslot[lcv].mbsize = 0;
1408 * en_init: init board and sync the card with the data in the softc.
1411 STATIC void en_init(sc)
1413 struct en_softc *sc;
1419 if ((sc->enif.if_flags & IFF_UP) == 0) {
1421 printf("%s: going down\n", sc->sc_dev.dv_xname);
1423 en_reset(sc); /* to be safe */
1424 sc->enif.if_flags &= ~IFF_RUNNING; /* disable */
1429 printf("%s: going up\n", sc->sc_dev.dv_xname);
1431 sc->enif.if_flags |= IFF_RUNNING; /* enable */
1433 if (sc->en_busreset)
1434 sc->en_busreset(sc);
1435 EN_WRITE(sc, MID_RESID, 0x0); /* reset */
1438 * init obmem data structures: vc tab, dma q's, slist.
1440 * note that we set drq_free/dtq_free to one less than the total number
1441 * of DTQ/DRQs present. we do this because the card uses the condition
1442 * (drq_chip == drq_us) to mean "list is empty"... but if you allow the
1443 * circular list to be completely full then (drq_chip == drq_us) [i.e.
1444 * the drq_us pointer will wrap all the way around]. by restricting
1445 * the number of active requests to (N - 1) we prevent the list from
1446 * becoming completely full. note that the card will sometimes give
1447 * us an interrupt for a DTQ/DRQ we have already processes... this helps
1448 * keep that interrupt from messing us up.
1451 for (vc = 0 ; vc < MID_N_VC ; vc++)
1454 bzero(&sc->drq, sizeof(sc->drq));
1455 sc->drq_free = MID_DRQ_N - 1; /* N - 1 */
1456 sc->drq_chip = MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX));
1457 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip));
1458 /* ensure zero queue */
1459 sc->drq_us = sc->drq_chip;
1461 bzero(&sc->dtq, sizeof(sc->dtq));
1462 sc->dtq_free = MID_DTQ_N - 1; /* N - 1 */
1463 sc->dtq_chip = MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX));
1464 EN_WRITE(sc, MID_DMA_WRTX, MID_DRQ_A2REG(sc->dtq_chip));
1465 /* ensure zero queue */
1466 sc->dtq_us = sc->dtq_chip;
1468 sc->hwslistp = MID_SL_REG2A(EN_READ(sc, MID_SERV_WRITE));
1469 sc->swsl_size = sc->swsl_head = sc->swsl_tail = 0;
1472 printf("%s: drq free/chip: %d/0x%x, dtq free/chip: %d/0x%x, hwslist: 0x%x\n",
1473 sc->sc_dev.dv_xname, sc->drq_free, sc->drq_chip,
1474 sc->dtq_free, sc->dtq_chip, sc->hwslistp);
1477 for (slot = 0 ; slot < EN_NTX ; slot++) {
1478 sc->txslot[slot].bfree = EN_TXSZ * 1024;
1479 EN_WRITE(sc, MIDX_READPTR(slot), 0);
1480 EN_WRITE(sc, MIDX_DESCSTART(slot), 0);
1481 loc = sc->txslot[slot].cur = sc->txslot[slot].start;
1482 loc = loc - MID_RAMOFF;
1483 loc = (loc & ~((EN_TXSZ*1024) - 1)) >> 2; /* mask, cvt to words */
1484 loc = loc >> MIDV_LOCTOPSHFT; /* top 11 bits */
1485 EN_WRITE(sc, MIDX_PLACE(slot), MIDX_MKPLACE(en_k2sz(EN_TXSZ), loc));
1487 printf("%s: tx%d: place 0x%x\n", sc->sc_dev.dv_xname, slot,
1488 EN_READ(sc, MIDX_PLACE(slot)));
1496 EN_WRITE(sc, MID_INTENA, MID_INT_TX|MID_INT_DMA_OVR|MID_INT_IDENT|
1497 MID_INT_LERR|MID_INT_DMA_ERR|MID_INT_DMA_RX|MID_INT_DMA_TX|
1498 MID_INT_SERVICE| /* >>> MID_INT_SUNI| XXXCDC<<< */ MID_INT_STATS);
1499 EN_WRITE(sc, MID_MAST_CSR, MID_SETIPL(sc->ipl)|MID_MCSR_ENDMA|
1500 MID_MCSR_ENTX|MID_MCSR_ENRX);
1506 * en_loadvc: load a vc tab entry from a slot
1509 STATIC void en_loadvc(sc, vc)
1511 struct en_softc *sc;
1516 u_int32_t reg = EN_READ(sc, MID_VC(vc));
1518 reg = MIDV_SETMODE(reg, MIDV_TRASH);
1519 EN_WRITE(sc, MID_VC(vc), reg);
1522 if ((slot = sc->rxvc2slot[vc]) == RX_NONE)
1525 /* no need to set CRC */
1526 EN_WRITE(sc, MID_DST_RP(vc), 0); /* read pointer = 0, desc. start = 0 */
1527 EN_WRITE(sc, MID_WP_ST_CNT(vc), 0); /* write pointer = 0 */
1528 EN_WRITE(sc, MID_VC(vc), sc->rxslot[slot].mode); /* set mode, size, loc */
1529 sc->rxslot[slot].cur = sc->rxslot[slot].start;
1532 printf("%s: rx%d: assigned to VCI %d\n", sc->sc_dev.dv_xname, slot, vc);
1538 * en_start: start transmitting the next packet that needs to go out
1539 * if there is one. note that atm_output() has already splimp()'d us.
1542 STATIC void en_start(ifp)
1547 struct en_softc *sc = (struct en_softc *) ifp->if_softc;
1548 struct ifqueue *ifq = &ifp->if_snd; /* if INPUT QUEUE */
1549 struct mbuf *m, *lastm, *prev;
1550 struct atm_pseudohdr *ap, *new_ap;
1551 int txchan, mlen, got, need, toadd, cellcnt, first;
1552 u_int32_t atm_vpi, atm_vci, atm_flags, *dat, aal;
1555 if ((ifp->if_flags & IFF_RUNNING) == 0)
1559 * remove everything from interface queue since we handle all queueing
1567 return; /* EMPTY: >>> exit here <<< */
1570 * calculate size of packet (in bytes)
1571 * also, if we are not doing transmit DMA we eliminate all stupid
1572 * (non-word) alignments here using en_mfix(). calls to en_mfix()
1573 * seem to be due to tcp retransmits for the most part.
1575 * after this loop mlen total length of mbuf chain (including atm_ph),
1576 * and lastm is a pointer to the last mbuf on the chain.
1584 if ((!sc->is_adaptec && EN_ENIDMAFIX) || EN_NOTXDMA || !en_dma) {
1585 if ( ((uintptr_t)mtod(lastm, void *) % sizeof(u_int32_t)) != 0 ||
1586 ((lastm->m_len % sizeof(u_int32_t)) != 0 && lastm->m_next)) {
1587 first = (lastm == m);
1588 if (en_mfix(sc, &lastm, prev) == 0) { /* failed? */
1594 m = lastm; /* update */
1599 mlen += lastm->m_len;
1600 if (lastm->m_next == NULL)
1602 lastm = lastm->m_next;
1605 if (m == NULL) /* happens only if mfix fails */
1608 ap = mtod(m, struct atm_pseudohdr *);
1610 atm_vpi = ATM_PH_VPI(ap);
1611 atm_vci = ATM_PH_VCI(ap);
1612 atm_flags = ATM_PH_FLAGS(ap) & ~(EN_OBHDR|EN_OBTRL);
1613 aal = ((atm_flags & ATM_PH_AAL5) != 0)
1614 ? MID_TBD_AAL5 : MID_TBD_NOAAL5;
1617 * check that vpi/vci is one we can use
1620 if (atm_vpi || atm_vci > MID_N_VC) {
1621 printf("%s: output vpi=%d, vci=%d out of card range, dropping...\n",
1622 sc->sc_dev.dv_xname, atm_vpi, atm_vci);
1628 * computing how much padding we need on the end of the mbuf, then
1629 * see if we can put the TBD at the front of the mbuf where the
1630 * link header goes (well behaved protocols will reserve room for us).
1631 * last, check if room for PDU tail.
1633 * got = number of bytes of data we have
1634 * cellcnt = number of cells in this mbuf
1635 * need = number of bytes of data + padding we need (excludes TBD)
1636 * toadd = number of bytes of data we need to add to end of mbuf,
1637 * [including AAL5 PDU, if AAL5]
1640 got = mlen - sizeof(struct atm_pseudohdr *);
1641 toadd = (aal == MID_TBD_AAL5) ? MID_PDU_SIZE : 0; /* PDU */
1642 cellcnt = (got + toadd + (MID_ATMDATASZ - 1)) / MID_ATMDATASZ;
1643 need = cellcnt * MID_ATMDATASZ;
1644 toadd = need - got; /* recompute, including zero padding */
1647 printf("%s: txvci%d: mlen=%d, got=%d, need=%d, toadd=%d, cell#=%d\n",
1648 sc->sc_dev.dv_xname, atm_vci, mlen, got, need, toadd, cellcnt);
1649 printf(" leading_space=%d, trailing_space=%d\n",
1650 M_LEADINGSPACE(m), M_TRAILINGSPACE(lastm));
1656 * note: external storage (M_EXT) can be shared between mbufs
1657 * to avoid copying (see m_copym()). this means that the same
1658 * data buffer could be shared by several mbufs, and thus it isn't
1659 * a good idea to try and write TBDs or PDUs to M_EXT data areas.
1662 if (M_LEADINGSPACE(m) >= MID_TBD_SIZE && (m->m_flags & M_EXT) == 0) {
1663 m->m_data -= MID_TBD_SIZE;
1664 m->m_len += MID_TBD_SIZE;
1665 mlen += MID_TBD_SIZE;
1666 new_ap = mtod(m, struct atm_pseudohdr *);
1667 *new_ap = *ap; /* move it back */
1669 dat = ((u_int32_t *) ap) + 1;
1670 /* make sure the TBD is in proper byte order */
1671 *dat++ = htonl(MID_TBD_MK1(aal, sc->txspeed[atm_vci], cellcnt));
1672 *dat = htonl(MID_TBD_MK2(atm_vci, 0, 0));
1673 atm_flags |= EN_OBHDR;
1676 if (toadd && (lastm->m_flags & M_EXT) == 0 &&
1677 M_TRAILINGSPACE(lastm) >= toadd) {
1678 cp = mtod(lastm, u_int8_t *) + lastm->m_len;
1679 lastm->m_len += toadd;
1681 if (aal == MID_TBD_AAL5) {
1682 bzero(cp, toadd - MID_PDU_SIZE);
1683 dat = (u_int32_t *)(cp + toadd - MID_PDU_SIZE);
1684 /* make sure the PDU is in proper byte order */
1685 *dat = htonl(MID_PDU_MK1(0, 0, got));
1689 atm_flags |= EN_OBTRL;
1691 ATM_PH_FLAGS(ap) = atm_flags; /* update EN_OBHDR/EN_OBTRL bits */
1692 #endif /* EN_MBUF_OPT */
1695 * get assigned channel (will be zero unless txspeed[atm_vci] is set)
1698 txchan = sc->txvc2slot[atm_vci];
1700 if (sc->txslot[txchan].mbsize > EN_TXHIWAT) {
1701 EN_COUNT(sc->txmbovr);
1704 printf("%s: tx%d: buffer space shortage\n", sc->sc_dev.dv_xname,
1710 sc->txslot[txchan].mbsize += mlen;
1713 printf("%s: tx%d: VPI=%d, VCI=%d, FLAGS=0x%x, speed=0x%x\n",
1714 sc->sc_dev.dv_xname, txchan, atm_vpi, atm_vci, atm_flags,
1715 sc->txspeed[atm_vci]);
1716 printf(" adjusted mlen=%d, mbsize=%d\n", mlen,
1717 sc->txslot[txchan].mbsize);
1720 IF_ENQUEUE(&sc->txslot[txchan].q, m);
1722 en_txdma(sc, txchan);
1730 * en_mfix: fix a stupid mbuf
1733 #if !defined(__DragonFly__) && !defined(__FreeBSD__)
1735 STATIC int en_mfix(sc, mm, prev)
1737 struct en_softc *sc;
1738 struct mbuf **mm, *prev;
1741 struct mbuf *m, *new;
1748 EN_COUNT(sc->mfix); /* count # of calls */
1750 printf("%s: mfix mbuf m_data=%p, m_len=%d\n", sc->sc_dev.dv_xname,
1751 m->m_data, m->m_len);
1754 d = mtod(m, u_char *);
1755 off = ((unsigned long) d) % sizeof(u_int32_t);
1758 if ((m->m_flags & M_EXT) == 0) {
1759 bcopy(d, d - off, m->m_len); /* ALIGN! (with costly data copy...) */
1761 m->m_data = (caddr_t)d;
1763 /* can't write to an M_EXT mbuf since it may be shared */
1764 MGET(new, MB_DONTWAIT, MT_DATA);
1766 EN_COUNT(sc->mfixfail);
1769 MCLGET(new, MB_DONTWAIT);
1770 if ((new->m_flags & M_EXT) == 0) {
1772 EN_COUNT(sc->mfixfail);
1775 bcopy(d, new->m_data, m->m_len); /* ALIGN! (with costly data copy...) */
1776 new->m_len = m->m_len;
1777 new->m_next = m->m_next;
1781 *mm = m = new; /* note: 'd' now invalid */
1785 off = m->m_len % sizeof(u_int32_t);
1789 d = mtod(m, u_char *) + m->m_len;
1790 off = sizeof(u_int32_t) - off;
1794 for ( ; nxt != NULL && nxt->m_len == 0 ; nxt = nxt->m_next)
1796 if (nxt == NULL) { /* out of data, zero fill */
1798 continue; /* next "off" */
1800 cp = mtod(nxt, u_char *);
1804 nxt->m_data = (caddr_t)cp;
1809 #else /* __FreeBSD__ */
1811 STATIC int en_makeexclusive(struct en_softc *, struct mbuf **, struct mbuf *);
1813 STATIC int en_makeexclusive(sc, mm, prev)
1814 struct en_softc *sc;
1815 struct mbuf **mm, *prev;
1817 struct mbuf *m, *new;
1821 if (m->m_flags & M_EXT) {
1822 if (m->m_ext.ext_nfree.any) {
1823 /* external buffer isn't an ordinary mbuf cluster! */
1824 printf("%s: mfix: special buffer! can't make a copy!\n",
1825 sc->sc_dev.dv_xname);
1829 if (m_sharecount(m) > 1) {
1830 /* make a real copy of the M_EXT mbuf since it is shared */
1831 MGET(new, MB_DONTWAIT, MT_DATA);
1833 EN_COUNT(sc->mfixfail);
1836 if (m->m_flags & M_PKTHDR)
1837 M_MOVE_PKTHDR(new, m);
1838 MCLGET(new, MB_DONTWAIT);
1839 if ((new->m_flags & M_EXT) == 0) {
1841 EN_COUNT(sc->mfixfail);
1844 bcopy(m->m_data, new->m_data, m->m_len);
1845 new->m_len = m->m_len;
1846 new->m_next = m->m_next;
1853 /* the buffer is not shared, align the data offset using
1855 u_char *d = mtod(m, u_char *);
1856 int off = ((uintptr_t)(void *)d) % sizeof(u_int32_t);
1859 bcopy(d, d - off, m->m_len);
1860 m->m_data = (caddr_t)d - off;
1867 STATIC int en_mfix(sc, mm, prev)
1869 struct en_softc *sc;
1870 struct mbuf **mm, *prev;
1880 EN_COUNT(sc->mfix); /* count # of calls */
1882 printf("%s: mfix mbuf m_data=0x%x, m_len=%d\n", sc->sc_dev.dv_xname,
1883 m->m_data, m->m_len);
1886 d = mtod(m, u_char *);
1887 off = ((uintptr_t) (void *) d) % sizeof(u_int32_t);
1890 if ((m->m_flags & M_EXT) == 0) {
1891 bcopy(d, d - off, m->m_len); /* ALIGN! (with costly data copy...) */
1893 m->m_data = (caddr_t)d;
1895 /* can't write to an M_EXT mbuf since it may be shared */
1896 if (en_makeexclusive(sc, &m, prev) == 0)
1898 *mm = m; /* note: 'd' now invalid */
1902 off = m->m_len % sizeof(u_int32_t);
1906 if (m->m_flags & M_EXT) {
1907 /* can't write to an M_EXT mbuf since it may be shared */
1908 if (en_makeexclusive(sc, &m, prev) == 0)
1910 *mm = m; /* note: 'd' now invalid */
1913 d = mtod(m, u_char *) + m->m_len;
1914 off = sizeof(u_int32_t) - off;
1918 if (nxt != NULL && nxt->m_len == 0) {
1919 /* remove an empty mbuf. this avoids odd byte padding to an empty
1921 m->m_next = nxt = m_free(nxt);
1923 if (nxt == NULL) { /* out of data, zero fill */
1925 continue; /* next "off" */
1927 cp = mtod(nxt, u_char *);
1931 nxt->m_data = (caddr_t)cp;
1933 if (nxt != NULL && nxt->m_len == 0)
1934 m->m_next = m_free(nxt);
1938 #endif /* __FreeBSD__ */
1941 * en_txdma: start trasmit DMA, if possible
1944 STATIC void en_txdma(sc, chan)
1946 struct en_softc *sc;
1951 struct atm_pseudohdr *ap;
1952 struct en_launch launch;
1953 int datalen = 0, dtqneed, len, ncells;
1958 printf("%s: tx%d: starting...\n", sc->sc_dev.dv_xname, chan);
1962 * note: now that txlaunch handles non-word aligned/sized requests
1963 * the only time you can safely set launch.nodma is if you've en_mfix()'d
1964 * the mbuf chain. this happens only if EN_NOTXDMA || !en_dma.
1967 launch.nodma = (EN_NOTXDMA || !en_dma);
1972 * get an mbuf waiting for DMA
1975 launch.t = sc->txslot[chan].q.ifq_head; /* peek at head of queue */
1977 if (launch.t == NULL) {
1979 printf("%s: tx%d: ...done!\n", sc->sc_dev.dv_xname, chan);
1981 return; /* >>> exit here if no data waiting for DMA <<< */
1987 * note: launch.need = # bytes we need to get on the card
1988 * dtqneed = # of DTQs we need for this packet
1989 * launch.mlen = # of bytes in in mbuf chain (<= launch.need)
1992 ap = mtod(launch.t, struct atm_pseudohdr *);
1993 launch.atm_vci = ATM_PH_VCI(ap);
1994 launch.atm_flags = ATM_PH_FLAGS(ap);
1995 launch.aal = ((launch.atm_flags & ATM_PH_AAL5) != 0) ?
1996 MID_TBD_AAL5 : MID_TBD_NOAAL5;
1999 * XXX: have to recompute the length again, even though we already did
2000 * it in en_start(). might as well compute dtqneed here as well, so
2001 * this isn't that bad.
2004 if ((launch.atm_flags & EN_OBHDR) == 0) {
2005 dtqneed = 1; /* header still needs to be added */
2006 launch.need = MID_TBD_SIZE; /* not includeded with mbuf */
2008 dtqneed = 0; /* header on-board, dma with mbuf */
2013 for (tmp = launch.t ; tmp != NULL ; tmp = tmp->m_next) {
2016 cp = mtod(tmp, u_int8_t *);
2017 if (tmp == launch.t) {
2018 len -= sizeof(struct atm_pseudohdr); /* don't count this! */
2019 cp += sizeof(struct atm_pseudohdr);
2023 continue; /* atm_pseudohdr alone in first mbuf */
2025 dtqneed += en_dqneed(sc, (caddr_t) cp, len, 1);
2028 if ((launch.need % sizeof(u_int32_t)) != 0)
2029 dtqneed++; /* need DTQ to FLUSH internal buffer */
2031 if ((launch.atm_flags & EN_OBTRL) == 0) {
2032 if (launch.aal == MID_TBD_AAL5) {
2033 datalen = launch.need - MID_TBD_SIZE;
2034 launch.need += MID_PDU_SIZE; /* AAL5: need PDU tail */
2036 dtqneed++; /* need to work on the end a bit */
2040 * finish calculation of launch.need (need to figure out how much padding
2041 * we will need). launch.need includes MID_TBD_SIZE, but we need to
2042 * remove that to so we can round off properly. we have to add
2043 * MID_TBD_SIZE back in after calculating ncells.
2046 launch.need = roundup(launch.need - MID_TBD_SIZE, MID_ATMDATASZ);
2047 ncells = launch.need / MID_ATMDATASZ;
2048 launch.need += MID_TBD_SIZE;
2050 if (launch.need > EN_TXSZ * 1024) {
2051 printf("%s: tx%d: packet larger than xmit buffer (%d > %d)\n",
2052 sc->sc_dev.dv_xname, chan, launch.need, EN_TXSZ * 1024);
2057 * note: don't use the entire buffer space. if WRTX becomes equal
2058 * to RDTX, the transmitter stops assuming the buffer is empty! --kjc
2060 if (launch.need >= sc->txslot[chan].bfree) {
2061 EN_COUNT(sc->txoutspace);
2063 printf("%s: tx%d: out of transmit space\n", sc->sc_dev.dv_xname, chan);
2065 return; /* >>> exit here if out of obmem buffer space <<< */
2069 * ensure we have enough dtqs to go, if not, wait for more.
2075 if (dtqneed > sc->dtq_free) {
2077 EN_COUNT(sc->txdtqout);
2079 printf("%s: tx%d: out of transmit DTQs\n", sc->sc_dev.dv_xname, chan);
2081 return; /* >>> exit here if out of dtqs <<< */
2085 * it is a go, commit! dequeue mbuf start working on the xfer.
2088 IF_DEQUEUE(&sc->txslot[chan].q, tmp);
2090 if (launch.t != tmp)
2091 panic("en dequeue");
2092 #endif /* EN_DIAG */
2098 EN_COUNT(sc->launch);
2102 if ((launch.atm_flags & EN_OBHDR) == 0) {
2103 EN_COUNT(sc->lheader);
2104 /* store tbd1/tbd2 in host byte order */
2105 launch.tbd1 = MID_TBD_MK1(launch.aal, sc->txspeed[launch.atm_vci], ncells);
2106 launch.tbd2 = MID_TBD_MK2(launch.atm_vci, 0, 0);
2108 if ((launch.atm_flags & EN_OBTRL) == 0 && launch.aal == MID_TBD_AAL5) {
2109 EN_COUNT(sc->ltail);
2110 launch.pdu1 = MID_PDU_MK1(0, 0, datalen); /* host byte order */
2113 en_txlaunch(sc, chan, &launch);
2118 * adjust the top of the mbuf to skip the pseudo atm header
2119 * (and TBD, if present) before passing the packet to bpf,
2120 * restore it afterwards.
2122 int size = sizeof(struct atm_pseudohdr);
2123 if (launch.atm_flags & EN_OBHDR)
2124 size += MID_TBD_SIZE;
2126 launch.t->m_data += size;
2127 launch.t->m_len -= size;
2129 BPF_MTAP(ifp, launch.t);
2131 launch.t->m_data -= size;
2132 launch.t->m_len += size;
2134 #endif /* NBPF > 0 */
2136 * do some housekeeping and get the next packet
2139 sc->txslot[chan].bfree -= launch.need;
2140 IF_ENQUEUE(&sc->txslot[chan].indma, launch.t);
2144 * END of txdma loop!
2152 IF_DEQUEUE(&sc->txslot[chan].q, tmp);
2153 if (launch.t != tmp)
2154 panic("en dequeue drop");
2156 sc->txslot[chan].mbsize -= launch.mlen;
2162 * en_txlaunch: launch an mbuf into the dma pool!
2165 STATIC void en_txlaunch(sc, chan, l)
2167 struct en_softc *sc;
2169 struct en_launch *l;
2173 u_int32_t cur = sc->txslot[chan].cur,
2174 start = sc->txslot[chan].start,
2175 stop = sc->txslot[chan].stop,
2176 dma, *data, *datastop, count, bcode;
2177 int pad, addtail, need, len, needalign, cnt, end, mx;
2182 * need = # bytes card still needs (decr. to zero)
2183 * len = # of bytes left in current mbuf
2184 * cur = our current pointer
2185 * dma = last place we programmed into the DMA
2186 * data = pointer into data area of mbuf that needs to go next
2187 * cnt = # of bytes to transfer in this DTQ
2188 * bcode/count = DMA burst code, and chip's version of cnt
2190 * a single buffer can require up to 5 DTQs depending on its size
2191 * and alignment requirements. the 5 possible requests are:
2192 * [1] 1, 2, or 3 byte DMA to align src data pointer to word boundary
2193 * [2] alburst DMA to align src data pointer to bestburstlen
2194 * [3] 1 or more bestburstlen DMAs
2195 * [4] clean up burst (to last word boundary)
2196 * [5] 1, 2, or 3 byte final clean up DMA
2201 addtail = (l->atm_flags & EN_OBTRL) == 0; /* add a tail? */
2204 if ((need - MID_TBD_SIZE) % MID_ATMDATASZ)
2205 printf("%s: tx%d: bogus trasmit needs (%d)\n", sc->sc_dev.dv_xname, chan,
2209 printf("%s: tx%d: launch mbuf %p! cur=0x%x[%d], need=%d, addtail=%d\n",
2210 sc->sc_dev.dv_xname, chan, l->t, cur, (cur-start)/4, need, addtail);
2211 count = EN_READ(sc, MIDX_PLACE(chan));
2212 printf(" HW: base_address=0x%x, size=%d, read=%d, descstart=%d\n",
2213 MIDX_BASE(count), MIDX_SZ(count), EN_READ(sc, MIDX_READPTR(chan)),
2214 EN_READ(sc, MIDX_DESCSTART(chan)));
2218 * do we need to insert the TBD by hand?
2219 * note that tbd1/tbd2/pdu1 are in host byte order.
2222 if ((l->atm_flags & EN_OBHDR) == 0) {
2224 printf("%s: tx%d: insert header 0x%x 0x%x\n", sc->sc_dev.dv_xname,
2225 chan, l->tbd1, l->tbd2);
2227 EN_WRITE(sc, cur, l->tbd1);
2228 EN_WRAPADD(start, stop, cur, 4);
2229 EN_WRITE(sc, cur, l->tbd2);
2230 EN_WRAPADD(start, stop, cur, 4);
2235 * now do the mbufs...
2238 for (tmp = l->t ; tmp != NULL ; tmp = tmp->m_next) {
2240 /* get pointer to data and length */
2241 data = mtod(tmp, u_int32_t *);
2244 data += sizeof(struct atm_pseudohdr)/sizeof(u_int32_t);
2245 len -= sizeof(struct atm_pseudohdr);
2248 /* now, determine if we should copy it */
2249 if (l->nodma || (len < EN_MINDMA &&
2250 (len % 4) == 0 && ((uintptr_t) (void *) data % 4) == 0 &&
2254 * roundup len: the only time this will change the value of len
2255 * is when l->nodma is true, tmp is the last mbuf, and there is
2256 * a non-word number of bytes to transmit. in this case it is
2257 * safe to round up because we've en_mfix'd the mbuf (so the first
2258 * byte is word aligned there must be enough free bytes at the end
2259 * to round off to the next word boundary)...
2261 len = roundup(len, sizeof(u_int32_t));
2262 datastop = data + (len / sizeof(u_int32_t));
2263 /* copy loop: preserve byte order!!! use WRITEDAT */
2264 while (data != datastop) {
2265 EN_WRITEDAT(sc, cur, *data);
2267 EN_WRAPADD(start, stop, cur, 4);
2271 printf("%s: tx%d: copied %d bytes (%d left, cur now 0x%x)\n",
2272 sc->sc_dev.dv_xname, chan, len, need, cur);
2274 continue; /* continue on to next mbuf */
2277 /* going to do DMA, first make sure the dtq is in sync. */
2279 EN_DTQADD(sc, WORD_IDX(start,cur), chan, MIDDMA_JK, 0, 0, 0);
2281 printf("%s: tx%d: dtq_sync: advance pointer to %d\n",
2282 sc->sc_dev.dv_xname, chan, cur);
2287 * if this is the last buffer, and it looks like we are going to need to
2288 * flush the internal buffer, can we extend the length of this mbuf to
2292 if (tmp->m_next == NULL) {
2293 cnt = (need - len) % sizeof(u_int32_t);
2294 if (cnt && M_TRAILINGSPACE(tmp) >= cnt)
2295 len += cnt; /* pad for FLUSH */
2298 #if !defined(MIDWAY_ENIONLY)
2301 * the adaptec DMA engine is smart and handles everything for us.
2304 if (sc->is_adaptec) {
2305 /* need to DMA "len" bytes out to card */
2307 EN_WRAPADD(start, stop, cur, len);
2309 printf("%s: tx%d: adp_dma %d bytes (%d left, cur now 0x%x)\n",
2310 sc->sc_dev.dv_xname, chan, len, need, cur);
2312 end = (need == 0) ? MID_DMA_END : 0;
2313 EN_DTQADD(sc, len, chan, 0, vtophys(data), l->mlen, end);
2316 dma = cur; /* update dma pointer */
2319 #endif /* !MIDWAY_ENIONLY */
2321 #if !defined(MIDWAY_ADPONLY)
2324 * the ENI DMA engine is not so smart and need more help from us
2327 /* do we need to do a DMA op to align to word boundary? */
2328 needalign = (uintptr_t) (void *) data % sizeof(u_int32_t);
2330 EN_COUNT(sc->headbyte);
2331 cnt = sizeof(u_int32_t) - needalign;
2332 if (cnt == 2 && len >= cnt) {
2334 bcode = MIDDMA_2BYTE;
2336 cnt = min(cnt, len); /* prevent overflow */
2338 bcode = MIDDMA_BYTE;
2341 EN_WRAPADD(start, stop, cur, cnt);
2343 printf("%s: tx%d: small al_dma %d bytes (%d left, cur now 0x%x)\n",
2344 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2347 end = (need == 0) ? MID_DMA_END : 0;
2348 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2351 data = (u_int32_t *) ((u_char *)data + cnt);
2354 /* do we need to do a DMA op to align? */
2356 (needalign = (((uintptr_t) (void *) data) & sc->bestburstmask)) != 0
2357 && len >= sizeof(u_int32_t)) {
2358 cnt = sc->bestburstlen - needalign;
2359 mx = len & ~(sizeof(u_int32_t)-1); /* don't go past end */
2362 count = cnt / sizeof(u_int32_t);
2363 bcode = MIDDMA_WORD;
2365 count = cnt / sizeof(u_int32_t);
2366 bcode = en_dmaplan[count].bcode;
2367 count = cnt >> en_dmaplan[count].divshift;
2370 EN_WRAPADD(start, stop, cur, cnt);
2372 printf("%s: tx%d: al_dma %d bytes (%d left, cur now 0x%x)\n",
2373 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2376 end = (need == 0) ? MID_DMA_END : 0;
2377 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2380 data = (u_int32_t *) ((u_char *)data + cnt);
2383 /* do we need to do a max-sized burst? */
2384 if (len >= sc->bestburstlen) {
2385 count = len >> sc->bestburstshift;
2386 cnt = count << sc->bestburstshift;
2387 bcode = sc->bestburstcode;
2389 EN_WRAPADD(start, stop, cur, cnt);
2391 printf("%s: tx%d: best_dma %d bytes (%d left, cur now 0x%x)\n",
2392 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2395 end = (need == 0) ? MID_DMA_END : 0;
2396 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2399 data = (u_int32_t *) ((u_char *)data + cnt);
2402 /* do we need to do a cleanup burst? */
2403 cnt = len & ~(sizeof(u_int32_t)-1);
2405 count = cnt / sizeof(u_int32_t);
2406 bcode = en_dmaplan[count].bcode;
2407 count = cnt >> en_dmaplan[count].divshift;
2409 EN_WRAPADD(start, stop, cur, cnt);
2411 printf("%s: tx%d: cleanup_dma %d bytes (%d left, cur now 0x%x)\n",
2412 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2415 end = (need == 0) ? MID_DMA_END : 0;
2416 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2419 data = (u_int32_t *) ((u_char *)data + cnt);
2422 /* any word fragments left? */
2424 EN_COUNT(sc->tailbyte);
2427 bcode = MIDDMA_2BYTE; /* use 2byte mode */
2430 bcode = MIDDMA_BYTE; /* use 1 byte mode */
2433 EN_WRAPADD(start, stop, cur, len);
2435 printf("%s: tx%d: byte cleanup_dma %d bytes (%d left, cur now 0x%x)\n",
2436 sc->sc_dev.dv_xname, chan, len, need, cur);
2438 end = (need == 0) ? MID_DMA_END : 0;
2439 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2444 dma = cur; /* update dma pointer */
2445 #endif /* !MIDWAY_ADPONLY */
2447 } /* next mbuf, please */
2450 * all mbuf data has been copied out to the obmem (or set up to be DMAd).
2451 * if the trailer or padding needs to be put in, do it now.
2453 * NOTE: experimental results reveal the following fact:
2454 * if you DMA "X" bytes to the card, where X is not a multiple of 4,
2455 * then the card will internally buffer the last (X % 4) bytes (in
2456 * hopes of getting (4 - (X % 4)) more bytes to make a complete word).
2457 * it is imporant to make sure we don't leave any important data in
2458 * this internal buffer because it is discarded on the last (end) DTQ.
2459 * one way to do this is to DMA in (4 - (X % 4)) more bytes to flush
2460 * the darn thing out.
2465 pad = need % sizeof(u_int32_t);
2468 * FLUSH internal data buffer. pad out with random data from the front
2469 * of the mbuf chain...
2471 bcode = (sc->is_adaptec) ? 0 : MIDDMA_BYTE;
2472 EN_COUNT(sc->tailflush);
2473 EN_WRAPADD(start, stop, cur, pad);
2474 EN_DTQADD(sc, pad, chan, bcode, vtophys(l->t->m_data), 0, 0);
2477 printf("%s: tx%d: pad/FLUSH dma %d bytes (%d left, cur now 0x%x)\n",
2478 sc->sc_dev.dv_xname, chan, pad, need, cur);
2483 pad = need / sizeof(u_int32_t); /* round *down* */
2484 if (l->aal == MID_TBD_AAL5)
2487 printf("%s: tx%d: padding %d bytes (cur now 0x%x)\n",
2488 sc->sc_dev.dv_xname, chan, pad * sizeof(u_int32_t), cur);
2491 EN_WRITEDAT(sc, cur, 0); /* no byte order issues with zero */
2492 EN_WRAPADD(start, stop, cur, 4);
2494 if (l->aal == MID_TBD_AAL5) {
2495 EN_WRITE(sc, cur, l->pdu1); /* in host byte order */
2496 EN_WRAPADD(start, stop, cur, 8);
2500 if (addtail || dma != cur) {
2501 /* write final descritor */
2502 EN_DTQADD(sc, WORD_IDX(start,cur), chan, MIDDMA_JK, 0,
2503 l->mlen, MID_DMA_END);
2504 /* dma = cur; */ /* not necessary since we are done */
2508 /* update current pointer */
2509 sc->txslot[chan].cur = cur;
2511 printf("%s: tx%d: DONE! cur now = 0x%x\n",
2512 sc->sc_dev.dv_xname, chan, cur);
2523 EN_INTR_TYPE en_intr(arg)
2528 struct en_softc *sc = (struct en_softc *) arg;
2530 struct atm_pseudohdr ah;
2532 u_int32_t reg, kick, val, mask, chip, vci, slot, dtq, drq;
2533 int lcv, idx, need_softserv = 0;
2535 reg = EN_READ(sc, MID_INTACK);
2537 if ((reg & MID_INT_ANY) == 0)
2538 EN_INTR_RET(0); /* not us */
2541 printf("%s: interrupt=0x%b\n", sc->sc_dev.dv_xname, reg, MID_INTBITS);
2545 * unexpected errors that need a reset
2548 if ((reg & (MID_INT_IDENT|MID_INT_LERR|MID_INT_DMA_ERR|MID_INT_SUNI)) != 0) {
2549 printf("%s: unexpected interrupt=0x%b, resetting card\n",
2550 sc->sc_dev.dv_xname, reg, MID_INTBITS);
2553 #if defined(__DragonFly__) || defined(__FreeBSD__)
2554 Debugger("en: unexpected error");
2559 sc->enif.if_flags &= ~IFF_RUNNING; /* FREEZE! */
2564 EN_INTR_RET(1); /* for us */
2567 /*******************
2571 kick = 0; /* bitmask of channels to kick */
2572 if (reg & MID_INT_TX) { /* TX done! */
2575 * check for tx complete, if detected then this means that some space
2576 * has come free on the card. we must account for it and arrange to
2577 * kick the channel to life (in case it is stalled waiting on the card).
2579 for (mask = 1, lcv = 0 ; lcv < EN_NTX ; lcv++, mask = mask * 2) {
2580 if (reg & MID_TXCHAN(lcv)) {
2581 kick = kick | mask; /* want to kick later */
2582 val = EN_READ(sc, MIDX_READPTR(lcv)); /* current read pointer */
2583 val = (val * sizeof(u_int32_t)) + sc->txslot[lcv].start;
2584 /* convert to offset */
2585 if (val > sc->txslot[lcv].cur)
2586 sc->txslot[lcv].bfree = val - sc->txslot[lcv].cur;
2588 sc->txslot[lcv].bfree = (val + (EN_TXSZ*1024)) - sc->txslot[lcv].cur;
2590 printf("%s: tx%d: trasmit done. %d bytes now free in buffer\n",
2591 sc->sc_dev.dv_xname, lcv, sc->txslot[lcv].bfree);
2597 if (reg & MID_INT_DMA_TX) { /* TX DMA done! */
2600 * check for TX DMA complete, if detected then this means that some DTQs
2601 * are now free. it also means some indma mbufs can be freed.
2602 * if we needed DTQs, kick all channels.
2604 val = EN_READ(sc, MID_DMA_RDTX); /* chip's current location */
2605 idx = MID_DTQ_A2REG(sc->dtq_chip);/* where we last saw chip */
2606 if (sc->need_dtqs) {
2607 kick = MID_NTX_CH - 1; /* assume power of 2, kick all! */
2608 sc->need_dtqs = 0; /* recalculated in "kick" loop below */
2610 printf("%s: cleared need DTQ condition\n", sc->sc_dev.dv_xname);
2613 while (idx != val) {
2615 if ((dtq = sc->dtq[idx]) != 0) {
2616 sc->dtq[idx] = 0; /* don't forget to zero it out when done */
2617 slot = EN_DQ_SLOT(dtq);
2618 IF_DEQUEUE(&sc->txslot[slot].indma, m);
2619 if (!m) panic("enintr: dtqsync");
2620 sc->txslot[slot].mbsize -= EN_DQ_LEN(dtq);
2622 printf("%s: tx%d: free %d dma bytes, mbsize now %d\n",
2623 sc->sc_dev.dv_xname, slot, EN_DQ_LEN(dtq),
2624 sc->txslot[slot].mbsize);
2628 EN_WRAPADD(0, MID_DTQ_N, idx, 1);
2630 sc->dtq_chip = MID_DTQ_REG2A(val); /* sync softc */
2635 * kick xmit channels as needed
2640 printf("%s: tx kick mask = 0x%x\n", sc->sc_dev.dv_xname, kick);
2642 for (mask = 1, lcv = 0 ; lcv < EN_NTX ; lcv++, mask = mask * 2) {
2643 if ((kick & mask) && sc->txslot[lcv].q.ifq_head) {
2644 en_txdma(sc, lcv); /* kick it! */
2646 } /* for each slot */
2650 /*******************
2655 * check for RX DMA complete, and pass the data "upstairs"
2658 if (reg & MID_INT_DMA_RX) {
2659 val = EN_READ(sc, MID_DMA_RDRX); /* chip's current location */
2660 idx = MID_DRQ_A2REG(sc->drq_chip);/* where we last saw chip */
2661 while (idx != val) {
2663 if ((drq = sc->drq[idx]) != 0) {
2664 sc->drq[idx] = 0; /* don't forget to zero it out when done */
2665 slot = EN_DQ_SLOT(drq);
2666 if (EN_DQ_LEN(drq) == 0) { /* "JK" trash DMA? */
2669 IF_DEQUEUE(&sc->rxslot[slot].indma, m);
2671 panic("enintr: drqsync: %s: lost mbuf in slot %d!",
2672 sc->sc_dev.dv_xname, slot);
2674 /* do something with this mbuf */
2675 if (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) { /* drain? */
2678 vci = sc->rxslot[slot].atm_vci;
2679 if (sc->rxslot[slot].indma.ifq_head == NULL &&
2680 sc->rxslot[slot].q.ifq_head == NULL &&
2681 (EN_READ(sc, MID_VC(vci)) & MIDV_INSERVICE) == 0 &&
2682 (sc->rxslot[slot].oth_flags & ENOTHER_SWSL) == 0) {
2683 sc->rxslot[slot].oth_flags = ENOTHER_FREE; /* done drain */
2684 sc->rxslot[slot].atm_vci = RX_NONE;
2685 sc->rxvc2slot[vci] = RX_NONE;
2687 printf("%s: rx%d: VCI %d now free\n", sc->sc_dev.dv_xname,
2691 } else if (m != NULL) {
2692 ATM_PH_FLAGS(&ah) = sc->rxslot[slot].atm_flags;
2693 ATM_PH_VPI(&ah) = 0;
2694 ATM_PH_SETVCI(&ah, sc->rxslot[slot].atm_vci);
2696 printf("%s: rx%d: rxvci%d: atm_input, mbuf %p, len %d, hand %p\n",
2697 sc->sc_dev.dv_xname, slot, sc->rxslot[slot].atm_vci, m,
2698 EN_DQ_LEN(drq), sc->rxslot[slot].rxhand);
2709 atm_input(ifp, &ah, m, sc->rxslot[slot].rxhand);
2713 EN_WRAPADD(0, MID_DRQ_N, idx, 1);
2715 sc->drq_chip = MID_DRQ_REG2A(val); /* sync softc */
2717 if (sc->need_drqs) { /* true if we had a DRQ shortage */
2721 printf("%s: cleared need DRQ condition\n", sc->sc_dev.dv_xname);
2727 * handle service interrupts
2730 if (reg & MID_INT_SERVICE) {
2731 chip = MID_SL_REG2A(EN_READ(sc, MID_SERV_WRITE));
2733 while (sc->hwslistp != chip) {
2735 /* fetch and remove it from hardware service list */
2736 vci = EN_READ(sc, sc->hwslistp);
2737 EN_WRAPADD(MID_SLOFF, MID_SLEND, sc->hwslistp, 4);/* advance hw ptr */
2738 slot = sc->rxvc2slot[vci];
2739 if (slot == RX_NONE) {
2741 printf("%s: unexpected rx interrupt on VCI %d\n",
2742 sc->sc_dev.dv_xname, vci);
2744 EN_WRITE(sc, MID_VC(vci), MIDV_TRASH); /* rx off, damn it! */
2745 continue; /* next */
2747 EN_WRITE(sc, MID_VC(vci), sc->rxslot[slot].mode); /* remove from hwsl */
2748 EN_COUNT(sc->hwpull);
2751 printf("%s: pulled VCI %d off hwslist\n", sc->sc_dev.dv_xname, vci);
2754 /* add it to the software service list (if needed) */
2755 if ((sc->rxslot[slot].oth_flags & ENOTHER_SWSL) == 0) {
2756 EN_COUNT(sc->swadd);
2758 sc->rxslot[slot].oth_flags |= ENOTHER_SWSL;
2759 sc->swslist[sc->swsl_tail] = slot;
2760 EN_WRAPADD(0, MID_SL_N, sc->swsl_tail, 1);
2763 printf("%s: added VCI %d to swslist\n", sc->sc_dev.dv_xname, vci);
2770 * now service (function too big to include here)
2780 if (reg & MID_INT_DMA_OVR) {
2781 EN_COUNT(sc->dmaovr);
2783 printf("%s: MID_INT_DMA_OVR\n", sc->sc_dev.dv_xname);
2786 reg = EN_READ(sc, MID_STAT);
2788 sc->otrash += MID_OTRASH(reg);
2789 sc->vtrash += MID_VTRASH(reg);
2792 EN_INTR_RET(1); /* for us */
2797 * en_service: handle a service interrupt
2799 * Q: why do we need a software service list?
2801 * A: if we remove a VCI from the hardware list and we find that we are
2802 * out of DRQs we must defer processing until some DRQs become free.
2803 * so we must remember to look at this RX VCI/slot later, but we can't
2804 * put it back on the hardware service list (since that isn't allowed).
2805 * so we instead save it on the software service list. it would be nice
2806 * if we could peek at the VCI on top of the hwservice list without removing
2807 * it, however this leads to a race condition: if we peek at it and
2808 * decide we are done with it new data could come in before we have a
2809 * chance to remove it from the hwslist. by the time we get it out of
2810 * the list the interrupt for the new data will be lost. oops!
2814 STATIC void en_service(sc)
2816 struct en_softc *sc;
2819 struct mbuf *m, *tmp;
2820 u_int32_t cur, dstart, rbd, pdu, *sav, dma, bcode, count, *data, *datastop;
2821 u_int32_t start, stop, cnt, needalign;
2822 int slot, raw, aal5, llc, vci, fill, mlen, tlen, drqneed, need, needfill, end;
2824 aal5 = 0; /* Silence gcc */
2826 if (sc->swsl_size == 0) {
2828 printf("%s: en_service done\n", sc->sc_dev.dv_xname);
2830 return; /* >>> exit here if swsl now empty <<< */
2834 * get slot/vci to service
2837 slot = sc->swslist[sc->swsl_head];
2838 vci = sc->rxslot[slot].atm_vci;
2840 if (sc->rxvc2slot[vci] != slot) panic("en_service rx slot/vci sync");
2844 * determine our mode and if we've got any work to do
2847 raw = sc->rxslot[slot].oth_flags & ENOTHER_RAW;
2848 start= sc->rxslot[slot].start;
2849 stop= sc->rxslot[slot].stop;
2850 cur = sc->rxslot[slot].cur;
2853 printf("%s: rx%d: service vci=%d raw=%d start/stop/cur=0x%x 0x%x 0x%x\n",
2854 sc->sc_dev.dv_xname, slot, vci, raw, start, stop, cur);
2858 dstart = MIDV_DSTART(EN_READ(sc, MID_DST_RP(vci)));
2859 dstart = (dstart * sizeof(u_int32_t)) + start;
2861 /* check to see if there is any data at all */
2862 if (dstart == cur) {
2863 defer: /* defer processing */
2864 EN_WRAPADD(0, MID_SL_N, sc->swsl_head, 1);
2865 sc->rxslot[slot].oth_flags &= ~ENOTHER_SWSL;
2867 /* >>> remove from swslist <<< */
2869 printf("%s: rx%d: remove vci %d from swslist\n",
2870 sc->sc_dev.dv_xname, slot, vci);
2876 * figure out how many bytes we need
2877 * [mlen = # bytes to go in mbufs, fill = # bytes to dump (MIDDMA_JK)]
2882 /* raw mode (aka boodi mode) */
2885 mlen = dstart - cur;
2887 mlen = (dstart + (EN_RXSZ*1024)) - cur;
2889 if (mlen < sc->rxslot[slot].raw_threshold)
2890 goto defer; /* too little data to deal with */
2895 aal5 = (sc->rxslot[slot].atm_flags & ATM_PH_AAL5);
2896 llc = (aal5 && (sc->rxslot[slot].atm_flags & ATM_PH_LLCSNAP)) ? 1 : 0;
2897 rbd = EN_READ(sc, cur);
2898 if (MID_RBD_ID(rbd) != MID_RBD_STDID)
2899 panic("en_service: id mismatch");
2901 if (rbd & MID_RBD_T) {
2902 mlen = 0; /* we've got trash */
2903 fill = MID_RBD_SIZE;
2904 EN_COUNT(sc->ttrash);
2906 printf("RX overflow lost %d cells!\n", MID_RBD_CNT(rbd));
2909 mlen = MID_RBD_SIZE + MID_CHDR_SIZE + MID_ATMDATASZ; /* 1 cell (ick!) */
2914 tlen = (MID_RBD_CNT(rbd) * MID_ATMDATASZ) + MID_RBD_SIZE;
2915 pdu = cur + tlen - MID_PDU_SIZE;
2917 pdu -= (EN_RXSZ*1024);
2918 pdu = EN_READ(sc, pdu); /* get PDU in correct byte order */
2919 fill = tlen - MID_RBD_SIZE - MID_PDU_LEN(pdu);
2920 if (fill < 0 || (rbd & MID_RBD_CRCERR) != 0) {
2921 static int first = 1;
2924 printf("%s: %s, dropping frame\n", sc->sc_dev.dv_xname,
2925 (rbd & MID_RBD_CRCERR) ?
2926 "CRC error" : "invalid AAL5 PDU length");
2927 printf("%s: got %d cells (%d bytes), AAL5 len is %d bytes (pdu=0x%x)\n",
2928 sc->sc_dev.dv_xname, MID_RBD_CNT(rbd),
2929 tlen - MID_RBD_SIZE, MID_PDU_LEN(pdu), pdu);
2931 printf("CRC error report disabled from now on!\n");
2947 * now allocate mbufs for mlen bytes of data, if out of mbufs, trash all
2950 * 1. it is possible that we've already allocated an mbuf for this pkt
2951 * but ran out of DRQs, in which case we saved the allocated mbuf on
2953 * 2. if we save an mbuf in "q" we store the "cur" (pointer) in the front
2954 * of the mbuf as an identity (that we can check later), and we also
2955 * store drqneed (so we don't have to recompute it).
2956 * 3. after this block of code, if m is still NULL then we ran out of mbufs
2959 m = sc->rxslot[slot].q.ifq_head;
2962 sav = mtod(m, u_int32_t *);
2963 if (sav[0] != cur) {
2965 printf("%s: rx%d: q'ed mbuf %p not ours\n",
2966 sc->sc_dev.dv_xname, slot, m);
2968 m = NULL; /* wasn't ours */
2969 EN_COUNT(sc->rxqnotus);
2971 EN_COUNT(sc->rxqus);
2972 IF_DEQUEUE(&sc->rxslot[slot].q, m);
2975 printf("%s: rx%d: recovered q'ed mbuf %p (drqneed=%d)\n",
2976 sc->sc_dev.dv_xname, slot, m, drqneed);
2981 if (mlen != 0 && m == NULL) {
2982 m = en_mget(sc, mlen, &drqneed); /* allocate! */
2986 EN_COUNT(sc->rxmbufout);
2988 printf("%s: rx%d: out of mbufs\n", sc->sc_dev.dv_xname, slot);
2992 printf("%s: rx%d: allocate mbuf %p, mlen=%d, drqneed=%d\n",
2993 sc->sc_dev.dv_xname, slot, m, mlen, drqneed);
2998 printf("%s: rx%d: VCI %d, mbuf_chain %p, mlen %d, fill %d\n",
2999 sc->sc_dev.dv_xname, slot, vci, m, mlen, fill);
3003 * now check to see if we've got the DRQs needed. if we are out of
3004 * DRQs we must quit (saving our mbuf, if we've got one).
3007 needfill = (fill) ? 1 : 0;
3008 if (drqneed + needfill > sc->drq_free) {
3009 sc->need_drqs = 1; /* flag condition */
3011 EN_COUNT(sc->rxoutboth);
3013 printf("%s: rx%d: out of DRQs *and* mbufs!\n", sc->sc_dev.dv_xname, slot);
3015 return; /* >>> exit here if out of both mbufs and DRQs <<< */
3017 sav = mtod(m, u_int32_t *);
3020 IF_ENQUEUE(&sc->rxslot[slot].q, m);
3021 EN_COUNT(sc->rxdrqout);
3023 printf("%s: rx%d: out of DRQs\n", sc->sc_dev.dv_xname, slot);
3025 return; /* >>> exit here if out of DRQs <<< */
3029 * at this point all resources have been allocated and we are commited
3030 * to servicing this slot.
3032 * dma = last location we told chip about
3033 * cur = current location
3034 * mlen = space in the mbuf we want
3035 * need = bytes to xfer in (decrs to zero)
3036 * fill = how much fill we need
3037 * tlen = how much data to transfer to this mbuf
3038 * cnt/bcode/count = <same as xmit>
3040 * 'needfill' not used after this point
3043 dma = cur; /* dma = last location we told chip about */
3044 need = roundup(mlen, sizeof(u_int32_t));
3045 fill = fill - (need - mlen); /* note: may invalidate 'needfill' */
3047 for (tmp = m ; tmp != NULL && need > 0 ; tmp = tmp->m_next) {
3048 tlen = roundup(tmp->m_len, sizeof(u_int32_t)); /* m_len set by en_mget */
3049 data = mtod(tmp, u_int32_t *);
3052 printf("%s: rx%d: load mbuf %p, m_len=%d, m_data=%p, tlen=%d\n",
3053 sc->sc_dev.dv_xname, slot, tmp, tmp->m_len, tmp->m_data, tlen);
3057 if (EN_NORXDMA || !en_dma || tlen < EN_MINDMA) {
3058 datastop = (u_int32_t *)((u_char *) data + tlen);
3059 /* copy loop: preserve byte order!!! use READDAT */
3060 while (data != datastop) {
3061 *data = EN_READDAT(sc, cur);
3063 EN_WRAPADD(start, stop, cur, 4);
3067 printf("%s: rx%d: vci%d: copied %d bytes (%d left)\n",
3068 sc->sc_dev.dv_xname, slot, vci, tlen, need);
3073 /* DMA data (check to see if we need to sync DRQ first) */
3075 EN_DRQADD(sc, WORD_IDX(start,cur), vci, MIDDMA_JK, 0, 0, 0, 0);
3077 printf("%s: rx%d: vci%d: drq_sync: advance pointer to %d\n",
3078 sc->sc_dev.dv_xname, slot, vci, cur);
3082 #if !defined(MIDWAY_ENIONLY)
3085 * the adaptec DMA engine is smart and handles everything for us.
3088 if (sc->is_adaptec) {
3090 EN_WRAPADD(start, stop, cur, tlen);
3092 printf("%s: rx%d: vci%d: adp_dma %d bytes (%d left)\n",
3093 sc->sc_dev.dv_xname, slot, vci, tlen, need);
3095 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3096 EN_DRQADD(sc, tlen, vci, 0, vtophys(data), mlen, slot, end);
3099 dma = cur; /* update dma pointer */
3102 #endif /* !MIDWAY_ENIONLY */
3105 #if !defined(MIDWAY_ADPONLY)
3108 * the ENI DMA engine is not so smart and need more help from us
3111 /* do we need to do a DMA op to align? */
3113 (needalign = (((uintptr_t) (void *) data) & sc->bestburstmask)) != 0) {
3114 cnt = sc->bestburstlen - needalign;
3117 count = cnt / sizeof(u_int32_t);
3118 bcode = MIDDMA_WORD;
3120 count = cnt / sizeof(u_int32_t);
3121 bcode = en_dmaplan[count].bcode;
3122 count = cnt >> en_dmaplan[count].divshift;
3125 EN_WRAPADD(start, stop, cur, cnt);
3127 printf("%s: rx%d: vci%d: al_dma %d bytes (%d left)\n",
3128 sc->sc_dev.dv_xname, slot, vci, cnt, need);
3131 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3132 EN_DRQADD(sc, count, vci, bcode, vtophys(data), mlen, slot, end);
3135 data = (u_int32_t *)((u_char *) data + cnt);
3138 /* do we need a max-sized burst? */
3139 if (tlen >= sc->bestburstlen) {
3140 count = tlen >> sc->bestburstshift;
3141 cnt = count << sc->bestburstshift;
3142 bcode = sc->bestburstcode;
3144 EN_WRAPADD(start, stop, cur, cnt);
3146 printf("%s: rx%d: vci%d: best_dma %d bytes (%d left)\n",
3147 sc->sc_dev.dv_xname, slot, vci, cnt, need);
3150 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3151 EN_DRQADD(sc, count, vci, bcode, vtophys(data), mlen, slot, end);
3154 data = (u_int32_t *)((u_char *) data + cnt);
3157 /* do we need to do a cleanup burst? */
3159 count = tlen / sizeof(u_int32_t);
3160 bcode = en_dmaplan[count].bcode;
3161 count = tlen >> en_dmaplan[count].divshift;
3163 EN_WRAPADD(start, stop, cur, tlen);
3165 printf("%s: rx%d: vci%d: cleanup_dma %d bytes (%d left)\n",
3166 sc->sc_dev.dv_xname, slot, vci, tlen, need);
3168 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3169 EN_DRQADD(sc, count, vci, bcode, vtophys(data), mlen, slot, end);
3174 dma = cur; /* update dma pointer */
3176 #endif /* !MIDWAY_ADPONLY */
3181 if (fill || dma != cur) {
3184 printf("%s: rx%d: vci%d: skipping %d bytes of fill\n",
3185 sc->sc_dev.dv_xname, slot, vci, fill);
3187 printf("%s: rx%d: vci%d: syncing chip from 0x%x to 0x%x [cur]\n",
3188 sc->sc_dev.dv_xname, slot, vci, dma, cur);
3190 EN_WRAPADD(start, stop, cur, fill);
3191 EN_DRQADD(sc, WORD_IDX(start,cur), vci, MIDDMA_JK, 0, mlen,
3193 /* dma = cur; */ /* not necessary since we are done */
3197 * done, remove stuff we don't want to pass up:
3198 * raw mode (boodi mode): pass everything up for later processing
3200 * aal0: remove RBD + cell header
3207 if (!aal5) cnt += MID_CHDR_SIZE;
3208 m->m_len -= cnt; /* chop! */
3209 m->m_pkthdr.len -= cnt;
3212 IF_ENQUEUE(&sc->rxslot[slot].indma, m);
3214 sc->rxslot[slot].cur = cur; /* update master copy of 'cur' */
3217 printf("%s: rx%d: vci%d: DONE! cur now =0x%x\n",
3218 sc->sc_dev.dv_xname, slot, vci, cur);
3221 goto same_vci; /* get next packet in this slot */
3227 * functions we can call from ddb
3231 * en_dump: dump the state
3234 #define END_SWSL 0x00000040 /* swsl state */
3235 #define END_DRQ 0x00000020 /* drq state */
3236 #define END_DTQ 0x00000010 /* dtq state */
3237 #define END_RX 0x00000008 /* rx state */
3238 #define END_TX 0x00000004 /* tx state */
3239 #define END_MREGS 0x00000002 /* registers */
3240 #define END_STATS 0x00000001 /* dump stats */
3242 #define END_BITS "\20\7SWSL\6DRQ\5DTQ\4RX\3TX\2MREGS\1STATS"
3244 /* Do not staticize - meant for calling from DDB! */
3245 int en_dump(unit, level)
3250 struct en_softc *sc;
3254 for (lcv = 0 ; lcv < en_cd.cd_ndevs ; lcv++) {
3255 sc = (struct en_softc *) en_cd.cd_devs[lcv];
3256 if (sc == NULL) continue;
3257 if (unit != -1 && unit != lcv)
3260 printf("dumping device %s at level 0x%b\n", sc->sc_dev.dv_xname, level,
3263 if (sc->dtq_us == 0) {
3264 printf("<hasn't been en_init'd yet>\n");
3268 if (level & END_STATS) {
3269 printf(" en_stats:\n");
3270 printf(" %d mfix (%d failed); %d/%d head/tail byte DMAs, %d flushes\n",
3271 sc->mfix, sc->mfixfail, sc->headbyte, sc->tailbyte, sc->tailflush);
3272 printf(" %d rx dma overflow interrupts\n", sc->dmaovr);
3273 printf(" %d times we ran out of TX space and stalled\n",
3275 printf(" %d times we ran out of DTQs\n", sc->txdtqout);
3276 printf(" %d times we launched a packet\n", sc->launch);
3277 printf(" %d times we launched without on-board header\n", sc->lheader);
3278 printf(" %d times we launched without on-board tail\n", sc->ltail);
3279 printf(" %d times we pulled the hw service list\n", sc->hwpull);
3280 printf(" %d times we pushed a vci on the sw service list\n",
3282 printf(" %d times RX pulled an mbuf from Q that wasn't ours\n",
3284 printf(" %d times RX pulled a good mbuf from Q\n", sc->rxqus);
3285 printf(" %d times we ran out of mbufs *and* DRQs\n", sc->rxoutboth);
3286 printf(" %d times we ran out of DRQs\n", sc->rxdrqout);
3288 printf(" %d trasmit packets dropped due to mbsize\n", sc->txmbovr);
3289 printf(" %d cells trashed due to turned off rxvc\n", sc->vtrash);
3290 printf(" %d cells trashed due to totally full buffer\n", sc->otrash);
3291 printf(" %d cells trashed due almost full buffer\n", sc->ttrash);
3292 printf(" %d rx mbuf allocation failures\n", sc->rxmbufout);
3293 #if defined(NATM) && defined(NATM_STAT)
3294 printf(" natmintr so_rcv: ok/drop cnt: %d/%d, ok/drop bytes: %d/%d\n",
3295 natm_sookcnt, natm_sodropcnt, natm_sookbytes, natm_sodropbytes);
3299 if (level & END_MREGS) {
3301 printf("resid = 0x%lx\n", (u_long)EN_READ(sc, MID_RESID));
3302 printf("interrupt status = 0x%b\n",
3303 (int)EN_READ(sc, MID_INTSTAT), MID_INTBITS);
3304 printf("interrupt enable = 0x%b\n",
3305 (int)EN_READ(sc, MID_INTENA), MID_INTBITS);
3306 printf("mcsr = 0x%b\n", (int)EN_READ(sc, MID_MAST_CSR), MID_MCSRBITS);
3307 printf("serv_write = [chip=%ld] [us=%d]\n",
3308 (long)EN_READ(sc, MID_SERV_WRITE),
3309 MID_SL_A2REG(sc->hwslistp));
3310 printf("dma addr = 0x%lx\n", (u_long)EN_READ(sc, MID_DMA_ADDR));
3311 printf("DRQ: chip[rd=0x%lx,wr=0x%lx], sc[chip=0x%x,us=0x%x]\n",
3312 (u_long)MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX)),
3313 (u_long)MID_DRQ_REG2A(EN_READ(sc, MID_DMA_WRRX)),
3314 sc->drq_chip, sc->drq_us);
3315 printf("DTQ: chip[rd=0x%lx,wr=0x%lx], sc[chip=0x%x,us=0x%x]\n",
3316 (u_long)MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX)),
3317 (u_long)MID_DTQ_REG2A(EN_READ(sc, MID_DMA_WRTX)),
3318 sc->dtq_chip, sc->dtq_us);
3320 printf(" unusal txspeeds: ");
3321 for (cnt = 0 ; cnt < MID_N_VC ; cnt++)
3322 if (sc->txspeed[cnt])
3323 printf(" vci%d=0x%x", cnt, sc->txspeed[cnt]);
3326 printf(" rxvc slot mappings: ");
3327 for (cnt = 0 ; cnt < MID_N_VC ; cnt++)
3328 if (sc->rxvc2slot[cnt] != RX_NONE)
3329 printf(" %d->%d", cnt, sc->rxvc2slot[cnt]);
3334 if (level & END_TX) {
3336 for (slot = 0 ; slot < EN_NTX; slot++) {
3337 printf("tx%d: start/stop/cur=0x%x/0x%x/0x%x [%d] ", slot,
3338 sc->txslot[slot].start, sc->txslot[slot].stop, sc->txslot[slot].cur,
3339 (sc->txslot[slot].cur - sc->txslot[slot].start)/4);
3340 printf("mbsize=%d, bfree=%d\n", sc->txslot[slot].mbsize,
3341 sc->txslot[slot].bfree);
3342 printf("txhw: base_address=0x%lx, size=%ld, read=%ld, descstart=%ld\n",
3343 (u_long)MIDX_BASE(EN_READ(sc, MIDX_PLACE(slot))),
3344 (u_long)MIDX_SZ(EN_READ(sc, MIDX_PLACE(slot))),
3345 (long)EN_READ(sc, MIDX_READPTR(slot)),
3346 (long)EN_READ(sc, MIDX_DESCSTART(slot)));
3350 if (level & END_RX) {
3351 printf(" recv slots:\n");
3352 for (slot = 0 ; slot < sc->en_nrx; slot++) {
3353 printf("rx%d: vci=%d: start/stop/cur=0x%x/0x%x/0x%x ", slot,
3354 sc->rxslot[slot].atm_vci, sc->rxslot[slot].start,
3355 sc->rxslot[slot].stop, sc->rxslot[slot].cur);
3356 printf("mode=0x%x, atm_flags=0x%x, oth_flags=0x%x\n",
3357 sc->rxslot[slot].mode, sc->rxslot[slot].atm_flags,
3358 sc->rxslot[slot].oth_flags);
3359 printf("RXHW: mode=0x%lx, DST_RP=0x%lx, WP_ST_CNT=0x%lx\n",
3360 (u_long)EN_READ(sc, MID_VC(sc->rxslot[slot].atm_vci)),
3361 (u_long)EN_READ(sc, MID_DST_RP(sc->rxslot[slot].atm_vci)),
3362 (u_long)EN_READ(sc, MID_WP_ST_CNT(sc->rxslot[slot].atm_vci)));
3366 if (level & END_DTQ) {
3367 printf(" dtq [need_dtqs=%d,dtq_free=%d]:\n",
3368 sc->need_dtqs, sc->dtq_free);
3370 while (ptr != sc->dtq_us) {
3371 reg = EN_READ(sc, ptr);
3372 printf("\t0x%x=[cnt=%d, chan=%d, end=%d, type=%d @ 0x%lx]\n",
3373 sc->dtq[MID_DTQ_A2REG(ptr)], MID_DMA_CNT(reg), MID_DMA_TXCHAN(reg),
3374 (reg & MID_DMA_END) != 0, MID_DMA_TYPE(reg),
3375 (u_long)EN_READ(sc, ptr+4));
3376 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, ptr, 8);
3380 if (level & END_DRQ) {
3381 printf(" drq [need_drqs=%d,drq_free=%d]:\n",
3382 sc->need_drqs, sc->drq_free);
3384 while (ptr != sc->drq_us) {
3385 reg = EN_READ(sc, ptr);
3386 printf("\t0x%x=[cnt=%d, chan=%d, end=%d, type=%d @ 0x%lx]\n",
3387 sc->drq[MID_DRQ_A2REG(ptr)], MID_DMA_CNT(reg), MID_DMA_RXVCI(reg),
3388 (reg & MID_DMA_END) != 0, MID_DMA_TYPE(reg),
3389 (u_long)EN_READ(sc, ptr+4));
3390 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, ptr, 8);
3394 if (level & END_SWSL) {
3395 printf(" swslist [size=%d]: ", sc->swsl_size);
3396 for (cnt = sc->swsl_head ; cnt != sc->swsl_tail ;
3397 cnt = (cnt + 1) % MID_SL_N)
3398 printf("0x%x ", sc->swslist[cnt]);
3406 * en_dumpmem: dump the memory
3409 /* Do not staticize - meant for calling from DDB! */
3410 int en_dumpmem(unit, addr, len)
3412 int unit, addr, len;
3415 struct en_softc *sc;
3418 if (unit < 0 || unit > en_cd.cd_ndevs ||
3419 (sc = (struct en_softc *) en_cd.cd_devs[unit]) == NULL) {
3420 printf("invalid unit number: %d\n", unit);
3424 if (addr < MID_RAMOFF || addr + len*4 > MID_MAXOFF || len <= 0) {
3425 printf("invalid addr/len number: %d, %d\n", addr, len);
3428 printf("dumping %d words starting at offset 0x%x\n", len, addr);
3430 reg = EN_READ(sc, addr);
3431 printf("mem[0x%x] = 0x%x\n", addr, reg);