sys/dev/netif/sr/if_sr.c

   1 /*
   2  * Copyright (c) 1996 - 2001 John Hay.
   3  * Copyright (c) 1996 SDL Communications, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of the author nor the names of any co-contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/sr/if_sr.c,v 1.48.2.1 2002/06/17 15:10:58 jhay Exp $
  31  * $DragonFly: src/sys/dev/netif/sr/if_sr.c,v 1.11 2004/09/15 00:49:46 joerg Exp $
  32  */
  33
  34 /*
  35  * Programming assumptions and other issues.
  36  *
  37  * Only a 16K window will be used.
  38  *
  39  * The descriptors of a DMA channel will fit in a 16K memory window.
  40  *
  41  * The buffers of a transmit DMA channel will fit in a 16K memory window.
  42  *
  43  * When interface is going up, handshaking is set and it is only cleared
  44  * when the interface is down'ed.
  45  *
  46  * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
  47  * internal/external clock, etc.....
  48  *
  49  */
  50
  51 #include "opt_netgraph.h"
  52 #ifdef NETGRAPH
  53 #include "if_sr.h"
  54 #endif  /* NETGRAPH */
  55
  56 #include <sys/param.h>
  57 #include <sys/systm.h>
  58 #include <sys/kernel.h>
  59 #include <sys/malloc.h>
  60 #include <sys/mbuf.h>
  61 #include <sys/sockio.h>
  62 #include <sys/socket.h>
  63 #include <sys/bus.h>
  64 #include <machine/bus.h>
  65 #include <machine/resource.h>
  66 #include <machine/bus_pio.h>
  67 #include <machine/bus_memio.h>
  68 #include <sys/rman.h>
  69
  70 #include <net/if.h>
  71 #ifdef NETGRAPH
  72 #include <sys/syslog.h>
  73 #else /* NETGRAPH */
  74 #include <net/sppp/if_sppp.h>
  75
  76 #include <net/bpf.h>
  77 #endif  /* NETGRAPH */
  78
  79 #include <machine/md_var.h>
  80
  81 #include "../ic_layer/hd64570.h"
  82 #include "if_srregs.h"
  83
  84 #ifdef NETGRAPH
  85 #include <netgraph/ng_message.h>
  86 #include <netgraph/netgraph.h>
  87 #endif /* NETGRAPH */
  88 /* #define USE_MODEMCK */
  89
  90 #ifndef BUGGY
  91 #define BUGGY           0
  92 #endif
  93
  94 #ifndef NETGRAPH
  95 #define PPP_HEADER_LEN  4
  96 #endif /* NETGRAPH */
  97
  98 static int      next_sc_unit = 0;
  99 #ifndef NETGRAPH
 100 #ifdef USE_MODEMCK
 101 static int      sr_watcher = 0;
 102 #endif
 103 #endif /* NETGRAPH */
 104
 105 /*
 106  * Define the software interface for the card... There is one for
 107  * every channel (port).
 108  */
 109 struct sr_softc {
 110 #ifndef NETGRAPH
 111         struct  sppp ifsppp;    /* PPP service w/in system */
 112 #endif /* NETGRAPH */
 113         struct  sr_hardc *hc;   /* card-level information */
 114
 115         int     unit;           /* With regard to all sr devices */
 116         int     subunit;        /* With regard to this card */
 117
 118         struct  buf_block {
 119                 u_int   txdesc; /* DPRAM offset */
 120                 u_int   txstart;/* DPRAM offset */
 121                 u_int   txend;  /* DPRAM offset */
 122                 u_int   txtail; /* # of 1st free gran */
 123                 u_int   txmax;  /* # of free grans */
 124                 u_int   txeda;  /* err descr addr */
 125         } block[SR_TX_BLOCKS];
 126
 127         char    xmit_busy;      /* Transmitter is busy */
 128         char    txb_inuse;      /* # of tx grans in use */
 129         u_int   txb_new;        /* ndx to new buffer */
 130         u_int   txb_next_tx;    /* ndx to next gran rdy tx */
 131
 132         u_int   rxdesc;         /* DPRAM offset */
 133         u_int   rxstart;        /* DPRAM offset */
 134         u_int   rxend;          /* DPRAM offset */
 135         u_int   rxhind;         /* ndx to the hd of rx bufrs */
 136         u_int   rxmax;          /* # of avail grans */
 137
 138         u_int   clk_cfg;        /* Clock configuration */
 139
 140         int     scachan;        /* channel # on card */
 141 #ifdef NETGRAPH
 142         int     running;        /* something is attached so we are running */
 143         int     dcd;            /* do we have dcd? */
 144         /* ---netgraph bits --- */
 145         char            nodename[NG_NODELEN + 1]; /* store our node name */
 146         int             datahooks;      /* number of data hooks attached */
 147         node_p          node;           /* netgraph node */
 148         hook_p          hook;           /* data hook */
 149         hook_p          debug_hook;
 150         struct ifqueue  xmitq_hipri;    /* hi-priority transmit queue */
 151         struct ifqueue  xmitq;          /* transmit queue */
 152         int             flags;          /* state */
 153 #define SCF_RUNNING     0x01            /* board is active */
 154 #define SCF_OACTIVE     0x02            /* output is active */
 155         int             out_dog;        /* watchdog cycles output count-down */
 156         struct callout  sr_timer;       /* timeout(9) handle */
 157         u_long          inbytes, outbytes;      /* stats */
 158         u_long          lastinbytes, lastoutbytes; /* a second ago */
 159         u_long          inrate, outrate;        /* highest rate seen */
 160         u_long          inlast;         /* last input N secs ago */
 161         u_long          out_deficit;    /* output since last input */
 162         u_long          oerrors, ierrors[6];
 163         u_long          opackets, ipackets;
 164 #endif /* NETGRAPH */
 165 };
 166
 167 #ifdef NETGRAPH
 168 #define DOG_HOLDOFF     6       /* dog holds off for 6 secs */
 169 #define QUITE_A_WHILE   300     /* 5 MINUTES */
 170 #define LOTS_OF_PACKETS 100
 171 #endif /* NETGRAPH */
 172
 173 /*
 174  * Baud Rate table for Sync Mode.
 175  * Each entry consists of 3 elements:
 176  * Baud Rate (x100) , TMC, BR
 177  *
 178  * Baud Rate = FCLK / TMC / 2^BR
 179  * Baud table for Crystal freq. of 9.8304 Mhz
 180  */
 181 #ifdef N2_TEST_SPEED
 182 struct rate_line {
 183         int     target;         /* target rate/100 */
 184         int     tmc_reg;        /* TMC register value */
 185         int     br_reg;         /* BR (BaudRateClk) selector */
 186 } n2_rates[] = {
 187         /* Baudx100     TMC             BR */
 188         { 3,            128,            8 },
 189         { 6,            128,            7 },
 190         { 12,           128,            6 },
 191         { 24,           128,            5 },
 192         { 48,           128,            4 },
 193         { 96,           128,            3 },
 194         { 192,          128,            2 },
 195         { 384,          128,            1 },
 196         { 560,          88,             1 },
 197         { 640,          77,             1 },
 198         { 1280,         38,             1 },
 199         { 2560,         19,             1 },
 200         { 5120,         10,             1 },
 201         { 10000,        5,              1 },
 202         { 15000,        3,              1 },
 203         { 25000,        2,              1 },
 204         { 50000,        1,              1 },
 205         { 0,            0,              0 }
 206 };
 207
 208 int     sr_test_speed[] = {
 209         N2_TEST_SPEED,
 210         N2_TEST_SPEED
 211 };
 212
 213 int     etc0vals[] = {
 214         SR_MCR_ETC0,            /* ISA channel 0 */
 215         SR_MCR_ETC1,            /* ISA channel 1 */
 216         SR_FECR_ETC0,           /* PCI channel 0 */
 217         SR_FECR_ETC1            /* PCI channel 1 */
 218 };
 219 #endif
 220
 221 devclass_t sr_devclass;
 222 #ifndef NETGRAPH
 223 DECLARE_DUMMY_MODULE(if_sr);
 224 MODULE_DEPEND(if_sr, sppp, 1, 1, 1);
 225 #else
 226 MODULE_DEPEND(ng_sync_sr, netgraph, 1, 1, 1);
 227 #endif
 228
 229 static void     srintr(void *arg);
 230 static void     sr_xmit(struct sr_softc *sc);
 231 #ifndef NETGRAPH
 232 static void     srstart(struct ifnet *ifp);
 233 static int      srioctl(struct ifnet *ifp, u_long cmd, caddr_t data,
 234                         struct ucred *);
 235 static void     srwatchdog(struct ifnet *ifp);
 236 #else
 237 static void     srstart(struct sr_softc *sc);
 238 static void     srwatchdog(struct sr_softc *sc);
 239 #endif /* NETGRAPH */
 240 static int      sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat);
 241 static void     sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len);
 242 static void     sr_eat_packet(struct sr_softc *sc, int single);
 243 static void     sr_get_packets(struct sr_softc *sc);
 244
 245 static void     sr_up(struct sr_softc *sc);
 246 static void     sr_down(struct sr_softc *sc);
 247 static void     src_init(struct sr_hardc *hc);
 248 static void     sr_init_sca(struct sr_hardc *hc);
 249 static void     sr_init_msci(struct sr_softc *sc);
 250 static void     sr_init_rx_dmac(struct sr_softc *sc);
 251 static void     sr_init_tx_dmac(struct sr_softc *sc);
 252 static void     sr_dmac_intr(struct sr_hardc *hc, u_char isr);
 253 static void     sr_msci_intr(struct sr_hardc *hc, u_char isr);
 254 static void     sr_timer_intr(struct sr_hardc *hc, u_char isr);
 255 #ifndef NETGRAPH
 256 #ifdef USE_MODEMCK
 257 static void     sr_modemck(void *x);
 258 #endif
 259 #else
 260 static void     sr_modemck(struct sr_softc *x);
 261 #endif /* NETGRAPH */
 262
 263 #ifdef NETGRAPH
 264 static  void    ngsr_watchdog_frame(void * arg);
 265 static  void    ngsr_init(void* ignored);
 266
 267 static ng_constructor_t ngsr_constructor;
 268 static ng_rcvmsg_t      ngsr_rcvmsg;
 269 static ng_shutdown_t    ngsr_rmnode;
 270 static ng_newhook_t     ngsr_newhook;
 271 /*static ng_findhook_t  ngsr_findhook; */
 272 static ng_connect_t     ngsr_connect;
 273 static ng_rcvdata_t     ngsr_rcvdata;
 274 static ng_disconnect_t  ngsr_disconnect;
 275
 276 static struct ng_type typestruct = {
 277         NG_VERSION,
 278         NG_SR_NODE_TYPE,
 279         NULL,
 280         ngsr_constructor,
 281         ngsr_rcvmsg,
 282         ngsr_rmnode,
 283         ngsr_newhook,
 284         NULL,
 285         ngsr_connect,
 286         ngsr_rcvdata,
 287         ngsr_rcvdata,
 288         ngsr_disconnect,
 289         NULL
 290 };
 291
 292 static int      ngsr_done_init = 0;
 293 #endif /* NETGRAPH */
 294
 295 /*
 296  * Register the ports on the adapter.
 297  * Fill in the info for each port.
 298 #ifndef NETGRAPH
 299  * Attach each port to sppp and bpf.
 300 #endif
 301  */
 302 int
 303 sr_attach(device_t device)
 304 {
 305         int intf_sw, pndx;
 306         u_int32_t flags;
 307         u_int fecr, *fecrp;
 308         struct sr_hardc *hc;
 309         struct sr_softc *sc;
 310 #ifndef NETGRAPH
 311         struct ifnet *ifp;
 312 #endif /* NETGRAPH */
 313         int unit;               /* index: channel w/in card */
 314
 315         hc = (struct sr_hardc *)device_get_softc(device);
 316         MALLOC(sc, struct sr_softc *,
 317                 hc->numports * sizeof(struct sr_softc),
 318                 M_DEVBUF, M_WAITOK | M_ZERO);
 319         if (sc == NULL)
 320                 goto errexit;
 321         hc->sc = sc;
 322
 323         /*
 324          * Get the TX clock direction and configuration. The default is a
 325          * single external clock which is used by RX and TX.
 326          */
 327         switch(hc->cardtype) {
 328         case SR_CRD_N2:
 329                 flags = device_get_flags(device);
 330 #ifdef N2_TEST_SPEED
 331                 if (sr_test_speed[0] > 0)
 332                         hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
 333                 else
 334 #endif
 335                 if (flags & SR_FLAGS_0_CLK_MSK)
 336                         hc->sc[0].clk_cfg =
 337                             (flags & SR_FLAGS_0_CLK_MSK)
 338                             >> SR_FLAGS_CLK_SHFT;
 339
 340                 if (hc->numports == 2)
 341 #ifdef N2_TEST_SPEED
 342                         if (sr_test_speed[1] > 0)
 343                                 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
 344                         else
 345 #endif
 346                         if (flags & SR_FLAGS_1_CLK_MSK)
 347                                 hc->sc[1].clk_cfg = (flags & SR_FLAGS_1_CLK_MSK)
 348                                     >> (SR_FLAGS_CLK_SHFT +
 349                                     SR_FLAGS_CLK_CHAN_SHFT);
 350                 break;
 351         case SR_CRD_N2PCI:
 352                 fecrp = (u_int *)(hc->sca_base + SR_FECR);
 353                 fecr = *fecrp;
 354                 for (pndx = 0; pndx < hc->numports; pndx++, sc++) {
 355                         switch (pndx) {
 356                         case 1:
 357                                 intf_sw = fecr & SR_FECR_ID1 >> SR_FE_ID1_SHFT;
 358                                 break;
 359                         case 0:
 360                         default:
 361                                 intf_sw = fecr & SR_FECR_ID0 >> SR_FE_ID0_SHFT;
 362                         }
 363
 364 #ifdef N2_TEST_SPEED
 365                         if (sr_test_speed[pndx] > 0)
 366                                 sc->clk_cfg = SR_FLAGS_INT_CLK;
 367                         else
 368 #endif
 369                                 switch (intf_sw) {
 370                                 default:
 371                                 case SR_FE_ID_RS232:
 372                                 case SR_FE_ID_HSSI:
 373                                 case SR_FE_ID_RS422:
 374                                 case SR_FE_ID_TEST:
 375                                         break;
 376
 377                                 case SR_FE_ID_V35:
 378                                         sc->clk_cfg = SR_FLAGS_EXT_SEP_CLK;
 379                                         break;
 380
 381                                 case SR_FE_ID_X21:
 382                                         sc->clk_cfg = SR_FLAGS_EXT_CLK;
 383                                         break;
 384                                 }
 385                 }
 386                 sc = hc->sc;
 387                 break;
 388         }
 389
 390         /*
 391          * Report Card configuration information before we start configuring
 392          * each channel on the card...
 393          */
 394         printf("src%d: %uK RAM (%d mempages) @ %08x-%08x, %u ports.\n",
 395                hc->cunit, hc->memsize / 1024, hc->mempages,
 396                (u_int)hc->mem_start, (u_int)hc->mem_end, hc->numports);
 397
 398         src_init(hc);
 399         sr_init_sca(hc);
 400
 401         if (BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
 402             INTR_TYPE_NET, srintr, hc, &hc->intr_cookie) != 0)
 403                 goto errexit;
 404
 405         /*
 406          * Now configure each port on the card.
 407          */
 408         for (unit = 0; unit < hc->numports; sc++, unit++) {
 409                 sc->hc = hc;
 410                 sc->subunit = unit;
 411                 sc->unit = next_sc_unit;
 412                 next_sc_unit++;
 413                 sc->scachan = unit % NCHAN;
 414
 415                 sr_init_rx_dmac(sc);
 416                 sr_init_tx_dmac(sc);
 417                 sr_init_msci(sc);
 418
 419                 printf("sr%d: Adapter %d, port %d.\n",
 420                        sc->unit, hc->cunit, sc->subunit);
 421
 422 #ifndef NETGRAPH
 423                 ifp = &sc->ifsppp.pp_if;
 424                 ifp->if_softc = sc;
 425                 if_initname(ifp, "sr", sc->unit);
 426                 ifp->if_mtu = PP_MTU;
 427                 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
 428                 ifp->if_ioctl = srioctl;
 429                 ifp->if_start = srstart;
 430                 ifp->if_watchdog = srwatchdog;
 431
 432                 sc->ifsppp.pp_flags = PP_KEEPALIVE;
 433                 sppp_attach((struct ifnet *)&sc->ifsppp);
 434                 if_attach(ifp);
 435
 436                 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
 437 #else   /* NETGRAPH */
 438                 /*
 439                  * we have found a node, make sure our 'type' is availabe.
 440                  */
 441                 if (ngsr_done_init == 0) ngsr_init(NULL);
 442                 if (ng_make_node_common(&typestruct, &sc->node) != 0)
 443                         goto errexit;
 444                 sc->node->private = sc;
 445                 callout_init(&sc->sr_timer);
 446                 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
 447                 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
 448                 sprintf(sc->nodename, "%s%d", NG_SR_NODE_TYPE, sc->unit);
 449                 if (ng_name_node(sc->node, sc->nodename)) {
 450                         ng_rmnode(sc->node);
 451                         ng_unref(sc->node);
 452                         return (0);
 453                 }
 454                 sc->running = 0;
 455 #endif  /* NETGRAPH */
 456         }
 457
 458         if (hc->mempages)
 459                 SRC_SET_OFF(hc->iobase);
 460
 461         return (0);
 462
 463 errexit:
 464         sr_deallocate_resources(device);
 465         return (ENXIO);
 466 }
 467
 468 int
 469 sr_detach(device_t device)
 470 {
 471         device_t parent = device_get_parent(device);
 472         struct sr_hardc *hc = device_get_softc(device);
 473
 474         if (hc->intr_cookie != NULL) {
 475                 if (BUS_TEARDOWN_INTR(parent, device,
 476                         hc->res_irq, hc->intr_cookie) != 0) {
 477                                 printf("intr teardown failed.. continuing\n");
 478                 }
 479                 hc->intr_cookie = NULL;
 480         }
 481
 482         /* XXX Stop the DMA. */
 483
 484         /*
 485          * deallocate any system resources we may have
 486          * allocated on behalf of this driver.
 487          */
 488         FREE(hc->sc, M_DEVBUF);
 489         hc->sc = NULL;
 490         hc->mem_start = NULL;
 491         return (sr_deallocate_resources(device));
 492 }
 493
 494 int
 495 sr_allocate_ioport(device_t device, int rid, u_long size)
 496 {
 497         struct sr_hardc *hc = device_get_softc(device);
 498
 499         hc->rid_ioport = rid;
 500         hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT,
 501                         &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE);
 502         if (hc->res_ioport == NULL) {
 503                 goto errexit;
 504         }
 505         return (0);
 506
 507 errexit:
 508         sr_deallocate_resources(device);
 509         return (ENXIO);
 510 }
 511
 512 int
 513 sr_allocate_irq(device_t device, int rid, u_long size)
 514 {
 515         struct sr_hardc *hc = device_get_softc(device);
 516
 517         hc->rid_irq = rid;
 518         hc->res_irq = bus_alloc_resource(device, SYS_RES_IRQ,
 519                         &hc->rid_irq, 0ul, ~0ul, 1, RF_SHAREABLE|RF_ACTIVE);
 520         if (hc->res_irq == NULL) {
 521                 goto errexit;
 522         }
 523         return (0);
 524
 525 errexit:
 526         sr_deallocate_resources(device);
 527         return (ENXIO);
 528 }
 529
 530 int
 531 sr_allocate_memory(device_t device, int rid, u_long size)
 532 {
 533         struct sr_hardc *hc = device_get_softc(device);
 534
 535         hc->rid_memory = rid;
 536         hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
 537                         &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
 538         if (hc->res_memory == NULL) {
 539                 goto errexit;
 540         }
 541         return (0);
 542
 543 errexit:
 544         sr_deallocate_resources(device);
 545         return (ENXIO);
 546 }
 547
 548 int
 549 sr_allocate_plx_memory(device_t device, int rid, u_long size)
 550 {
 551         struct sr_hardc *hc = device_get_softc(device);
 552
 553         hc->rid_plx_memory = rid;
 554         hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
 555                         &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
 556         if (hc->res_plx_memory == NULL) {
 557                 goto errexit;
 558         }
 559         return (0);
 560
 561 errexit:
 562         sr_deallocate_resources(device);
 563         return (ENXIO);
 564 }
 565
 566 int
 567 sr_deallocate_resources(device_t device)
 568 {
 569         struct sr_hardc *hc = device_get_softc(device);
 570
 571         if (hc->res_irq != 0) {
 572                 bus_deactivate_resource(device, SYS_RES_IRQ,
 573                         hc->rid_irq, hc->res_irq);
 574                 bus_release_resource(device, SYS_RES_IRQ,
 575                         hc->rid_irq, hc->res_irq);
 576                 hc->res_irq = 0;
 577         }
 578         if (hc->res_ioport != 0) {
 579                 bus_deactivate_resource(device, SYS_RES_IOPORT,
 580                         hc->rid_ioport, hc->res_ioport);
 581                 bus_release_resource(device, SYS_RES_IOPORT,
 582                         hc->rid_ioport, hc->res_ioport);
 583                 hc->res_ioport = 0;
 584         }
 585         if (hc->res_memory != 0) {
 586                 bus_deactivate_resource(device, SYS_RES_MEMORY,
 587                         hc->rid_memory, hc->res_memory);
 588                 bus_release_resource(device, SYS_RES_MEMORY,
 589                         hc->rid_memory, hc->res_memory);
 590                 hc->res_memory = 0;
 591         }
 592         if (hc->res_plx_memory != 0) {
 593                 bus_deactivate_resource(device, SYS_RES_MEMORY,
 594                         hc->rid_plx_memory, hc->res_plx_memory);
 595                 bus_release_resource(device, SYS_RES_MEMORY,
 596                         hc->rid_plx_memory, hc->res_plx_memory);
 597                 hc->res_plx_memory = 0;
 598         }
 599         return (0);
 600 }
 601
 602 /*
 603  * N2 Interrupt Service Routine
 604  *
 605  * First figure out which SCA gave the interrupt.
 606  * Process it.
 607  * See if there is other interrupts pending.
 608  * Repeat until there no interrupts remain.
 609  */
 610 static void
 611 srintr(void *arg)
 612 {
 613         struct sr_hardc *hc = (struct sr_hardc *)arg;
 614         sca_regs *sca = hc->sca;        /* MSCI register tree */
 615         u_char  isr0, isr1, isr2;       /* interrupt statii captured */
 616
 617 #if BUGGY > 1
 618         printf("sr: srintr_hc(hc=%08x)\n", hc);
 619 #endif
 620
 621         /*
 622          * Since multiple interfaces may share this interrupt, we must loop
 623          * until no interrupts are still pending service.
 624          */
 625         while (1) {
 626                 /*
 627                  * Read all three interrupt status registers from the N2
 628                  * card...
 629                  */
 630                 isr0 = SRC_GET8(hc->sca_base, sca->isr0);
 631                 isr1 = SRC_GET8(hc->sca_base, sca->isr1);
 632                 isr2 = SRC_GET8(hc->sca_base, sca->isr2);
 633
 634                 /*
 635                  * If all three registers returned 0, we've finished
 636                  * processing interrupts from this device, so we can quit
 637                  * this loop...
 638                  */
 639                 if ((isr0 | isr1 | isr2) == 0)
 640                         break;
 641
 642 #if BUGGY > 2
 643                 printf("src%d: srintr_hc isr0 %x, isr1 %x, isr2 %x\n",
 644 #ifndef NETGRAPH
 645                         unit, isr0, isr1, isr2);
 646 #else
 647                         hc->cunit, isr0, isr1, isr2);
 648 #endif /* NETGRAPH */
 649 #endif
 650
 651                 /*
 652                  * Now we can dispatch the interrupts. Since we don't expect
 653                  * either MSCI or timer interrupts, we'll test for DMA
 654                  * interrupts first...
 655                  */
 656                 if (isr1)       /* DMA-initiated interrupt */
 657                         sr_dmac_intr(hc, isr1);
 658
 659                 if (isr0)       /* serial part IRQ? */
 660                         sr_msci_intr(hc, isr0);
 661
 662                 if (isr2)       /* timer-initiated interrupt */
 663                         sr_timer_intr(hc, isr2);
 664         }
 665 }
 666
 667 /*
 668  * This will only start the transmitter. It is assumed that the data
 669  * is already there.
 670  * It is normally called from srstart() or sr_dmac_intr().
 671  */
 672 static void
 673 sr_xmit(struct sr_softc *sc)
 674 {
 675         u_short cda_value;      /* starting descriptor */
 676         u_short eda_value;      /* ending descriptor */
 677         struct sr_hardc *hc;
 678 #ifndef NETGRAPH
 679         struct ifnet *ifp;      /* O/S Network Services */
 680 #endif /* NETGRAPH */
 681         dmac_channel *dmac;     /* DMA channel registers */
 682
 683 #if BUGGY > 0
 684         printf("sr: sr_xmit( sc=%08x)\n", sc);
 685 #endif
 686
 687         hc = sc->hc;
 688 #ifndef NETGRAPH
 689         ifp = &sc->ifsppp.pp_if;
 690 #endif /* NETGRAPH */
 691         dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
 692
 693         /*
 694          * Get the starting and ending addresses of the chain to be
 695          * transmitted and pass these on to the DMA engine on-chip.
 696          */
 697         cda_value = sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart;
 698         cda_value &= 0x00ffff;
 699         eda_value = sc->block[sc->txb_next_tx].txeda + hc->mem_pstart;
 700         eda_value &= 0x00ffff;
 701
 702         SRC_PUT16(hc->sca_base, dmac->cda, cda_value);
 703         SRC_PUT16(hc->sca_base, dmac->eda, eda_value);
 704
 705         /*
 706          * Now we'll let the DMA status register know about this change
 707          */
 708         SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
 709
 710         sc->xmit_busy = 1;      /* mark transmitter busy */
 711
 712 #if BUGGY > 2
 713         printf("sr%d: XMIT  cda=%04x, eda=%4x, rcda=%08lx\n",
 714                sc->unit, cda_value, eda_value,
 715                sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart);
 716 #endif
 717
 718         sc->txb_next_tx++;      /* update next transmit seq# */
 719
 720         if (sc->txb_next_tx == SR_TX_BLOCKS)    /* handle wrap... */
 721                 sc->txb_next_tx = 0;
 722
 723 #ifndef NETGRAPH
 724         /*
 725          * Finally, we'll set a timout (which will start srwatchdog())
 726          * within the O/S network services layer...
 727          */
 728         ifp->if_timer = 2;      /* Value in seconds. */
 729 #else
 730         /*
 731          * Don't time out for a while.
 732          */
 733         sc->out_dog = DOG_HOLDOFF;      /* give ourself some breathing space*/
 734 #endif /* NETGRAPH */
 735 }
 736
 737 /*
 738  * This function will be called from the upper level when a user add a
 739  * packet to be send, and from the interrupt handler after a finished
 740  * transmit.
 741  *
 742  * NOTE: it should run at spl_imp().
 743  *
 744  * This function only place the data in the oncard buffers. It does not
 745  * start the transmition. sr_xmit() does that.
 746  *
 747  * Transmitter idle state is indicated by the IFF_OACTIVE flag.
 748  * The function that clears that should ensure that the transmitter
 749  * and its DMA is in a "good" idle state.
 750  */
 751 #ifndef NETGRAPH
 752 static void
 753 srstart(struct ifnet *ifp)
 754 {
 755         struct sr_softc *sc;    /* channel control structure */
 756 #else
 757 static void
 758 srstart(struct sr_softc *sc)
 759 {
 760 #endif /* NETGRAPH */
 761         struct sr_hardc *hc;    /* card control/config block */
 762         int len;                /* total length of a packet */
 763         int pkts;               /* packets placed in DPRAM */
 764         int tlen;               /* working length of pkt */
 765         u_int i;
 766         struct mbuf *mtx;       /* message buffer from O/S */
 767         u_char *txdata;         /* buffer address in DPRAM */
 768         sca_descriptor *txdesc; /* working descriptor pointr */
 769         struct buf_block *blkp;
 770
 771 #ifndef NETGRAPH
 772 #if BUGGY > 0
 773         printf("sr: srstart( ifp=%08x)\n", ifp);
 774 #endif
 775         sc = ifp->if_softc;
 776         if ((ifp->if_flags & IFF_RUNNING) == 0)
 777                 return;
 778 #endif /* NETGRAPH */
 779         hc = sc->hc;
 780         /*
 781          * It is OK to set the memory window outside the loop because all tx
 782          * buffers and descriptors are assumed to be in the same 16K window.
 783          */
 784         if (hc->mempages) {
 785                 SRC_SET_ON(hc->iobase);
 786                 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
 787         }
 788
 789         /*
 790          * Loop to place packets into DPRAM.
 791          *
 792          * We stay in this loop until there is nothing in
 793          * the TX queue left or the tx buffers are full.
 794          */
 795 top_srstart:
 796
 797         /*
 798          * See if we have space for more packets.
 799          */
 800         if (sc->txb_inuse == SR_TX_BLOCKS) {    /* out of space? */
 801 #ifndef NETGRAPH
 802                 ifp->if_flags |= IFF_OACTIVE;   /* yes, mark active */
 803 #else
 804                 /*ifp->if_flags |= IFF_OACTIVE;*/       /* yes, mark active */
 805 #endif /* NETGRAPH */
 806
 807                 if (hc->mempages)
 808                         SRC_SET_OFF(hc->iobase);
 809
 810 #if BUGGY > 9
 811                 printf("sr%d.srstart: sc->txb_inuse=%d; DPRAM full...\n",
 812                        sc->unit, sc->txb_inuse);
 813 #endif
 814                 return;
 815         }
 816         /*
 817          * OK, the card can take more traffic.  Let's see if there's any
 818          * pending from the system...
 819          *
 820          * NOTE:
 821          * The architecture of the networking interface doesn't
 822          * actually call us like 'write()', providing an address.  We get
 823          * started, a lot like a disk strategy routine, and we actually call
 824          * back out to the system to get traffic to send...
 825          *
 826          * NOTE:
 827          * If we were gonna run through another layer, we would use a
 828          * dispatch table to select the service we're getting a packet
 829          * from...
 830          */
 831 #ifndef NETGRAPH
 832         mtx = sppp_dequeue(ifp);
 833 #else /* NETGRAPH */
 834         IF_DEQUEUE(&sc->xmitq_hipri, mtx);
 835         if (mtx == NULL) {
 836                 IF_DEQUEUE(&sc->xmitq, mtx);
 837         }
 838 #endif /* NETGRAPH */
 839         if (!mtx) {
 840                 if (hc->mempages)
 841                         SRC_SET_OFF(hc->iobase);
 842                 return;
 843         }
 844         /*
 845          * OK, we got a packet from the network services of the O/S. Now we
 846          * can move it into the DPRAM (under control of the descriptors) and
 847          * fire it off...
 848          */
 849         pkts = 0;
 850         i = 0;                  /* counts # of granules used */
 851
 852         blkp = &sc->block[sc->txb_new]; /* address of free granule */
 853         txdesc = (sca_descriptor *)
 854             (hc->mem_start + (blkp->txdesc & hc->winmsk));
 855
 856         txdata = (u_char *)(hc->mem_start
 857                             + (blkp->txstart & hc->winmsk));
 858
 859         /*
 860          * Now we'll try to install as many packets as possible into the
 861          * card's DP RAM buffers.
 862          */
 863         for (;;) {              /* perform actual copy of packet */
 864                 len = mtx->m_pkthdr.len;        /* length of message */
 865
 866 #if BUGGY > 1
 867                 printf("sr%d.srstart: mbuf @ %08lx, %d bytes\n",
 868                            sc->unit, mtx, len);
 869 #endif
 870
 871 #ifndef NETGRAPH
 872                 if (ifp->if_bpf)
 873                         bpf_mtap(ifp, mtx);
 874 #else   /* NETGRAPH */
 875                 sc->outbytes += len;
 876 #endif  /* NETGRAPH */
 877
 878                 /*
 879                  * We can perform a straight copy because the tranmit
 880                  * buffers won't wrap.
 881                  */
 882                 m_copydata(mtx, 0, len, txdata);
 883
 884                 /*
 885                  * Now we know how big the message is gonna be.  We must now
 886                  * construct the descriptors to drive this message out...
 887                  */
 888                 tlen = len;
 889                 while (tlen > SR_BUF_SIZ) {     /* loop for full granules */
 890                         txdesc->stat = 0;       /* reset bits */
 891                         txdesc->len = SR_BUF_SIZ;       /* size of granule */
 892                         tlen -= SR_BUF_SIZ;
 893
 894                         txdesc++;       /* move to next dscr */
 895                         txdata += SR_BUF_SIZ;   /* adjust data addr */
 896                         i++;
 897                 }
 898
 899                 /*
 900                  * This section handles the setting of the final piece of a
 901                  * message.
 902                  */
 903                 txdesc->stat = SCA_DESC_EOM;
 904                 txdesc->len = tlen;
 905                 pkts++;
 906
 907                 /*
 908                  * prepare for subsequent packets (if any)
 909                  */
 910                 txdesc++;
 911                 txdata += SR_BUF_SIZ;   /* next mem granule */
 912                 i++;            /* count of granules */
 913
 914                 /*
 915                  * OK, we've now placed the message into the DPRAM where it
 916                  * can be transmitted.  We'll now release the message memory
 917                  * and update the statistics...
 918                  */
 919                 m_freem(mtx);
 920 #ifndef NETGRAPH
 921                 ++sc->ifsppp.pp_if.if_opackets;
 922 #else   /* NETGRAPH */
 923                 sc->opackets++;
 924 #endif /* NETGRAPH */
 925
 926                 /*
 927                  * Check if we have space for another packet. XXX This is
 928                  * hardcoded.  A packet can't be larger than 3 buffers (3 x
 929                  * 512).
 930                  */
 931                 if ((i + 3) >= blkp->txmax) {   /* enough remains? */
 932 #if BUGGY > 9
 933                         printf("sr%d.srstart: i=%d (%d pkts); card full.\n",
 934                                sc->unit, i, pkts);
 935 #endif
 936                         break;
 937                 }
 938                 /*
 939                  * We'll pull the next message to be sent (if any)
 940                  */
 941 #ifndef NETGRAPH
 942                 mtx = sppp_dequeue(ifp);
 943 #else /* NETGRAPH */
 944                 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
 945                 if (mtx == NULL) {
 946                         IF_DEQUEUE(&sc->xmitq, mtx);
 947                 }
 948 #endif /* NETGRAPH */
 949                 if (!mtx) {     /* no message?  We're done! */
 950 #if BUGGY > 9
 951                         printf("sr%d.srstart: pending=0, pkts=%d\n",
 952                                sc->unit, pkts);
 953 #endif
 954                         break;
 955                 }
 956         }
 957
 958         blkp->txtail = i;       /* record next free granule */
 959
 960         /*
 961          * Mark the last descriptor, so that the SCA know where to stop.
 962          */
 963         txdesc--;               /* back up to last descriptor in list */
 964         txdesc->stat |= SCA_DESC_EOT;   /* mark as end of list */
 965
 966         /*
 967          * Now we'll reset the transmit granule's descriptor address so we
 968          * can record this in the structure and fire it off w/ the DMA
 969          * processor of the serial chip...
 970          */
 971         txdesc = (sca_descriptor *)blkp->txdesc;
 972         blkp->txeda = (u_short)((u_int)&txdesc[i]);
 973
 974         sc->txb_inuse++;        /* update inuse status */
 975         sc->txb_new++;          /* new traffic wuz added */
 976
 977         if (sc->txb_new == SR_TX_BLOCKS)
 978                 sc->txb_new = 0;
 979
 980         /*
 981          * If the tranmitter wasn't marked as "busy" we will force it to be
 982          * started...
 983          */
 984         if (sc->xmit_busy == 0) {
 985                 sr_xmit(sc);
 986 #if BUGGY > 9
 987                 printf("sr%d.srstart: called sr_xmit()\n", sc->unit);
 988 #endif
 989         }
 990         goto top_srstart;
 991 }
 992
 993 #ifndef NETGRAPH
 994 /*
 995  * Handle ioctl's at the device level, though we *will* call up
 996  * a layer...
 997  */
 998 #if BUGGY > 2
 999 static int bug_splats[] = {0, 0, 0, 0, 0, 0, 0, 0};
1000 #endif
1001
1002 static int
1003 srioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1004 {
1005         int s, error, was_up, should_be_up;
1006         struct sr_softc *sc = ifp->if_softc;
1007
1008 #if BUGGY > 0
1009         printf("%s: srioctl(ifp=%08x, cmd=%08x, data=%08x)\n",
1010                ifp->if_xname, ifp, cmd, data);
1011 #endif
1012
1013         was_up = ifp->if_flags & IFF_RUNNING;
1014
1015         error = sppp_ioctl(ifp, cmd, data);
1016
1017 #if BUGGY > 1
1018         printf("%s: ioctl: ifsppp.pp_flags = %08x, if_flags %08x.\n",
1019               ifp->if_xname, ((struct sppp *)ifp)->pp_flags, ifp->if_flags);
1020 #endif
1021
1022         if (error)
1023                 return error;
1024
1025         if ((cmd != SIOCSIFFLAGS) && (cmd != SIOCSIFADDR)) {
1026 #if BUGGY > 2
1027                 if (bug_splats[sc->unit]++ < 2) {
1028                         printf("sr(%d).if_addrlist = %08x\n",
1029                                sc->unit, ifp->if_addrlist);
1030                         printf("sr(%d).if_bpf = %08x\n",
1031                                sc->unit, ifp->if_bpf);
1032                         printf("sr(%d).if_init = %08x\n",
1033                                sc->unit, ifp->if_init);
1034                         printf("sr(%d).if_output = %08x\n",
1035                                sc->unit, ifp->if_output);
1036                         printf("sr(%d).if_start = %08x\n",
1037                                sc->unit, ifp->if_start);
1038                         printf("sr(%d).if_done = %08x\n",
1039                                sc->unit, ifp->if_done);
1040                         printf("sr(%d).if_ioctl = %08x\n",
1041                                sc->unit, ifp->if_ioctl);
1042                         printf("sr(%d).if_reset = %08x\n",
1043                                sc->unit, ifp->if_reset);
1044                         printf("sr(%d).if_watchdog = %08x\n",
1045                                sc->unit, ifp->if_watchdog);
1046                 }
1047 #endif
1048                 return 0;
1049         }
1050
1051         s = splimp();
1052         should_be_up = ifp->if_flags & IFF_RUNNING;
1053
1054         if (!was_up && should_be_up) {
1055                 /*
1056                  * Interface should be up -- start it.
1057                  */
1058                 sr_up(sc);
1059                 srstart(ifp);
1060
1061                 /*
1062                  * XXX Clear the IFF_UP flag so that the link will only go
1063                  * up after sppp lcp and ipcp negotiation.
1064                  */
1065                 /* ifp->if_flags &= ~IFF_UP; */
1066         } else if (was_up && !should_be_up) {
1067                 /*
1068                  * Interface should be down -- stop it.
1069                  */
1070                 sr_down(sc);
1071                 sppp_flush(ifp);
1072         }
1073         splx(s);
1074         return 0;
1075 }
1076 #endif /* NETGRAPH */
1077
1078 /*
1079  * This is to catch lost tx interrupts.
1080  */
1081 static void
1082 #ifndef NETGRAPH
1083 srwatchdog(struct ifnet *ifp)
1084 #else
1085 srwatchdog(struct sr_softc *sc)
1086 #endif /* NETGRAPH */
1087 {
1088         int     got_st0, got_st1, got_st3, got_dsr;
1089 #ifndef NETGRAPH
1090         struct sr_softc *sc = ifp->if_softc;
1091 #endif /* NETGRAPH */
1092         struct sr_hardc *hc = sc->hc;
1093         msci_channel *msci = &hc->sca->msci[sc->scachan];
1094         dmac_channel *dmac = &sc->hc->sca->dmac[sc->scachan];
1095
1096 #if BUGGY > 0
1097 #ifndef NETGRAPH
1098         printf("srwatchdog(unit=%d)\n", unit);
1099 #else
1100         printf("srwatchdog(unit=%d)\n", sc->unit);
1101 #endif /* NETGRAPH */
1102 #endif
1103
1104 #ifndef NETGRAPH
1105         if (!(ifp->if_flags & IFF_RUNNING))
1106                 return;
1107
1108         ifp->if_oerrors++;      /* update output error count */
1109 #else   /* NETGRAPH */
1110         sc->oerrors++;  /* update output error count */
1111 #endif /* NETGRAPH */
1112
1113         got_st0 = SRC_GET8(hc->sca_base, msci->st0);
1114         got_st1 = SRC_GET8(hc->sca_base, msci->st1);
1115         got_st3 = SRC_GET8(hc->sca_base, msci->st3);
1116         got_dsr = SRC_GET8(hc->sca_base, dmac->dsr);
1117
1118 #ifndef NETGRAPH
1119 #if     0
1120         if (ifp->if_flags & IFF_DEBUG)
1121 #endif
1122                 printf("sr%d: transmit failed, "
1123 #else   /* NETGRAPH */
1124         printf("sr%d: transmit failed, "
1125 #endif /* NETGRAPH */
1126                        "ST0 %02x, ST1 %02x, ST3 %02x, DSR %02x.\n",
1127                        sc->unit,
1128                        got_st0, got_st1, got_st3, got_dsr);
1129
1130         if (SRC_GET8(hc->sca_base, msci->st1) & SCA_ST1_UDRN) {
1131                 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXABORT);
1132                 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1133                 SRC_PUT8(hc->sca_base, msci->st1, SCA_ST1_UDRN);
1134         }
1135         sc->xmit_busy = 0;
1136 #ifndef NETGRAPH
1137         ifp->if_flags &= ~IFF_OACTIVE;
1138 #else
1139         /*ifp->if_flags &= ~IFF_OACTIVE; */
1140 #endif /* NETGRAPH */
1141
1142         if (sc->txb_inuse && --sc->txb_inuse)
1143                 sr_xmit(sc);
1144
1145 #ifndef NETGRAPH
1146         srstart(ifp);   /* restart transmitter */
1147 #else
1148         srstart(sc);    /* restart transmitter */
1149 #endif /* NETGRAPH */
1150 }
1151
1152 static void
1153 sr_up(struct sr_softc *sc)
1154 {
1155         u_int *fecrp;
1156         struct sr_hardc *hc = sc->hc;
1157         sca_regs *sca = hc->sca;
1158         msci_channel *msci = &sca->msci[sc->scachan];
1159
1160 #if BUGGY > 0
1161         printf("sr_up(sc=%08x)\n", sc);
1162 #endif
1163
1164         /*
1165          * Enable transmitter and receiver. Raise DTR and RTS. Enable
1166          * interrupts.
1167          *
1168          * XXX What about using AUTO mode in msci->md0 ???
1169          */
1170         SRC_PUT8(hc->sca_base, msci->ctl,
1171                  SRC_GET8(hc->sca_base, msci->ctl) & ~SCA_CTL_RTS);
1172
1173         if (sc->scachan == 0)
1174                 switch (hc->cardtype) {
1175                 case SR_CRD_N2:
1176                         outb(hc->iobase + SR_MCR,
1177                              (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR0));
1178                         break;
1179                 case SR_CRD_N2PCI:
1180                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1181                         *fecrp &= ~SR_FECR_DTR0;
1182                         break;
1183                 }
1184         else
1185                 switch (hc->cardtype) {
1186                 case SR_CRD_N2:
1187                         outb(hc->iobase + SR_MCR,
1188                              (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR1));
1189                         break;
1190                 case SR_CRD_N2PCI:
1191                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1192                         *fecrp &= ~SR_FECR_DTR1;
1193                         break;
1194                 }
1195
1196         if (sc->scachan == 0) {
1197                 SRC_PUT8(hc->sca_base, sca->ier0,
1198                          SRC_GET8(hc->sca_base, sca->ier0) | 0x000F);
1199                 SRC_PUT8(hc->sca_base, sca->ier1,
1200                          SRC_GET8(hc->sca_base, sca->ier1) | 0x000F);
1201         } else {
1202                 SRC_PUT8(hc->sca_base, sca->ier0,
1203                          SRC_GET8(hc->sca_base, sca->ier0) | 0x00F0);
1204                 SRC_PUT8(hc->sca_base, sca->ier1,
1205                          SRC_GET8(hc->sca_base, sca->ier1) | 0x00F0);
1206         }
1207
1208         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXENABLE);
1209         inb(hc->iobase);        /* XXX slow it down a bit. */
1210         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1211
1212 #ifndef NETGRAPH
1213 #ifdef USE_MODEMCK
1214         if (sr_watcher == 0)
1215                 sr_modemck(NULL);
1216 #endif
1217 #else   /* NETGRAPH */
1218         callout_reset(&sc->sr_timer, hz, ngsr_watchdog_frame, sc);
1219         sc->running = 1;
1220 #endif /* NETGRAPH */
1221 }
1222
1223 static void
1224 sr_down(struct sr_softc *sc)
1225 {
1226         u_int *fecrp;
1227         struct sr_hardc *hc = sc->hc;
1228         sca_regs *sca = hc->sca;
1229         msci_channel *msci = &sca->msci[sc->scachan];
1230
1231 #if BUGGY > 0
1232         printf("sr_down(sc=%08x)\n", sc);
1233 #endif
1234 #ifdef NETGRAPH
1235         callout_stop(&sc->sr_timer);
1236         sc->running = 0;
1237 #endif /* NETGRAPH */
1238
1239         /*
1240          * Disable transmitter and receiver. Lower DTR and RTS. Disable
1241          * interrupts.
1242          */
1243         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXDISABLE);
1244         inb(hc->iobase);        /* XXX slow it down a bit. */
1245         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXDISABLE);
1246
1247         SRC_PUT8(hc->sca_base, msci->ctl,
1248                  SRC_GET8(hc->sca_base, msci->ctl) | SCA_CTL_RTS);
1249
1250         if (sc->scachan == 0)
1251                 switch (hc->cardtype) {
1252                 case SR_CRD_N2:
1253                         outb(hc->iobase + SR_MCR,
1254                              (inb(hc->iobase + SR_MCR) | SR_MCR_DTR0));
1255                         break;
1256                 case SR_CRD_N2PCI:
1257                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1258                         *fecrp |= SR_FECR_DTR0;
1259                         break;
1260                 }
1261         else
1262                 switch (hc->cardtype) {
1263                 case SR_CRD_N2:
1264                         outb(hc->iobase + SR_MCR,
1265                              (inb(hc->iobase + SR_MCR) | SR_MCR_DTR1));
1266                         break;
1267                 case SR_CRD_N2PCI:
1268                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1269                         *fecrp |= SR_FECR_DTR1;
1270                         break;
1271                 }
1272
1273         if (sc->scachan == 0) {
1274                 SRC_PUT8(hc->sca_base, sca->ier0,
1275                          SRC_GET8(hc->sca_base, sca->ier0) & ~0x0F);
1276                 SRC_PUT8(hc->sca_base, sca->ier1,
1277                          SRC_GET8(hc->sca_base, sca->ier1) & ~0x0F);
1278         } else {
1279                 SRC_PUT8(hc->sca_base, sca->ier0,
1280                          SRC_GET8(hc->sca_base, sca->ier0) & ~0xF0);
1281                 SRC_PUT8(hc->sca_base, sca->ier1,
1282                          SRC_GET8(hc->sca_base, sca->ier1) & ~0xF0);
1283         }
1284 }
1285
1286 /*
1287  * Initialize the card, allocate memory for the sr_softc structures
1288  * and fill in the pointers.
1289  */
1290 static void
1291 src_init(struct sr_hardc *hc)
1292 {
1293         struct sr_softc *sc = hc->sc;
1294         int x;
1295         u_int chanmem;
1296         u_int bufmem;
1297         u_int next;
1298         u_int descneeded;
1299
1300 #if BUGGY > 0
1301         printf("src_init(hc=%08x)\n", hc);
1302 #endif
1303
1304         chanmem = hc->memsize / hc->numports;
1305         next = 0;
1306
1307         for (x = 0; x < hc->numports; x++, sc++) {
1308                 int blk;
1309
1310                 for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1311                         sc->block[blk].txdesc = next;
1312                         bufmem = (16 * 1024) / SR_TX_BLOCKS;
1313                         descneeded = bufmem / SR_BUF_SIZ;
1314
1315                         sc->block[blk].txstart = sc->block[blk].txdesc
1316                             + ((((descneeded * sizeof(sca_descriptor))
1317                                  / SR_BUF_SIZ) + 1)
1318                                * SR_BUF_SIZ);
1319
1320                         sc->block[blk].txend = next + bufmem;
1321                         sc->block[blk].txmax =
1322                             (sc->block[blk].txend - sc->block[blk].txstart)
1323                             / SR_BUF_SIZ;
1324                         next += bufmem;
1325
1326 #if BUGGY > 2
1327                         printf("sr%d: blk %d: txdesc %08x, txstart %08x\n",
1328                                sc->unit, blk,
1329                                sc->block[blk].txdesc, sc->block[blk].txstart);
1330 #endif
1331                 }
1332
1333                 sc->rxdesc = next;
1334                 bufmem = chanmem - (bufmem * SR_TX_BLOCKS);
1335                 descneeded = bufmem / SR_BUF_SIZ;
1336                 sc->rxstart = sc->rxdesc +
1337                     ((((descneeded * sizeof(sca_descriptor)) /
1338                        SR_BUF_SIZ) + 1) * SR_BUF_SIZ);
1339                 sc->rxend = next + bufmem;
1340                 sc->rxmax = (sc->rxend - sc->rxstart) / SR_BUF_SIZ;
1341                 next += bufmem;
1342         }
1343 }
1344
1345 /*
1346  * The things done here are channel independent.
1347  *
1348  * Configure the sca waitstates.
1349  * Configure the global interrupt registers.
1350  * Enable master dma enable.
1351  */
1352 static void
1353 sr_init_sca(struct sr_hardc *hc)
1354 {
1355         sca_regs *sca = hc->sca;
1356
1357 #if BUGGY > 0
1358         printf("sr_init_sca(hc=%08x)\n", hc);
1359 #endif
1360
1361         /*
1362          * Do the wait registers. Set everything to 0 wait states.
1363          */
1364         SRC_PUT8(hc->sca_base, sca->pabr0, 0);
1365         SRC_PUT8(hc->sca_base, sca->pabr1, 0);
1366         SRC_PUT8(hc->sca_base, sca->wcrl, 0);
1367         SRC_PUT8(hc->sca_base, sca->wcrm, 0);
1368         SRC_PUT8(hc->sca_base, sca->wcrh, 0);
1369
1370         /*
1371          * Configure the interrupt registers. Most are cleared until the
1372          * interface is configured.
1373          */
1374         SRC_PUT8(hc->sca_base, sca->ier0, 0x00);        /* MSCI interrupts. */
1375         SRC_PUT8(hc->sca_base, sca->ier1, 0x00);        /* DMAC interrupts */
1376         SRC_PUT8(hc->sca_base, sca->ier2, 0x00);        /* TIMER interrupts. */
1377         SRC_PUT8(hc->sca_base, sca->itcr, 0x00);        /* Use ivr and no intr
1378                                                          * ack */
1379         SRC_PUT8(hc->sca_base, sca->ivr, 0x40); /* Interrupt vector. */
1380         SRC_PUT8(hc->sca_base, sca->imvr, 0x40);
1381
1382         /*
1383          * Configure the timers. XXX Later
1384          */
1385
1386         /*
1387          * Set the DMA channel priority to rotate between all four channels.
1388          *
1389          * Enable all dma channels.
1390          */
1391         SRC_PUT8(hc->sca_base, sca->pcr, SCA_PCR_PR2);
1392         SRC_PUT8(hc->sca_base, sca->dmer, SCA_DMER_EN);
1393 }
1394
1395 /*
1396  * Configure the msci
1397  *
1398  * NOTE: The serial port configuration is hardcoded at the moment.
1399  */
1400 static void
1401 sr_init_msci(struct sr_softc *sc)
1402 {
1403         int portndx;            /* on-board port number */
1404         u_int mcr_v;            /* contents of modem control */
1405         u_int *fecrp;           /* pointer for PCI's MCR i/o */
1406         struct sr_hardc *hc = sc->hc;
1407         msci_channel *msci = &hc->sca->msci[sc->scachan];
1408 #ifdef N2_TEST_SPEED
1409         int br_v;               /* contents for BR divisor */
1410         int etcndx;             /* index into ETC table */
1411         int fifo_v, gotspeed;   /* final tabled speed found */
1412         int tmc_v;              /* timer control register */
1413         int wanted;             /* speed (bitrate) wanted... */
1414         struct rate_line *rtp;
1415 #endif
1416
1417         portndx = sc->scachan;
1418
1419 #if BUGGY > 0
1420         printf("sr: sr_init_msci( sc=%08x)\n", sc);
1421 #endif
1422
1423         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RESET);
1424         SRC_PUT8(hc->sca_base, msci->md0, SCA_MD0_CRC_1 |
1425                  SCA_MD0_CRC_CCITT |
1426                  SCA_MD0_CRC_ENABLE |
1427                  SCA_MD0_MODE_HDLC);
1428         SRC_PUT8(hc->sca_base, msci->md1, SCA_MD1_NOADDRCHK);
1429         SRC_PUT8(hc->sca_base, msci->md2, SCA_MD2_DUPLEX | SCA_MD2_NRZ);
1430
1431         /*
1432          * According to the manual I should give a reset after changing the
1433          * mode registers.
1434          */
1435         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXRESET);
1436         SRC_PUT8(hc->sca_base, msci->ctl, SCA_CTL_IDLPAT |
1437                  SCA_CTL_UDRNC |
1438                  SCA_CTL_RTS);
1439
1440         /*
1441          * XXX Later we will have to support different clock settings.
1442          */
1443         switch (sc->clk_cfg) {
1444         default:
1445 #if BUGGY > 0
1446                 printf("sr%: clk_cfg=%08x, selected default clock.\n",
1447                        portndx, sc->clk_cfg);
1448 #endif
1449                 /* FALLTHROUGH */
1450         case SR_FLAGS_EXT_CLK:
1451                 /*
1452                  * For now all interfaces are programmed to use the RX clock
1453                  * for the TX clock.
1454                  */
1455
1456 #if BUGGY > 0
1457                 printf("sr%d: External Clock Selected.\n", portndx);
1458 #endif
1459
1460                 SRC_PUT8(hc->sca_base, msci->rxs,
1461                          SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1462                 SRC_PUT8(hc->sca_base, msci->txs,
1463                          SCA_TXS_CLK_RX | SCA_TXS_DIV1);
1464                 break;
1465
1466         case SR_FLAGS_EXT_SEP_CLK:
1467 #if BUGGY > 0
1468                 printf("sr%d: Split Clocking Selected.\n", portndx);
1469 #endif
1470
1471                 SRC_PUT8(hc->sca_base, msci->rxs,
1472                          SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1473                 SRC_PUT8(hc->sca_base, msci->txs,
1474                          SCA_TXS_CLK_TXC | SCA_TXS_DIV1);
1475                 break;
1476
1477         case SR_FLAGS_INT_CLK:
1478 #if BUGGY > 0
1479                 printf("sr%d: Internal Clocking selected.\n", portndx);
1480 #endif
1481
1482                 /*
1483                  * XXX I do need some code to set the baud rate here!
1484                  */
1485 #ifdef N2_TEST_SPEED
1486                 switch (hc->cardtype) {
1487                 case SR_CRD_N2PCI:
1488                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1489                         mcr_v = *fecrp;
1490                         etcndx = 2;
1491                         break;
1492                 case SR_CRD_N2:
1493                 default:
1494                         mcr_v = inb(hc->iobase + SR_MCR);
1495                         etcndx = 0;
1496                 }
1497
1498                 fifo_v = 0x10;  /* stolen from Linux version */
1499
1500                 /*
1501                  * search for appropriate speed in table, don't calc it:
1502                  */
1503                 wanted = sr_test_speed[portndx];
1504                 rtp = &n2_rates[0];     /* point to first table item */
1505
1506                 while ((rtp->target > 0)        /* search table for speed */
1507                        &&(rtp->target != wanted))
1508                         rtp++;
1509
1510                 /*
1511                  * We've searched the table for a matching speed.  If we've
1512                  * found the correct rate line, we'll get the pre-calc'd
1513                  * values for the TMC and baud rate divisor for subsequent
1514                  * use...
1515                  */
1516                 if (rtp->target > 0) {  /* use table-provided values */
1517                         gotspeed = wanted;
1518                         tmc_v = rtp->tmc_reg;
1519                         br_v = rtp->br_reg;
1520                 } else {        /* otherwise assume 1MBit comm rate */
1521                         gotspeed = 10000;
1522                         tmc_v = 5;
1523                         br_v = 1;
1524                 }
1525
1526                 /*
1527                  * Now we mask in the enable clock output for the MCR:
1528                  */
1529                 mcr_v |= etc0vals[etcndx + portndx];
1530
1531                 /*
1532                  * Now we'll program the registers with these speed- related
1533                  * contents...
1534                  */
1535                 SRC_PUT8(hc->sca_base, msci->tmc, tmc_v);
1536                 SRC_PUT8(hc->sca_base, msci->trc0, fifo_v);
1537                 SRC_PUT8(hc->sca_base, msci->rxs, SCA_RXS_CLK_INT + br_v);
1538                 SRC_PUT8(hc->sca_base, msci->txs, SCA_TXS_CLK_INT + br_v);
1539
1540                 switch (hc->cardtype) {
1541                 case SR_CRD_N2PCI:
1542                         *fecrp = mcr_v;
1543                         break;
1544                 case SR_CRD_N2:
1545                 default:
1546                         outb(hc->iobase + SR_MCR, mcr_v);
1547                 }
1548
1549 #if BUGGY > 0
1550                 if (wanted != gotspeed)
1551                         printf("sr%d: Speed wanted=%d, found=%d\n",
1552                                wanted, gotspeed);
1553
1554                 printf("sr%d: Internal Clock %dx100 BPS, tmc=%d, div=%d\n",
1555                        portndx, gotspeed, tmc_v, br_v);
1556 #endif
1557 #else
1558                 SRC_PUT8(hc->sca_base, msci->rxs,
1559                          SCA_RXS_CLK_INT | SCA_RXS_DIV1);
1560                 SRC_PUT8(hc->sca_base, msci->txs,
1561                          SCA_TXS_CLK_INT | SCA_TXS_DIV1);
1562
1563                 SRC_PUT8(hc->sca_base, msci->tmc, 5);
1564
1565                 if (portndx == 0)
1566                         switch (hc->cardtype) {
1567                         case SR_CRD_N2PCI:
1568                                 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1569                                 *fecrp |= SR_FECR_ETC0;
1570                                 break;
1571                         case SR_CRD_N2:
1572                         default:
1573                                 mcr_v = inb(hc->iobase + SR_MCR);
1574                                 mcr_v |= SR_MCR_ETC0;
1575                                 outb(hc->iobase + SR_MCR, mcr_v);
1576                         }
1577                 else
1578                         switch (hc->cardtype) {
1579                         case SR_CRD_N2:
1580                                 mcr_v = inb(hc->iobase + SR_MCR);
1581                                 mcr_v |= SR_MCR_ETC1;
1582                                 outb(hc->iobase + SR_MCR, mcr_v);
1583                                 break;
1584                         case SR_CRD_N2PCI:
1585                                 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1586                                 *fecrp |= SR_FECR_ETC1;
1587                                 break;
1588                         }
1589 #endif
1590         }
1591
1592         /*
1593          * XXX Disable all interrupts for now. I think if you are using the
1594          * dmac you don't use these interrupts.
1595          */
1596         SRC_PUT8(hc->sca_base, msci->ie0, 0);
1597         SRC_PUT8(hc->sca_base, msci->ie1, 0x0C);
1598         SRC_PUT8(hc->sca_base, msci->ie2, 0);
1599         SRC_PUT8(hc->sca_base, msci->fie, 0);
1600
1601         SRC_PUT8(hc->sca_base, msci->sa0, 0);
1602         SRC_PUT8(hc->sca_base, msci->sa1, 0);
1603
1604         SRC_PUT8(hc->sca_base, msci->idl, 0x7E);        /* set flags value */
1605
1606         SRC_PUT8(hc->sca_base, msci->rrc, 0x0E);
1607         SRC_PUT8(hc->sca_base, msci->trc0, 0x10);
1608         SRC_PUT8(hc->sca_base, msci->trc1, 0x1F);
1609 }
1610
1611 /*
1612  * Configure the rx dma controller.
1613  */
1614 static void
1615 sr_init_rx_dmac(struct sr_softc *sc)
1616 {
1617         struct sr_hardc *hc;
1618         dmac_channel *dmac;
1619         sca_descriptor *rxd;
1620         u_int cda_v, sarb_v, rxbuf, rxda, rxda_d;
1621
1622 #if BUGGY > 0
1623         printf("sr_init_rx_dmac(sc=%08x)\n", sc);
1624 #endif
1625
1626         hc = sc->hc;
1627         dmac = &hc->sca->dmac[DMAC_RXCH(sc->scachan)];
1628
1629         if (hc->mempages)
1630                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1631
1632         /*
1633          * This phase initializes the contents of the descriptor table
1634          * needed to construct a circular buffer...
1635          */
1636         rxd = (sca_descriptor *)(hc->mem_start + (sc->rxdesc & hc->winmsk));
1637         rxda_d = (u_int) hc->mem_start - (sc->rxdesc & ~hc->winmsk);
1638
1639         for (rxbuf = sc->rxstart;
1640              rxbuf < sc->rxend;
1641              rxbuf += SR_BUF_SIZ, rxd++) {
1642                 /*
1643                  * construct the circular chain...
1644                  */
1645                 rxda = (u_int) & rxd[1] - rxda_d + hc->mem_pstart;
1646                 rxd->cp = (u_short)(rxda & 0xffff);
1647
1648                 /*
1649                  * set the on-card buffer address...
1650                  */
1651                 rxd->bp = (u_short)((rxbuf + hc->mem_pstart) & 0xffff);
1652                 rxd->bpb = (u_char)(((rxbuf + hc->mem_pstart) >> 16) & 0xff);
1653
1654                 rxd->len = 0;   /* bytes resident w/in granule */
1655                 rxd->stat = 0xff;       /* The sca write here when finished */
1656         }
1657
1658         /*
1659          * heal the chain so that the last entry points to the first...
1660          */
1661         rxd--;
1662         rxd->cp = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1663
1664         /*
1665          * reset the reception handler's index...
1666          */
1667         sc->rxhind = 0;
1668
1669         /*
1670          * We'll now configure the receiver's DMA logic...
1671          */
1672         SRC_PUT8(hc->sca_base, dmac->dsr, 0);   /* Disable DMA transfer */
1673         SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1674
1675         /* XXX maybe also SCA_DMR_CNTE */
1676         SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1677         SRC_PUT16(hc->sca_base, dmac->bfl, SR_BUF_SIZ);
1678
1679         cda_v = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1680         sarb_v = (u_char)(((sc->rxdesc + hc->mem_pstart) >> 16) & 0xff);
1681
1682         SRC_PUT16(hc->sca_base, dmac->cda, cda_v);
1683         SRC_PUT8(hc->sca_base, dmac->sarb, sarb_v);
1684
1685         rxd = (sca_descriptor *)sc->rxstart;
1686
1687         SRC_PUT16(hc->sca_base, dmac->eda,
1688                   (u_short)((u_int) & rxd[sc->rxmax - 1] & 0xffff));
1689
1690         SRC_PUT8(hc->sca_base, dmac->dir, 0xF0);
1691
1692
1693         SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);  /* Enable DMA */
1694 }
1695
1696 /*
1697  * Configure the TX DMA descriptors.
1698  * Initialize the needed values and chain the descriptors.
1699  */
1700 static void
1701 sr_init_tx_dmac(struct sr_softc *sc)
1702 {
1703         int blk;
1704         u_int txbuf, txda, txda_d;
1705         struct sr_hardc *hc;
1706         sca_descriptor *txd;
1707         dmac_channel *dmac;
1708         struct buf_block *blkp;
1709         u_int x;
1710         u_int sarb_v;
1711
1712 #if BUGGY > 0
1713         printf("sr_init_tx_dmac(sc=%08x)\n", sc);
1714 #endif
1715
1716         hc = sc->hc;
1717         dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
1718
1719         if (hc->mempages)
1720                 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
1721
1722         /*
1723          * Initialize the array of descriptors for transmission
1724          */
1725         for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1726                 blkp = &sc->block[blk];
1727                 txd = (sca_descriptor *)(hc->mem_start
1728                                          + (blkp->txdesc & hc->winmsk));
1729                 txda_d = (u_int) hc->mem_start
1730                     - (blkp->txdesc & ~hc->winmsk);
1731
1732                 x = 0;
1733                 txbuf = blkp->txstart;
1734                 for (; txbuf < blkp->txend; txbuf += SR_BUF_SIZ, txd++) {
1735                         txda = (u_int) & txd[1] - txda_d + hc->mem_pstart;
1736                         txd->cp = (u_short)(txda & 0xffff);
1737
1738                         txd->bp = (u_short)((txbuf + hc->mem_pstart)
1739                                             & 0xffff);
1740                         txd->bpb = (u_char)(((txbuf + hc->mem_pstart) >> 16)
1741                                             & 0xff);
1742                         txd->len = 0;
1743                         txd->stat = 0;
1744                         x++;
1745                 }
1746
1747                 txd--;
1748                 txd->cp = (u_short)((blkp->txdesc + hc->mem_pstart)
1749                                     & 0xffff);
1750
1751                 blkp->txtail = (u_int)txd - (u_int)hc->mem_start;
1752         }
1753
1754         SRC_PUT8(hc->sca_base, dmac->dsr, 0);   /* Disable DMA */
1755         SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1756         SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1757         SRC_PUT8(hc->sca_base, dmac->dir,
1758                  SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF);
1759
1760         sarb_v = (sc->block[0].txdesc + hc->mem_pstart) >> 16;
1761         sarb_v &= 0x00ff;
1762
1763         SRC_PUT8(hc->sca_base, dmac->sarb, (u_char) sarb_v);
1764 }
1765
1766 /*
1767  * Look through the descriptors to see if there is a complete packet
1768  * available. Stop if we get to where the sca is busy.
1769  *
1770  * Return the length and status of the packet.
1771  * Return nonzero if there is a packet available.
1772  *
1773  * NOTE:
1774  * It seems that we get the interrupt a bit early. The updateing of
1775  * descriptor values is not always completed when this is called.
1776  */
1777 static int
1778 sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat)
1779 {
1780         int granules;   /* count of granules in pkt */
1781         int wki, wko;
1782         struct sr_hardc *hc;
1783         sca_descriptor *rxdesc; /* current descriptor */
1784         sca_descriptor *endp;   /* ending descriptor */
1785         sca_descriptor *cda;    /* starting descriptor */
1786
1787         hc = sc->hc;            /* get card's information */
1788
1789         /*
1790          * set up starting descriptor by pulling that info from the DMA half
1791          * of the HD chip...
1792          */
1793         wki = DMAC_RXCH(sc->scachan);
1794         wko = SRC_GET16(hc->sca_base, hc->sca->dmac[wki].cda);
1795
1796         cda = (sca_descriptor *)(hc->mem_start + (wko & hc->winmsk));
1797
1798 #if BUGGY > 1
1799         printf("sr_packet_avail(): wki=%d, wko=%04x, cda=%08x\n",
1800                wki, wko, cda);
1801 #endif
1802
1803         /*
1804          * open the appropriate memory window and set our expectations...
1805          */
1806         if (hc->mempages) {
1807                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1808                 SRC_SET_ON(hc->iobase);
1809         }
1810         rxdesc = (sca_descriptor *)
1811             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1812         endp = rxdesc;
1813         rxdesc = &rxdesc[sc->rxhind];
1814         endp = &endp[sc->rxmax];
1815
1816         *len = 0;               /* reset result total length */
1817         granules = 0;           /* reset count of granules */
1818
1819         /*
1820          * This loop will scan descriptors, but it *will* puke up if we wrap
1821          * around to our starting point...
1822          */
1823         while (rxdesc != cda) {
1824                 *len += rxdesc->len;    /* increment result length */
1825                 granules++;
1826
1827                 /*
1828                  * If we hit a valid packet's completion we'll know we've
1829                  * got a live one, and that we can deliver the packet.
1830                  * Since we're only allowed to report a packet available,
1831                  * somebody else does that...
1832                  */
1833                 if (rxdesc->stat & SCA_DESC_EOM) {      /* End Of Message */
1834                         *rxstat = rxdesc->stat; /* return closing */
1835 #if BUGGY > 0
1836                         printf("sr%d: PKT AVAIL len %d, %x, bufs %u.\n",
1837                                sc->unit, *len, *rxstat, granules);
1838 #endif
1839                         return 1;       /* indicate success */
1840                 }
1841                 /*
1842                  * OK, this packet take up multiple granules.  Move on to
1843                  * the next descriptor so we can consider it...
1844                  */
1845                 rxdesc++;
1846
1847                 if (rxdesc == endp)     /* recognize & act on wrap point */
1848                         rxdesc = (sca_descriptor *)
1849                             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1850         }
1851
1852         /*
1853          * Nothing found in the DPRAM.  Let the caller know...
1854          */
1855         *len = 0;
1856         *rxstat = 0;
1857
1858         return 0;
1859 }
1860
1861 /*
1862  * Copy a packet from the on card memory into a provided mbuf.
1863  * Take into account that buffers wrap and that a packet may
1864  * be larger than a buffer.
1865  */
1866 static void
1867 sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len)
1868 {
1869         struct sr_hardc *hc;
1870         sca_descriptor *rxdesc;
1871         u_int rxdata;
1872         u_int rxmax;
1873         u_int off = 0;
1874         u_int tlen;
1875
1876 #if BUGGY > 0
1877         printf("sr_copy_rxbuf(m=%08x,sc=%08x,len=%d)\n",
1878                m, sc, len);
1879 #endif
1880
1881         hc = sc->hc;
1882
1883         rxdata = sc->rxstart + (sc->rxhind * SR_BUF_SIZ);
1884         rxmax = sc->rxstart + (sc->rxmax * SR_BUF_SIZ);
1885
1886         rxdesc = (sca_descriptor *)
1887             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1888         rxdesc = &rxdesc[sc->rxhind];
1889
1890         /*
1891          * Using the count of bytes in the received packet, we decrement it
1892          * for each granule (controller by an SCA descriptor) to control the
1893          * looping...
1894          */
1895         while (len) {
1896                 /*
1897                  * tlen gets the length of *this* granule... ...which is
1898                  * then copied to the target buffer.
1899                  */
1900                 tlen = (len < SR_BUF_SIZ) ? len : SR_BUF_SIZ;
1901
1902                 if (hc->mempages)
1903                         SRC_SET_MEM(hc->iobase, rxdata);
1904
1905                 bcopy(hc->mem_start + (rxdata & hc->winmsk),
1906                       mtod(m, caddr_t) +off,
1907                       tlen);
1908
1909                 off += tlen;
1910                 len -= tlen;
1911
1912                 /*
1913                  * now, return to the descriptor's window in DPRAM and reset
1914                  * the descriptor we've just suctioned...
1915                  */
1916                 if (hc->mempages)
1917                         SRC_SET_MEM(hc->iobase, sc->rxdesc);
1918
1919                 rxdesc->len = 0;
1920                 rxdesc->stat = 0xff;
1921
1922                 /*
1923                  * Move on to the next granule.  If we've any remaining
1924                  * bytes to process we'll just continue in our loop...
1925                  */
1926                 rxdata += SR_BUF_SIZ;
1927                 rxdesc++;
1928
1929                 if (rxdata == rxmax) {  /* handle the wrap point */
1930                         rxdata = sc->rxstart;
1931                         rxdesc = (sca_descriptor *)
1932                             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1933                 }
1934         }
1935 }
1936
1937 /*
1938  * If single is set, just eat a packet. Otherwise eat everything up to
1939  * where cda points. Update pointers to point to the next packet.
1940  *
1941  * This handles "flushing" of a packet as received...
1942  *
1943  * If the "single" parameter is zero, all pending reeceive traffic will
1944  * be flushed out of existence.  A non-zero value will only drop the
1945  * *next* (currently) pending packet...
1946  */
1947 static void
1948 sr_eat_packet(struct sr_softc *sc, int single)
1949 {
1950         struct sr_hardc *hc;
1951         sca_descriptor *rxdesc; /* current descriptor being eval'd */
1952         sca_descriptor *endp;   /* last descriptor in chain */
1953         sca_descriptor *cda;    /* current start point */
1954         u_int loopcnt = 0;      /* count of packets flushed ??? */
1955         u_char stat;            /* captured status byte from descr */
1956
1957         hc = sc->hc;
1958         cda = (sca_descriptor *)(hc->mem_start +
1959                                  (SRC_GET16(hc->sca_base,
1960                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda) &
1961                                   hc->winmsk));
1962
1963         /*
1964          * loop until desc->stat == (0xff || EOM) Clear the status and
1965          * length in the descriptor. Increment the descriptor.
1966          */
1967         if (hc->mempages)
1968                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1969
1970         rxdesc = (sca_descriptor *)
1971             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1972         endp = rxdesc;
1973         rxdesc = &rxdesc[sc->rxhind];
1974         endp = &endp[sc->rxmax];
1975
1976         /*
1977          * allow loop, but abort it if we wrap completely...
1978          */
1979         while (rxdesc != cda) {
1980                 loopcnt++;
1981
1982                 if (loopcnt > sc->rxmax) {
1983                         printf("sr%d: eat pkt %d loop, cda %x, "
1984                                "rxdesc %x, stat %x.\n",
1985                                sc->unit, loopcnt, (u_int) cda, (u_int) rxdesc,
1986                                rxdesc->stat);
1987                         break;
1988                 }
1989                 stat = rxdesc->stat;
1990
1991                 rxdesc->len = 0;
1992                 rxdesc->stat = 0xff;
1993
1994                 rxdesc++;
1995                 sc->rxhind++;
1996
1997                 if (rxdesc == endp) {
1998                         rxdesc = (sca_descriptor *)
1999                             (hc->mem_start + (sc->rxdesc & hc->winmsk));
2000                         sc->rxhind = 0;
2001                 }
2002                 if (single && (stat == SCA_DESC_EOM))
2003                         break;
2004         }
2005
2006         /*
2007          * Update the eda to the previous descriptor.
2008          */
2009         rxdesc = (sca_descriptor *)sc->rxdesc;
2010         rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2) % sc->rxmax];
2011
2012         SRC_PUT16(hc->sca_base,
2013                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2014                   (u_short)((u_int)(rxdesc + hc->mem_pstart) & 0xffff));
2015 }
2016
2017 /*
2018  * While there is packets available in the rx buffer, read them out
2019  * into mbufs and ship them off.
2020  */
2021 static void
2022 sr_get_packets(struct sr_softc *sc)
2023 {
2024         u_char rxstat;          /* acquired status byte */
2025         int i;
2026         int pkts;               /* count of packets found */
2027         int rxndx;              /* rcv buffer index */
2028         int tries;              /* settling time counter */
2029         u_int len;              /* length of pending packet */
2030         struct sr_hardc *hc;    /* card-level information */
2031         sca_descriptor *rxdesc; /* descriptor in memory */
2032 #ifndef NETGRAPH
2033         struct ifnet *ifp;      /* network intf ctl table */
2034 #endif /* NETGRAPH */
2035         struct mbuf *m = NULL;  /* message buffer */
2036
2037 #if BUGGY > 0
2038         printf("sr_get_packets(sc=%08x)\n", sc);
2039 #endif
2040
2041         hc = sc->hc;
2042 #ifndef NETGRAPH
2043         ifp = &sc->ifsppp.pp_if;
2044 #endif /* NETGRAPH */
2045
2046         if (hc->mempages) {
2047                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2048                 SRC_SET_ON(hc->iobase); /* enable shared memory */
2049         }
2050         pkts = 0;               /* reset count of found packets */
2051
2052         /*
2053          * for each complete packet in the receiving pool, process each
2054          * packet...
2055          */
2056         while (sr_packet_avail(sc, &len, &rxstat)) {    /* packet pending? */
2057                 /*
2058                  * I have seen situations where we got the interrupt but the
2059                  * status value wasn't deposited.  This code should allow
2060                  * the status byte's value to settle...
2061                  */
2062
2063                 tries = 5;
2064
2065                 while ((rxstat == 0x00ff)
2066                        && --tries)
2067                         sr_packet_avail(sc, &len, &rxstat);
2068
2069 #if BUGGY > 1
2070                 printf("sr_packet_avail() returned len=%d, rxstat=%02ux\n",
2071                        len, rxstat);
2072 #endif
2073
2074                 pkts++;
2075 #ifdef NETGRAPH
2076                 sc->inbytes += len;
2077                 sc->inlast = 0;
2078 #endif /* NETGRAPH */
2079
2080                 /*
2081                  * OK, we've settled the incoming message status. We can now
2082                  * process it...
2083                  */
2084                 if (((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
2085 #if BUGGY > 1
2086                         printf("sr%d: sr_get_packet() rxstat=%02x, len=%d\n",
2087                                sc->unit, rxstat, len);
2088 #endif
2089
2090                         MGETHDR(m, MB_DONTWAIT, MT_DATA);
2091                         if (m == NULL) {
2092                                 /*
2093                                  * eat (flush) packet if get mbuf fail!!
2094                                  */
2095                                 sr_eat_packet(sc, 1);
2096                                 continue;
2097                         }
2098                         /*
2099                          * construct control information for pass-off
2100                          */
2101 #ifndef NETGRAPH
2102                         m->m_pkthdr.rcvif = ifp;
2103 #else
2104                         m->m_pkthdr.rcvif = NULL;
2105 #endif /* NETGRAPH */
2106                         m->m_pkthdr.len = m->m_len = len;
2107                         if (len > MHLEN) {
2108                                 MCLGET(m, MB_DONTWAIT);
2109                                 if ((m->m_flags & M_EXT) == 0) {
2110                                         /*
2111                                          * We couldn't get a big enough
2112                                          * message packet, so we'll send the
2113                                          * packet to /dev/null...
2114                                          */
2115                                         m_freem(m);
2116                                         sr_eat_packet(sc, 1);
2117                                         continue;
2118                                 }
2119                         }
2120                         /*
2121                          * OK, we've got a good message buffer.  Now we can
2122                          * copy the received message into it
2123                          */
2124                         sr_copy_rxbuf(m, sc, len);      /* copy from DPRAM */
2125
2126 #ifndef NETGRAPH
2127                         if (ifp->if_bpf)
2128                                 bpf_mtap(ifp, m);
2129
2130 #if BUGGY > 3
2131                         {
2132                                 u_char *bp;
2133
2134                                 bp = (u_char *)m;
2135                                 printf("sr%d: rcvd=%02x%02x%02x%02x%02x%02x\n",
2136                                        sc->unit,
2137                                        bp[0], bp[1], bp[2],
2138                                        bp[4], bp[5], bp[6]);
2139                         }
2140 #endif
2141                         sppp_input(ifp, m);
2142                         ifp->if_ipackets++;
2143
2144 #else   /* NETGRAPH */
2145 #if BUGGY > 3
2146                         {
2147                                 u_char *bp;
2148
2149                                 bp = mtod(m,u_char *);
2150                                 printf("sr%d: rd=%02x:%02x:%02x:%02x:%02x:%02x",
2151                                        sc->unit,
2152                                        bp[0], bp[1], bp[2],
2153                                        bp[4], bp[5], bp[6]);
2154                                 printf(":%02x:%02x:%02x:%02x:%02x:%02x\n",
2155                                        bp[6], bp[7], bp[8],
2156                                        bp[9], bp[10], bp[11]);
2157                         }
2158 #endif
2159                         ng_queue_data(sc->hook, m, NULL);
2160                         sc->ipackets++;
2161 #endif /* NETGRAPH */
2162                         /*
2163                          * Update the eda to the previous descriptor.
2164                          */
2165                         i = (len + SR_BUF_SIZ - 1) / SR_BUF_SIZ;
2166                         sc->rxhind = (sc->rxhind + i) % sc->rxmax;
2167
2168                         rxdesc = (sca_descriptor *)sc->rxdesc;
2169                         rxndx = (sc->rxhind + sc->rxmax - 2) % sc->rxmax;
2170                         rxdesc = &rxdesc[rxndx];
2171
2172                         SRC_PUT16(hc->sca_base,
2173                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2174                                   (u_short)((u_int)(rxdesc + hc->mem_pstart)
2175                                              & 0xffff));
2176
2177                 } else {
2178                         int got_st3, got_cda, got_eda;
2179                         int tries = 5;
2180
2181                         while ((rxstat == 0xff) && --tries)
2182                                 sr_packet_avail(sc, &len, &rxstat);
2183
2184                         /*
2185                          * It look like we get an interrupt early
2186                          * sometimes and then the status is not
2187                          * filled in yet.
2188                          */
2189                         if (tries && (tries != 5))
2190                                 continue;
2191
2192                         /*
2193                          * This chunk of code handles the error packets.
2194                          * We'll log them for posterity...
2195                          */
2196                         sr_eat_packet(sc, 1);
2197
2198 #ifndef NETGRAPH
2199                         ifp->if_ierrors++;
2200 #else
2201                         sc->ierrors[0]++;
2202 #endif /* NETGRAPH */
2203
2204                         got_st3 = SRC_GET8(hc->sca_base,
2205                                   hc->sca->msci[sc->scachan].st3);
2206                         got_cda = SRC_GET16(hc->sca_base,
2207                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda);
2208                         got_eda = SRC_GET16(hc->sca_base,
2209                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda);
2210
2211 #if BUGGY > 0
2212                         printf("sr%d: Receive error chan %d, "
2213                                "stat %02x, msci st3 %02x,"
2214                                "rxhind %d, cda %04x, eda %04x.\n",
2215                                sc->unit, sc->scachan, rxstat,
2216                                got_st3, sc->rxhind, got_cda, got_eda);
2217 #endif
2218                 }
2219         }
2220
2221 #if BUGGY > 0
2222         printf("sr%d: sr_get_packets() found %d packet(s)\n",
2223                sc->unit, pkts);
2224 #endif
2225
2226         if (hc->mempages)
2227                 SRC_SET_OFF(hc->iobase);
2228 }
2229
2230 /*
2231  * All DMA interrupts come here.
2232  *
2233  * Each channel has two interrupts.
2234  * Interrupt A for errors and Interrupt B for normal stuff like end
2235  * of transmit or receive dmas.
2236  */
2237 static void
2238 sr_dmac_intr(struct sr_hardc *hc, u_char isr1)
2239 {
2240         u_char dsr;             /* contents of DMA Stat Reg */
2241         u_char dotxstart;       /* enables for tranmit part */
2242         int mch;                /* channel being processed */
2243         struct sr_softc *sc;    /* channel's softc structure */
2244         sca_regs *sca = hc->sca;
2245         dmac_channel *dmac;     /* dma structure of chip */
2246
2247 #if BUGGY > 0
2248         printf("sr_dmac_intr(hc=%08x,isr1=%04x)\n", hc, isr1);
2249 #endif
2250
2251         mch = 0;                /* assume chan0 on card */
2252         dotxstart = isr1;       /* copy for xmitter starts */
2253
2254         /*
2255          * Shortcut if there is no interrupts for dma channel 0 or 1.
2256          * Skip processing for channel 0 if no incoming hit
2257          */
2258         if ((isr1 & 0x0F) == 0) {
2259                 mch = 1;
2260                 isr1 >>= 4;
2261         }
2262         do {
2263                 sc = &hc->sc[mch];
2264
2265                 /*
2266                  * Transmit channel - DMA Status Register Evaluation
2267                  */
2268                 if (isr1 & 0x0C) {
2269                         dmac = &sca->dmac[DMAC_TXCH(mch)];
2270
2271                         /*
2272                          * get the DMA Status Register contents and write
2273                          * back to reset interrupt...
2274                          */
2275                         dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2276                         SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2277
2278                         /*
2279                          * Check for (& process) a Counter overflow
2280                          */
2281                         if (dsr & SCA_DSR_COF) {
2282                                 printf("sr%d: TX DMA Counter overflow, "
2283                                        "txpacket no %lu.\n",
2284 #ifndef NETGRAPH
2285                                        sc->unit, sc->ifsppp.pp_if.if_opackets);
2286                                 sc->ifsppp.pp_if.if_oerrors++;
2287 #else
2288                                        sc->unit, sc->opackets);
2289                                 sc->oerrors++;
2290 #endif /* NETGRAPH */
2291                         }
2292                         /*
2293                          * Check for (& process) a Buffer overflow
2294                          */
2295                         if (dsr & SCA_DSR_BOF) {
2296                                 printf("sr%d: TX DMA Buffer overflow, "
2297                                        "txpacket no %lu, dsr %02x, "
2298                                        "cda %04x, eda %04x.\n",
2299 #ifndef NETGRAPH
2300                                        sc->unit, sc->ifsppp.pp_if.if_opackets,
2301 #else
2302                                        sc->unit, sc->opackets,
2303 #endif /* NETGRAPH */
2304                                        dsr,
2305                                        SRC_GET16(hc->sca_base, dmac->cda),
2306                                        SRC_GET16(hc->sca_base, dmac->eda));
2307 #ifndef NETGRAPH
2308                                 sc->ifsppp.pp_if.if_oerrors++;
2309 #else
2310                                 sc->oerrors++;
2311 #endif /* NETGRAPH */
2312                         }
2313                         /*
2314                          * Check for (& process) an End of Transfer (OK)
2315                          */
2316                         if (dsr & SCA_DSR_EOT) {
2317                                 /*
2318                                  * This should be the most common case.
2319                                  *
2320                                  * Clear the IFF_OACTIVE flag.
2321                                  *
2322                                  * Call srstart to start a new transmit if
2323                                  * there is data to transmit.
2324                                  */
2325 #if BUGGY > 0
2326                                 printf("sr%d: TX Completed OK\n", sc->unit);
2327 #endif
2328                                 sc->xmit_busy = 0;
2329 #ifndef NETGRAPH
2330                                 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE;
2331                                 sc->ifsppp.pp_if.if_timer = 0;
2332 #else
2333                                 /* XXX may need to mark tx inactive? */
2334                                 sc->out_deficit++;
2335                                 sc->out_dog = DOG_HOLDOFF;
2336 #endif /* NETGRAPH */
2337
2338                                 if (sc->txb_inuse && --sc->txb_inuse)
2339                                         sr_xmit(sc);
2340                         }
2341                 }
2342                 /*
2343                  * Receive channel processing of DMA Status Register
2344                  */
2345                 if (isr1 & 0x03) {
2346                         dmac = &sca->dmac[DMAC_RXCH(mch)];
2347
2348                         dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2349                         SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2350
2351                         /*
2352                          * End of frame processing (MSG OK?)
2353                          */
2354                         if (dsr & SCA_DSR_EOM) {
2355 #if BUGGY > 0
2356                                 int tt, ind;
2357
2358 #ifndef NETGRAPH
2359                                 tt = sc->ifsppp.pp_if.if_ipackets;
2360 #else   /* NETGRAPH */
2361                                 tt = sc->ipackets;
2362 #endif /* NETGRAPH */
2363                                 ind = sc->rxhind;
2364 #endif
2365
2366                                 sr_get_packets(sc);
2367 #if BUGGY > 0
2368 #ifndef NETGRAPH
2369                                 if (tt == sc->ifsppp.pp_if.if_ipackets)
2370 #else   /* NETGRAPH */
2371                                 if (tt == sc->ipackets)
2372 #endif /* NETGRAPH */
2373                                 {
2374                                         sca_descriptor *rxdesc;
2375                                         int i;
2376
2377                                         printf("SR: RXINTR isr1 %x, dsr %x, "
2378                                                "no data %d pkts, orxind %d.\n",
2379                                                dotxstart, dsr, tt, ind);
2380                                         printf("SR: rxdesc %x, rxstart %x, "
2381                                                "rxend %x, rxhind %d, "
2382                                                "rxmax %d.\n",
2383                                                sc->rxdesc, sc->rxstart,
2384                                                sc->rxend, sc->rxhind,
2385                                                sc->rxmax);
2386                                         printf("SR: cda %x, eda %x.\n",
2387                                             SRC_GET16(hc->sca_base, dmac->cda),
2388                                             SRC_GET16(hc->sca_base, dmac->eda));
2389
2390                                         if (hc->mempages) {
2391                                                 SRC_SET_ON(hc->iobase);
2392                                                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2393                                         }
2394                                         rxdesc = (sca_descriptor *)
2395                                                  (hc->mem_start +
2396                                                   (sc->rxdesc & hc->winmsk));
2397                                         rxdesc = &rxdesc[sc->rxhind];
2398
2399                                         for (i = 0; i < 3; i++, rxdesc++)
2400                                                 printf("SR: rxdesc->stat %x, "
2401                                                        "len %d.\n",
2402                                                        rxdesc->stat,
2403                                                        rxdesc->len);
2404
2405                                         if (hc->mempages)
2406                                                 SRC_SET_OFF(hc->iobase);
2407                                 }
2408 #endif /* BUGGY */
2409                         }
2410                         /*
2411                          * Check for Counter overflow
2412                          */
2413                         if (dsr & SCA_DSR_COF) {
2414                                 printf("sr%d: RX DMA Counter overflow, "
2415                                        "rxpkts %lu.\n",
2416 #ifndef NETGRAPH
2417                                        sc->unit, sc->ifsppp.pp_if.if_ipackets);
2418                                 sc->ifsppp.pp_if.if_ierrors++;
2419 #else   /* NETGRAPH */
2420                                        sc->unit, sc->ipackets);
2421                                 sc->ierrors[1]++;
2422 #endif /* NETGRAPH */
2423                         }
2424                         /*
2425                          * Check for Buffer overflow
2426                          */
2427                         if (dsr & SCA_DSR_BOF) {
2428                                 printf("sr%d: RX DMA Buffer overflow, "
2429                                        "rxpkts %lu, rxind %d, "
2430                                        "cda %x, eda %x, dsr %x.\n",
2431 #ifndef NETGRAPH
2432                                        sc->unit, sc->ifsppp.pp_if.if_ipackets,
2433 #else   /* NETGRAPH */
2434                                        sc->unit, sc->ipackets,
2435 #endif /* NETGRAPH */
2436                                        sc->rxhind,
2437                                        SRC_GET16(hc->sca_base, dmac->cda),
2438                                        SRC_GET16(hc->sca_base, dmac->eda),
2439                                        dsr);
2440
2441                                 /*
2442                                  * Make sure we eat as many as possible.
2443                                  * Then get the system running again.
2444                                  */
2445                                 if (hc->mempages)
2446                                         SRC_SET_ON(hc->iobase);
2447
2448                                 sr_eat_packet(sc, 0);
2449 #ifndef NETGRAPH
2450                                 sc->ifsppp.pp_if.if_ierrors++;
2451 #else   /* NETGRAPH */
2452                                 sc->ierrors[2]++;
2453 #endif /* NETGRAPH */
2454
2455                                 SRC_PUT8(hc->sca_base,
2456                                          sca->msci[mch].cmd,
2457                                          SCA_CMD_RXMSGREJ);
2458
2459                                 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
2460
2461 #if BUGGY > 0
2462                                 printf("sr%d: RX DMA Buffer overflow, "
2463                                        "rxpkts %lu, rxind %d, "
2464                                        "cda %x, eda %x, dsr %x. After\n",
2465                                        sc->unit,
2466 #ifndef NETGRAPH
2467                                        sc->ipackets,
2468 #else   /* NETGRAPH */
2469                                        sc->ifsppp.pp_if.if_ipackets,
2470 #endif /* NETGRAPH */
2471                                        sc->rxhind,
2472                                        SRC_GET16(hc->sca_base, dmac->cda),
2473                                        SRC_GET16(hc->sca_base, dmac->eda),
2474                                        SRC_GET8(hc->sca_base, dmac->dsr));
2475 #endif
2476
2477                                 if (hc->mempages)
2478                                         SRC_SET_OFF(hc->iobase);
2479                         }
2480                         /*
2481                          * End of Transfer
2482                          */
2483                         if (dsr & SCA_DSR_EOT) {
2484                                 /*
2485                                  * If this happen, it means that we are
2486                                  * receiving faster than what the processor
2487                                  * can handle.
2488                                  *
2489                                  * XXX We should enable the dma again.
2490                                  */
2491                                 printf("sr%d: RX End of xfer, rxpkts %lu.\n",
2492                                        sc->unit,
2493 #ifndef NETGRAPH
2494                                        sc->ifsppp.pp_if.if_ipackets);
2495                                 sc->ifsppp.pp_if.if_ierrors++;
2496 #else
2497                                        sc->ipackets);
2498                                 sc->ierrors[3]++;
2499 #endif /* NETGRAPH */
2500                         }
2501                 }
2502                 isr1 >>= 4;     /* process next half of ISR */
2503                 mch++;          /* and move to next channel */
2504         } while ((mch < NCHAN) && isr1);        /* loop for each chn */
2505
2506         /*
2507          * Now that we have done all the urgent things, see if we can fill
2508          * the transmit buffers.
2509          */
2510         for (mch = 0; mch < NCHAN; mch++) {
2511                 if (dotxstart & 0x0C) { /* TX initiation enabled? */
2512                         sc = &hc->sc[mch];
2513 #ifndef NETGRAPH
2514                         srstart(&sc->ifsppp.pp_if);
2515 #else
2516                         srstart(sc);
2517 #endif /* NETGRAPH */
2518                 }
2519                 dotxstart >>= 4;/* shift for next channel */
2520         }
2521 }
2522 #ifndef NETGRAPH
2523 #ifdef USE_MODEMCK
2524 /*
2525  * Perform timeout on an FR channel
2526  *
2527  * Establish a periodic check of open N2 ports;  If
2528  * a port is open/active, its DCD state is checked
2529  * and a loss of DCD is recognized (and eventually
2530  * processed).
2531  */
2532 static void
2533 sr_modemck(void *arg)
2534 {
2535         u_int s;
2536         int card;               /* card index in table */
2537         int cards;              /* card list index */
2538         int mch;                /* channel on card */
2539         u_char dcd_v;           /* Data Carrier Detect */
2540         u_char got_st0;         /* contents of ST0 */
2541         u_char got_st1;         /* contents of ST1 */
2542         u_char got_st2;         /* contents of ST2 */
2543         u_char got_st3;         /* contents of ST3 */
2544         struct sr_hardc *hc;    /* card's configuration */
2545         struct sr_hardc *Card[16];/* up to 16 cards in system */
2546         struct sr_softc *sc;    /* channel's softc structure */
2547         struct ifnet *ifp;      /* interface control table */
2548         msci_channel *msci;     /* regs specific to channel */
2549
2550         s = splimp();
2551
2552 #if     0
2553         if (sr_opens == 0) {    /* count of "up" channels */
2554                 sr_watcher = 0; /* indicate no watcher */
2555                 splx(s);
2556                 return;
2557         }
2558 #endif
2559
2560         sr_watcher = 1;         /* mark that we're online */
2561
2562         /*
2563          * Now we'll need a list of cards to process.  Since we can handle
2564          * both ISA and PCI cards (and I didn't think of making this logic
2565          * global YET) we'll generate a single table of card table
2566          * addresses.
2567          */
2568         cards = 0;
2569
2570         for (card = 0; card < NSR; card++) {
2571                 hc = &sr_hardc[card];
2572
2573                 if (hc->sc == (void *)0)
2574                         continue;
2575
2576                 Card[cards++] = hc;
2577         }
2578
2579         hc = sr_hardc_pci;
2580
2581         while (hc) {
2582                 Card[cards++] = hc;
2583                 hc = hc->next;
2584         }
2585
2586         /*
2587          * OK, we've got work we can do.  Let's do it... (Please note that
2588          * this code _only_ deals w/ ISA cards)
2589          */
2590         for (card = 0; card < cards; card++) {
2591                 hc = Card[card];/* get card table */
2592
2593                 for (mch = 0; mch < hc->numports; mch++) {
2594                         sc = &hc->sc[mch];
2595
2596                         ifp = &sc->ifsppp.pp_if;
2597
2598                         /*
2599                          * if this channel isn't "up", skip it
2600                          */
2601                         if ((ifp->if_flags & IFF_UP) == 0)
2602                                 continue;
2603
2604                         /*
2605                          * OK, now we can go looking at this channel's
2606                          * actual register contents...
2607                          */
2608                         msci = &hc->sca->msci[sc->scachan];
2609
2610                         /*
2611                          * OK, now we'll look into the actual status of this
2612                          * channel...
2613                          *
2614                          * I suck in more registers than strictly needed
2615                          */
2616                         got_st0 = SRC_GET8(hc->sca_base, msci->st0);
2617                         got_st1 = SRC_GET8(hc->sca_base, msci->st1);
2618                         got_st2 = SRC_GET8(hc->sca_base, msci->st2);
2619                         got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2620
2621                         /*
2622                          * We want to see if the DCD signal is up (DCD is
2623                          * true if zero)
2624                          */
2625                         dcd_v = (got_st3 & SCA_ST3_DCD) == 0;
2626
2627                         if (dcd_v == 0)
2628                                 printf("sr%d: DCD lost\n", sc->unit);
2629                 }
2630         }
2631
2632         /*
2633          * OK, now set up for the next modem signal checking pass...
2634          */
2635         timeout(sr_modemck, NULL, hz);
2636
2637         splx(s);
2638 }
2639 #endif
2640 #else   /* NETGRAPH */
2641 /*
2642  * If a port is open/active, it's DCD state is checked
2643  * and a loss of DCD is recognized (and eventually processed?).
2644  */
2645 static void
2646 sr_modemck(struct sr_softc *sc )
2647 {
2648         u_int s;
2649         u_char got_st3;                 /* contents of ST3 */
2650         struct sr_hardc *hc = sc->hc;   /* card's configuration */
2651         msci_channel *msci;             /* regs specific to channel */
2652
2653         s = splimp();
2654
2655
2656         if (sc->running == 0)
2657                 return;
2658         /*
2659          * OK, now we can go looking at this channel's register contents...
2660          */
2661         msci = &hc->sca->msci[sc->scachan];
2662         got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2663
2664         /*
2665          * We want to see if the DCD signal is up (DCD is true if zero)
2666          */
2667         sc->dcd = (got_st3 & SCA_ST3_DCD) == 0;
2668         splx(s);
2669 }
2670
2671 #endif  /* NETGRAPH */
2672 static void
2673 sr_msci_intr(struct sr_hardc *hc, u_char isr0)
2674 {
2675         printf("src%d: SRINTR: MSCI\n", hc->cunit);
2676 }
2677
2678 static void
2679 sr_timer_intr(struct sr_hardc *hc, u_char isr2)
2680 {
2681         printf("src%d: SRINTR: TIMER\n", hc->cunit);
2682 }
2683
2684 #ifdef  NETGRAPH
2685 /*****************************************
2686  * Device timeout/watchdog routine.
2687  * called once per second.
2688  * checks to see that if activity was expected, that it hapenned.
2689  * At present we only look to see if expected output was completed.
2690  */
2691 static void
2692 ngsr_watchdog_frame(void * arg)
2693 {
2694         struct sr_softc * sc = arg;
2695         int s;
2696         int     speed;
2697
2698         if (sc->running == 0)
2699                 return; /* if we are not running let timeouts die */
2700         /*
2701          * calculate the apparent throughputs
2702          *  XXX a real hack
2703          */
2704         s = splimp();
2705         speed = sc->inbytes - sc->lastinbytes;
2706         sc->lastinbytes = sc->inbytes;
2707         if ( sc->inrate < speed )
2708                 sc->inrate = speed;
2709         speed = sc->outbytes - sc->lastoutbytes;
2710         sc->lastoutbytes = sc->outbytes;
2711         if ( sc->outrate < speed )
2712                 sc->outrate = speed;
2713         sc->inlast++;
2714         splx(s);
2715
2716         if ((sc->inlast > QUITE_A_WHILE)
2717         && (sc->out_deficit > LOTS_OF_PACKETS)) {
2718                 log(LOG_ERR, "sr%d: No response from remote end\n", sc->unit);
2719                 s = splimp();
2720                 sr_down(sc);
2721                 sr_up(sc);
2722                 sc->inlast = sc->out_deficit = 0;
2723                 splx(s);
2724         } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2725                 if (sc->out_dog == 0) {
2726                         log(LOG_ERR, "sr%d: Transmit failure.. no clock?\n",
2727                                         sc->unit);
2728                         s = splimp();
2729                         srwatchdog(sc);
2730 #if 0
2731                         sr_down(sc);
2732                         sr_up(sc);
2733 #endif
2734                         splx(s);
2735                         sc->inlast = sc->out_deficit = 0;
2736                 } else {
2737                         sc->out_dog--;
2738                 }
2739         }
2740         sr_modemck(sc);         /* update the DCD status */
2741         callout_reset(&sc->sr_timer, hz, ngsr_watchdog_frame, sc);
2742 }
2743
2744 /***********************************************************************
2745  * This section contains the methods for the Netgraph interface
2746  ***********************************************************************/
2747 /*
2748  * It is not possible or allowable to create a node of this type.
2749  * If the hardware exists, it will already have created it.
2750  */
2751 static  int
2752 ngsr_constructor(node_p *nodep)
2753 {
2754         return (EINVAL);
2755 }
2756
2757 /*
2758  * give our ok for a hook to be added...
2759  * If we are not running this should kick the device into life.
2760  * The hook's private info points to our stash of info about that
2761  * channel.
2762  */
2763 static int
2764 ngsr_newhook(node_p node, hook_p hook, const char *name)
2765 {
2766         struct sr_softc *       sc = node->private;
2767
2768         /*
2769          * check if it's our friend the debug hook
2770          */
2771         if (strcmp(name, NG_SR_HOOK_DEBUG) == 0) {
2772                 hook->private = NULL; /* paranoid */
2773                 sc->debug_hook = hook;
2774                 return (0);
2775         }
2776
2777         /*
2778          * Check for raw mode hook.
2779          */
2780         if (strcmp(name, NG_SR_HOOK_RAW) != 0) {
2781                 return (EINVAL);
2782         }
2783         hook->private = sc;
2784         sc->hook = hook;
2785         sc->datahooks++;
2786         sr_up(sc);
2787         return (0);
2788 }
2789
2790 /*
2791  * incoming messages.
2792  * Just respond to the generic TEXT_STATUS message
2793  */
2794 static  int
2795 ngsr_rcvmsg(node_p node,
2796         struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp)
2797 {
2798         struct sr_softc *       sc;
2799         int error = 0;
2800
2801         sc = node->private;
2802         switch (msg->header.typecookie) {
2803             case        NG_SR_COOKIE:
2804                 error = EINVAL;
2805                 break;
2806             case        NGM_GENERIC_COOKIE:
2807                 switch(msg->header.cmd) {
2808                     case NGM_TEXT_STATUS: {
2809                             char        *arg;
2810                             int pos = 0;
2811                             int resplen = sizeof(struct ng_mesg) + 512;
2812                             MALLOC(*resp, struct ng_mesg *, resplen,
2813                                         M_NETGRAPH, M_INTWAIT | M_ZERO);
2814                             if (*resp == NULL) {
2815                                 error = ENOMEM;
2816                                 break;
2817                             }
2818                             arg = (*resp)->data;
2819
2820                             /*
2821                              * Put in the throughput information.
2822                              */
2823                             pos = sprintf(arg, "%ld bytes in, %ld bytes out\n"
2824                             "highest rate seen: %ld B/S in, %ld B/S out\n",
2825                             sc->inbytes, sc->outbytes,
2826                             sc->inrate, sc->outrate);
2827                             pos += sprintf(arg + pos,
2828                                 "%ld output errors\n",
2829                                 sc->oerrors);
2830                             pos += sprintf(arg + pos,
2831                                 "ierrors = %ld, %ld, %ld, %ld, %ld, %ld\n",
2832                                 sc->ierrors[0],
2833                                 sc->ierrors[1],
2834                                 sc->ierrors[2],
2835                                 sc->ierrors[3],
2836                                 sc->ierrors[4],
2837                                 sc->ierrors[5]);
2838
2839                             (*resp)->header.version = NG_VERSION;
2840                             (*resp)->header.arglen = strlen(arg) + 1;
2841                             (*resp)->header.token = msg->header.token;
2842                             (*resp)->header.typecookie = NG_SR_COOKIE;
2843                             (*resp)->header.cmd = msg->header.cmd;
2844                             strncpy((*resp)->header.cmdstr, "status",
2845                                         NG_CMDSTRLEN);
2846                         }
2847                         break;
2848                     default:
2849                         error = EINVAL;
2850                         break;
2851                     }
2852                 break;
2853             default:
2854                 error = EINVAL;
2855                 break;
2856         }
2857         free(msg, M_NETGRAPH);
2858         return (error);
2859 }
2860
2861 /*
2862  * get data from another node and transmit it to the correct channel
2863  */
2864 static  int
2865 ngsr_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
2866 {
2867         int s;
2868         int error = 0;
2869         struct sr_softc * sc = hook->node->private;
2870         struct ifqueue  *xmitq_p;
2871
2872         /*
2873          * data doesn't come in from just anywhere (e.g control hook)
2874          */
2875         if ( hook->private == NULL) {
2876                 error = ENETDOWN;
2877                 goto bad;
2878         }
2879
2880         /*
2881          * Now queue the data for when it can be sent
2882          */
2883         if (meta && meta->priority > 0) {
2884                 xmitq_p = (&sc->xmitq_hipri);
2885         } else {
2886                 xmitq_p = (&sc->xmitq);
2887         }
2888         s = splimp();
2889         if (IF_QFULL(xmitq_p)) {
2890                 IF_DROP(xmitq_p);
2891                 splx(s);
2892                 error = ENOBUFS;
2893                 goto bad;
2894         }
2895         IF_ENQUEUE(xmitq_p, m);
2896         srstart(sc);
2897         splx(s);
2898         return (0);
2899
2900 bad:
2901         /*
2902          * It was an error case.
2903          * check if we need to free the mbuf, and then return the error
2904          */
2905         NG_FREE_DATA(m, meta);
2906         return (error);
2907 }
2908
2909 /*
2910  * do local shutdown processing..
2911  * this node will refuse to go away, unless the hardware says to..
2912  * don't unref the node, or remove our name. just clear our links up.
2913  */
2914 static  int
2915 ngsr_rmnode(node_p node)
2916 {
2917         struct sr_softc * sc = node->private;
2918
2919         sr_down(sc);
2920         ng_cutlinks(node);
2921         node->flags &= ~NG_INVALID; /* bounce back to life */
2922         return (0);
2923 }
2924
2925 /* already linked */
2926 static  int
2927 ngsr_connect(hook_p hook)
2928 {
2929         /* be really amiable and just say "YUP that's OK by me! " */
2930         return (0);
2931 }
2932
2933 /*
2934  * notify on hook disconnection (destruction)
2935  *
2936  * Invalidate the private data associated with this dlci.
2937  * For this type, removal of the last link resets tries to destroy the node.
2938  * As the device still exists, the shutdown method will not actually
2939  * destroy the node, but reset the device and leave it 'fresh' :)
2940  *
2941  * The node removal code will remove all references except that owned by the
2942  * driver.
2943  */
2944 static  int
2945 ngsr_disconnect(hook_p hook)
2946 {
2947         struct sr_softc * sc = hook->node->private;
2948         int     s;
2949         /*
2950          * If it's the data hook, then free resources etc.
2951          */
2952         if (hook->private) {
2953                 s = splimp();
2954                 sc->datahooks--;
2955                 if (sc->datahooks == 0)
2956                         sr_down(sc);
2957                 splx(s);
2958         } else {
2959                 sc->debug_hook = NULL;
2960         }
2961         return (0);
2962 }
2963
2964 /*
2965  * called during bootup
2966  * or LKM loading to put this type into the list of known modules
2967  */
2968 static void
2969 ngsr_init(void *ignored)
2970 {
2971         if (ng_newtype(&typestruct))
2972                 printf("ngsr install failed\n");
2973         ngsr_done_init = 1;
2974 }
2975 #endif /* NETGRAPH */
2976
2977 /*
2978  ********************************* END ************************************
2979  */