2 * Copyright (c) 1991 The Regents of the University of California.
3 * Copyright (c) 2008 The DragonFly Project.
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34 * $FreeBSD: src/sys/i386/isa/intr_machdep.h,v 1.19.2.2 2001/10/14 20:05:50 luigi Exp $
35 * $DragonFly: src/sys/platform/pc64/isa/intr_machdep.h,v 1.1 2008/08/29 17:07:19 dillon Exp $
38 #ifndef _ARCH_INTR_MACHDEP_H_
39 #define _ARCH_INTR_MACHDEP_H_
43 #include <sys/types.h>
48 * Low level interrupt code.
53 #define IDT_OFFSET 0x20
54 #define IDT_OFFSET_SYSCALL 0x80
55 #define IDT_OFFSET_IPI 0xe0
60 * Local APIC TPR priority vector levels:
62 * 0xff (255) +-------------+
63 * | | 15 (IPIs: Xcpustop, Xspuriousint)
64 * 0xf0 (240) +-------------+
65 * | | 14 (IPIs: Xinvltlb, Xipiq, Xtimer)
66 * 0xe0 (224) +-------------+
68 * 0xd0 (208) +-------------+
70 * 0xc0 (192) +-------------+
72 * 0xb0 (176) +-------------+
74 * 0xa0 (160) +-------------+
76 * 0x90 (144) +-------------+
77 * | | 8 (syscall at 0x80)
78 * 0x80 (128) +-------------+
80 * 0x70 (112) +-------------+
82 * 0x60 (96) +-------------+
84 * 0x50 (80) +-------------+
86 * 0x40 (64) +-------------+
88 * 0x30 (48) +-------------+
89 * | | 2 (hardware INTs)
90 * 0x20 (32) +-------------+
91 * | | 1 (exceptions, traps, etc.)
92 * 0x10 (16) +-------------+
93 * | | 0 (exceptions, traps, etc.)
94 * 0x00 (0) +-------------+
98 /* Local APIC Task Priority Register */
99 #define TPR_IPI (IDT_OFFSET_IPI - 1)
105 #define IDT_OFFSET_IPIG1 IDT_OFFSET_IPI
108 #define XINVLTLB_OFFSET (IDT_OFFSET_IPIG1 + 0)
110 /* IPI group1 1: unused (was inter-cpu clock handling) */
111 /* IPI group1 2: unused (was inter-cpu rendezvous) */
113 /* IPIQ rendezvous */
114 #define XIPIQ_OFFSET (IDT_OFFSET_IPIG1 + 3)
116 /* TIMER rendezvous */
117 #define XTIMER_OFFSET (IDT_OFFSET_IPIG1 + 4)
119 /* IPI group1 5 ~ 15: unused */
125 #define IDT_OFFSET_IPIG2 (IDT_OFFSET_IPIG1 + TPR_STEP)
127 /* IPI to signal CPUs to stop and wait for another CPU to restart them */
128 #define XCPUSTOP_OFFSET (IDT_OFFSET_IPIG2 + 0)
130 /* IPI group2 1 ~ 14: unused */
132 /* NOTE: this vector MUST be xxxx1111 */
133 #define XSPURIOUSINT_OFFSET (IDT_OFFSET_IPIG2 + 15)
140 * Type of the first (asm) part of an interrupt handler.
142 #ifndef JG_defined_inthand_t
143 #define JG_defined_inthand_t
144 typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
147 #define IDTVEC(name) __CONCAT(X,name)
151 Xinvltlb, /* TLB shootdowns */
152 Xcpuast, /* Additional software trap on other cpu */
153 Xforward_irq, /* Forward irq to cpu holding ISR lock */
154 Xcpustop, /* CPU stops & waits for another CPU to restart it */
155 Xspuriousint, /* handle APIC "spurious INTs" */
156 Xtimer, /* handle LAPIC timer INT */
157 Xipiq; /* handle lwkt_send_ipiq() requests */
164 #endif /* !_ARCH_INTR_MACHDEP_H_ */