3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/dev/mii/rgephy.c,v 1.7 2005/09/30 19:39:27 imp Exp $
33 * $DragonFly: src/sys/dev/netif/mii_layer/rgephy.c,v 1.1 2005/12/26 13:36:18 sephe Exp $
37 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY.
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
47 #include <machine/bus.h>
48 #include <machine/clock.h>
51 #include <net/if_arp.h>
52 #include <net/if_media.h>
54 #include <dev/netif/mii_layer/mii.h>
55 #include <dev/netif/mii_layer/miivar.h>
56 #include <dev/netif/mii_layer/miidevs.h>
58 #include <dev/netif/re/if_rereg.h>
59 #include <dev/netif/mii_layer/rgephyreg.h>
61 #include "miibus_if.h"
63 #include <machine/bus.h>
65 static int rgephy_probe(device_t);
66 static int rgephy_attach(device_t);
68 static device_method_t rgephy_methods[] = {
69 /* device interface */
70 DEVMETHOD(device_probe, rgephy_probe),
71 DEVMETHOD(device_attach, rgephy_attach),
72 DEVMETHOD(device_detach, ukphy_detach),
73 DEVMETHOD(device_shutdown, bus_generic_shutdown),
77 static devclass_t rgephy_devclass;
79 static driver_t rgephy_driver = {
82 sizeof(struct mii_softc)
85 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0);
87 static int rgephy_service(struct mii_softc *, struct mii_data *, int);
88 static void rgephy_status(struct mii_softc *);
89 static int rgephy_mii_phy_auto(struct mii_softc *);
90 static void rgephy_reset(struct mii_softc *);
91 static void rgephy_loop(struct mii_softc *);
92 static void rgephy_load_dspcode(struct mii_softc *);
93 static int rgephy_mii_model;
96 rgephy_probe(device_t dev)
98 struct mii_attach_args *ma;
100 ma = device_get_ivars(dev);
102 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxREALTEK &&
103 MII_MODEL(ma->mii_id2) == MII_MODEL_xxREALTEK_RTL8169S) {
104 device_set_desc(dev, MII_STR_xxREALTEK_RTL8169S);
112 rgephy_attach(device_t dev)
114 struct mii_softc *sc;
115 struct mii_attach_args *ma;
116 struct mii_data *mii;
117 const char *sep = "";
119 sc = device_get_softc(dev);
120 ma = device_get_ivars(dev);
121 mii_softc_init(sc, ma);
122 sc->mii_dev = device_get_parent(dev);
124 mii = device_get_softc(sc->mii_dev);
125 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
127 sc->mii_inst = mii->mii_instance;
128 sc->mii_service = rgephy_service;
131 sc->mii_flags |= MIIF_NOISOLATE;
134 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
135 #define PRINT(s) printf("%s%s", sep, s); sep = ", "
137 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
140 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
141 BMCR_LOOP|BMCR_S100);
144 rgephy_mii_model = MII_MODEL(ma->mii_id2);
147 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
148 sc->mii_capabilities &= ~BMSR_ANEG;
150 device_printf(dev, " ");
151 mii_add_media(sc, sc->mii_capabilities);
152 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst),
154 PRINT(", 1000baseTX");
155 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0);
156 PRINT("1000baseTX-FDX");
157 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
164 /* Make mii_bmsr_media_to_anar() work correctly */
165 sc->mii_flags |= MIIF_IS_1000X;
167 MIIBUS_MEDIAINIT(sc->mii_dev);
172 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
174 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
180 * If we're not polling our PHY instance, just return.
182 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
188 * If the media indicates a different PHY instance,
191 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
192 reg = PHY_READ(sc, MII_BMCR);
193 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
198 * If the interface is not up, don't do anything.
200 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
203 rgephy_reset(sc); /* XXX hardware bug work-around */
205 switch (IFM_SUBTYPE(ife->ifm_media)) {
209 * If we're already in auto mode, just return.
211 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
214 rgephy_mii_phy_auto(sc);
217 speed = RGEPHY_S1000;
226 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
227 speed |= RGEPHY_BMCR_FDX;
228 gig = RGEPHY_1000CTL_AFD;
230 gig = RGEPHY_1000CTL_AHD;
233 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
234 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
235 PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE);
237 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
240 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
241 PHY_WRITE(sc, RGEPHY_MII_BMCR,
242 speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG);
245 * When settning the link manually, one side must
246 * be the master and the other the slave. However
247 * ifmedia doesn't give us a good way to specify
248 * this, so we fake it by using one of the LINK
249 * flags. If LINK0 is set, we program the PHY to
250 * be a master, otherwise it's a slave.
252 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
253 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
254 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC);
256 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
257 gig|RGEPHY_1000CTL_MSE);
262 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
273 * If we're not currently selected, just return.
275 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
279 * Is the interface even up?
281 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
285 * Only used for autonegotiation.
287 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
291 * Check to see if we have link. If we do, we don't
292 * need to restart the autonegotiation process.
294 * XXX Read the BMSR twice in case it's latched?
296 reg = PHY_READ(sc, RE_GMEDIASTAT);
297 if (reg & RE_GMEDIASTAT_LINK)
301 * Only retry autonegotiation every 5 seconds.
303 if (++sc->mii_ticks <= 5/*10*/)
307 rgephy_mii_phy_auto(sc);
311 /* Update the media status. */
315 * Callback if something changed. Note that we need to poke
316 * the DSP on the RealTek PHYs if the media changes.
318 if (sc->mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) {
319 rgephy_load_dspcode(sc);
320 MIIBUS_STATCHG(sc->mii_dev);
321 sc->mii_active = mii->mii_media_active;
327 rgephy_status(struct mii_softc *sc)
329 struct mii_data *mii = sc->mii_pdata;
332 mii->mii_media_status = IFM_AVALID;
333 mii->mii_media_active = IFM_ETHER;
335 bmsr = PHY_READ(sc, RE_GMEDIASTAT);
337 if (bmsr & RE_GMEDIASTAT_LINK)
338 mii->mii_media_status |= IFM_ACTIVE;
339 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
341 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
343 if (bmcr & RGEPHY_BMCR_LOOP)
344 mii->mii_media_active |= IFM_LOOP;
346 if (bmcr & RGEPHY_BMCR_AUTOEN) {
347 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
348 /* Erg, still trying, I guess... */
349 mii->mii_media_active |= IFM_NONE;
354 bmsr = PHY_READ(sc, RE_GMEDIASTAT);
356 if (bmsr & RE_GMEDIASTAT_1000MBPS) {
357 mii->mii_media_active |= IFM_1000_T;
358 } else if (bmsr & RE_GMEDIASTAT_100MBPS) {
359 mii->mii_media_active |= IFM_100_TX;
360 } else if (bmsr & RE_GMEDIASTAT_10MBPS) {
361 mii->mii_media_active |= IFM_10_T;
363 mii->mii_media_active |= IFM_NONE;
367 if (bmsr & RE_GMEDIASTAT_FDX)
368 mii->mii_media_active |= IFM_FDX;
372 rgephy_mii_phy_auto(struct mii_softc *mii)
377 PHY_WRITE(mii, RGEPHY_MII_ANAR, mii_bmsr_media_to_anar(mii));
379 PHY_WRITE(mii, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AFD);
381 PHY_WRITE(mii, RGEPHY_MII_BMCR,
382 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
385 return (EJUSTRETURN);
389 rgephy_loop(struct mii_softc *sc)
394 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
397 for (i = 0; i < 15000; i++) {
398 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
399 if (!(bmsr & RGEPHY_BMSR_LINK)) {
401 device_printf(sc->mii_dev, "looped %d\n", i);
409 #define PHY_SETBIT(x, y, z) \
410 PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
411 #define PHY_CLRBIT(x, y, z) \
412 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
415 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
416 * existing revisions of the 8169S/8110S chips need to be tuned in
417 * order to reliably negotiate a 1000Mbps link. Later revs of the
418 * chips may not require this software tuning.
421 rgephy_load_dspcode(struct mii_softc *sc)
425 PHY_WRITE(sc, 31, 0x0001);
426 PHY_WRITE(sc, 21, 0x1000);
427 PHY_WRITE(sc, 24, 0x65C7);
428 PHY_CLRBIT(sc, 4, 0x0800);
429 val = PHY_READ(sc, 4) & 0xFFF;
430 PHY_WRITE(sc, 4, val);
431 PHY_WRITE(sc, 3, 0x00A1);
432 PHY_WRITE(sc, 2, 0x0008);
433 PHY_WRITE(sc, 1, 0x1020);
434 PHY_WRITE(sc, 0, 0x1000);
435 PHY_SETBIT(sc, 4, 0x0800);
436 PHY_CLRBIT(sc, 4, 0x0800);
437 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
438 PHY_WRITE(sc, 4, val);
439 PHY_WRITE(sc, 3, 0xFF41);
440 PHY_WRITE(sc, 2, 0xDE60);
441 PHY_WRITE(sc, 1, 0x0140);
442 PHY_WRITE(sc, 0, 0x0077);
443 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
444 PHY_WRITE(sc, 4, val);
445 PHY_WRITE(sc, 3, 0xDF01);
446 PHY_WRITE(sc, 2, 0xDF20);
447 PHY_WRITE(sc, 1, 0xFF95);
448 PHY_WRITE(sc, 0, 0xFA00);
449 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
450 PHY_WRITE(sc, 4, val);
451 PHY_WRITE(sc, 3, 0xFF41);
452 PHY_WRITE(sc, 2, 0xDE20);
453 PHY_WRITE(sc, 1, 0x0140);
454 PHY_WRITE(sc, 0, 0x00BB);
455 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
456 PHY_WRITE(sc, 4, val);
457 PHY_WRITE(sc, 3, 0xDF01);
458 PHY_WRITE(sc, 2, 0xDF20);
459 PHY_WRITE(sc, 1, 0xFF95);
460 PHY_WRITE(sc, 0, 0xBF00);
461 PHY_SETBIT(sc, 4, 0x0800);
462 PHY_CLRBIT(sc, 4, 0x0800);
463 PHY_WRITE(sc, 31, 0x0000);
469 rgephy_reset(struct mii_softc *sc)
473 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_AUTOEN);
475 rgephy_load_dspcode(sc);