1 /* Rtl-level induction variable analysis.
2 Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by the
9 Free Software Foundation; either version 3, or (at your option) any
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 /* This is a simple analysis of induction variables of the loop. The major use
22 is for determining the number of iterations of a loop for loop unrolling,
23 doloop optimization and branch prediction. The iv information is computed
26 Induction variables are analyzed by walking the use-def chains. When
27 a basic induction variable (biv) is found, it is cached in the bivs
28 hash table. When register is proved to be a biv, its description
29 is stored to DF_REF_DATA of the def reference.
31 The analysis works always with one loop -- you must call
32 iv_analysis_loop_init (loop) for it. All the other functions then work with
33 this loop. When you need to work with another loop, just call
34 iv_analysis_loop_init for it. When you no longer need iv analysis, call
35 iv_analysis_done () to clean up the memory.
37 The available functions are:
39 iv_analyze (insn, reg, iv): Stores the description of the induction variable
40 corresponding to the use of register REG in INSN to IV. Returns true if
41 REG is an induction variable in INSN. false otherwise.
42 If use of REG is not found in INSN, following insns are scanned (so that
43 we may call this function on insn returned by get_condition).
44 iv_analyze_result (insn, def, iv): Stores to IV the description of the iv
45 corresponding to DEF, which is a register defined in INSN.
46 iv_analyze_expr (insn, rhs, mode, iv): Stores to IV the description of iv
47 corresponding to expression EXPR evaluated at INSN. All registers used bu
48 EXPR must also be used in INSN.
53 #include "coretypes.h"
56 #include "hard-reg-set.h"
58 #include "basic-block.h"
67 /* Possible return values of iv_get_reaching_def. */
71 /* More than one reaching def, or reaching def that does not
75 /* The use is trivial invariant of the loop, i.e. is not changed
79 /* The use is reached by initial value and a value from the
80 previous iteration. */
83 /* The use has single dominating def. */
87 /* Information about a biv. */
91 unsigned regno; /* The register of the biv. */
92 struct rtx_iv iv; /* Value of the biv. */
95 static bool clean_slate = true;
97 static unsigned int iv_ref_table_size = 0;
99 /* Table of rtx_ivs indexed by the df_ref uid field. */
100 static struct rtx_iv ** iv_ref_table;
102 /* Induction variable stored at the reference. */
103 #define DF_REF_IV(REF) iv_ref_table[DF_REF_ID(REF)]
104 #define DF_REF_IV_SET(REF, IV) iv_ref_table[DF_REF_ID(REF)] = (IV)
106 /* The current loop. */
108 static struct loop *current_loop;
110 /* Bivs of the current loop. */
114 static bool iv_analyze_op (rtx, rtx, struct rtx_iv *);
116 /* Dumps information about IV to FILE. */
118 extern void dump_iv_info (FILE *, struct rtx_iv *);
120 dump_iv_info (FILE *file, struct rtx_iv *iv)
124 fprintf (file, "not simple");
128 if (iv->step == const0_rtx
129 && !iv->first_special)
130 fprintf (file, "invariant ");
132 print_rtl (file, iv->base);
133 if (iv->step != const0_rtx)
135 fprintf (file, " + ");
136 print_rtl (file, iv->step);
137 fprintf (file, " * iteration");
139 fprintf (file, " (in %s)", GET_MODE_NAME (iv->mode));
141 if (iv->mode != iv->extend_mode)
142 fprintf (file, " %s to %s",
143 rtx_name[iv->extend],
144 GET_MODE_NAME (iv->extend_mode));
146 if (iv->mult != const1_rtx)
148 fprintf (file, " * ");
149 print_rtl (file, iv->mult);
151 if (iv->delta != const0_rtx)
153 fprintf (file, " + ");
154 print_rtl (file, iv->delta);
156 if (iv->first_special)
157 fprintf (file, " (first special)");
160 /* Generates a subreg to get the least significant part of EXPR (in mode
161 INNER_MODE) to OUTER_MODE. */
164 lowpart_subreg (enum machine_mode outer_mode, rtx expr,
165 enum machine_mode inner_mode)
167 return simplify_gen_subreg (outer_mode, expr, inner_mode,
168 subreg_lowpart_offset (outer_mode, inner_mode));
172 check_iv_ref_table_size (void)
174 if (iv_ref_table_size < DF_DEFS_TABLE_SIZE())
176 unsigned int new_size = DF_DEFS_TABLE_SIZE () + (DF_DEFS_TABLE_SIZE () / 4);
177 iv_ref_table = XRESIZEVEC (struct rtx_iv *, iv_ref_table, new_size);
178 memset (&iv_ref_table[iv_ref_table_size], 0,
179 (new_size - iv_ref_table_size) * sizeof (struct rtx_iv *));
180 iv_ref_table_size = new_size;
185 /* Checks whether REG is a well-behaved register. */
188 simple_reg_p (rtx reg)
192 if (GET_CODE (reg) == SUBREG)
194 if (!subreg_lowpart_p (reg))
196 reg = SUBREG_REG (reg);
203 if (HARD_REGISTER_NUM_P (r))
206 if (GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
212 /* Clears the information about ivs stored in df. */
217 unsigned i, n_defs = DF_DEFS_TABLE_SIZE ();
220 check_iv_ref_table_size ();
221 for (i = 0; i < n_defs; i++)
223 iv = iv_ref_table[i];
227 iv_ref_table[i] = NULL;
234 /* Returns hash value for biv B. */
237 biv_hash (const void *b)
239 return ((const struct biv_entry *) b)->regno;
242 /* Compares biv B and register R. */
245 biv_eq (const void *b, const void *r)
247 return ((const struct biv_entry *) b)->regno == REGNO ((const_rtx) r);
250 /* Prepare the data for an induction variable analysis of a LOOP. */
253 iv_analysis_loop_init (struct loop *loop)
255 basic_block *body = get_loop_body_in_dom_order (loop), bb;
256 bitmap blocks = BITMAP_ALLOC (NULL);
261 /* Clear the information from the analysis of the previous loop. */
264 df_set_flags (DF_EQ_NOTES + DF_DEFER_INSN_RESCAN);
265 bivs = htab_create (10, biv_hash, biv_eq, free);
271 for (i = 0; i < loop->num_nodes; i++)
274 bitmap_set_bit (blocks, bb->index);
276 /* Get rid of the ud chains before processing the rescans. Then add
278 df_remove_problem (df_chain);
279 df_process_deferred_rescans ();
280 df_chain_add_problem (DF_UD_CHAIN);
281 df_set_blocks (blocks);
284 df_dump_region (dump_file);
286 check_iv_ref_table_size ();
287 BITMAP_FREE (blocks);
291 /* Finds the definition of REG that dominates loop latch and stores
292 it to DEF. Returns false if there is not a single definition
293 dominating the latch. If REG has no definition in loop, DEF
294 is set to NULL and true is returned. */
297 latch_dominating_def (rtx reg, df_ref *def)
299 df_ref single_rd = NULL, adef;
300 unsigned regno = REGNO (reg);
301 struct df_rd_bb_info *bb_info = DF_RD_BB_INFO (current_loop->latch);
303 for (adef = DF_REG_DEF_CHAIN (regno); adef; adef = DF_REF_NEXT_REG (adef))
305 if (!bitmap_bit_p (df->blocks_to_analyze, DF_REF_BBNO (adef))
306 || !bitmap_bit_p (bb_info->out, DF_REF_ID (adef)))
309 /* More than one reaching definition. */
313 if (!just_once_each_iteration_p (current_loop, DF_REF_BB (adef)))
323 /* Gets definition of REG reaching its use in INSN and stores it to DEF. */
325 static enum iv_grd_result
326 iv_get_reaching_def (rtx insn, rtx reg, df_ref *def)
329 basic_block def_bb, use_bb;
334 if (!simple_reg_p (reg))
336 if (GET_CODE (reg) == SUBREG)
337 reg = SUBREG_REG (reg);
338 gcc_assert (REG_P (reg));
340 use = df_find_use (insn, reg);
341 gcc_assert (use != NULL);
343 if (!DF_REF_CHAIN (use))
344 return GRD_INVARIANT;
346 /* More than one reaching def. */
347 if (DF_REF_CHAIN (use)->next)
350 adef = DF_REF_CHAIN (use)->ref;
352 /* We do not handle setting only part of the register. */
353 if (DF_REF_FLAGS (adef) & DF_REF_READ_WRITE)
356 def_insn = DF_REF_INSN (adef);
357 def_bb = DF_REF_BB (adef);
358 use_bb = BLOCK_FOR_INSN (insn);
360 if (use_bb == def_bb)
361 dom_p = (DF_INSN_LUID (def_insn) < DF_INSN_LUID (insn));
363 dom_p = dominated_by_p (CDI_DOMINATORS, use_bb, def_bb);
368 return GRD_SINGLE_DOM;
371 /* The definition does not dominate the use. This is still OK if
372 this may be a use of a biv, i.e. if the def_bb dominates loop
374 if (just_once_each_iteration_p (current_loop, def_bb))
375 return GRD_MAYBE_BIV;
380 /* Sets IV to invariant CST in MODE. Always returns true (just for
381 consistency with other iv manipulation functions that may fail). */
384 iv_constant (struct rtx_iv *iv, rtx cst, enum machine_mode mode)
386 if (mode == VOIDmode)
387 mode = GET_MODE (cst);
391 iv->step = const0_rtx;
392 iv->first_special = false;
393 iv->extend = UNKNOWN;
394 iv->extend_mode = iv->mode;
395 iv->delta = const0_rtx;
396 iv->mult = const1_rtx;
401 /* Evaluates application of subreg to MODE on IV. */
404 iv_subreg (struct rtx_iv *iv, enum machine_mode mode)
406 /* If iv is invariant, just calculate the new value. */
407 if (iv->step == const0_rtx
408 && !iv->first_special)
410 rtx val = get_iv_value (iv, const0_rtx);
411 val = lowpart_subreg (mode, val, iv->extend_mode);
414 iv->extend = UNKNOWN;
415 iv->mode = iv->extend_mode = mode;
416 iv->delta = const0_rtx;
417 iv->mult = const1_rtx;
421 if (iv->extend_mode == mode)
424 if (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (iv->mode))
427 iv->extend = UNKNOWN;
430 iv->base = simplify_gen_binary (PLUS, iv->extend_mode, iv->delta,
431 simplify_gen_binary (MULT, iv->extend_mode,
432 iv->base, iv->mult));
433 iv->step = simplify_gen_binary (MULT, iv->extend_mode, iv->step, iv->mult);
434 iv->mult = const1_rtx;
435 iv->delta = const0_rtx;
436 iv->first_special = false;
441 /* Evaluates application of EXTEND to MODE on IV. */
444 iv_extend (struct rtx_iv *iv, enum rtx_code extend, enum machine_mode mode)
446 /* If iv is invariant, just calculate the new value. */
447 if (iv->step == const0_rtx
448 && !iv->first_special)
450 rtx val = get_iv_value (iv, const0_rtx);
451 val = simplify_gen_unary (extend, mode, val, iv->extend_mode);
454 iv->extend = UNKNOWN;
455 iv->mode = iv->extend_mode = mode;
456 iv->delta = const0_rtx;
457 iv->mult = const1_rtx;
461 if (mode != iv->extend_mode)
464 if (iv->extend != UNKNOWN
465 && iv->extend != extend)
473 /* Evaluates negation of IV. */
476 iv_neg (struct rtx_iv *iv)
478 if (iv->extend == UNKNOWN)
480 iv->base = simplify_gen_unary (NEG, iv->extend_mode,
481 iv->base, iv->extend_mode);
482 iv->step = simplify_gen_unary (NEG, iv->extend_mode,
483 iv->step, iv->extend_mode);
487 iv->delta = simplify_gen_unary (NEG, iv->extend_mode,
488 iv->delta, iv->extend_mode);
489 iv->mult = simplify_gen_unary (NEG, iv->extend_mode,
490 iv->mult, iv->extend_mode);
496 /* Evaluates addition or subtraction (according to OP) of IV1 to IV0. */
499 iv_add (struct rtx_iv *iv0, struct rtx_iv *iv1, enum rtx_code op)
501 enum machine_mode mode;
504 /* Extend the constant to extend_mode of the other operand if necessary. */
505 if (iv0->extend == UNKNOWN
506 && iv0->mode == iv0->extend_mode
507 && iv0->step == const0_rtx
508 && GET_MODE_SIZE (iv0->extend_mode) < GET_MODE_SIZE (iv1->extend_mode))
510 iv0->extend_mode = iv1->extend_mode;
511 iv0->base = simplify_gen_unary (ZERO_EXTEND, iv0->extend_mode,
512 iv0->base, iv0->mode);
514 if (iv1->extend == UNKNOWN
515 && iv1->mode == iv1->extend_mode
516 && iv1->step == const0_rtx
517 && GET_MODE_SIZE (iv1->extend_mode) < GET_MODE_SIZE (iv0->extend_mode))
519 iv1->extend_mode = iv0->extend_mode;
520 iv1->base = simplify_gen_unary (ZERO_EXTEND, iv1->extend_mode,
521 iv1->base, iv1->mode);
524 mode = iv0->extend_mode;
525 if (mode != iv1->extend_mode)
528 if (iv0->extend == UNKNOWN && iv1->extend == UNKNOWN)
530 if (iv0->mode != iv1->mode)
533 iv0->base = simplify_gen_binary (op, mode, iv0->base, iv1->base);
534 iv0->step = simplify_gen_binary (op, mode, iv0->step, iv1->step);
539 /* Handle addition of constant. */
540 if (iv1->extend == UNKNOWN
542 && iv1->step == const0_rtx)
544 iv0->delta = simplify_gen_binary (op, mode, iv0->delta, iv1->base);
548 if (iv0->extend == UNKNOWN
550 && iv0->step == const0_rtx)
558 iv0->delta = simplify_gen_binary (PLUS, mode, iv0->delta, arg);
565 /* Evaluates multiplication of IV by constant CST. */
568 iv_mult (struct rtx_iv *iv, rtx mby)
570 enum machine_mode mode = iv->extend_mode;
572 if (GET_MODE (mby) != VOIDmode
573 && GET_MODE (mby) != mode)
576 if (iv->extend == UNKNOWN)
578 iv->base = simplify_gen_binary (MULT, mode, iv->base, mby);
579 iv->step = simplify_gen_binary (MULT, mode, iv->step, mby);
583 iv->delta = simplify_gen_binary (MULT, mode, iv->delta, mby);
584 iv->mult = simplify_gen_binary (MULT, mode, iv->mult, mby);
590 /* Evaluates shift of IV by constant CST. */
593 iv_shift (struct rtx_iv *iv, rtx mby)
595 enum machine_mode mode = iv->extend_mode;
597 if (GET_MODE (mby) != VOIDmode
598 && GET_MODE (mby) != mode)
601 if (iv->extend == UNKNOWN)
603 iv->base = simplify_gen_binary (ASHIFT, mode, iv->base, mby);
604 iv->step = simplify_gen_binary (ASHIFT, mode, iv->step, mby);
608 iv->delta = simplify_gen_binary (ASHIFT, mode, iv->delta, mby);
609 iv->mult = simplify_gen_binary (ASHIFT, mode, iv->mult, mby);
615 /* The recursive part of get_biv_step. Gets the value of the single value
616 defined by DEF wrto initial value of REG inside loop, in shape described
620 get_biv_step_1 (df_ref def, rtx reg,
621 rtx *inner_step, enum machine_mode *inner_mode,
622 enum rtx_code *extend, enum machine_mode outer_mode,
625 rtx set, rhs, op0 = NULL_RTX, op1 = NULL_RTX;
626 rtx next, nextr, tmp;
628 rtx insn = DF_REF_INSN (def);
630 enum iv_grd_result res;
632 set = single_set (insn);
636 rhs = find_reg_equal_equiv_note (insn);
642 code = GET_CODE (rhs);
655 if (code == PLUS && CONSTANT_P (op0))
657 tmp = op0; op0 = op1; op1 = tmp;
660 if (!simple_reg_p (op0)
661 || !CONSTANT_P (op1))
664 if (GET_MODE (rhs) != outer_mode)
666 /* ppc64 uses expressions like
668 (set x:SI (plus:SI (subreg:SI y:DI) 1)).
670 this is equivalent to
672 (set x':DI (plus:DI y:DI 1))
673 (set x:SI (subreg:SI (x':DI)). */
674 if (GET_CODE (op0) != SUBREG)
676 if (GET_MODE (SUBREG_REG (op0)) != outer_mode)
685 if (GET_MODE (rhs) != outer_mode)
689 if (!simple_reg_p (op0))
699 if (GET_CODE (next) == SUBREG)
701 if (!subreg_lowpart_p (next))
704 nextr = SUBREG_REG (next);
705 if (GET_MODE (nextr) != outer_mode)
711 res = iv_get_reaching_def (insn, nextr, &next_def);
713 if (res == GRD_INVALID || res == GRD_INVARIANT)
716 if (res == GRD_MAYBE_BIV)
718 if (!rtx_equal_p (nextr, reg))
721 *inner_step = const0_rtx;
723 *inner_mode = outer_mode;
724 *outer_step = const0_rtx;
726 else if (!get_biv_step_1 (next_def, reg,
727 inner_step, inner_mode, extend, outer_mode,
731 if (GET_CODE (next) == SUBREG)
733 enum machine_mode amode = GET_MODE (next);
735 if (GET_MODE_SIZE (amode) > GET_MODE_SIZE (*inner_mode))
739 *inner_step = simplify_gen_binary (PLUS, outer_mode,
740 *inner_step, *outer_step);
741 *outer_step = const0_rtx;
753 if (*inner_mode == outer_mode
754 /* See comment in previous switch. */
755 || GET_MODE (rhs) != outer_mode)
756 *inner_step = simplify_gen_binary (code, outer_mode,
759 *outer_step = simplify_gen_binary (code, outer_mode,
765 gcc_assert (GET_MODE (op0) == *inner_mode
766 && *extend == UNKNOWN
767 && *outer_step == const0_rtx);
779 /* Gets the operation on register REG inside loop, in shape
781 OUTER_STEP + EXTEND_{OUTER_MODE} (SUBREG_{INNER_MODE} (REG + INNER_STEP))
783 If the operation cannot be described in this shape, return false.
784 LAST_DEF is the definition of REG that dominates loop latch. */
787 get_biv_step (df_ref last_def, rtx reg, rtx *inner_step,
788 enum machine_mode *inner_mode, enum rtx_code *extend,
789 enum machine_mode *outer_mode, rtx *outer_step)
791 *outer_mode = GET_MODE (reg);
793 if (!get_biv_step_1 (last_def, reg,
794 inner_step, inner_mode, extend, *outer_mode,
798 gcc_assert ((*inner_mode == *outer_mode) != (*extend != UNKNOWN));
799 gcc_assert (*inner_mode != *outer_mode || *outer_step == const0_rtx);
804 /* Records information that DEF is induction variable IV. */
807 record_iv (df_ref def, struct rtx_iv *iv)
809 struct rtx_iv *recorded_iv = XNEW (struct rtx_iv);
812 check_iv_ref_table_size ();
813 DF_REF_IV_SET (def, recorded_iv);
816 /* If DEF was already analyzed for bivness, store the description of the biv to
817 IV and return true. Otherwise return false. */
820 analyzed_for_bivness_p (rtx def, struct rtx_iv *iv)
822 struct biv_entry *biv =
823 (struct biv_entry *) htab_find_with_hash (bivs, def, REGNO (def));
833 record_biv (rtx def, struct rtx_iv *iv)
835 struct biv_entry *biv = XNEW (struct biv_entry);
836 void **slot = htab_find_slot_with_hash (bivs, def, REGNO (def), INSERT);
838 biv->regno = REGNO (def);
844 /* Determines whether DEF is a biv and if so, stores its description
848 iv_analyze_biv (rtx def, struct rtx_iv *iv)
850 rtx inner_step, outer_step;
851 enum machine_mode inner_mode, outer_mode;
852 enum rtx_code extend;
857 fprintf (dump_file, "Analyzing ");
858 print_rtl (dump_file, def);
859 fprintf (dump_file, " for bivness.\n");
864 if (!CONSTANT_P (def))
867 return iv_constant (iv, def, VOIDmode);
870 if (!latch_dominating_def (def, &last_def))
873 fprintf (dump_file, " not simple.\n");
878 return iv_constant (iv, def, VOIDmode);
880 if (analyzed_for_bivness_p (def, iv))
883 fprintf (dump_file, " already analysed.\n");
884 return iv->base != NULL_RTX;
887 if (!get_biv_step (last_def, def, &inner_step, &inner_mode, &extend,
888 &outer_mode, &outer_step))
894 /* Loop transforms base to es (base + inner_step) + outer_step,
895 where es means extend of subreg between inner_mode and outer_mode.
896 The corresponding induction variable is
898 es ((base - outer_step) + i * (inner_step + outer_step)) + outer_step */
900 iv->base = simplify_gen_binary (MINUS, outer_mode, def, outer_step);
901 iv->step = simplify_gen_binary (PLUS, outer_mode, inner_step, outer_step);
902 iv->mode = inner_mode;
903 iv->extend_mode = outer_mode;
905 iv->mult = const1_rtx;
906 iv->delta = outer_step;
907 iv->first_special = inner_mode != outer_mode;
912 fprintf (dump_file, " ");
913 dump_iv_info (dump_file, iv);
914 fprintf (dump_file, "\n");
917 record_biv (def, iv);
918 return iv->base != NULL_RTX;
921 /* Analyzes expression RHS used at INSN and stores the result to *IV.
922 The mode of the induction variable is MODE. */
925 iv_analyze_expr (rtx insn, rtx rhs, enum machine_mode mode, struct rtx_iv *iv)
927 rtx mby = NULL_RTX, tmp;
928 rtx op0 = NULL_RTX, op1 = NULL_RTX;
929 struct rtx_iv iv0, iv1;
930 enum rtx_code code = GET_CODE (rhs);
931 enum machine_mode omode = mode;
937 gcc_assert (GET_MODE (rhs) == mode || GET_MODE (rhs) == VOIDmode);
943 if (!iv_analyze_op (insn, rhs, iv))
946 if (iv->mode == VOIDmode)
949 iv->extend_mode = mode;
965 omode = GET_MODE (op0);
977 if (!CONSTANT_P (mby))
983 if (!CONSTANT_P (mby))
990 if (!CONSTANT_P (mby))
999 && !iv_analyze_expr (insn, op0, omode, &iv0))
1003 && !iv_analyze_expr (insn, op1, omode, &iv1))
1010 if (!iv_extend (&iv0, code, mode))
1021 if (!iv_add (&iv0, &iv1, code))
1026 if (!iv_mult (&iv0, mby))
1031 if (!iv_shift (&iv0, mby))
1040 return iv->base != NULL_RTX;
1043 /* Analyzes iv DEF and stores the result to *IV. */
1046 iv_analyze_def (df_ref def, struct rtx_iv *iv)
1048 rtx insn = DF_REF_INSN (def);
1049 rtx reg = DF_REF_REG (def);
1054 fprintf (dump_file, "Analyzing def of ");
1055 print_rtl (dump_file, reg);
1056 fprintf (dump_file, " in insn ");
1057 print_rtl_single (dump_file, insn);
1060 check_iv_ref_table_size ();
1061 if (DF_REF_IV (def))
1064 fprintf (dump_file, " already analysed.\n");
1065 *iv = *DF_REF_IV (def);
1066 return iv->base != NULL_RTX;
1069 iv->mode = VOIDmode;
1070 iv->base = NULL_RTX;
1071 iv->step = NULL_RTX;
1076 set = single_set (insn);
1080 if (!REG_P (SET_DEST (set)))
1083 gcc_assert (SET_DEST (set) == reg);
1084 rhs = find_reg_equal_equiv_note (insn);
1086 rhs = XEXP (rhs, 0);
1088 rhs = SET_SRC (set);
1090 iv_analyze_expr (insn, rhs, GET_MODE (reg), iv);
1091 record_iv (def, iv);
1095 print_rtl (dump_file, reg);
1096 fprintf (dump_file, " in insn ");
1097 print_rtl_single (dump_file, insn);
1098 fprintf (dump_file, " is ");
1099 dump_iv_info (dump_file, iv);
1100 fprintf (dump_file, "\n");
1103 return iv->base != NULL_RTX;
1106 /* Analyzes operand OP of INSN and stores the result to *IV. */
1109 iv_analyze_op (rtx insn, rtx op, struct rtx_iv *iv)
1112 enum iv_grd_result res;
1116 fprintf (dump_file, "Analyzing operand ");
1117 print_rtl (dump_file, op);
1118 fprintf (dump_file, " of insn ");
1119 print_rtl_single (dump_file, insn);
1122 if (CONSTANT_P (op))
1123 res = GRD_INVARIANT;
1124 else if (GET_CODE (op) == SUBREG)
1126 if (!subreg_lowpart_p (op))
1129 if (!iv_analyze_op (insn, SUBREG_REG (op), iv))
1132 return iv_subreg (iv, GET_MODE (op));
1136 res = iv_get_reaching_def (insn, op, &def);
1137 if (res == GRD_INVALID)
1140 fprintf (dump_file, " not simple.\n");
1145 if (res == GRD_INVARIANT)
1147 iv_constant (iv, op, VOIDmode);
1151 fprintf (dump_file, " ");
1152 dump_iv_info (dump_file, iv);
1153 fprintf (dump_file, "\n");
1158 if (res == GRD_MAYBE_BIV)
1159 return iv_analyze_biv (op, iv);
1161 return iv_analyze_def (def, iv);
1164 /* Analyzes value VAL at INSN and stores the result to *IV. */
1167 iv_analyze (rtx insn, rtx val, struct rtx_iv *iv)
1171 /* We must find the insn in that val is used, so that we get to UD chains.
1172 Since the function is sometimes called on result of get_condition,
1173 this does not necessarily have to be directly INSN; scan also the
1175 if (simple_reg_p (val))
1177 if (GET_CODE (val) == SUBREG)
1178 reg = SUBREG_REG (val);
1182 while (!df_find_use (insn, reg))
1183 insn = NEXT_INSN (insn);
1186 return iv_analyze_op (insn, val, iv);
1189 /* Analyzes definition of DEF in INSN and stores the result to IV. */
1192 iv_analyze_result (rtx insn, rtx def, struct rtx_iv *iv)
1196 adef = df_find_def (insn, def);
1200 return iv_analyze_def (adef, iv);
1203 /* Checks whether definition of register REG in INSN is a basic induction
1204 variable. IV analysis must have been initialized (via a call to
1205 iv_analysis_loop_init) for this function to produce a result. */
1208 biv_p (rtx insn, rtx reg)
1211 df_ref def, last_def;
1213 if (!simple_reg_p (reg))
1216 def = df_find_def (insn, reg);
1217 gcc_assert (def != NULL);
1218 if (!latch_dominating_def (reg, &last_def))
1220 if (last_def != def)
1223 if (!iv_analyze_biv (reg, &iv))
1226 return iv.step != const0_rtx;
1229 /* Calculates value of IV at ITERATION-th iteration. */
1232 get_iv_value (struct rtx_iv *iv, rtx iteration)
1236 /* We would need to generate some if_then_else patterns, and so far
1237 it is not needed anywhere. */
1238 gcc_assert (!iv->first_special);
1240 if (iv->step != const0_rtx && iteration != const0_rtx)
1241 val = simplify_gen_binary (PLUS, iv->extend_mode, iv->base,
1242 simplify_gen_binary (MULT, iv->extend_mode,
1243 iv->step, iteration));
1247 if (iv->extend_mode == iv->mode)
1250 val = lowpart_subreg (iv->mode, val, iv->extend_mode);
1252 if (iv->extend == UNKNOWN)
1255 val = simplify_gen_unary (iv->extend, iv->extend_mode, val, iv->mode);
1256 val = simplify_gen_binary (PLUS, iv->extend_mode, iv->delta,
1257 simplify_gen_binary (MULT, iv->extend_mode,
1263 /* Free the data for an induction variable analysis. */
1266 iv_analysis_done (void)
1272 df_finish_pass (true);
1274 free (iv_ref_table);
1275 iv_ref_table = NULL;
1276 iv_ref_table_size = 0;
1281 /* Computes inverse to X modulo (1 << MOD). */
1283 static unsigned HOST_WIDEST_INT
1284 inverse (unsigned HOST_WIDEST_INT x, int mod)
1286 unsigned HOST_WIDEST_INT mask =
1287 ((unsigned HOST_WIDEST_INT) 1 << (mod - 1) << 1) - 1;
1288 unsigned HOST_WIDEST_INT rslt = 1;
1291 for (i = 0; i < mod - 1; i++)
1293 rslt = (rslt * x) & mask;
1300 /* Checks whether register *REG is in set ALT. Callback for for_each_rtx. */
1303 altered_reg_used (rtx *reg, void *alt)
1308 return REGNO_REG_SET_P ((bitmap) alt, REGNO (*reg));
1311 /* Marks registers altered by EXPR in set ALT. */
1314 mark_altered (rtx expr, const_rtx by ATTRIBUTE_UNUSED, void *alt)
1316 if (GET_CODE (expr) == SUBREG)
1317 expr = SUBREG_REG (expr);
1321 SET_REGNO_REG_SET ((bitmap) alt, REGNO (expr));
1324 /* Checks whether RHS is simple enough to process. */
1327 simple_rhs_p (rtx rhs)
1331 if (CONSTANT_P (rhs)
1332 || (REG_P (rhs) && !HARD_REGISTER_P (rhs)))
1335 switch (GET_CODE (rhs))
1339 op0 = XEXP (rhs, 0);
1340 op1 = XEXP (rhs, 1);
1341 /* Allow reg + const and reg + reg. */
1342 if (!(REG_P (op0) && !HARD_REGISTER_P (op0))
1343 && !CONSTANT_P (op0))
1345 if (!(REG_P (op1) && !HARD_REGISTER_P (op1))
1346 && !CONSTANT_P (op1))
1352 op0 = XEXP (rhs, 0);
1353 op1 = XEXP (rhs, 1);
1354 /* Allow reg << const. */
1355 if (!(REG_P (op0) && !HARD_REGISTER_P (op0)))
1357 if (!CONSTANT_P (op1))
1367 /* Simplifies *EXPR using assignment in INSN. ALTERED is the set of registers
1371 simplify_using_assignment (rtx insn, rtx *expr, regset altered)
1373 rtx set = single_set (insn);
1374 rtx lhs = NULL_RTX, rhs;
1379 lhs = SET_DEST (set);
1381 || altered_reg_used (&lhs, altered))
1387 note_stores (PATTERN (insn), mark_altered, altered);
1392 /* Kill all call clobbered registers. */
1393 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1394 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
1395 SET_REGNO_REG_SET (altered, i);
1401 rhs = find_reg_equal_equiv_note (insn);
1403 rhs = XEXP (rhs, 0);
1405 rhs = SET_SRC (set);
1407 if (!simple_rhs_p (rhs))
1410 if (for_each_rtx (&rhs, altered_reg_used, altered))
1413 *expr = simplify_replace_rtx (*expr, lhs, rhs);
1416 /* Checks whether A implies B. */
1419 implies_p (rtx a, rtx b)
1421 rtx op0, op1, opb0, opb1, r;
1422 enum machine_mode mode;
1424 if (GET_CODE (a) == EQ)
1431 r = simplify_replace_rtx (b, op0, op1);
1432 if (r == const_true_rtx)
1438 r = simplify_replace_rtx (b, op1, op0);
1439 if (r == const_true_rtx)
1444 if (b == const_true_rtx)
1447 if ((GET_RTX_CLASS (GET_CODE (a)) != RTX_COMM_COMPARE
1448 && GET_RTX_CLASS (GET_CODE (a)) != RTX_COMPARE)
1449 || (GET_RTX_CLASS (GET_CODE (b)) != RTX_COMM_COMPARE
1450 && GET_RTX_CLASS (GET_CODE (b)) != RTX_COMPARE))
1458 mode = GET_MODE (op0);
1459 if (mode != GET_MODE (opb0))
1461 else if (mode == VOIDmode)
1463 mode = GET_MODE (op1);
1464 if (mode != GET_MODE (opb1))
1468 /* A < B implies A + 1 <= B. */
1469 if ((GET_CODE (a) == GT || GET_CODE (a) == LT)
1470 && (GET_CODE (b) == GE || GET_CODE (b) == LE))
1473 if (GET_CODE (a) == GT)
1480 if (GET_CODE (b) == GE)
1487 if (SCALAR_INT_MODE_P (mode)
1488 && rtx_equal_p (op1, opb1)
1489 && simplify_gen_binary (MINUS, mode, opb0, op0) == const1_rtx)
1494 /* A < B or A > B imply A != B. TODO: Likewise
1495 A + n < B implies A != B + n if neither wraps. */
1496 if (GET_CODE (b) == NE
1497 && (GET_CODE (a) == GT || GET_CODE (a) == GTU
1498 || GET_CODE (a) == LT || GET_CODE (a) == LTU))
1500 if (rtx_equal_p (op0, opb0)
1501 && rtx_equal_p (op1, opb1))
1505 /* For unsigned comparisons, A != 0 implies A > 0 and A >= 1. */
1506 if (GET_CODE (a) == NE
1507 && op1 == const0_rtx)
1509 if ((GET_CODE (b) == GTU
1510 && opb1 == const0_rtx)
1511 || (GET_CODE (b) == GEU
1512 && opb1 == const1_rtx))
1513 return rtx_equal_p (op0, opb0);
1516 /* A != N is equivalent to A - (N + 1) <u -1. */
1517 if (GET_CODE (a) == NE
1518 && GET_CODE (op1) == CONST_INT
1519 && GET_CODE (b) == LTU
1520 && opb1 == constm1_rtx
1521 && GET_CODE (opb0) == PLUS
1522 && GET_CODE (XEXP (opb0, 1)) == CONST_INT
1523 /* Avoid overflows. */
1524 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (opb0, 1))
1525 != ((unsigned HOST_WIDE_INT)1
1526 << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
1527 && INTVAL (XEXP (opb0, 1)) + 1 == -INTVAL (op1))
1528 return rtx_equal_p (op0, XEXP (opb0, 0));
1530 /* Likewise, A != N implies A - N > 0. */
1531 if (GET_CODE (a) == NE
1532 && GET_CODE (op1) == CONST_INT)
1534 if (GET_CODE (b) == GTU
1535 && GET_CODE (opb0) == PLUS
1536 && opb1 == const0_rtx
1537 && GET_CODE (XEXP (opb0, 1)) == CONST_INT
1538 /* Avoid overflows. */
1539 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (opb0, 1))
1540 != ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
1541 && rtx_equal_p (XEXP (opb0, 0), op0))
1542 return INTVAL (op1) == -INTVAL (XEXP (opb0, 1));
1543 if (GET_CODE (b) == GEU
1544 && GET_CODE (opb0) == PLUS
1545 && opb1 == const1_rtx
1546 && GET_CODE (XEXP (opb0, 1)) == CONST_INT
1547 /* Avoid overflows. */
1548 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (opb0, 1))
1549 != ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
1550 && rtx_equal_p (XEXP (opb0, 0), op0))
1551 return INTVAL (op1) == -INTVAL (XEXP (opb0, 1));
1554 /* A >s X, where X is positive, implies A <u Y, if Y is negative. */
1555 if ((GET_CODE (a) == GT || GET_CODE (a) == GE)
1556 && GET_CODE (op1) == CONST_INT
1557 && ((GET_CODE (a) == GT && op1 == constm1_rtx)
1558 || INTVAL (op1) >= 0)
1559 && GET_CODE (b) == LTU
1560 && GET_CODE (opb1) == CONST_INT
1561 && rtx_equal_p (op0, opb0))
1562 return INTVAL (opb1) < 0;
1567 /* Canonicalizes COND so that
1569 (1) Ensure that operands are ordered according to
1570 swap_commutative_operands_p.
1571 (2) (LE x const) will be replaced with (LT x <const+1>) and similarly
1572 for GE, GEU, and LEU. */
1575 canon_condition (rtx cond)
1580 enum machine_mode mode;
1582 code = GET_CODE (cond);
1583 op0 = XEXP (cond, 0);
1584 op1 = XEXP (cond, 1);
1586 if (swap_commutative_operands_p (op0, op1))
1588 code = swap_condition (code);
1594 mode = GET_MODE (op0);
1595 if (mode == VOIDmode)
1596 mode = GET_MODE (op1);
1597 gcc_assert (mode != VOIDmode);
1599 if (GET_CODE (op1) == CONST_INT
1600 && GET_MODE_CLASS (mode) != MODE_CC
1601 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1603 HOST_WIDE_INT const_val = INTVAL (op1);
1604 unsigned HOST_WIDE_INT uconst_val = const_val;
1605 unsigned HOST_WIDE_INT max_val
1606 = (unsigned HOST_WIDE_INT) GET_MODE_MASK (mode);
1611 if ((unsigned HOST_WIDE_INT) const_val != max_val >> 1)
1612 code = LT, op1 = gen_int_mode (const_val + 1, GET_MODE (op0));
1615 /* When cross-compiling, const_val might be sign-extended from
1616 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
1618 if ((HOST_WIDE_INT) (const_val & max_val)
1619 != (((HOST_WIDE_INT) 1
1620 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
1621 code = GT, op1 = gen_int_mode (const_val - 1, mode);
1625 if (uconst_val < max_val)
1626 code = LTU, op1 = gen_int_mode (uconst_val + 1, mode);
1630 if (uconst_val != 0)
1631 code = GTU, op1 = gen_int_mode (uconst_val - 1, mode);
1639 if (op0 != XEXP (cond, 0)
1640 || op1 != XEXP (cond, 1)
1641 || code != GET_CODE (cond)
1642 || GET_MODE (cond) != SImode)
1643 cond = gen_rtx_fmt_ee (code, SImode, op0, op1);
1648 /* Tries to use the fact that COND holds to simplify EXPR. ALTERED is the
1649 set of altered regs. */
1652 simplify_using_condition (rtx cond, rtx *expr, regset altered)
1654 rtx rev, reve, exp = *expr;
1656 if (!COMPARISON_P (exp))
1659 /* If some register gets altered later, we do not really speak about its
1660 value at the time of comparison. */
1662 && for_each_rtx (&cond, altered_reg_used, altered))
1665 rev = reversed_condition (cond);
1666 reve = reversed_condition (exp);
1668 cond = canon_condition (cond);
1669 exp = canon_condition (exp);
1671 rev = canon_condition (rev);
1673 reve = canon_condition (reve);
1675 if (rtx_equal_p (exp, cond))
1677 *expr = const_true_rtx;
1682 if (rev && rtx_equal_p (exp, rev))
1688 if (implies_p (cond, exp))
1690 *expr = const_true_rtx;
1694 if (reve && implies_p (cond, reve))
1700 /* A proof by contradiction. If *EXPR implies (not cond), *EXPR must
1702 if (rev && implies_p (exp, rev))
1708 /* Similarly, If (not *EXPR) implies (not cond), *EXPR must be true. */
1709 if (rev && reve && implies_p (reve, rev))
1711 *expr = const_true_rtx;
1715 /* We would like to have some other tests here. TODO. */
1720 /* Use relationship between A and *B to eventually eliminate *B.
1721 OP is the operation we consider. */
1724 eliminate_implied_condition (enum rtx_code op, rtx a, rtx *b)
1729 /* If A implies *B, we may replace *B by true. */
1730 if (implies_p (a, *b))
1731 *b = const_true_rtx;
1735 /* If *B implies A, we may replace *B by false. */
1736 if (implies_p (*b, a))
1745 /* Eliminates the conditions in TAIL that are implied by HEAD. OP is the
1746 operation we consider. */
1749 eliminate_implied_conditions (enum rtx_code op, rtx *head, rtx tail)
1753 for (elt = tail; elt; elt = XEXP (elt, 1))
1754 eliminate_implied_condition (op, *head, &XEXP (elt, 0));
1755 for (elt = tail; elt; elt = XEXP (elt, 1))
1756 eliminate_implied_condition (op, XEXP (elt, 0), head);
1759 /* Simplifies *EXPR using initial values at the start of the LOOP. If *EXPR
1760 is a list, its elements are assumed to be combined using OP. */
1763 simplify_using_initial_values (struct loop *loop, enum rtx_code op, rtx *expr)
1765 rtx head, tail, insn;
1773 if (CONSTANT_P (*expr))
1776 if (GET_CODE (*expr) == EXPR_LIST)
1778 head = XEXP (*expr, 0);
1779 tail = XEXP (*expr, 1);
1781 eliminate_implied_conditions (op, &head, tail);
1786 neutral = const_true_rtx;
1791 neutral = const0_rtx;
1792 aggr = const_true_rtx;
1799 simplify_using_initial_values (loop, UNKNOWN, &head);
1802 XEXP (*expr, 0) = aggr;
1803 XEXP (*expr, 1) = NULL_RTX;
1806 else if (head == neutral)
1809 simplify_using_initial_values (loop, op, expr);
1812 simplify_using_initial_values (loop, op, &tail);
1814 if (tail && XEXP (tail, 0) == aggr)
1820 XEXP (*expr, 0) = head;
1821 XEXP (*expr, 1) = tail;
1825 gcc_assert (op == UNKNOWN);
1827 e = loop_preheader_edge (loop);
1828 if (e->src == ENTRY_BLOCK_PTR)
1831 altered = ALLOC_REG_SET (®_obstack);
1835 insn = BB_END (e->src);
1836 if (any_condjump_p (insn))
1838 rtx cond = get_condition (BB_END (e->src), NULL, false, true);
1840 if (cond && (e->flags & EDGE_FALLTHRU))
1841 cond = reversed_condition (cond);
1844 simplify_using_condition (cond, expr, altered);
1845 if (CONSTANT_P (*expr))
1847 FREE_REG_SET (altered);
1853 FOR_BB_INSNS_REVERSE (e->src, insn)
1858 simplify_using_assignment (insn, expr, altered);
1859 if (CONSTANT_P (*expr))
1861 FREE_REG_SET (altered);
1864 if (for_each_rtx (expr, altered_reg_used, altered))
1866 FREE_REG_SET (altered);
1871 if (!single_pred_p (e->src)
1872 || single_pred (e->src) == ENTRY_BLOCK_PTR)
1874 e = single_pred_edge (e->src);
1877 FREE_REG_SET (altered);
1880 /* Transforms invariant IV into MODE. Adds assumptions based on the fact
1881 that IV occurs as left operands of comparison COND and its signedness
1882 is SIGNED_P to DESC. */
1885 shorten_into_mode (struct rtx_iv *iv, enum machine_mode mode,
1886 enum rtx_code cond, bool signed_p, struct niter_desc *desc)
1888 rtx mmin, mmax, cond_over, cond_under;
1890 get_mode_bounds (mode, signed_p, iv->extend_mode, &mmin, &mmax);
1891 cond_under = simplify_gen_relational (LT, SImode, iv->extend_mode,
1893 cond_over = simplify_gen_relational (GT, SImode, iv->extend_mode,
1902 if (cond_under != const0_rtx)
1904 alloc_EXPR_LIST (0, cond_under, desc->infinite);
1905 if (cond_over != const0_rtx)
1906 desc->noloop_assumptions =
1907 alloc_EXPR_LIST (0, cond_over, desc->noloop_assumptions);
1914 if (cond_over != const0_rtx)
1916 alloc_EXPR_LIST (0, cond_over, desc->infinite);
1917 if (cond_under != const0_rtx)
1918 desc->noloop_assumptions =
1919 alloc_EXPR_LIST (0, cond_under, desc->noloop_assumptions);
1923 if (cond_over != const0_rtx)
1925 alloc_EXPR_LIST (0, cond_over, desc->infinite);
1926 if (cond_under != const0_rtx)
1928 alloc_EXPR_LIST (0, cond_under, desc->infinite);
1936 iv->extend = signed_p ? SIGN_EXTEND : ZERO_EXTEND;
1939 /* Transforms IV0 and IV1 compared by COND so that they are both compared as
1940 subregs of the same mode if possible (sometimes it is necessary to add
1941 some assumptions to DESC). */
1944 canonicalize_iv_subregs (struct rtx_iv *iv0, struct rtx_iv *iv1,
1945 enum rtx_code cond, struct niter_desc *desc)
1947 enum machine_mode comp_mode;
1950 /* If the ivs behave specially in the first iteration, or are
1951 added/multiplied after extending, we ignore them. */
1952 if (iv0->first_special || iv0->mult != const1_rtx || iv0->delta != const0_rtx)
1954 if (iv1->first_special || iv1->mult != const1_rtx || iv1->delta != const0_rtx)
1957 /* If there is some extend, it must match signedness of the comparison. */
1962 if (iv0->extend == ZERO_EXTEND
1963 || iv1->extend == ZERO_EXTEND)
1970 if (iv0->extend == SIGN_EXTEND
1971 || iv1->extend == SIGN_EXTEND)
1977 if (iv0->extend != UNKNOWN
1978 && iv1->extend != UNKNOWN
1979 && iv0->extend != iv1->extend)
1983 if (iv0->extend != UNKNOWN)
1984 signed_p = iv0->extend == SIGN_EXTEND;
1985 if (iv1->extend != UNKNOWN)
1986 signed_p = iv1->extend == SIGN_EXTEND;
1993 /* Values of both variables should be computed in the same mode. These
1994 might indeed be different, if we have comparison like
1996 (compare (subreg:SI (iv0)) (subreg:SI (iv1)))
1998 and iv0 and iv1 are both ivs iterating in SI mode, but calculated
1999 in different modes. This does not seem impossible to handle, but
2000 it hardly ever occurs in practice.
2002 The only exception is the case when one of operands is invariant.
2003 For example pentium 3 generates comparisons like
2004 (lt (subreg:HI (reg:SI)) 100). Here we assign HImode to 100, but we
2005 definitely do not want this prevent the optimization. */
2006 comp_mode = iv0->extend_mode;
2007 if (GET_MODE_BITSIZE (comp_mode) < GET_MODE_BITSIZE (iv1->extend_mode))
2008 comp_mode = iv1->extend_mode;
2010 if (iv0->extend_mode != comp_mode)
2012 if (iv0->mode != iv0->extend_mode
2013 || iv0->step != const0_rtx)
2016 iv0->base = simplify_gen_unary (signed_p ? SIGN_EXTEND : ZERO_EXTEND,
2017 comp_mode, iv0->base, iv0->mode);
2018 iv0->extend_mode = comp_mode;
2021 if (iv1->extend_mode != comp_mode)
2023 if (iv1->mode != iv1->extend_mode
2024 || iv1->step != const0_rtx)
2027 iv1->base = simplify_gen_unary (signed_p ? SIGN_EXTEND : ZERO_EXTEND,
2028 comp_mode, iv1->base, iv1->mode);
2029 iv1->extend_mode = comp_mode;
2032 /* Check that both ivs belong to a range of a single mode. If one of the
2033 operands is an invariant, we may need to shorten it into the common
2035 if (iv0->mode == iv0->extend_mode
2036 && iv0->step == const0_rtx
2037 && iv0->mode != iv1->mode)
2038 shorten_into_mode (iv0, iv1->mode, cond, signed_p, desc);
2040 if (iv1->mode == iv1->extend_mode
2041 && iv1->step == const0_rtx
2042 && iv0->mode != iv1->mode)
2043 shorten_into_mode (iv1, iv0->mode, swap_condition (cond), signed_p, desc);
2045 if (iv0->mode != iv1->mode)
2048 desc->mode = iv0->mode;
2049 desc->signed_p = signed_p;
2054 /* Tries to estimate the maximum number of iterations. */
2056 static unsigned HOST_WIDEST_INT
2057 determine_max_iter (struct loop *loop, struct niter_desc *desc)
2059 rtx niter = desc->niter_expr;
2060 rtx mmin, mmax, cmp;
2061 unsigned HOST_WIDEST_INT nmax, inc;
2063 if (GET_CODE (niter) == AND
2064 && GET_CODE (XEXP (niter, 0)) == CONST_INT)
2066 nmax = INTVAL (XEXP (niter, 0));
2067 if (!(nmax & (nmax + 1)))
2069 desc->niter_max = nmax;
2074 get_mode_bounds (desc->mode, desc->signed_p, desc->mode, &mmin, &mmax);
2075 nmax = INTVAL (mmax) - INTVAL (mmin);
2077 if (GET_CODE (niter) == UDIV)
2079 if (GET_CODE (XEXP (niter, 1)) != CONST_INT)
2081 desc->niter_max = nmax;
2084 inc = INTVAL (XEXP (niter, 1));
2085 niter = XEXP (niter, 0);
2090 /* We could use a binary search here, but for now improving the upper
2091 bound by just one eliminates one important corner case. */
2092 cmp = gen_rtx_fmt_ee (desc->signed_p ? LT : LTU, VOIDmode, niter, mmax);
2093 simplify_using_initial_values (loop, UNKNOWN, &cmp);
2094 if (cmp == const_true_rtx)
2099 fprintf (dump_file, ";; improved upper bound by one.\n");
2101 desc->niter_max = nmax / inc;
2105 /* Computes number of iterations of the CONDITION in INSN in LOOP and stores
2106 the result into DESC. Very similar to determine_number_of_iterations
2107 (basically its rtl version), complicated by things like subregs. */
2110 iv_number_of_iterations (struct loop *loop, rtx insn, rtx condition,
2111 struct niter_desc *desc)
2113 rtx op0, op1, delta, step, bound, may_xform, tmp, tmp0, tmp1;
2114 struct rtx_iv iv0, iv1, tmp_iv;
2115 rtx assumption, may_not_xform;
2117 enum machine_mode mode, comp_mode;
2118 rtx mmin, mmax, mode_mmin, mode_mmax;
2119 unsigned HOST_WIDEST_INT s, size, d, inv;
2120 HOST_WIDEST_INT up, down, inc, step_val;
2121 int was_sharp = false;
2125 /* The meaning of these assumptions is this:
2127 then the rest of information does not have to be valid
2128 if noloop_assumptions then the loop does not roll
2129 if infinite then this exit is never used */
2131 desc->assumptions = NULL_RTX;
2132 desc->noloop_assumptions = NULL_RTX;
2133 desc->infinite = NULL_RTX;
2134 desc->simple_p = true;
2136 desc->const_iter = false;
2137 desc->niter_expr = NULL_RTX;
2138 desc->niter_max = 0;
2140 cond = GET_CODE (condition);
2141 gcc_assert (COMPARISON_P (condition));
2143 mode = GET_MODE (XEXP (condition, 0));
2144 if (mode == VOIDmode)
2145 mode = GET_MODE (XEXP (condition, 1));
2146 /* The constant comparisons should be folded. */
2147 gcc_assert (mode != VOIDmode);
2149 /* We only handle integers or pointers. */
2150 if (GET_MODE_CLASS (mode) != MODE_INT
2151 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
2154 op0 = XEXP (condition, 0);
2155 if (!iv_analyze (insn, op0, &iv0))
2157 if (iv0.extend_mode == VOIDmode)
2158 iv0.mode = iv0.extend_mode = mode;
2160 op1 = XEXP (condition, 1);
2161 if (!iv_analyze (insn, op1, &iv1))
2163 if (iv1.extend_mode == VOIDmode)
2164 iv1.mode = iv1.extend_mode = mode;
2166 if (GET_MODE_BITSIZE (iv0.extend_mode) > HOST_BITS_PER_WIDE_INT
2167 || GET_MODE_BITSIZE (iv1.extend_mode) > HOST_BITS_PER_WIDE_INT)
2170 /* Check condition and normalize it. */
2178 tmp_iv = iv0; iv0 = iv1; iv1 = tmp_iv;
2179 cond = swap_condition (cond);
2191 /* Handle extends. This is relatively nontrivial, so we only try in some
2192 easy cases, when we can canonicalize the ivs (possibly by adding some
2193 assumptions) to shape subreg (base + i * step). This function also fills
2194 in desc->mode and desc->signed_p. */
2196 if (!canonicalize_iv_subregs (&iv0, &iv1, cond, desc))
2199 comp_mode = iv0.extend_mode;
2201 size = GET_MODE_BITSIZE (mode);
2202 get_mode_bounds (mode, (cond == LE || cond == LT), comp_mode, &mmin, &mmax);
2203 mode_mmin = lowpart_subreg (mode, mmin, comp_mode);
2204 mode_mmax = lowpart_subreg (mode, mmax, comp_mode);
2206 if (GET_CODE (iv0.step) != CONST_INT || GET_CODE (iv1.step) != CONST_INT)
2209 /* We can take care of the case of two induction variables chasing each other
2210 if the test is NE. I have never seen a loop using it, but still it is
2212 if (iv0.step != const0_rtx && iv1.step != const0_rtx)
2217 iv0.step = simplify_gen_binary (MINUS, comp_mode, iv0.step, iv1.step);
2218 iv1.step = const0_rtx;
2221 /* This is either infinite loop or the one that ends immediately, depending
2222 on initial values. Unswitching should remove this kind of conditions. */
2223 if (iv0.step == const0_rtx && iv1.step == const0_rtx)
2228 if (iv0.step == const0_rtx)
2229 step_val = -INTVAL (iv1.step);
2231 step_val = INTVAL (iv0.step);
2233 /* Ignore loops of while (i-- < 10) type. */
2237 step_is_pow2 = !(step_val & (step_val - 1));
2241 /* We do not care about whether the step is power of two in this
2243 step_is_pow2 = false;
2247 /* Some more condition normalization. We must record some assumptions
2248 due to overflows. */
2253 /* We want to take care only of non-sharp relationals; this is easy,
2254 as in cases the overflow would make the transformation unsafe
2255 the loop does not roll. Seemingly it would make more sense to want
2256 to take care of sharp relationals instead, as NE is more similar to
2257 them, but the problem is that here the transformation would be more
2258 difficult due to possibly infinite loops. */
2259 if (iv0.step == const0_rtx)
2261 tmp = lowpart_subreg (mode, iv0.base, comp_mode);
2262 assumption = simplify_gen_relational (EQ, SImode, mode, tmp,
2264 if (assumption == const_true_rtx)
2265 goto zero_iter_simplify;
2266 iv0.base = simplify_gen_binary (PLUS, comp_mode,
2267 iv0.base, const1_rtx);
2271 tmp = lowpart_subreg (mode, iv1.base, comp_mode);
2272 assumption = simplify_gen_relational (EQ, SImode, mode, tmp,
2274 if (assumption == const_true_rtx)
2275 goto zero_iter_simplify;
2276 iv1.base = simplify_gen_binary (PLUS, comp_mode,
2277 iv1.base, constm1_rtx);
2280 if (assumption != const0_rtx)
2281 desc->noloop_assumptions =
2282 alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions);
2283 cond = (cond == LT) ? LE : LEU;
2285 /* It will be useful to be able to tell the difference once more in
2286 LE -> NE reduction. */
2292 /* Take care of trivially infinite loops. */
2295 if (iv0.step == const0_rtx)
2297 tmp = lowpart_subreg (mode, iv0.base, comp_mode);
2298 if (rtx_equal_p (tmp, mode_mmin))
2301 alloc_EXPR_LIST (0, const_true_rtx, NULL_RTX);
2302 /* Fill in the remaining fields somehow. */
2303 goto zero_iter_simplify;
2308 tmp = lowpart_subreg (mode, iv1.base, comp_mode);
2309 if (rtx_equal_p (tmp, mode_mmax))
2312 alloc_EXPR_LIST (0, const_true_rtx, NULL_RTX);
2313 /* Fill in the remaining fields somehow. */
2314 goto zero_iter_simplify;
2319 /* If we can we want to take care of NE conditions instead of size
2320 comparisons, as they are much more friendly (most importantly
2321 this takes care of special handling of loops with step 1). We can
2322 do it if we first check that upper bound is greater or equal to
2323 lower bound, their difference is constant c modulo step and that
2324 there is not an overflow. */
2327 if (iv0.step == const0_rtx)
2328 step = simplify_gen_unary (NEG, comp_mode, iv1.step, comp_mode);
2331 delta = simplify_gen_binary (MINUS, comp_mode, iv1.base, iv0.base);
2332 delta = lowpart_subreg (mode, delta, comp_mode);
2333 delta = simplify_gen_binary (UMOD, mode, delta, step);
2334 may_xform = const0_rtx;
2335 may_not_xform = const_true_rtx;
2337 if (GET_CODE (delta) == CONST_INT)
2339 if (was_sharp && INTVAL (delta) == INTVAL (step) - 1)
2341 /* A special case. We have transformed condition of type
2342 for (i = 0; i < 4; i += 4)
2344 for (i = 0; i <= 3; i += 4)
2345 obviously if the test for overflow during that transformation
2346 passed, we cannot overflow here. Most importantly any
2347 loop with sharp end condition and step 1 falls into this
2348 category, so handling this case specially is definitely
2349 worth the troubles. */
2350 may_xform = const_true_rtx;
2352 else if (iv0.step == const0_rtx)
2354 bound = simplify_gen_binary (PLUS, comp_mode, mmin, step);
2355 bound = simplify_gen_binary (MINUS, comp_mode, bound, delta);
2356 bound = lowpart_subreg (mode, bound, comp_mode);
2357 tmp = lowpart_subreg (mode, iv0.base, comp_mode);
2358 may_xform = simplify_gen_relational (cond, SImode, mode,
2360 may_not_xform = simplify_gen_relational (reverse_condition (cond),
2366 bound = simplify_gen_binary (MINUS, comp_mode, mmax, step);
2367 bound = simplify_gen_binary (PLUS, comp_mode, bound, delta);
2368 bound = lowpart_subreg (mode, bound, comp_mode);
2369 tmp = lowpart_subreg (mode, iv1.base, comp_mode);
2370 may_xform = simplify_gen_relational (cond, SImode, mode,
2372 may_not_xform = simplify_gen_relational (reverse_condition (cond),
2378 if (may_xform != const0_rtx)
2380 /* We perform the transformation always provided that it is not
2381 completely senseless. This is OK, as we would need this assumption
2382 to determine the number of iterations anyway. */
2383 if (may_xform != const_true_rtx)
2385 /* If the step is a power of two and the final value we have
2386 computed overflows, the cycle is infinite. Otherwise it
2387 is nontrivial to compute the number of iterations. */
2389 desc->infinite = alloc_EXPR_LIST (0, may_not_xform,
2392 desc->assumptions = alloc_EXPR_LIST (0, may_xform,
2396 /* We are going to lose some information about upper bound on
2397 number of iterations in this step, so record the information
2399 inc = INTVAL (iv0.step) - INTVAL (iv1.step);
2400 if (GET_CODE (iv1.base) == CONST_INT)
2401 up = INTVAL (iv1.base);
2403 up = INTVAL (mode_mmax) - inc;
2404 down = INTVAL (GET_CODE (iv0.base) == CONST_INT
2407 desc->niter_max = (up - down) / inc + 1;
2409 if (iv0.step == const0_rtx)
2411 iv0.base = simplify_gen_binary (PLUS, comp_mode, iv0.base, delta);
2412 iv0.base = simplify_gen_binary (MINUS, comp_mode, iv0.base, step);
2416 iv1.base = simplify_gen_binary (MINUS, comp_mode, iv1.base, delta);
2417 iv1.base = simplify_gen_binary (PLUS, comp_mode, iv1.base, step);
2420 tmp0 = lowpart_subreg (mode, iv0.base, comp_mode);
2421 tmp1 = lowpart_subreg (mode, iv1.base, comp_mode);
2422 assumption = simplify_gen_relational (reverse_condition (cond),
2423 SImode, mode, tmp0, tmp1);
2424 if (assumption == const_true_rtx)
2425 goto zero_iter_simplify;
2426 else if (assumption != const0_rtx)
2427 desc->noloop_assumptions =
2428 alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions);
2433 /* Count the number of iterations. */
2436 /* Everything we do here is just arithmetics modulo size of mode. This
2437 makes us able to do more involved computations of number of iterations
2438 than in other cases. First transform the condition into shape
2439 s * i <> c, with s positive. */
2440 iv1.base = simplify_gen_binary (MINUS, comp_mode, iv1.base, iv0.base);
2441 iv0.base = const0_rtx;
2442 iv0.step = simplify_gen_binary (MINUS, comp_mode, iv0.step, iv1.step);
2443 iv1.step = const0_rtx;
2444 if (INTVAL (iv0.step) < 0)
2446 iv0.step = simplify_gen_unary (NEG, comp_mode, iv0.step, mode);
2447 iv1.base = simplify_gen_unary (NEG, comp_mode, iv1.base, mode);
2449 iv0.step = lowpart_subreg (mode, iv0.step, comp_mode);
2451 /* Let nsd (s, size of mode) = d. If d does not divide c, the loop
2452 is infinite. Otherwise, the number of iterations is
2453 (inverse(s/d) * (c/d)) mod (size of mode/d). */
2454 s = INTVAL (iv0.step); d = 1;
2461 bound = GEN_INT (((unsigned HOST_WIDEST_INT) 1 << (size - 1 ) << 1) - 1);
2463 tmp1 = lowpart_subreg (mode, iv1.base, comp_mode);
2464 tmp = simplify_gen_binary (UMOD, mode, tmp1, GEN_INT (d));
2465 assumption = simplify_gen_relational (NE, SImode, mode, tmp, const0_rtx);
2466 desc->infinite = alloc_EXPR_LIST (0, assumption, desc->infinite);
2468 tmp = simplify_gen_binary (UDIV, mode, tmp1, GEN_INT (d));
2469 inv = inverse (s, size);
2470 tmp = simplify_gen_binary (MULT, mode, tmp, gen_int_mode (inv, mode));
2471 desc->niter_expr = simplify_gen_binary (AND, mode, tmp, bound);
2475 if (iv1.step == const0_rtx)
2476 /* Condition in shape a + s * i <= b
2477 We must know that b + s does not overflow and a <= b + s and then we
2478 can compute number of iterations as (b + s - a) / s. (It might
2479 seem that we in fact could be more clever about testing the b + s
2480 overflow condition using some information about b - a mod s,
2481 but it was already taken into account during LE -> NE transform). */
2484 tmp0 = lowpart_subreg (mode, iv0.base, comp_mode);
2485 tmp1 = lowpart_subreg (mode, iv1.base, comp_mode);
2487 bound = simplify_gen_binary (MINUS, mode, mode_mmax,
2488 lowpart_subreg (mode, step,
2494 /* If s is power of 2, we know that the loop is infinite if
2495 a % s <= b % s and b + s overflows. */
2496 assumption = simplify_gen_relational (reverse_condition (cond),
2500 t0 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp0), step);
2501 t1 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp1), step);
2502 tmp = simplify_gen_relational (cond, SImode, mode, t0, t1);
2503 assumption = simplify_gen_binary (AND, SImode, assumption, tmp);
2505 alloc_EXPR_LIST (0, assumption, desc->infinite);
2509 assumption = simplify_gen_relational (cond, SImode, mode,
2512 alloc_EXPR_LIST (0, assumption, desc->assumptions);
2515 tmp = simplify_gen_binary (PLUS, comp_mode, iv1.base, iv0.step);
2516 tmp = lowpart_subreg (mode, tmp, comp_mode);
2517 assumption = simplify_gen_relational (reverse_condition (cond),
2518 SImode, mode, tmp0, tmp);
2520 delta = simplify_gen_binary (PLUS, mode, tmp1, step);
2521 delta = simplify_gen_binary (MINUS, mode, delta, tmp0);
2525 /* Condition in shape a <= b - s * i
2526 We must know that a - s does not overflow and a - s <= b and then
2527 we can again compute number of iterations as (b - (a - s)) / s. */
2528 step = simplify_gen_unary (NEG, mode, iv1.step, mode);
2529 tmp0 = lowpart_subreg (mode, iv0.base, comp_mode);
2530 tmp1 = lowpart_subreg (mode, iv1.base, comp_mode);
2532 bound = simplify_gen_binary (PLUS, mode, mode_mmin,
2533 lowpart_subreg (mode, step, comp_mode));
2538 /* If s is power of 2, we know that the loop is infinite if
2539 a % s <= b % s and a - s overflows. */
2540 assumption = simplify_gen_relational (reverse_condition (cond),
2544 t0 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp0), step);
2545 t1 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp1), step);
2546 tmp = simplify_gen_relational (cond, SImode, mode, t0, t1);
2547 assumption = simplify_gen_binary (AND, SImode, assumption, tmp);
2549 alloc_EXPR_LIST (0, assumption, desc->infinite);
2553 assumption = simplify_gen_relational (cond, SImode, mode,
2556 alloc_EXPR_LIST (0, assumption, desc->assumptions);
2559 tmp = simplify_gen_binary (PLUS, comp_mode, iv0.base, iv1.step);
2560 tmp = lowpart_subreg (mode, tmp, comp_mode);
2561 assumption = simplify_gen_relational (reverse_condition (cond),
2564 delta = simplify_gen_binary (MINUS, mode, tmp0, step);
2565 delta = simplify_gen_binary (MINUS, mode, tmp1, delta);
2567 if (assumption == const_true_rtx)
2568 goto zero_iter_simplify;
2569 else if (assumption != const0_rtx)
2570 desc->noloop_assumptions =
2571 alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions);
2572 delta = simplify_gen_binary (UDIV, mode, delta, step);
2573 desc->niter_expr = delta;
2576 old_niter = desc->niter_expr;
2578 simplify_using_initial_values (loop, AND, &desc->assumptions);
2579 if (desc->assumptions
2580 && XEXP (desc->assumptions, 0) == const0_rtx)
2582 simplify_using_initial_values (loop, IOR, &desc->noloop_assumptions);
2583 simplify_using_initial_values (loop, IOR, &desc->infinite);
2584 simplify_using_initial_values (loop, UNKNOWN, &desc->niter_expr);
2586 /* Rerun the simplification. Consider code (created by copying loop headers)
2598 The first pass determines that i = 0, the second pass uses it to eliminate
2599 noloop assumption. */
2601 simplify_using_initial_values (loop, AND, &desc->assumptions);
2602 if (desc->assumptions
2603 && XEXP (desc->assumptions, 0) == const0_rtx)
2605 simplify_using_initial_values (loop, IOR, &desc->noloop_assumptions);
2606 simplify_using_initial_values (loop, IOR, &desc->infinite);
2607 simplify_using_initial_values (loop, UNKNOWN, &desc->niter_expr);
2609 if (desc->noloop_assumptions
2610 && XEXP (desc->noloop_assumptions, 0) == const_true_rtx)
2613 if (GET_CODE (desc->niter_expr) == CONST_INT)
2615 unsigned HOST_WIDEST_INT val = INTVAL (desc->niter_expr);
2617 desc->const_iter = true;
2618 desc->niter_max = desc->niter = val & GET_MODE_MASK (desc->mode);
2622 if (!desc->niter_max)
2623 desc->niter_max = determine_max_iter (loop, desc);
2625 /* simplify_using_initial_values does a copy propagation on the registers
2626 in the expression for the number of iterations. This prolongs life
2627 ranges of registers and increases register pressure, and usually
2628 brings no gain (and if it happens to do, the cse pass will take care
2629 of it anyway). So prevent this behavior, unless it enabled us to
2630 derive that the number of iterations is a constant. */
2631 desc->niter_expr = old_niter;
2637 /* Simplify the assumptions. */
2638 simplify_using_initial_values (loop, AND, &desc->assumptions);
2639 if (desc->assumptions
2640 && XEXP (desc->assumptions, 0) == const0_rtx)
2642 simplify_using_initial_values (loop, IOR, &desc->infinite);
2646 desc->const_iter = true;
2648 desc->niter_max = 0;
2649 desc->noloop_assumptions = NULL_RTX;
2650 desc->niter_expr = const0_rtx;
2654 desc->simple_p = false;
2658 /* Checks whether E is a simple exit from LOOP and stores its description
2662 check_simple_exit (struct loop *loop, edge e, struct niter_desc *desc)
2664 basic_block exit_bb;
2669 desc->simple_p = false;
2671 /* It must belong directly to the loop. */
2672 if (exit_bb->loop_father != loop)
2675 /* It must be tested (at least) once during any iteration. */
2676 if (!dominated_by_p (CDI_DOMINATORS, loop->latch, exit_bb))
2679 /* It must end in a simple conditional jump. */
2680 if (!any_condjump_p (BB_END (exit_bb)))
2683 ein = EDGE_SUCC (exit_bb, 0);
2685 ein = EDGE_SUCC (exit_bb, 1);
2688 desc->in_edge = ein;
2690 /* Test whether the condition is suitable. */
2691 if (!(condition = get_condition (BB_END (ein->src), &at, false, false)))
2694 if (ein->flags & EDGE_FALLTHRU)
2696 condition = reversed_condition (condition);
2701 /* Check that we are able to determine number of iterations and fill
2702 in information about it. */
2703 iv_number_of_iterations (loop, at, condition, desc);
2706 /* Finds a simple exit of LOOP and stores its description into DESC. */
2709 find_simple_exit (struct loop *loop, struct niter_desc *desc)
2714 struct niter_desc act;
2718 desc->simple_p = false;
2719 body = get_loop_body (loop);
2721 for (i = 0; i < loop->num_nodes; i++)
2723 FOR_EACH_EDGE (e, ei, body[i]->succs)
2725 if (flow_bb_inside_loop_p (loop, e->dest))
2728 check_simple_exit (loop, e, &act);
2736 /* Prefer constant iterations; the less the better. */
2738 || (desc->const_iter && act.niter >= desc->niter))
2741 /* Also if the actual exit may be infinite, while the old one
2742 not, prefer the old one. */
2743 if (act.infinite && !desc->infinite)
2755 fprintf (dump_file, "Loop %d is simple:\n", loop->num);
2756 fprintf (dump_file, " simple exit %d -> %d\n",
2757 desc->out_edge->src->index,
2758 desc->out_edge->dest->index);
2759 if (desc->assumptions)
2761 fprintf (dump_file, " assumptions: ");
2762 print_rtl (dump_file, desc->assumptions);
2763 fprintf (dump_file, "\n");
2765 if (desc->noloop_assumptions)
2767 fprintf (dump_file, " does not roll if: ");
2768 print_rtl (dump_file, desc->noloop_assumptions);
2769 fprintf (dump_file, "\n");
2773 fprintf (dump_file, " infinite if: ");
2774 print_rtl (dump_file, desc->infinite);
2775 fprintf (dump_file, "\n");
2778 fprintf (dump_file, " number of iterations: ");
2779 print_rtl (dump_file, desc->niter_expr);
2780 fprintf (dump_file, "\n");
2782 fprintf (dump_file, " upper bound: ");
2783 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, desc->niter_max);
2784 fprintf (dump_file, "\n");
2787 fprintf (dump_file, "Loop %d is not simple.\n", loop->num);
2793 /* Creates a simple loop description of LOOP if it was not computed
2797 get_simple_loop_desc (struct loop *loop)
2799 struct niter_desc *desc = simple_loop_desc (loop);
2804 /* At least desc->infinite is not always initialized by
2805 find_simple_loop_exit. */
2806 desc = XCNEW (struct niter_desc);
2807 iv_analysis_loop_init (loop);
2808 find_simple_exit (loop, desc);
2811 if (desc->simple_p && (desc->assumptions || desc->infinite))
2813 const char *wording;
2815 /* Assume that no overflow happens and that the loop is finite.
2816 We already warned at the tree level if we ran optimizations there. */
2817 if (!flag_tree_loop_optimize && warn_unsafe_loop_optimizations)
2822 flag_unsafe_loop_optimizations
2823 ? N_("assuming that the loop is not infinite")
2824 : N_("cannot optimize possibly infinite loops");
2825 warning (OPT_Wunsafe_loop_optimizations, "%s",
2828 if (desc->assumptions)
2831 flag_unsafe_loop_optimizations
2832 ? N_("assuming that the loop counter does not overflow")
2833 : N_("cannot optimize loop, the loop counter may overflow");
2834 warning (OPT_Wunsafe_loop_optimizations, "%s",
2839 if (flag_unsafe_loop_optimizations)
2841 desc->assumptions = NULL_RTX;
2842 desc->infinite = NULL_RTX;
2849 /* Releases simple loop description for LOOP. */
2852 free_simple_loop_desc (struct loop *loop)
2854 struct niter_desc *desc = simple_loop_desc (loop);