1 @c Copyright 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011
2 @c Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
8 @chapter PowerPC Dependent Features
11 @node Machine Dependencies
12 @chapter PowerPC Dependent Features
15 @cindex PowerPC support
17 * PowerPC-Opts:: Options
18 * PowerPC-Pseudo:: PowerPC Assembler Directives
24 @cindex options for PowerPC
25 @cindex PowerPC options
26 @cindex architectures, PowerPC
27 @cindex PowerPC architectures
28 The PowerPC chip family includes several successive levels, using the same
29 core instruction set, but including a few additional instructions at
30 each level. There are exceptions to this however. For details on what
31 instructions each variant supports, please see the chip's architecture
34 The following table lists all available PowerPC options.
38 Generate ELF32 or XCOFF32.
41 Generate ELF64 or XCOFF64.
44 Set EF_PPC_RELOCATABLE_LIB in ELF flags.
47 Generate code for POWER/2 (RIOS2).
50 Generate code for POWER (RIOS1)
53 Generate code for PowerPC 601.
55 @item -mppc, -mppc32, -m603, -m604
56 Generate code for PowerPC 603/604.
59 Generate code for PowerPC 403/405.
62 Generate code for PowerPC 440. BookE and some 405 instructions.
65 Generate code for PowerPC 464.
68 Generate code for PowerPC 476.
70 @item -m7400, -m7410, -m7450, -m7455
71 Generate code for PowerPC 7400/7410/7450/7455.
74 Generate code for PowerPC 750CL.
77 Generate code for PowerPC 620/625/630.
79 @item -me500, -me500x2
80 Generate code for Motorola e500 core complex.
83 Generate code for Freescale e500mc core complex.
86 Generate code for Freescale e500mc64 core complex.
89 Generate code for Motorola SPE instructions.
92 Generate code for AppliedMicro Titan core complex.
95 Generate code for PowerPC 64, including bridge insns.
98 Generate code for 32-bit BookE.
101 Generate code for A2 architecture.
104 Generate code for PowerPC e300 family.
107 Generate code for processors with AltiVec instructions.
110 Generate code for processors with Vector-Scalar (VSX) instructions.
112 @item -mpower4, -mpwr4
113 Generate code for Power4 architecture.
115 @item -mpower5, -mpwr5, -mpwr5x
116 Generate code for Power5 architecture.
118 @item -mpower6, -mpwr6
119 Generate code for Power6 architecture.
121 @item -mpower7, -mpwr7
122 Generate code for Power7 architecture.
125 Generate code for Cell Broadband Engine architecture.
128 Generate code Power/PowerPC common instructions.
131 Generate code for any architecture (PWR/PWRX/PPC).
134 Allow symbolic names for registers.
137 Do not allow symbolic names for registers.
140 Support for GCC's -mrelocatable option.
142 @item -mrelocatable-lib
143 Support for GCC's -mrelocatable-lib option.
146 Set PPC_EMB bit in ELF flags.
148 @item -mlittle, -mlittle-endian, -le
149 Generate code for a little endian machine.
151 @item -mbig, -mbig-endian, -be
152 Generate code for a big endian machine.
155 Generate code for Solaris.
158 Do not generate code for Solaris.
160 @item -nops=@var{count}
161 If an alignment directive inserts more than @var{count} nops, put a
162 branch at the beginning to skip execution of the nops.
167 @section PowerPC Assembler Directives
169 @cindex directives for PowerPC
170 @cindex PowerPC directives
171 A number of assembler directives are available for PowerPC. The
172 following table is far from complete.
175 @item .machine "string"
176 This directive allows you to change the machine for which code is
177 generated. @code{"string"} may be any of the -m cpu selection options
178 (without the -m) enclosed in double quotes, @code{"push"}, or
179 @code{"pop"}. @code{.machine "push"} saves the currently selected
180 cpu, which may be restored with @code{.machine "pop"}.