2 * Copyright (c) 1998 - 2006 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/dev/ata/ata-chipset.c,v 1.196 2007/04/08 19:18:51 sos Exp $
27 * $DragonFly: src/sys/dev/disk/nata/ata-chipset.c,v 1.12 2008/01/01 12:16:40 swildner Exp $
32 #include <sys/param.h>
34 #include <sys/bus_dma.h>
35 #include <sys/bus_resource.h>
36 #include <sys/callout.h>
37 #include <sys/endian.h>
38 #include <sys/libkern.h>
39 #include <sys/lock.h> /* for {get,rel}_mplock() */
40 #include <sys/malloc.h>
42 #include <sys/queue.h>
44 #include <sys/spinlock.h>
45 #include <sys/spinlock2.h>
46 #include <sys/systm.h>
47 #include <sys/taskqueue.h>
49 #include <machine/bus_dma.h>
51 #include <bus/pci/pcireg.h>
52 #include <bus/pci/pcivar.h>
58 /* local prototypes */
60 static int ata_generic_chipinit(device_t dev);
61 static void ata_generic_intr(void *data);
62 static void ata_generic_setmode(device_t dev, int mode);
63 static void ata_sata_phy_check_events(device_t dev);
64 static void ata_sata_phy_event(void *context, int dummy);
65 static int ata_sata_phy_reset(device_t dev);
66 static int ata_sata_connect(struct ata_channel *ch);
67 static void ata_sata_setmode(device_t dev, int mode);
68 static int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis);
69 static int ata_ahci_chipinit(device_t dev);
70 static int ata_ahci_allocate(device_t dev);
71 static int ata_ahci_status(device_t dev);
72 static int ata_ahci_begin_transaction(struct ata_request *request);
73 static int ata_ahci_end_transaction(struct ata_request *request);
74 static void ata_ahci_reset(device_t dev);
75 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
76 static void ata_ahci_dmainit(device_t dev);
77 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request);
78 static int ata_genahci_chipinit(device_t dev);
79 static int ata_acard_chipinit(device_t dev);
80 static int ata_acard_allocate(device_t dev);
81 static int ata_acard_status(device_t dev);
82 static void ata_acard_850_setmode(device_t dev, int mode);
83 static void ata_acard_86X_setmode(device_t dev, int mode);
84 static int ata_ali_chipinit(device_t dev);
85 static int ata_ali_allocate(device_t dev);
86 static int ata_ali_sata_allocate(device_t dev);
87 static void ata_ali_reset(device_t dev);
88 static void ata_ali_setmode(device_t dev, int mode);
89 static int ata_amd_chipinit(device_t dev);
90 static int ata_ati_chipinit(device_t dev);
91 static void ata_ati_setmode(device_t dev, int mode);
92 static int ata_cyrix_chipinit(device_t dev);
93 static void ata_cyrix_setmode(device_t dev, int mode);
94 static int ata_cypress_chipinit(device_t dev);
95 static void ata_cypress_setmode(device_t dev, int mode);
96 static int ata_highpoint_chipinit(device_t dev);
97 static int ata_highpoint_allocate(device_t dev);
98 static void ata_highpoint_setmode(device_t dev, int mode);
99 static int ata_highpoint_check_80pin(device_t dev, int mode);
100 static int ata_intel_chipinit(device_t dev);
101 static int ata_intel_allocate(device_t dev);
102 static void ata_intel_reset(device_t dev);
103 static void ata_intel_old_setmode(device_t dev, int mode);
104 static void ata_intel_new_setmode(device_t dev, int mode);
105 static int ata_intel_31244_allocate(device_t dev);
106 static int ata_intel_31244_status(device_t dev);
107 static int ata_intel_31244_command(struct ata_request *request);
108 static void ata_intel_31244_reset(device_t dev);
109 static int ata_ite_chipinit(device_t dev);
110 static void ata_ite_setmode(device_t dev, int mode);
111 static int ata_jmicron_chipinit(device_t dev);
112 static int ata_jmicron_allocate(device_t dev);
113 static void ata_jmicron_reset(device_t dev);
114 static void ata_jmicron_dmainit(device_t dev);
115 static void ata_jmicron_setmode(device_t dev, int mode);
116 static int ata_marvell_pata_chipinit(device_t dev);
117 static int ata_marvell_pata_allocate(device_t dev);
118 static void ata_marvell_pata_setmode(device_t dev, int mode);
119 static int ata_marvell_edma_chipinit(device_t dev);
120 static int ata_marvell_edma_allocate(device_t dev);
121 static int ata_marvell_edma_status(device_t dev);
122 static int ata_marvell_edma_begin_transaction(struct ata_request *request);
123 static int ata_marvell_edma_end_transaction(struct ata_request *request);
124 static void ata_marvell_edma_reset(device_t dev);
125 static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
126 static void ata_marvell_edma_dmainit(device_t dev);
127 static int ata_national_chipinit(device_t dev);
128 static void ata_national_setmode(device_t dev, int mode);
129 static int ata_netcell_chipinit(device_t dev);
130 static int ata_netcell_allocate(device_t dev);
131 static int ata_nvidia_chipinit(device_t dev);
132 static int ata_nvidia_allocate(device_t dev);
133 static int ata_nvidia_status(device_t dev);
134 static void ata_nvidia_reset(device_t dev);
135 static int ata_promise_chipinit(device_t dev);
136 static int ata_promise_allocate(device_t dev);
137 static int ata_promise_status(device_t dev);
138 static int ata_promise_dmastart(device_t dev);
139 static int ata_promise_dmastop(device_t dev);
140 static void ata_promise_dmareset(device_t dev);
141 static void ata_promise_dmainit(device_t dev);
142 static void ata_promise_setmode(device_t dev, int mode);
143 static int ata_promise_tx2_allocate(device_t dev);
144 static int ata_promise_tx2_status(device_t dev);
145 static int ata_promise_mio_allocate(device_t dev);
146 static void ata_promise_mio_intr(void *data);
147 static int ata_promise_mio_status(device_t dev);
148 static int ata_promise_mio_command(struct ata_request *request);
149 static void ata_promise_mio_reset(device_t dev);
150 static void ata_promise_mio_dmainit(device_t dev);
151 static void ata_promise_mio_setmode(device_t dev, int mode);
152 static void ata_promise_sx4_intr(void *data);
153 static int ata_promise_sx4_command(struct ata_request *request);
154 static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request);
155 static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt);
156 static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr);
157 static int ata_serverworks_chipinit(device_t dev);
158 static int ata_serverworks_allocate(device_t dev);
159 static void ata_serverworks_setmode(device_t dev, int mode);
160 static int ata_sii_chipinit(device_t dev);
161 static int ata_cmd_allocate(device_t dev);
162 static int ata_cmd_status(device_t dev);
163 static void ata_cmd_setmode(device_t dev, int mode);
164 static int ata_sii_allocate(device_t dev);
165 static int ata_sii_status(device_t dev);
166 static void ata_sii_reset(device_t dev);
167 static void ata_sii_setmode(device_t dev, int mode);
168 static int ata_siiprb_allocate(device_t dev);
169 static int ata_siiprb_status(device_t dev);
170 static int ata_siiprb_begin_transaction(struct ata_request *request);
171 static int ata_siiprb_end_transaction(struct ata_request *request);
172 static void ata_siiprb_reset(device_t dev);
173 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
174 static void ata_siiprb_dmainit(device_t dev);
175 static int ata_sis_chipinit(device_t dev);
176 static int ata_sis_allocate(device_t dev);
177 static void ata_sis_reset(device_t dev);
178 static void ata_sis_setmode(device_t dev, int mode);
179 static int ata_via_chipinit(device_t dev);
180 static int ata_via_allocate(device_t dev);
181 static void ata_via_reset(device_t dev);
182 static void ata_via_setmode(device_t dev, int mode);
183 static void ata_via_southbridge_fixup(device_t dev);
184 static void ata_via_family_setmode(device_t dev, int mode);
185 static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index);
186 static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot);
187 static int ata_setup_interrupt(device_t dev);
188 static int ata_serialize(device_t dev, int flags);
189 static void ata_print_cable(device_t dev, u_int8_t *who);
190 static int ata_atapi(device_t dev);
191 static int ata_check_80pin(device_t dev, int mode);
192 static int ata_mode2idx(int mode);
196 * generic ATA support functions
199 ata_generic_ident(device_t dev)
201 struct ata_pci_controller *ctlr = device_get_softc(dev);
203 device_set_desc(dev, "GENERIC ATA controller");
204 ctlr->chipinit = ata_generic_chipinit;
209 ata_generic_chipinit(device_t dev)
211 struct ata_pci_controller *ctlr = device_get_softc(dev);
213 if (ata_setup_interrupt(dev))
215 ctlr->setmode = ata_generic_setmode;
220 ata_generic_intr(void *data)
222 struct ata_pci_controller *ctlr = data;
223 struct ata_channel *ch;
226 for (unit = 0; unit < ctlr->channels; unit++) {
227 if ((ch = ctlr->interrupt[unit].argument))
228 ctlr->interrupt[unit].function(ch);
233 ata_generic_setmode(device_t dev, int mode)
235 struct ata_device *atadev = device_get_softc(dev);
237 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
238 mode = ata_check_80pin(dev, mode);
239 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
245 * SATA support functions
248 ata_sata_phy_check_events(device_t dev)
250 struct ata_channel *ch = device_get_softc(dev);
251 u_int32_t error = ATA_IDX_INL(ch, ATA_SERROR);
253 /* clear error bits/interrupt */
254 ATA_IDX_OUTL(ch, ATA_SERROR, error);
256 /* do we have any events flagged ? */
258 struct ata_connect_task *tp;
259 u_int32_t status = ATA_IDX_INL(ch, ATA_SSTATUS);
261 /* if we have a connection event deal with it */
262 if ((error & ATA_SE_PHY_CHANGED) &&
263 (tp = (struct ata_connect_task *)
264 kmalloc(sizeof(struct ata_connect_task),
265 M_ATA, M_INTWAIT | M_ZERO))) {
267 if (((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1) ||
268 ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)) {
270 device_printf(ch->dev, "CONNECT requested\n");
271 tp->action = ATA_C_ATTACH;
275 device_printf(ch->dev, "DISCONNECT requested\n");
276 tp->action = ATA_C_DETACH;
279 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
280 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task);
286 ata_sata_phy_event(void *context, int dummy)
288 struct ata_connect_task *tp = (struct ata_connect_task *)context;
289 struct ata_channel *ch = device_get_softc(tp->dev);
294 if (tp->action == ATA_C_ATTACH) {
296 device_printf(tp->dev, "CONNECTED\n");
298 ata_identify(tp->dev);
300 if (tp->action == ATA_C_DETACH) {
301 if (!device_get_children(tp->dev, &children, &nchildren)) {
302 for (i = 0; i < nchildren; i++)
304 device_delete_child(tp->dev, children[i]);
305 kfree(children, M_TEMP);
307 spin_lock_wr(&ch->state_mtx);
308 ch->state = ATA_IDLE;
309 spin_unlock_wr(&ch->state_mtx);
311 device_printf(tp->dev, "DISCONNECTED\n");
318 ata_sata_phy_reset(device_t dev)
320 struct ata_channel *ch = device_get_softc(dev);
323 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE)
324 return ata_sata_connect(ch);
326 for (retry = 0; retry < 10; retry++) {
327 for (loop = 0; loop < 10; loop++) {
328 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_RESET);
330 if ((ATA_IDX_INL(ch, ATA_SCONTROL) &
331 ATA_SC_DET_MASK) == ATA_SC_DET_RESET)
335 for (loop = 0; loop < 10; loop++) {
336 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_IDLE |
337 ATA_SC_IPM_DIS_PARTIAL |
338 ATA_SC_IPM_DIS_SLUMBER);
340 if ((ATA_IDX_INL(ch, ATA_SCONTROL) & ATA_SC_DET_MASK) == 0)
341 return ata_sata_connect(ch);
348 ata_sata_connect(struct ata_channel *ch)
353 /* wait up to 1 second for "connect well" */
354 for (timeout = 0; timeout < 100 ; timeout++) {
355 status = ATA_IDX_INL(ch, ATA_SSTATUS);
356 if ((status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN1 ||
357 (status & ATA_SS_CONWELL_MASK) == ATA_SS_CONWELL_GEN2)
361 if (timeout >= 100) {
363 device_printf(ch->dev, "SATA connect status=%08x\n", status);
368 device_printf(ch->dev, "SATA connect time=%dms\n", timeout * 10);
370 /* clear SATA error register */
371 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
377 ata_sata_setmode(device_t dev, int mode)
379 struct ata_device *atadev = device_get_softc(dev);
382 * if we detect that the device isn't a real SATA device we limit
383 * the transfer mode to UDMA5/ATA100.
384 * this works around the problems some devices has with the
385 * Marvell 88SX8030 SATA->PATA converters and UDMA6/ATA133.
387 if (atadev->param.satacapabilities != 0x0000 &&
388 atadev->param.satacapabilities != 0xffff) {
389 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
391 /* on some drives we need to set the transfer mode */
392 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
393 ata_limit_mode(dev, mode, ATA_UDMA6));
395 /* query SATA STATUS for the speed */
396 if (ch->r_io[ATA_SSTATUS].res &&
397 ((ATA_IDX_INL(ch, ATA_SSTATUS) & ATA_SS_CONWELL_MASK) ==
398 ATA_SS_CONWELL_GEN2))
399 atadev->mode = ATA_SA300;
401 atadev->mode = ATA_SA150;
404 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
405 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
411 ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis)
413 struct ata_device *atadev = device_get_softc(request->dev);
415 if (request->flags & ATA_R_ATAPI) {
416 fis[0] = 0x27; /* host to device */
417 fis[1] = 0x80; /* command FIS (note PM goes here) */
418 fis[2] = ATA_PACKET_CMD;
419 if (request->flags & (ATA_R_READ | ATA_R_WRITE))
422 fis[5] = request->transfersize;
423 fis[6] = request->transfersize >> 8;
425 fis[7] = ATA_D_LBA | atadev->unit;
426 fis[15] = ATA_A_4BIT;
430 ata_modify_if_48bit(request);
431 fis[0] = 0x27; /* host to device */
432 fis[1] = 0x80; /* command FIS (note PM goes here) */
433 fis[2] = request->u.ata.command;
434 fis[3] = request->u.ata.feature;
435 fis[4] = request->u.ata.lba;
436 fis[5] = request->u.ata.lba >> 8;
437 fis[6] = request->u.ata.lba >> 16;
438 fis[7] = ATA_D_LBA | atadev->unit;
439 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
440 fis[7] |= (request->u.ata.lba >> 24 & 0x0f);
441 fis[8] = request->u.ata.lba >> 24;
442 fis[9] = request->u.ata.lba >> 32;
443 fis[10] = request->u.ata.lba >> 40;
444 fis[11] = request->u.ata.feature >> 8;
445 fis[12] = request->u.ata.count;
446 fis[13] = request->u.ata.count >> 8;
447 fis[15] = ATA_A_4BIT;
454 * AHCI v1.x compliant SATA chipset support functions
457 ata_ahci_chipinit(device_t dev)
459 struct ata_pci_controller *ctlr = device_get_softc(dev);
463 /* reset AHCI controller */
464 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
465 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_HR);
467 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) {
468 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
469 device_printf(dev, "AHCI controller reset failure\n");
473 /* enable AHCI mode */
474 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
475 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_AE);
477 /* get the number of HW channels */
479 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)),
480 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
482 /* disable interrupt sources and clear interrupts */
483 for (unit = 0; unit < ctlr->channels; unit++) {
484 int offset = unit << 7;
485 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0);
486 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, -1);
488 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));
490 /* enable AHCI interrupts */
491 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
492 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
494 ctlr->reset = ata_ahci_reset;
495 ctlr->dmainit = ata_ahci_dmainit;
496 ctlr->allocate = ata_ahci_allocate;
497 ctlr->setmode = ata_sata_setmode;
499 /* enable PCI interrupt */
500 pci_write_config(dev, PCIR_COMMAND,
501 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
503 /* announce we support the HW */
504 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
506 "AHCI Version %x%x.%x%x controller with %d ports detected\n",
507 (version >> 24) & 0xff, (version >> 16) & 0xff,
508 (version >> 8) & 0xff, version & 0xff,
509 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
514 ata_ahci_allocate(device_t dev)
516 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
517 struct ata_channel *ch = device_get_softc(dev);
519 int offset = ch->unit << 7;
521 /* set the SATA resources */
522 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
523 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
524 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
525 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
526 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
527 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
528 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
529 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
531 ch->hw.status = ata_ahci_status;
532 ch->hw.begin_transaction = ata_ahci_begin_transaction;
533 ch->hw.end_transaction = ata_ahci_end_transaction;
534 ch->hw.command = NULL; /* not used here */
536 /* setup work areas */
537 work = ch->dma->work_bus + ATA_AHCI_CL_OFFSET;
538 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff);
539 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32);
541 work = ch->dma->work_bus + ATA_AHCI_FB_OFFSET;
542 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff);
543 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32);
545 /* enable wanted port interrupts */
546 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
547 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
548 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
549 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP |
550 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS |
551 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
553 /* start operations on this channel */
554 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
555 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
556 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
561 ata_ahci_status(device_t dev)
563 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
564 struct ata_channel *ch = device_get_softc(dev);
565 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
566 int offset = ch->unit << 7;
569 if (action & (1 << ch->unit)) {
570 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
571 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
573 /* clear interrupt(s) */
574 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit));
575 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus);
577 /* do we have any PHY events ? */
578 /* XXX SOS check istatus phy bits */
579 ata_sata_phy_check_events(dev);
581 /* do we have a potentially hanging engine to take care of? */
582 if ((istatus & 0x78400050) && (cstatus & (1 << tag))) {
584 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
587 /* kill off all activity on this channel */
588 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
589 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
591 /* XXX SOS this is not entirely wrong */
594 if (timeout++ > 500) {
595 device_printf(dev, "stopping AHCI engine failed\n");
598 } while (ATA_INL(ctlr->r_res2,
599 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
601 /* start operations on this channel */
602 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
603 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
608 return (!(cstatus & (1 << tag)));
613 /* must be called with ATA channel locked and state_mtx held */
615 ata_ahci_begin_transaction(struct ata_request *request)
617 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
618 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
619 struct ata_ahci_cmd_tab *ctp;
620 struct ata_ahci_cmd_list *clp;
621 int offset = ch->unit << 7;
622 int tag = 0, entries = 0;
625 /* get a piece of the workspace for this request */
626 ctp = (struct ata_ahci_cmd_tab *)
627 (ch->dma->work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE * tag));
629 /* setup the FIS for this request */
630 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) {
631 device_printf(request->dev, "setting up SATA FIS failed\n");
632 request->result = EIO;
633 return ATA_OP_FINISHED;
636 /* if request moves data setup and load SG list */
637 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
638 if (ch->dma->load(ch->dev, request->data, request->bytecount,
639 request->flags & ATA_R_READ,
640 ctp->prd_tab, &entries)) {
641 device_printf(request->dev, "setting up DMA failed\n");
642 request->result = EIO;
643 return ATA_OP_FINISHED;
647 /* setup the command list entry */
648 clp = (struct ata_ahci_cmd_list *)
649 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
651 clp->prd_length = entries;
652 clp->cmd_flags = (request->flags & ATA_R_WRITE ? (1<<6) : 0) |
653 (request->flags & ATA_R_ATAPI ? ((1<<5) | (1<<7)) : 0) |
654 (fis_size / sizeof(u_int32_t));
656 clp->cmd_table_phys = htole64(ch->dma->work_bus + ATA_AHCI_CT_OFFSET +
657 (ATA_AHCI_CT_SIZE * tag));
659 /* clear eventual ACTIVE bit */
660 ATA_IDX_OUTL(ch, ATA_SACTIVE, ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << tag));
662 /* set command type bit */
663 if (request->flags & ATA_R_ATAPI)
664 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
665 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) |
666 ATA_AHCI_P_CMD_ATAPI);
668 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
669 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) &
670 ~ATA_AHCI_P_CMD_ATAPI);
672 /* issue command to controller */
673 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << tag));
675 if (!(request->flags & ATA_R_ATAPI)) {
676 /* device reset doesn't interrupt */
677 if (request->u.ata.command == ATA_DEVICE_RESET) {
679 int timeout = 1000000;
683 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7));
684 } while ((tf_data & ATA_S_BUSY) && timeout--);
686 device_printf(ch->dev, "device_reset timeout=%dus\n",
687 (1000000-timeout)*10);
688 request->status = tf_data;
689 if (request->status & ATA_S_ERROR)
690 request->error = tf_data >> 8;
691 return ATA_OP_FINISHED;
695 /* start the timeout */
696 callout_reset(&request->callout, request->timeout * hz,
697 (timeout_t*)ata_timeout, request);
698 return ATA_OP_CONTINUES;
701 /* must be called with ATA channel locked and state_mtx held */
703 ata_ahci_end_transaction(struct ata_request *request)
705 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
706 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
707 struct ata_ahci_cmd_list *clp;
709 int offset = ch->unit << 7;
712 /* kill the timeout */
713 callout_stop(&request->callout);
716 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset);
717 request->status = tf_data;
719 /* if error status get details */
720 if (request->status & ATA_S_ERROR)
721 request->error = tf_data >> 8;
723 /* record how much data we actually moved */
724 clp = (struct ata_ahci_cmd_list *)
725 (ch->dma->work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE * tag));
726 request->donecount = clp->bytecount;
728 /* release SG list etc */
729 ch->dma->unload(ch->dev);
731 return ATA_OP_FINISHED;
735 ata_ahci_reset(device_t dev)
737 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
738 struct ata_channel *ch = device_get_softc(dev);
739 u_int32_t cmd, signature;
740 int offset = ch->unit << 7;
743 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) {
744 device_printf(dev, "port not implemented\n");
749 /* kill off all activity on this channel */
750 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
751 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
752 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
754 /* XXX SOS this is not entirely wrong */
758 if (timeout++ > 500) {
759 device_printf(dev, "stopping AHCI engine failed\n");
763 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
765 /* issue Command List Override if supported */
766 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) {
767 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
768 cmd |= ATA_AHCI_P_CMD_CLO;
769 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd);
773 if (timeout++ > 500) {
774 device_printf(dev, "executing CLO failed\n");
778 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
781 /* reset PHY and decide what is present */
782 if (ata_sata_phy_reset(dev)) {
784 /* clear any interrupts pending on this channel */
785 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
786 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
788 /* clear SATA error register */
789 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
791 /* start operations on this channel */
792 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
793 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_FRE |
794 ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | ATA_AHCI_P_CMD_ST));
796 signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset);
799 ch->devices = ATA_ATA_MASTER;
802 ch->devices = ATA_PORTMULTIPLIER;
803 device_printf(ch->dev, "Portmultipliers not supported yet\n");
807 ch->devices = ATA_ATAPI_MASTER;
809 default: /* SOS XXX */
811 device_printf(ch->dev, "No signature, assuming disk device\n");
812 ch->devices = ATA_ATA_MASTER;
816 device_printf(dev, "ahci_reset devices=0x%b\n", ch->devices,
817 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
821 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
823 struct ata_dmasetprd_args *args = xsc;
824 struct ata_ahci_dma_prd *prd = args->dmatab;
827 if (!(args->error = error)) {
828 for (i = 0; i < nsegs; i++) {
829 prd[i].dba = htole64(segs[i].ds_addr);
830 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
837 ata_ahci_dmainit(device_t dev)
839 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
840 struct ata_channel *ch = device_get_softc(dev);
844 /* note start and stop are not used here */
845 ch->dma->setprd = ata_ahci_dmasetprd;
846 ch->dma->max_iosize = 8192 * DEV_BSIZE;
847 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
848 ch->dma->max_address = BUS_SPACE_MAXADDR;
853 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request)
855 bzero(ctp->cfis, 64);
856 if (request->flags & ATA_R_ATAPI) {
857 bzero(ctp->acmd, 32);
858 bcopy(request->u.atapi.ccb, ctp->acmd, 16);
860 return ata_request2fis_h2d(request, &ctp->cfis[0]);
864 * Generic AHCI part support functions.
867 ata_genahci_ident(device_t dev)
869 struct ata_pci_controller *ctlr = device_get_softc(dev);
870 static struct ata_chip_id id = {0, 0, 0, 0x00, ATA_SA300, "AHCI"};
873 if(!(pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI)) {
877 ksprintf(buffer, "GENERIC %s %s controller", id.text, ata_mode2str(id.max_dma));
878 device_set_desc_copy(dev, buffer);
880 ctlr->chipinit = ata_genahci_chipinit;
885 ata_genahci_chipinit(device_t dev)
887 struct ata_pci_controller *ctlr = device_get_softc(dev);
889 if (ata_setup_interrupt(dev))
892 /* Check if the chip has PCI BAR 5 as memory resource. */
893 ctlr->r_type2 = SYS_RES_MEMORY;
894 ctlr->r_rid2 = PCIR_BAR(5); /* 0x24 */
895 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
896 &ctlr->r_rid2, RF_ACTIVE))) {
897 return ata_ahci_chipinit(dev);
903 * Acard chipset support functions
906 ata_acard_ident(device_t dev)
908 struct ata_pci_controller *ctlr = device_get_softc(dev);
909 struct ata_chip_id *idx;
910 static struct ata_chip_id ids[] =
911 {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" },
912 { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" },
913 { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "ATP860R" },
914 { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" },
915 { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" },
916 { 0, 0, 0, 0, 0, 0}};
919 if (!(idx = ata_match_chip(dev, ids)))
922 ksprintf(buffer, "Acard %s %s controller",
923 idx->text, ata_mode2str(idx->max_dma));
924 device_set_desc_copy(dev, buffer);
926 ctlr->chipinit = ata_acard_chipinit;
931 ata_acard_chipinit(device_t dev)
933 struct ata_pci_controller *ctlr = device_get_softc(dev);
935 if (ata_setup_interrupt(dev))
938 ctlr->allocate = ata_acard_allocate;
939 if (ctlr->chip->cfg1 == ATPOLD) {
940 ctlr->setmode = ata_acard_850_setmode;
941 ctlr->locking = ata_serialize;
944 ctlr->setmode = ata_acard_86X_setmode;
949 ata_acard_allocate(device_t dev)
951 struct ata_channel *ch = device_get_softc(dev);
953 /* setup the usual register normal pci style */
954 if (ata_pci_allocate(dev))
957 ch->hw.status = ata_acard_status;
962 ata_acard_status(device_t dev)
964 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
965 struct ata_channel *ch = device_get_softc(dev);
967 if (ctlr->chip->cfg1 == ATPOLD &&
968 ATA_LOCKING(ch->dev, ATA_LF_WHICH) != ch->unit)
970 if (ch->dma && (ch->dma->flags & ATA_DMA_ACTIVE)) {
971 int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
973 if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
974 ATA_BMSTAT_INTERRUPT)
976 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
978 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
979 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
982 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
984 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
991 ata_acard_850_setmode(device_t dev, int mode)
993 device_t gparent = GRANDPARENT(dev);
994 struct ata_pci_controller *ctlr = device_get_softc(gparent);
995 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
996 struct ata_device *atadev = device_get_softc(dev);
997 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1000 mode = ata_limit_mode(dev, mode,
1001 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
1003 /* XXX SOS missing WDMA0+1 + PIO modes */
1004 if (mode >= ATA_WDMA2) {
1005 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1007 device_printf(dev, "%ssetting %s on %s chip\n",
1008 (error) ? "FAILURE " : "",
1009 ata_mode2str(mode), ctlr->chip->text);
1011 u_int8_t reg54 = pci_read_config(gparent, 0x54, 1);
1013 reg54 &= ~(0x03 << (devno << 1));
1014 if (mode >= ATA_UDMA0)
1015 reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1));
1016 pci_write_config(gparent, 0x54, reg54, 1);
1017 pci_write_config(gparent, 0x4a, 0xa6, 1);
1018 pci_write_config(gparent, 0x40 + (devno << 1), 0x0301, 2);
1019 atadev->mode = mode;
1023 /* we could set PIO mode timings, but we assume the BIOS did that */
1027 ata_acard_86X_setmode(device_t dev, int mode)
1029 device_t gparent = GRANDPARENT(dev);
1030 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1031 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1032 struct ata_device *atadev = device_get_softc(dev);
1033 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1037 mode = ata_limit_mode(dev, mode,
1038 ata_atapi(dev) ? ATA_PIO_MAX : ctlr->chip->max_dma);
1040 mode = ata_check_80pin(dev, mode);
1042 /* XXX SOS missing WDMA0+1 + PIO modes */
1043 if (mode >= ATA_WDMA2) {
1044 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1046 device_printf(dev, "%ssetting %s on %s chip\n",
1047 (error) ? "FAILURE " : "",
1048 ata_mode2str(mode), ctlr->chip->text);
1050 u_int16_t reg44 = pci_read_config(gparent, 0x44, 2);
1052 reg44 &= ~(0x000f << (devno << 2));
1053 if (mode >= ATA_UDMA0)
1054 reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2));
1055 pci_write_config(gparent, 0x44, reg44, 2);
1056 pci_write_config(gparent, 0x4a, 0xa6, 1);
1057 pci_write_config(gparent, 0x40 + devno, 0x31, 1);
1058 atadev->mode = mode;
1062 /* we could set PIO mode timings, but we assume the BIOS did that */
1067 * Acer Labs Inc (ALI) chipset support functions
1070 ata_ali_ident(device_t dev)
1072 struct ata_pci_controller *ctlr = device_get_softc(dev);
1073 struct ata_chip_id *idx;
1074 static struct ata_chip_id ids[] =
1075 {{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" },
1076 { ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" },
1077 { ATA_ALI_5287, 0x00, 4, ALISATA, ATA_SA150, "M5287" },
1078 { ATA_ALI_5281, 0x00, 2, ALISATA, ATA_SA150, "M5281" },
1079 { ATA_ALI_5229, 0xc5, 0, ALINEW, ATA_UDMA6, "M5229" },
1080 { ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "M5229" },
1081 { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "M5229" },
1082 { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" },
1083 { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" },
1084 { 0, 0, 0, 0, 0, 0}};
1087 if (!(idx = ata_match_chip(dev, ids)))
1090 ksprintf(buffer, "AcerLabs %s %s controller",
1091 idx->text, ata_mode2str(idx->max_dma));
1092 device_set_desc_copy(dev, buffer);
1094 ctlr->chipinit = ata_ali_chipinit;
1099 ata_ali_chipinit(device_t dev)
1101 struct ata_pci_controller *ctlr = device_get_softc(dev);
1103 if (ata_setup_interrupt(dev))
1106 switch (ctlr->chip->cfg2) {
1108 ctlr->channels = ctlr->chip->cfg1;
1109 ctlr->allocate = ata_ali_sata_allocate;
1110 ctlr->setmode = ata_sata_setmode;
1112 /* if we have a memory resource we can likely do AHCI */
1113 ctlr->r_type2 = SYS_RES_MEMORY;
1114 ctlr->r_rid2 = PCIR_BAR(5);
1115 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1116 &ctlr->r_rid2, RF_ACTIVE)))
1117 return ata_ahci_chipinit(dev);
1119 /* enable PCI interrupt */
1120 pci_write_config(dev, PCIR_COMMAND,
1121 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1125 /* use device interrupt as byte count end */
1126 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
1128 /* enable cable detection and UDMA support on newer chips */
1129 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1);
1131 /* enable ATAPI UDMA mode */
1132 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x01, 1);
1134 /* only chips with revision > 0xc4 can do 48bit DMA */
1135 if (ctlr->chip->chiprev <= 0xc4)
1137 "using PIO transfers above 137GB as workaround for "
1138 "48bit DMA access bug, expect reduced performance\n");
1139 ctlr->allocate = ata_ali_allocate;
1140 ctlr->reset = ata_ali_reset;
1141 ctlr->setmode = ata_ali_setmode;
1145 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
1146 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
1147 ctlr->setmode = ata_ali_setmode;
1154 ata_ali_allocate(device_t dev)
1156 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1157 struct ata_channel *ch = device_get_softc(dev);
1159 /* setup the usual register normal pci style */
1160 if (ata_pci_allocate(dev))
1163 /* older chips can't do 48bit DMA transfers */
1164 if (ctlr->chip->chiprev <= 0xc4)
1165 ch->flags |= ATA_NO_48BIT_DMA;
1171 ata_ali_sata_allocate(device_t dev)
1173 device_t parent = device_get_parent(dev);
1174 struct ata_pci_controller *ctlr = device_get_softc(parent);
1175 struct ata_channel *ch = device_get_softc(dev);
1176 struct resource *io = NULL, *ctlio = NULL;
1177 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
1180 rid = PCIR_BAR(0) + (unit01 ? 8 : 0);
1181 io = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1185 rid = PCIR_BAR(1) + (unit01 ? 8 : 0);
1186 ctlio = bus_alloc_resource_any(parent, SYS_RES_IOPORT, &rid, RF_ACTIVE);
1188 bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io);
1192 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
1193 ch->r_io[i].res = io;
1194 ch->r_io[i].offset = i + (unit10 ? 8 : 0);
1196 ch->r_io[ATA_CONTROL].res = ctlio;
1197 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
1198 ch->r_io[ATA_IDX_ADDR].res = io;
1199 ata_default_registers(dev);
1201 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
1202 ch->r_io[i].res = ctlr->r_res1;
1203 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
1206 ch->flags |= ATA_NO_SLAVE;
1208 /* XXX SOS PHY handling awkward in ALI chip not supported yet */
1214 ata_ali_reset(device_t dev)
1216 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
1217 struct ata_channel *ch = device_get_softc(dev);
1221 ata_generic_reset(dev);
1224 * workaround for datacorruption bug found on at least SUN Blade-100
1225 * find the ISA function on the southbridge and disable then enable
1226 * the ATA channel tristate buffer
1228 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
1229 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
1230 for (i = 0; i < nchildren; i++) {
1231 if (pci_get_devid(children[i]) == ATA_ALI_1533) {
1232 pci_write_config(children[i], 0x58,
1233 pci_read_config(children[i], 0x58, 1) &
1234 ~(0x04 << ch->unit), 1);
1235 pci_write_config(children[i], 0x58,
1236 pci_read_config(children[i], 0x58, 1) |
1237 (0x04 << ch->unit), 1);
1241 kfree(children, M_TEMP);
1247 ata_ali_setmode(device_t dev, int mode)
1249 device_t gparent = GRANDPARENT(dev);
1250 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1251 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1252 struct ata_device *atadev = device_get_softc(dev);
1253 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1256 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1258 if (ctlr->chip->cfg2 & ALINEW) {
1259 if (mode > ATA_UDMA2 &&
1260 pci_read_config(gparent, 0x4a, 1) & (1 << ch->unit)) {
1261 ata_print_cable(dev, "controller");
1266 mode = ata_check_80pin(dev, mode);
1268 if (ctlr->chip->cfg2 & ALIOLD) {
1269 /* doesn't support ATAPI DMA on write */
1270 ch->flags |= ATA_ATAPI_DMA_RO;
1271 if (ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
1272 /* doesn't support ATAPI DMA on two ATAPI devices */
1273 device_printf(dev, "two atapi devices on this channel, no DMA\n");
1274 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1278 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1281 device_printf(dev, "%ssetting %s on %s chip\n",
1282 (error) ? "FAILURE " : "",
1283 ata_mode2str(mode), ctlr->chip->text);
1285 if (mode >= ATA_UDMA0) {
1286 u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f, 0x0d};
1287 u_int32_t word54 = pci_read_config(gparent, 0x54, 4);
1289 word54 &= ~(0x000f000f << (devno << 2));
1290 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
1291 pci_write_config(gparent, 0x54, word54, 4);
1292 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1296 u_int32_t piotimings[] =
1297 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
1298 0x00310001, 0x00440001, 0x00330001, 0x00310001};
1300 pci_write_config(gparent, 0x54, pci_read_config(gparent, 0x54, 4) &
1301 ~(0x0008000f << (devno << 2)), 4);
1302 pci_write_config(gparent, 0x58 + (ch->unit << 2),
1303 piotimings[ata_mode2idx(mode)], 4);
1305 atadev->mode = mode;
1311 * American Micro Devices (AMD) chipset support functions
1314 ata_amd_ident(device_t dev)
1316 struct ata_pci_controller *ctlr = device_get_softc(dev);
1317 struct ata_chip_id *idx;
1318 static struct ata_chip_id ids[] =
1319 {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" },
1320 { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" },
1321 { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "768" },
1322 { ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" },
1323 { 0, 0, 0, 0, 0, 0}};
1326 if (!(idx = ata_match_chip(dev, ids)))
1329 ksprintf(buffer, "AMD %s %s controller",
1330 idx->text, ata_mode2str(idx->max_dma));
1331 device_set_desc_copy(dev, buffer);
1333 ctlr->chipinit = ata_amd_chipinit;
1338 ata_amd_chipinit(device_t dev)
1340 struct ata_pci_controller *ctlr = device_get_softc(dev);
1342 if (ata_setup_interrupt(dev))
1345 /* disable/set prefetch, postwrite */
1346 if (ctlr->chip->cfg2 & AMDBUG)
1347 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
1349 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
1351 ctlr->setmode = ata_via_family_setmode;
1357 * ATI chipset support functions
1360 ata_ati_ident(device_t dev)
1362 struct ata_pci_controller *ctlr = device_get_softc(dev);
1363 struct ata_chip_id *idx;
1364 static struct ata_chip_id ids[] =
1365 {{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" },
1366 { ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" },
1367 { ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" },
1368 { ATA_ATI_SB600, 0x00, 0, 0, ATA_UDMA6, "SB600" },
1369 { ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" },
1370 { ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1371 { ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
1372 { ATA_ATI_SB600_S1, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" },
1373 { ATA_ATI_SB600_S2, 0x00, ATIAHCI, 0, ATA_SA300, "SB600" },
1374 { 0, 0, 0, 0, 0, 0}};
1377 if (!(idx = ata_match_chip(dev, ids)))
1380 ksprintf(buffer, "ATI %s %s controller",
1381 idx->text, ata_mode2str(idx->max_dma));
1382 device_set_desc_copy(dev, buffer);
1386 * The ATI SATA controllers are actually a SiI 3112 controller, except
1389 if (ctlr->chip->cfg1 & SIIMEMIO)
1390 ctlr->chipinit = ata_sii_chipinit;
1392 ctlr->chipinit = ata_ati_chipinit;
1397 ata_ati_chipinit(device_t dev)
1399 struct ata_pci_controller *ctlr = device_get_softc(dev);
1401 if (ata_setup_interrupt(dev))
1404 /* The SB600 needs special treatment. */
1405 if (ctlr->chip->cfg1 & ATIAHCI) {
1406 /* Check if the chip is configured as an AHCI part. */
1407 if ((pci_get_subclass(dev) == PCIS_STORAGE_SATA) &&
1408 (pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI)) {
1409 /* Check if the chip has PCI BAR 5 as memory resource. */
1410 ctlr->r_type2 = SYS_RES_MEMORY;
1411 ctlr->r_rid2 = PCIR_BAR(5); /* 0x24 */
1412 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1415 return ata_ahci_chipinit(dev);
1420 ctlr->setmode = ata_ati_setmode;
1425 ata_ati_setmode(device_t dev, int mode)
1427 device_t gparent = GRANDPARENT(dev);
1428 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1429 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1430 struct ata_device *atadev = device_get_softc(dev);
1431 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1432 int offset = (devno ^ 0x01) << 3;
1434 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1435 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1436 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
1438 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1440 mode = ata_check_80pin(dev, mode);
1442 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1445 device_printf(dev, "%ssetting %s on %s chip\n",
1446 (error) ? "FAILURE " : "",
1447 ata_mode2str(mode), ctlr->chip->text);
1449 if (mode >= ATA_UDMA0) {
1450 pci_write_config(gparent, 0x56,
1451 (pci_read_config(gparent, 0x56, 2) &
1452 ~(0xf << (devno << 2))) |
1453 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
1454 pci_write_config(gparent, 0x54,
1455 pci_read_config(gparent, 0x54, 1) |
1456 (0x01 << devno), 1);
1457 pci_write_config(gparent, 0x44,
1458 (pci_read_config(gparent, 0x44, 4) &
1459 ~(0xff << offset)) |
1460 (dmatimings[2] << offset), 4);
1462 else if (mode >= ATA_WDMA0) {
1463 pci_write_config(gparent, 0x54,
1464 pci_read_config(gparent, 0x54, 1) &
1465 ~(0x01 << devno), 1);
1466 pci_write_config(gparent, 0x44,
1467 (pci_read_config(gparent, 0x44, 4) &
1468 ~(0xff << offset)) |
1469 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
1472 pci_write_config(gparent, 0x54,
1473 pci_read_config(gparent, 0x54, 1) &
1474 ~(0x01 << devno), 1);
1476 pci_write_config(gparent, 0x4a,
1477 (pci_read_config(gparent, 0x4a, 2) &
1478 ~(0xf << (devno << 2))) |
1479 (((mode - ATA_PIO0) & ATA_MODE_MASK) << (devno<<2)),2);
1480 pci_write_config(gparent, 0x40,
1481 (pci_read_config(gparent, 0x40, 4) &
1482 ~(0xff << offset)) |
1483 (piotimings[ata_mode2idx(mode)] << offset), 4);
1484 atadev->mode = mode;
1489 * Cyrix chipset support functions
1492 ata_cyrix_ident(device_t dev)
1494 struct ata_pci_controller *ctlr = device_get_softc(dev);
1496 if (pci_get_devid(dev) == ATA_CYRIX_5530) {
1497 device_set_desc(dev, "Cyrix 5530 ATA33 controller");
1498 ctlr->chipinit = ata_cyrix_chipinit;
1505 ata_cyrix_chipinit(device_t dev)
1507 struct ata_pci_controller *ctlr = device_get_softc(dev);
1509 if (ata_setup_interrupt(dev))
1513 ctlr->setmode = ata_cyrix_setmode;
1515 ctlr->setmode = ata_generic_setmode;
1520 ata_cyrix_setmode(device_t dev, int mode)
1522 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1523 struct ata_device *atadev = device_get_softc(dev);
1524 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1525 u_int32_t piotiming[] =
1526 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1527 u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
1528 u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
1531 ch->dma->alignment = 16;
1532 ch->dma->max_iosize = 126 * DEV_BSIZE;
1534 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
1536 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1539 device_printf(dev, "%ssetting %s on Cyrix chip\n",
1540 (error) ? "FAILURE " : "", ata_mode2str(mode));
1542 if (mode >= ATA_UDMA0) {
1543 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1544 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]);
1546 else if (mode >= ATA_WDMA0) {
1547 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1548 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]);
1551 ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res,
1552 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]);
1554 atadev->mode = mode;
1560 * Cypress chipset support functions
1563 ata_cypress_ident(device_t dev)
1565 struct ata_pci_controller *ctlr = device_get_softc(dev);
1568 * the Cypress chip is a mess, it contains two ATA functions, but
1569 * both channels are visible on the first one.
1570 * simply ignore the second function for now, as the right
1571 * solution (ignoring the second channel on the first function)
1572 * doesn't work with the crappy ATA interrupt setup on the alpha.
1574 if (pci_get_devid(dev) == ATA_CYPRESS_82C693 &&
1575 pci_get_function(dev) == 1 &&
1576 pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
1577 device_set_desc(dev, "Cypress 82C693 ATA controller");
1578 ctlr->chipinit = ata_cypress_chipinit;
1585 ata_cypress_chipinit(device_t dev)
1587 struct ata_pci_controller *ctlr = device_get_softc(dev);
1589 if (ata_setup_interrupt(dev))
1592 ctlr->setmode = ata_cypress_setmode;
1597 ata_cypress_setmode(device_t dev, int mode)
1599 device_t gparent = GRANDPARENT(dev);
1600 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1601 struct ata_device *atadev = device_get_softc(dev);
1604 mode = ata_limit_mode(dev, mode, ATA_WDMA2);
1606 /* XXX SOS missing WDMA0+1 + PIO modes */
1607 if (mode == ATA_WDMA2) {
1608 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
1610 device_printf(dev, "%ssetting WDMA2 on Cypress chip\n",
1611 error ? "FAILURE " : "");
1613 pci_write_config(gparent, ch->unit ? 0x4e : 0x4c, 0x2020, 2);
1614 atadev->mode = mode;
1618 /* we could set PIO mode timings, but we assume the BIOS did that */
1623 * HighPoint chipset support functions
1626 ata_highpoint_ident(device_t dev)
1628 struct ata_pci_controller *ctlr = device_get_softc(dev);
1629 struct ata_chip_id *idx;
1630 static struct ata_chip_id ids[] =
1631 {{ ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HPT374" },
1632 { ATA_HPT372, 0x02, HPT372, 0x00, ATA_UDMA6, "HPT372N" },
1633 { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1634 { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT371" },
1635 { ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HPT372" },
1636 { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HPT370" },
1637 { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HPT368" },
1638 { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HPT366" },
1639 { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HPT302" },
1640 { 0, 0, 0, 0, 0, 0}};
1643 if (!(idx = ata_match_chip(dev, ids)))
1646 strcpy(buffer, "HighPoint ");
1647 strcat(buffer, idx->text);
1648 if (idx->cfg1 == HPT374) {
1649 if (pci_get_function(dev) == 0)
1650 strcat(buffer, " (channel 0+1)");
1651 if (pci_get_function(dev) == 1)
1652 strcat(buffer, " (channel 2+3)");
1654 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
1655 device_set_desc_copy(dev, buffer);
1657 ctlr->chipinit = ata_highpoint_chipinit;
1662 ata_highpoint_chipinit(device_t dev)
1664 struct ata_pci_controller *ctlr = device_get_softc(dev);
1666 if (ata_setup_interrupt(dev))
1669 if (ctlr->chip->cfg2 == HPTOLD) {
1670 /* disable interrupt prediction */
1671 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
1674 /* disable interrupt prediction */
1675 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
1676 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
1678 /* enable interrupts */
1679 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
1681 /* set clocks etc */
1682 if (ctlr->chip->cfg1 < HPT372)
1683 pci_write_config(dev, 0x5b, 0x22, 1);
1685 pci_write_config(dev, 0x5b,
1686 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
1688 ctlr->allocate = ata_highpoint_allocate;
1689 ctlr->setmode = ata_highpoint_setmode;
1694 ata_highpoint_allocate(device_t dev)
1696 struct ata_channel *ch = device_get_softc(dev);
1698 /* setup the usual register normal pci style */
1699 if (ata_pci_allocate(dev))
1702 ch->flags |= ATA_ALWAYS_DMASTAT;
1707 ata_highpoint_setmode(device_t dev, int mode)
1709 device_t gparent = GRANDPARENT(dev);
1710 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1711 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1712 struct ata_device *atadev = device_get_softc(dev);
1713 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1715 u_int32_t timings33[][4] = {
1716 /* HPT366 HPT370 HPT372 HPT374 mode */
1717 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
1718 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
1719 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
1720 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
1721 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
1722 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
1723 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
1724 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
1725 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */
1726 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */
1727 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */
1728 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */
1729 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */
1730 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */
1731 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */
1734 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
1736 if (ctlr->chip->cfg1 == HPT366 && ata_atapi(dev))
1737 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
1739 mode = ata_highpoint_check_80pin(dev, mode);
1742 * most if not all HPT chips cant really handle that the device is
1743 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to
1744 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance
1746 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
1747 ata_limit_mode(dev, mode, ATA_UDMA5));
1749 device_printf(dev, "%ssetting %s on HighPoint chip\n",
1750 (error) ? "FAILURE " : "", ata_mode2str(mode));
1752 pci_write_config(gparent, 0x40 + (devno << 2),
1753 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
1754 atadev->mode = mode;
1758 ata_highpoint_check_80pin(device_t dev, int mode)
1760 device_t gparent = GRANDPARENT(dev);
1761 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1762 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1763 u_int8_t reg, val, res;
1765 if (ctlr->chip->cfg1 == HPT374 && pci_get_function(gparent) == 1) {
1766 reg = ch->unit ? 0x57 : 0x53;
1767 val = pci_read_config(gparent, reg, 1);
1768 pci_write_config(gparent, reg, val | 0x80, 1);
1772 val = pci_read_config(gparent, reg, 1);
1773 pci_write_config(gparent, reg, val & 0xfe, 1);
1775 res = pci_read_config(gparent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
1776 pci_write_config(gparent, reg, val, 1);
1778 if (mode > ATA_UDMA2 && res) {
1779 ata_print_cable(dev, "controller");
1787 * Intel chipset support functions
1790 ata_intel_ident(device_t dev)
1792 struct ata_pci_controller *ctlr = device_get_softc(dev);
1793 struct ata_chip_id *idx;
1794 static struct ata_chip_id ids[] =
1795 {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" },
1796 { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" },
1797 { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1798 { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1799 { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "PIIX4" },
1800 { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "ICH0" },
1801 { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1802 { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "ICH" },
1803 { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1804 { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "ICH2" },
1805 { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1806 { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "ICH3" },
1807 { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1808 { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "ICH4" },
1809 { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "ICH5" },
1810 { ATA_I82801EB_S1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1811 { ATA_I82801EB_R1, 0, 0, 0x00, ATA_SA150, "ICH5" },
1812 { ATA_I6300ESB, 0, 0, 0x00, ATA_UDMA5, "6300ESB" },
1813 { ATA_I6300ESB_S1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1814 { ATA_I6300ESB_R1, 0, 0, 0x00, ATA_SA150, "6300ESB" },
1815 { ATA_I82801FB, 0, 0, 0x00, ATA_UDMA5, "ICH6" },
1816 { ATA_I82801FB_S1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1817 { ATA_I82801FB_R1, 0, AHCI, 0x00, ATA_SA150, "ICH6" },
1818 { ATA_I82801FBM, 0, AHCI, 0x00, ATA_SA150, "ICH6M" },
1819 { ATA_I82801GB, 0, 0, 0x00, ATA_UDMA5, "ICH7" },
1820 { ATA_I82801GB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1821 { ATA_I82801GB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1822 { ATA_I82801GB_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7" },
1823 { ATA_I82801GBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1824 { ATA_I82801GBM_R1, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1825 { ATA_I82801GBM_AH, 0, AHCI, 0x00, ATA_SA300, "ICH7M" },
1826 { ATA_I63XXESB2, 0, 0, 0x00, ATA_UDMA5, "63XXESB2" },
1827 { ATA_I63XXESB2_S1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1828 { ATA_I63XXESB2_S2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1829 { ATA_I63XXESB2_R1, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1830 { ATA_I63XXESB2_R2, 0, AHCI, 0x00, ATA_SA300, "63XXESB2" },
1831 { ATA_I82801HB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1832 { ATA_I82801HB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1833 { ATA_I82801HB_R1, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1834 { ATA_I82801HB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1835 { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" },
1836 { ATA_I82801HBM_S1, 0, 0, 0x00, ATA_SA300, "ICH8M" },
1837 { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1838 { ATA_I82801HBM_S3, 0, AHCI, 0x00, ATA_SA300, "ICH8M" },
1839 { ATA_I82801IB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1840 { ATA_I82801IB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1841 { ATA_I82801IB_AH2, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1842 { ATA_I82801IB_AH4, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1843 { ATA_I82801IB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
1844 { ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" },
1845 { 0, 0, 0, 0, 0, 0}};
1848 if (!(idx = ata_match_chip(dev, ids)))
1851 ksprintf(buffer, "Intel %s %s controller",
1852 idx->text, ata_mode2str(idx->max_dma));
1853 device_set_desc_copy(dev, buffer);
1855 ctlr->chipinit = ata_intel_chipinit;
1860 ata_intel_chipinit(device_t dev)
1862 struct ata_pci_controller *ctlr = device_get_softc(dev);
1864 if (ata_setup_interrupt(dev))
1867 /* good old PIIX needs special treatment (not implemented) */
1868 if (ctlr->chip->chipid == ATA_I82371FB) {
1869 ctlr->setmode = ata_intel_old_setmode;
1872 /* the intel 31244 needs special care if in DPA mode */
1873 else if (ctlr->chip->chipid == ATA_I31244) {
1874 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) {
1875 ctlr->r_type2 = SYS_RES_MEMORY;
1876 ctlr->r_rid2 = PCIR_BAR(0);
1877 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1882 ctlr->allocate = ata_intel_31244_allocate;
1883 ctlr->reset = ata_intel_31244_reset;
1885 ctlr->setmode = ata_sata_setmode;
1888 /* non SATA intel chips goes here */
1889 else if (ctlr->chip->max_dma < ATA_SA150) {
1890 ctlr->allocate = ata_intel_allocate;
1891 ctlr->setmode = ata_intel_new_setmode;
1894 /* SATA parts can be either compat or AHCI */
1896 /* force all ports active "the legacy way" */
1897 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f,2);
1899 ctlr->allocate = ata_intel_allocate;
1900 ctlr->reset = ata_intel_reset;
1903 * if we have AHCI capability and BAR(5) as a memory resource
1904 * and AHCI or RAID mode enabled in BIOS we go for AHCI mode
1906 if ((ctlr->chip->cfg1 == AHCI) &&
1907 (pci_read_config(dev, 0x90, 1) & 0xc0)) {
1908 ctlr->r_type2 = SYS_RES_MEMORY;
1909 ctlr->r_rid2 = PCIR_BAR(5);
1910 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
1913 return ata_ahci_chipinit(dev);
1915 ctlr->setmode = ata_sata_setmode;
1917 /* enable PCI interrupt */
1918 pci_write_config(dev, PCIR_COMMAND,
1919 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
1925 ata_intel_allocate(device_t dev)
1927 struct ata_channel *ch = device_get_softc(dev);
1929 /* setup the usual register normal pci style */
1930 if (ata_pci_allocate(dev))
1933 ch->flags |= ATA_ALWAYS_DMASTAT;
1938 ata_intel_reset(device_t dev)
1940 device_t parent = device_get_parent(dev);
1941 struct ata_pci_controller *ctlr = device_get_softc(parent);
1942 struct ata_channel *ch = device_get_softc(dev);
1945 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */
1946 if (ctlr->chip->cfg1) {
1947 mask = (0x0005 << ch->unit);
1950 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
1951 if (pci_read_config(parent, 0x90, 1) & 0x04)
1954 mask = (0x0001 << ch->unit);
1955 /* XXX SOS should be in intel_allocate if we grow it */
1956 ch->flags |= ATA_NO_SLAVE;
1959 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
1961 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
1963 /* wait up to 1 sec for "connect well" */
1964 for (timeout = 0; timeout < 100 ; timeout++) {
1965 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) &&
1966 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
1970 ata_generic_reset(dev);
1974 ata_intel_old_setmode(device_t dev, int mode)
1980 ata_intel_new_setmode(device_t dev, int mode)
1982 device_t gparent = GRANDPARENT(dev);
1983 struct ata_pci_controller *ctlr = device_get_softc(gparent);
1984 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
1985 struct ata_device *atadev = device_get_softc(dev);
1986 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
1987 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4);
1988 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
1989 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
1990 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
1991 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
1992 u_int32_t mask40 = 0, new40 = 0;
1993 u_int8_t mask44 = 0, new44 = 0;
1995 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1996 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
1997 /* PIO0 PIO1 PIO2 PIO3 PIO4 WDMA0 WDMA1 WDMA2 */
1998 /* UDMA0 UDMA1 UDMA2 UDMA3 UDMA4 UDMA5 UDMA6 */
2000 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
2002 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
2003 ata_print_cable(dev, "controller");
2007 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2010 device_printf(dev, "%ssetting %s on %s chip\n",
2011 (error) ? "FAILURE " : "",
2012 ata_mode2str(mode), ctlr->chip->text);
2017 * reg48: 1 bit per (primary drive 0, primary drive 1, secondary
2018 * drive 0, secondary drive 1)
2020 * 0 Disable Ultra DMA mode
2021 * 1 Enable Ultra DMA mode
2023 * reg4a: 4 bits per (primary drive 0, primary drive 1, secondary
2024 * drive 0, secondary drive 1).
2026 * 0001 UDMA mode 1, 3, 5
2027 * 0010 UDMA mode 2, 4, reserved
2029 * (top two bits for each drive reserved)
2033 "regs before 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n",
2034 reg40, reg44, reg48 ,reg4a, reg54);
2036 reg48 &= ~(0x0001 << devno);
2037 reg4a &= ~(0x3 << (devno << 2));
2038 if (mode >= ATA_UDMA0) {
2039 reg48 |= 0x0001 << devno;
2040 if (mode > ATA_UDMA0)
2041 reg4a |= (1 + !(mode & 0x01)) << (devno << 2);
2043 pci_write_config(gparent, 0x48, reg48, 2);
2044 pci_write_config(gparent, 0x4a, reg4a, 2);
2050 * 19:18 Secondary ATA signal mode
2051 * 17:16 Primary ATA signal mode
2052 * 00 = Normal (enabled)
2053 * 01 = Tri-state (disabled)
2054 * 10 = Drive Low (disabled)
2057 * 15 Secondary drive 1 - Base Clock
2058 * 14 Secondary drive 0 - Base Clock
2059 * 13 Primary drive 1 - Base Clock
2060 * 12 Primary drive 0 - Base Clock
2061 * 0 = Select 33 MHz clock
2062 * 1 = Select 100 Mhz clock
2065 * 10 Vendor specific (set by BIOS?)
2068 * 07 Secondary drive 1 - Cable Type
2069 * 06 Secondary drive 0 - Cable Type
2070 * 05 Primary drive 1 - Cable Type
2071 * 04 Primary drive 0 - Cable Type
2073 * 1 = 80 Conductor (or high speed cable)
2075 * 03 Secondary drive 1 - Select 33/66 clock
2076 * 02 Secondary drive 0 - Select 33/66 clock
2077 * 01 Primary drive 1 - Select 33/66 clock
2078 * 00 Primary drive 0 - Select 33/66 clock
2082 * It is unclear what this should be set to when operating
2085 * NOTE: UDMA2 = 33 MHz
2086 * UDMA3 = 40 MHz (?) - unsupported
2091 reg54 |= 0x0400; /* set vendor specific bit */
2092 reg54 &= ~((0x1 << devno) | (0x1000 << devno));
2094 if (mode >= ATA_UDMA5)
2095 reg54 |= (0x1000 << devno);
2096 else if (mode >= ATA_UDMA3) /* XXX should this be ATA_UDMA3 or 4? */
2097 reg54 |= (0x1 << devno);
2099 pci_write_config(gparent, 0x54, reg54, 2);
2102 * Reg40 (32 bits... well, actually two 16 bit registers)
2104 * Primary channel bits 15:00, Secondary channel bits 31:00. Note
2105 * that slave timings are handled in register 44.
2107 * 15 ATA Decode Enable (R/W) 1 = enable decoding of I/O ranges
2109 * 14 Slave ATA Timing Register Enable (R/W)
2111 * 13:12 IORDY Sample Mode
2114 * 10 PIO-3, PIO-4, MW-1, MW-2
2119 * 09:08 Recovery Mode
2120 * 00 PIO-0, PIO-2, SW-2
2125 * 07:04 Secondary Device Control Bits
2126 * 03:00 Primary Device Control Bits
2128 * bit 3 DMA Timing Enable
2130 * bit 2 Indicate Presence of ATA(1) or ATAPI(0) device
2132 * bit 1 Enable IORDY sample point capability for PIO
2133 * xfers. Always enabled for PIO4 and PIO3, enabled
2134 * for PIO2 if indicated by the device, and otherwise
2135 * probably should be 0.
2137 * bit 0 Fast Drive Timing Enable. Enables faster then PIO-0
2142 * Modify reg40 according to the table
2144 if (atadev->unit == ATA_MASTER) {
2146 new40 = timings[ata_mode2idx(mode)] << 8;
2150 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
2151 (timings[ata_mode2idx(mode)] & 0x03);
2155 * Slave ATA timing register enable
2161 * Device control bits 3:0 for master, 7:4 for slave.
2163 * bit3 DMA Timing enable.
2164 * bit2 Indicate presence of ATA(1) or ATAPI(0) device, set accordingly
2165 * bit1 Enable IORDY sample point capability for PIO xfers. Always
2166 * enabled for PIO4 and PIO3, enabled for PIO2 if indicated by
2167 * the device, and otherwise should be 0.
2168 * bit0 Fast Drive Timing Enable. Enable faster then PIO-0 timing modes.
2173 if (atadev->unit == ATA_MASTER) {
2176 if (!ata_atapi(dev))
2181 if (!ata_atapi(dev))
2185 reg40 &= ~0x00ff00ff;
2186 reg40 |= 0x40774077;
2190 * Primary or Secondary controller
2198 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
2199 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
2202 reg40 = pci_read_config(gparent, 0x40, 4);
2203 reg44 = pci_read_config(gparent, 0x44, 1);
2204 reg48 = pci_read_config(gparent, 0x48, 1);
2205 reg4a = pci_read_config(gparent, 0x4a, 2);
2206 reg54 = pci_read_config(gparent, 0x54, 2);
2208 "regs after 40=%08x 44=%02x 48=%02x 4a=%04x 54=%04x\n",
2209 reg40, reg44, reg48 ,reg4a, reg54);
2212 atadev->mode = mode;
2216 ata_intel_31244_allocate(device_t dev)
2218 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2219 struct ata_channel *ch = device_get_softc(dev);
2223 ch_offset = 0x200 + ch->unit * 0x200;
2225 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
2226 ch->r_io[i].res = ctlr->r_res2;
2228 /* setup ATA registers */
2229 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
2230 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06;
2231 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
2232 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
2233 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
2234 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
2235 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
2236 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d;
2237 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04;
2238 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c;
2239 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28;
2240 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29;
2242 /* setup DMA registers */
2243 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100;
2244 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104;
2245 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
2247 /* setup SATA registers */
2248 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
2249 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
2250 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
2252 ch->flags |= ATA_NO_SLAVE;
2254 ch->hw.status = ata_intel_31244_status;
2255 ch->hw.command = ata_intel_31244_command;
2257 /* enable PHY state change interrupt */
2258 ATA_OUTL(ctlr->r_res2, 0x4,
2259 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
2264 ata_intel_31244_status(device_t dev)
2266 /* do we have any PHY events ? */
2267 ata_sata_phy_check_events(dev);
2269 /* any drive action to take care of ? */
2270 return ata_pci_status(dev);
2274 ata_intel_31244_command(struct ata_request *request)
2276 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2277 struct ata_device *atadev = device_get_softc(request->dev);
2280 if (!(atadev->flags & ATA_D_48BIT_ACTIVE))
2281 return (ata_generic_command(request));
2283 lba = request->u.ata.lba;
2284 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit);
2285 /* enable interrupt */
2286 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
2287 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
2288 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
2289 ATA_IDX_OUTW(ch, ATA_SECTOR, ((lba >> 16) & 0xff00) | (lba & 0x00ff));
2290 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((lba >> 24) & 0xff00) |
2291 ((lba >> 8) & 0x00ff));
2292 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((lba >> 32) & 0xff00) |
2293 ((lba >> 16) & 0x00ff));
2295 /* issue command to controller */
2296 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
2302 ata_intel_31244_reset(device_t dev)
2304 if (ata_sata_phy_reset(dev))
2305 ata_generic_reset(dev);
2310 * Integrated Technology Express Inc. (ITE) chipset support functions
2313 ata_ite_ident(device_t dev)
2315 struct ata_pci_controller *ctlr = device_get_softc(dev);
2316 struct ata_chip_id *idx;
2317 static struct ata_chip_id ids[] =
2318 {{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" },
2319 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" },
2320 { 0, 0, 0, 0, 0, 0}};
2323 if (!(idx = ata_match_chip(dev, ids)))
2326 ksprintf(buffer, "ITE %s %s controller",
2327 idx->text, ata_mode2str(idx->max_dma));
2328 device_set_desc_copy(dev, buffer);
2330 ctlr->chipinit = ata_ite_chipinit;
2335 ata_ite_chipinit(device_t dev)
2337 struct ata_pci_controller *ctlr = device_get_softc(dev);
2339 if (ata_setup_interrupt(dev))
2342 ctlr->setmode = ata_ite_setmode;
2344 /* set PCI mode and 66Mhz reference clock */
2345 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
2347 /* set default active & recover timings */
2348 pci_write_config(dev, 0x54, 0x31, 1);
2349 pci_write_config(dev, 0x56, 0x31, 1);
2354 ata_ite_setmode(device_t dev, int mode)
2356 device_t gparent = GRANDPARENT(dev);
2357 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2358 struct ata_device *atadev = device_get_softc(dev);
2359 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
2362 /* correct the mode for what the HW supports */
2363 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2365 /* check the CBLID bits for 80 conductor cable detection */
2366 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) &
2367 (ch->unit ? (1<<3) : (1<<2)))) {
2368 ata_print_cable(dev, "controller");
2372 /* set the wanted mode on the device */
2373 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
2376 device_printf(dev, "%s setting %s on ITE8212F chip\n",
2377 (error) ? "failed" : "success", ata_mode2str(mode));
2379 /* if the device accepted the mode change, setup the HW accordingly */
2381 if (mode >= ATA_UDMA0) {
2382 u_int8_t udmatiming[] =
2383 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
2385 /* enable UDMA mode */
2386 pci_write_config(gparent, 0x50,
2387 pci_read_config(gparent, 0x50, 1) &
2388 ~(1 << (devno + 3)), 1);
2390 /* set UDMA timing */
2391 pci_write_config(gparent,
2392 0x56 + (ch->unit << 2) + ATA_DEV(atadev->unit),
2393 udmatiming[mode & ATA_MODE_MASK], 1);
2396 u_int8_t chtiming[] =
2397 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
2399 /* disable UDMA mode */
2400 pci_write_config(gparent, 0x50,
2401 pci_read_config(gparent, 0x50, 1) |
2402 (1 << (devno + 3)), 1);
2404 /* set active and recover timing (shared between master & slave) */
2405 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) <
2406 chtiming[ata_mode2idx(mode)])
2407 pci_write_config(gparent, 0x54 + (ch->unit << 2),
2408 chtiming[ata_mode2idx(mode)], 1);
2410 atadev->mode = mode;
2416 * JMicron chipset support functions
2419 ata_jmicron_ident(device_t dev)
2421 struct ata_pci_controller *ctlr = device_get_softc(dev);
2422 struct ata_chip_id *idx;
2423 static struct ata_chip_id ids[] =
2424 {{ ATA_JMB360, 0, 1, 0, ATA_SA300, "JMB360" },
2425 { ATA_JMB361, 0, 1, 1, ATA_SA300, "JMB361" },
2426 { ATA_JMB363, 0, 2, 1, ATA_SA300, "JMB363" },
2427 { ATA_JMB365, 0, 1, 2, ATA_SA300, "JMB365" },
2428 { ATA_JMB366, 0, 2, 2, ATA_SA300, "JMB366" },
2429 { ATA_JMB368, 0, 0, 1, ATA_UDMA6, "JMB368" },
2430 { 0, 0, 0, 0, 0, 0}};
2433 if (!(idx = ata_match_chip(dev, ids)))
2436 if ((pci_read_config(dev, 0xdf, 1) & 0x40) &&
2437 (pci_get_function(dev) == (pci_read_config(dev, 0x40, 1) & 0x02 >> 1)))
2438 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller",
2439 idx->text, ata_mode2str(ATA_UDMA6));
2441 ksnprintf(buffer, sizeof(buffer), "JMicron %s %s controller",
2442 idx->text, ata_mode2str(idx->max_dma));
2443 device_set_desc_copy(dev, buffer);
2445 ctlr->chipinit = ata_jmicron_chipinit;
2450 ata_jmicron_chipinit(device_t dev)
2452 struct ata_pci_controller *ctlr = device_get_softc(dev);
2455 if (ata_setup_interrupt(dev))
2458 /* do we have multiple PCI functions ? */
2459 if (pci_read_config(dev, 0xdf, 1) & 0x40) {
2460 /* if we have a memory BAR(5) we are on the AHCI part */
2461 ctlr->r_type2 = SYS_RES_MEMORY;
2462 ctlr->r_rid2 = PCIR_BAR(5);
2463 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
2464 &ctlr->r_rid2, RF_ACTIVE)))
2465 return ata_ahci_chipinit(dev);
2467 /* otherwise we are on the PATA part */
2468 ctlr->allocate = ata_pci_allocate;
2469 ctlr->reset = ata_generic_reset;
2470 ctlr->dmainit = ata_pci_dmainit;
2471 ctlr->setmode = ata_jmicron_setmode;
2472 ctlr->channels = ctlr->chip->cfg2;
2475 /* set controller configuration to a combined setup we support */
2476 pci_write_config(dev, 0x40, 0x80c0a131, 4);
2477 pci_write_config(dev, 0x80, 0x01200000, 4);
2479 ctlr->r_type2 = SYS_RES_MEMORY;
2480 ctlr->r_rid2 = PCIR_BAR(5);
2481 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
2482 &ctlr->r_rid2, RF_ACTIVE))) {
2483 if ((error = ata_ahci_chipinit(dev)))
2487 ctlr->allocate = ata_jmicron_allocate;
2488 ctlr->reset = ata_jmicron_reset;
2489 ctlr->dmainit = ata_jmicron_dmainit;
2490 ctlr->setmode = ata_jmicron_setmode;
2492 /* set the number of HW channels */
2493 ctlr->channels = ctlr->chip->cfg1 + ctlr->chip->cfg2;
2499 ata_jmicron_allocate(device_t dev)
2501 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2502 struct ata_channel *ch = device_get_softc(dev);
2505 if (ch->unit >= ctlr->chip->cfg1) {
2506 ch->unit -= ctlr->chip->cfg1;
2507 error = ata_pci_allocate(dev);
2508 ch->unit += ctlr->chip->cfg1;
2511 error = ata_ahci_allocate(dev);
2516 ata_jmicron_reset(device_t dev)
2518 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2519 struct ata_channel *ch = device_get_softc(dev);
2521 if (ch->unit >= ctlr->chip->cfg1)
2522 ata_generic_reset(dev);
2524 ata_ahci_reset(dev);
2528 ata_jmicron_dmainit(device_t dev)
2530 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2531 struct ata_channel *ch = device_get_softc(dev);
2533 if (ch->unit >= ctlr->chip->cfg1)
2534 ata_pci_dmainit(dev);
2536 ata_ahci_dmainit(dev);
2540 ata_jmicron_setmode(device_t dev, int mode)
2542 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
2543 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
2545 if (pci_read_config(dev, 0xdf, 1) & 0x40 || ch->unit >= ctlr->chip->cfg1) {
2546 struct ata_device *atadev = device_get_softc(dev);
2548 /* check for 80pin cable present */
2549 if (pci_read_config(dev, 0x40, 1) & 0x08)
2550 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
2552 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
2554 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2555 atadev->mode = mode;
2558 ata_sata_setmode(dev, mode);
2563 * Marvell chipset support functions
2565 #define ATA_MV_HOST_BASE(ch) \
2566 ((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000)
2567 #define ATA_MV_EDMA_BASE(ch) \
2568 ((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000)
2570 struct ata_marvell_response {
2572 u_int8_t edma_status;
2573 u_int8_t dev_status;
2574 u_int32_t timestamp;
2577 struct ata_marvell_dma_prdentry {
2585 ata_marvell_ident(device_t dev)
2587 struct ata_pci_controller *ctlr = device_get_softc(dev);
2588 struct ata_chip_id *idx;
2589 static struct ata_chip_id ids[] =
2590 {{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" },
2591 { ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" },
2592 { ATA_M88SX5080, 0, 8, MV50XX, ATA_SA150, "88SX5080" },
2593 { ATA_M88SX5081, 0, 8, MV50XX, ATA_SA150, "88SX5081" },
2594 { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" },
2595 { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" },
2596 { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" },
2597 { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" },
2598 { 0, 0, 0, 0, 0, 0}};
2601 if (!(idx = ata_match_chip(dev, ids)))
2604 ksprintf(buffer, "Marvell %s %s controller",
2605 idx->text, ata_mode2str(idx->max_dma));
2606 device_set_desc_copy(dev, buffer);
2608 switch (ctlr->chip->cfg2) {
2611 ctlr->chipinit = ata_marvell_edma_chipinit;
2614 ctlr->chipinit = ata_marvell_pata_chipinit;
2621 ata_marvell_pata_chipinit(device_t dev)
2623 struct ata_pci_controller *ctlr = device_get_softc(dev);
2625 if (ata_setup_interrupt(dev))
2628 ctlr->allocate = ata_marvell_pata_allocate;
2629 ctlr->setmode = ata_marvell_pata_setmode;
2630 ctlr->channels = ctlr->chip->cfg1;
2635 ata_marvell_pata_allocate(device_t dev)
2637 struct ata_channel *ch = device_get_softc(dev);
2639 /* setup the usual register normal pci style */
2640 if (ata_pci_allocate(dev))
2643 /* dont use 32 bit PIO transfers */
2644 ch->flags |= ATA_USE_16BIT;
2650 ata_marvell_pata_setmode(device_t dev, int mode)
2652 device_t gparent = GRANDPARENT(dev);
2653 struct ata_pci_controller *ctlr = device_get_softc(gparent);
2654 struct ata_device *atadev = device_get_softc(dev);
2656 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
2657 mode = ata_check_80pin(dev, mode);
2658 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
2659 atadev->mode = mode;
2663 ata_marvell_edma_chipinit(device_t dev)
2665 struct ata_pci_controller *ctlr = device_get_softc(dev);
2667 if (ata_setup_interrupt(dev))
2670 ctlr->r_type1 = SYS_RES_MEMORY;
2671 ctlr->r_rid1 = PCIR_BAR(0);
2672 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
2673 &ctlr->r_rid1, RF_ACTIVE)))
2676 /* mask all host controller interrupts */
2677 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);
2679 /* mask all PCI interrupts */
2680 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);
2682 ctlr->allocate = ata_marvell_edma_allocate;
2683 ctlr->reset = ata_marvell_edma_reset;
2684 ctlr->dmainit = ata_marvell_edma_dmainit;
2685 ctlr->setmode = ata_sata_setmode;
2686 ctlr->channels = ctlr->chip->cfg1;
2688 /* clear host controller interrupts */
2689 ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
2690 if (ctlr->chip->cfg1 > 4)
2691 ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);
2693 /* clear PCI interrupts */
2694 ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);
2696 /* unmask PCI interrupts we want */
2697 ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);
2699 /* unmask host controller interrupts we want */
2700 ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
2701 /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));
2703 /* enable PCI interrupt */
2704 pci_write_config(dev, PCIR_COMMAND,
2705 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
2710 ata_marvell_edma_allocate(device_t dev)
2712 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2713 struct ata_channel *ch = device_get_softc(dev);
2714 u_int64_t work = ch->dma->work_bus;
2717 /* clear work area */
2718 bzero(ch->dma->work, 1024+256);
2720 /* set legacy ATA resources */
2721 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
2722 ch->r_io[i].res = ctlr->r_res1;
2723 ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
2725 ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
2726 ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
2727 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
2728 ata_default_registers(dev);
2730 /* set SATA resources */
2731 switch (ctlr->chip->cfg2) {
2733 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2734 ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch);
2735 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2736 ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
2737 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2738 ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
2741 ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
2742 ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch);
2743 ch->r_io[ATA_SERROR].res = ctlr->r_res1;
2744 ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
2745 ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
2746 ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
2747 ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
2748 ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
2752 ch->flags |= ATA_NO_SLAVE;
2753 ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */
2754 ata_generic_hw(dev);
2755 ch->hw.begin_transaction = ata_marvell_edma_begin_transaction;
2756 ch->hw.end_transaction = ata_marvell_edma_end_transaction;
2757 ch->hw.status = ata_marvell_edma_status;
2759 /* disable the EDMA machinery */
2760 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2761 DELAY(100000); /* SOS should poll for disabled */
2763 /* set configuration to non-queued 128b read transfers stop on error */
2764 ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));
2766 /* request queue base high */
2767 ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32);
2769 /* request queue in ptr */
2770 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2772 /* request queue out ptr */
2773 ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);
2775 /* response queue base high */
2777 ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32);
2779 /* response queue in ptr */
2780 ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
2782 /* response queue out ptr */
2783 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
2785 /* clear SATA error register */
2786 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2788 /* clear any outstanding error interrupts */
2789 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2791 /* unmask all error interrupts */
2792 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2794 /* enable EDMA machinery */
2795 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2800 ata_marvell_edma_status(device_t dev)
2802 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2803 struct ata_channel *ch = device_get_softc(dev);
2804 u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
2805 int shift = (ch->unit << 1) + (ch->unit > 3);
2807 if (cause & (1 << shift)) {
2809 /* clear interrupt(s) */
2810 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2812 /* do we have any PHY events ? */
2813 ata_sata_phy_check_events(dev);
2816 /* do we have any device action ? */
2817 return (cause & (2 << shift));
2820 /* must be called with ATA channel locked and state_mtx held */
2822 ata_marvell_edma_begin_transaction(struct ata_request *request)
2824 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2825 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2831 int dummy, error, slot;
2833 /* only DMA R/W goes through the EMDA machine */
2834 if (request->u.ata.command != ATA_READ_DMA &&
2835 request->u.ata.command != ATA_WRITE_DMA) {
2837 /* disable the EDMA machinery */
2838 if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
2839 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2840 return ata_begin_transaction(request);
2843 /* check for 48 bit access and convert if needed */
2844 ata_modify_if_48bit(request);
2846 /* check sanity, setup SG list and DMA engine */
2847 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
2848 request->flags & ATA_R_READ, ch->dma->sg,
2850 device_printf(request->dev, "setting up DMA failed\n");
2851 request->result = error;
2852 return ATA_OP_FINISHED;
2855 /* get next free request queue slot */
2856 req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
2857 slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
2858 bytep = (u_int8_t *)(ch->dma->work);
2859 bytep += (slot << 5);
2860 wordp = (u_int16_t *)bytep;
2861 quadp = (u_int32_t *)bytep;
2863 /* fill in this request */
2864 quadp[0] = (long)ch->dma->sg_bus & 0xffffffff;
2865 quadp[1] = (u_int64_t)ch->dma->sg_bus >> 32;
2866 wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1);
2869 bytep[i++] = (request->u.ata.count >> 8) & 0xff;
2870 bytep[i++] = 0x10 | ATA_COUNT;
2871 bytep[i++] = request->u.ata.count & 0xff;
2872 bytep[i++] = 0x10 | ATA_COUNT;
2874 bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
2875 bytep[i++] = 0x10 | ATA_SECTOR;
2876 bytep[i++] = request->u.ata.lba & 0xff;
2877 bytep[i++] = 0x10 | ATA_SECTOR;
2879 bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
2880 bytep[i++] = 0x10 | ATA_CYL_LSB;
2881 bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
2882 bytep[i++] = 0x10 | ATA_CYL_LSB;
2884 bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
2885 bytep[i++] = 0x10 | ATA_CYL_MSB;
2886 bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
2887 bytep[i++] = 0x10 | ATA_CYL_MSB;
2889 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf);
2890 bytep[i++] = 0x10 | ATA_DRIVE;
2892 bytep[i++] = request->u.ata.command;
2893 bytep[i++] = 0x90 | ATA_COMMAND;
2895 /* enable EDMA machinery if needed */
2896 if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
2897 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2898 while (!(ATA_INL(ctlr->r_res1,
2899 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2903 /* tell EDMA it has a new request */
2904 slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
2905 req_in &= 0xfffffc00;
2906 req_in += (slot << 5);
2907 ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
2909 return ATA_OP_CONTINUES;
2912 /* must be called with ATA channel locked and state_mtx held */
2914 ata_marvell_edma_end_transaction(struct ata_request *request)
2916 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
2917 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
2918 int offset = (ch->unit > 3 ? 0x30014 : 0x20014);
2919 u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
2922 /* EDMA interrupt */
2923 if ((icr & (0x0001 << (ch->unit & 3)))) {
2924 struct ata_marvell_response *response;
2925 u_int32_t rsp_in, rsp_out;
2929 callout_stop(&request->callout);
2931 /* get response ptr's */
2932 rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
2933 rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
2934 slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
2935 rsp_out &= 0xffffff00;
2936 rsp_out += (slot << 3);
2937 response = (struct ata_marvell_response *)
2938 (ch->dma->work + 1024 + (slot << 3));
2940 /* record status for this request */
2941 request->status = response->dev_status;
2945 ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
2947 /* update progress */
2948 if (!(request->status & ATA_S_ERROR) &&
2949 !(request->flags & ATA_R_TIMEOUT))
2950 request->donecount = request->bytecount;
2952 /* unload SG list */
2953 ch->dma->unload(ch->dev);
2955 res = ATA_OP_FINISHED;
2958 /* legacy ATA interrupt */
2960 res = ata_end_transaction(request);
2964 ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3))));
2969 ata_marvell_edma_reset(device_t dev)
2971 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
2972 struct ata_channel *ch = device_get_softc(dev);
2974 /* disable the EDMA machinery */
2975 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
2976 while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
2979 /* clear SATA error register */
2980 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
2982 /* clear any outstanding error interrupts */
2983 ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
2985 /* unmask all error interrupts */
2986 ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
2988 /* enable channel and test for devices */
2989 if (ata_sata_phy_reset(dev))
2990 ata_generic_reset(dev);
2992 /* enable EDMA machinery */
2993 ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
2997 ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
3000 struct ata_dmasetprd_args *args = xsc;
3001 struct ata_marvell_dma_prdentry *prd = args->dmatab;
3004 if ((args->error = error))
3007 for (i = 0; i < nsegs; i++) {
3008 prd[i].addrlo = htole32(segs[i].ds_addr);
3009 prd[i].count = htole32(segs[i].ds_len);
3010 prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32);
3012 prd[i - 1].count |= htole32(ATA_DMA_EOT);
3016 ata_marvell_edma_dmainit(device_t dev)
3018 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3019 struct ata_channel *ch = device_get_softc(dev);
3023 /* note start and stop are not used here */
3024 ch->dma->setprd = ata_marvell_edma_dmasetprd;
3026 if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004)
3027 ch->dma->max_address = BUS_SPACE_MAXADDR;
3033 * National chipset support functions
3036 ata_national_ident(device_t dev)
3038 struct ata_pci_controller *ctlr = device_get_softc(dev);
3040 /* this chip is a clone of the Cyrix chip, bugs and all */
3041 if (pci_get_devid(dev) == ATA_SC1100) {
3042 device_set_desc(dev, "National Geode SC1100 ATA33 controller");
3043 ctlr->chipinit = ata_national_chipinit;
3050 ata_national_chipinit(device_t dev)
3052 struct ata_pci_controller *ctlr = device_get_softc(dev);
3054 if (ata_setup_interrupt(dev))
3057 ctlr->setmode = ata_national_setmode;
3062 ata_national_setmode(device_t dev, int mode)
3064 device_t gparent = GRANDPARENT(dev);
3065 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3066 struct ata_device *atadev = device_get_softc(dev);
3067 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3068 u_int32_t piotiming[] =
3069 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
3070 0x00803020, 0x20102010, 0x00100010,
3071 0x00100010, 0x00100010, 0x00100010 };
3072 u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
3073 u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
3076 ch->dma->alignment = 16;
3077 ch->dma->max_iosize = 126 * DEV_BSIZE;
3079 mode = ata_limit_mode(dev, mode, ATA_UDMA2);
3081 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3084 device_printf(dev, "%s setting %s on National chip\n",
3085 (error) ? "failed" : "success", ata_mode2str(mode));
3087 if (mode >= ATA_UDMA0) {
3088 pci_write_config(gparent, 0x44 + (devno << 3),
3089 udmatiming[mode & ATA_MODE_MASK], 4);
3091 else if (mode >= ATA_WDMA0) {
3092 pci_write_config(gparent, 0x44 + (devno << 3),
3093 dmatiming[mode & ATA_MODE_MASK], 4);
3096 pci_write_config(gparent, 0x44 + (devno << 3),
3097 pci_read_config(gparent, 0x44 + (devno << 3), 4) |
3100 pci_write_config(gparent, 0x40 + (devno << 3),
3101 piotiming[ata_mode2idx(mode)], 4);
3102 atadev->mode = mode;
3107 * NetCell chipset support functions
3110 ata_netcell_ident(device_t dev)
3112 struct ata_pci_controller *ctlr = device_get_softc(dev);
3114 if (pci_get_devid(dev) == ATA_NETCELL_SR) {
3115 device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller");
3116 ctlr->chipinit = ata_netcell_chipinit;
3123 ata_netcell_chipinit(device_t dev)
3125 struct ata_pci_controller *ctlr = device_get_softc(dev);
3127 if (ata_generic_chipinit(dev))
3130 ctlr->allocate = ata_netcell_allocate;
3135 ata_netcell_allocate(device_t dev)
3137 struct ata_channel *ch = device_get_softc(dev);
3139 /* setup the usual register normal pci style */
3140 if (ata_pci_allocate(dev))
3143 /* the NetCell only supports 16 bit PIO transfers */
3144 ch->flags |= ATA_USE_16BIT;
3151 * nVidia chipset support functions
3154 ata_nvidia_ident(device_t dev)
3156 struct ata_pci_controller *ctlr = device_get_softc(dev);
3157 struct ata_chip_id *idx;
3158 static struct ata_chip_id ids[] =
3159 {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" },
3160 { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" },
3161 { ATA_NFORCE2_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2 Pro" },
3162 { ATA_NFORCE2_PRO_S1, 0, 0, 0, ATA_SA150, "nForce2 Pro" },
3163 { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3" },
3164 { ATA_NFORCE3_PRO, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce3 Pro" },
3165 { ATA_NFORCE3_PRO_S1, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
3166 { ATA_NFORCE3_PRO_S2, 0, 0, 0, ATA_SA150, "nForce3 Pro" },
3167 { ATA_NFORCE_MCP04, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP" },
3168 { ATA_NFORCE_MCP04_S1, 0, 0, NV4, ATA_SA150, "nForce MCP" },
3169 { ATA_NFORCE_MCP04_S2, 0, 0, NV4, ATA_SA150, "nForce MCP" },
3170 { ATA_NFORCE_CK804, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce CK804" },
3171 { ATA_NFORCE_CK804_S1, 0, 0, NV4, ATA_SA300, "nForce CK804" },
3172 { ATA_NFORCE_CK804_S2, 0, 0, NV4, ATA_SA300, "nForce CK804" },
3173 { ATA_NFORCE_MCP51, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP51" },
3174 { ATA_NFORCE_MCP51_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3175 { ATA_NFORCE_MCP51_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP51" },
3176 { ATA_NFORCE_MCP55, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP55" },
3177 { ATA_NFORCE_MCP55_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3178 { ATA_NFORCE_MCP55_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP55" },
3179 { 0, 0, 0, 0, 0, 0}} ;
3182 if (!(idx = ata_match_chip(dev, ids)))
3185 ksprintf(buffer, "nVidia %s %s controller",
3186 idx->text, ata_mode2str(idx->max_dma));
3187 device_set_desc_copy(dev, buffer);
3189 ctlr->chipinit = ata_nvidia_chipinit;
3194 ata_nvidia_chipinit(device_t dev)
3196 struct ata_pci_controller *ctlr = device_get_softc(dev);
3198 if (ata_setup_interrupt(dev))
3201 if (ctlr->chip->max_dma >= ATA_SA150) {
3202 if (pci_read_config(dev, PCIR_BAR(5), 1) & 1)
3203 ctlr->r_type2 = SYS_RES_IOPORT;
3205 ctlr->r_type2 = SYS_RES_MEMORY;
3206 ctlr->r_rid2 = PCIR_BAR(5);
3207 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3208 &ctlr->r_rid2, RF_ACTIVE))) {
3209 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3211 ctlr->allocate = ata_nvidia_allocate;
3212 ctlr->reset = ata_nvidia_reset;
3214 /* enable control access */
3215 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
3217 if (ctlr->chip->cfg2 & NVQ) {
3218 /* clear interrupt status */
3219 ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff);
3221 /* enable device and PHY state change interrupts */
3222 ATA_OUTL(ctlr->r_res2, offset + 4, 0x000d000d);
3224 /* disable NCQ support */
3225 ATA_OUTL(ctlr->r_res2, 0x0400,
3226 ATA_INL(ctlr->r_res2, 0x0400) & 0xfffffff9);
3229 /* clear interrupt status */
3230 ATA_OUTB(ctlr->r_res2, offset, 0xff);
3232 /* enable device and PHY state change interrupts */
3233 ATA_OUTB(ctlr->r_res2, offset + 1, 0xdd);
3236 /* enable PCI interrupt */
3237 pci_write_config(dev, PCIR_COMMAND,
3238 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
3241 ctlr->setmode = ata_sata_setmode;
3244 /* disable prefetch, postwrite */
3245 pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1);
3246 ctlr->setmode = ata_via_family_setmode;
3252 ata_nvidia_allocate(device_t dev)
3254 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3255 struct ata_channel *ch = device_get_softc(dev);
3257 /* setup the usual register normal pci style */
3258 if (ata_pci_allocate(dev))
3261 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3262 ch->r_io[ATA_SSTATUS].offset = (ch->unit << 6);
3263 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3264 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << 6);
3265 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3266 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << 6);
3268 ch->hw.status = ata_nvidia_status;
3269 ch->flags |= ATA_NO_SLAVE;
3275 ata_nvidia_status(device_t dev)
3277 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3278 struct ata_channel *ch = device_get_softc(dev);
3279 int offset = ctlr->chip->cfg2 & NV4 ? 0x0440 : 0x0010;
3280 int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2);
3281 u_int32_t istatus = ATA_INL(ctlr->r_res2, offset);
3283 /* do we have any PHY events ? */
3284 if (istatus & (0x0c << shift))
3285 ata_sata_phy_check_events(dev);
3287 /* clear interrupt(s) */
3288 ATA_OUTB(ctlr->r_res2, offset,
3289 (0x0f << shift) | (ctlr->chip->cfg2 & NVQ ? 0x00f000f0 : 0));
3291 /* do we have any device action ? */
3292 return (istatus & (0x01 << shift));
3296 ata_nvidia_reset(device_t dev)
3298 if (ata_sata_phy_reset(dev))
3299 ata_generic_reset(dev);
3304 * Promise chipset support functions
3306 #define ATA_PDC_APKT_OFFSET 0x00000010
3307 #define ATA_PDC_HPKT_OFFSET 0x00000040
3308 #define ATA_PDC_ASG_OFFSET 0x00000080
3309 #define ATA_PDC_LSG_OFFSET 0x000000c0
3310 #define ATA_PDC_HSG_OFFSET 0x00000100
3311 #define ATA_PDC_CHN_OFFSET 0x00000400
3312 #define ATA_PDC_BUF_BASE 0x00400000
3313 #define ATA_PDC_BUF_OFFSET 0x00100000
3314 #define ATA_PDC_MAX_HPKT 8
3315 #define ATA_PDC_WRITE_REG 0x00
3316 #define ATA_PDC_WRITE_CTL 0x0e
3317 #define ATA_PDC_WRITE_END 0x08
3318 #define ATA_PDC_WAIT_NBUSY 0x10
3319 #define ATA_PDC_WAIT_READY 0x18
3320 #define ATA_PDC_1B 0x20
3321 #define ATA_PDC_2B 0x40
3323 struct host_packet {
3325 TAILQ_ENTRY(host_packet) chain;
3328 struct ata_promise_sx4 {
3329 struct spinlock mtx;
3330 TAILQ_HEAD(, host_packet) queue;
3335 ata_promise_ident(device_t dev)
3337 struct ata_pci_controller *ctlr = device_get_softc(dev);
3338 struct ata_chip_id *idx;
3339 static struct ata_chip_id ids[] =
3340 {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "PDC20246" },
3341 { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20262" },
3342 { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "PDC20263" },
3343 { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20265" },
3344 { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "PDC20267" },
3345 { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20268" },
3346 { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "PDC20269" },
3347 { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "PDC20270" },
3348 { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "PDC20271" },
3349 { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "PDC20275" },
3350 { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "PDC20276" },
3351 { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "PDC20277" },
3352 { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "PDC20318" },
3353 { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "PDC20319" },
3354 { ATA_PDC20371, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20371" },
3355 { ATA_PDC20375, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20375" },
3356 { ATA_PDC20376, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20376" },
3357 { ATA_PDC20377, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20377" },
3358 { ATA_PDC20378, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20378" },
3359 { ATA_PDC20379, 0, PRMIO, PRCMBO, ATA_SA150, "PDC20379" },
3360 { ATA_PDC20571, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20571" },
3361 { ATA_PDC20575, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20575" },
3362 { ATA_PDC20579, 0, PRMIO, PRCMBO2, ATA_SA150, "PDC20579" },
3363 { ATA_PDC20771, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC20771" },
3364 { ATA_PDC40775, 0, PRMIO, PRCMBO2, ATA_SA300, "PDC40775" },
3365 { ATA_PDC20617, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20617" },
3366 { ATA_PDC20618, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20618" },
3367 { ATA_PDC20619, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20619" },
3368 { ATA_PDC20620, 0, PRMIO, PRPATA, ATA_UDMA6, "PDC20620" },
3369 { ATA_PDC20621, 0, PRMIO, PRSX4X, ATA_UDMA5, "PDC20621" },
3370 { ATA_PDC20622, 0, PRMIO, PRSX4X, ATA_SA150, "PDC20622" },
3371 { ATA_PDC40518, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40518" },
3372 { ATA_PDC40519, 0, PRMIO, PRSATA2, ATA_SA150, "PDC40519" },
3373 { ATA_PDC40718, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40718" },
3374 { ATA_PDC40719, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40719" },
3375 { ATA_PDC40779, 0, PRMIO, PRSATA2, ATA_SA300, "PDC40779" },
3376 { 0, 0, 0, 0, 0, 0}};
3378 uintptr_t devid = 0;
3380 if (!(idx = ata_match_chip(dev, ids)))
3383 /* if we are on a SuperTrak SX6000 dont attach */
3384 if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3385 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3386 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3387 devid == ATA_I960RM)
3390 strcpy(buffer, "Promise ");
3391 strcat(buffer, idx->text);
3393 /* if we are on a FastTrak TX4, adjust the interrupt resource */
3394 if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
3395 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
3396 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
3397 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) {
3398 static long start = 0, end = 0;
3400 if (pci_get_slot(dev) == 1) {
3401 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
3402 strcat(buffer, " (channel 0+1)");
3404 else if (pci_get_slot(dev) == 2 && start && end) {
3405 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
3406 strcat(buffer, " (channel 2+3)");
3412 ksprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
3413 device_set_desc_copy(dev, buffer);
3415 ctlr->chipinit = ata_promise_chipinit;
3420 ata_promise_chipinit(device_t dev)
3422 struct ata_pci_controller *ctlr = device_get_softc(dev);
3423 int fake_reg, stat_reg;
3425 if (ata_setup_interrupt(dev))
3428 switch (ctlr->chip->cfg1) {
3431 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
3433 ctlr->dmainit = ata_promise_dmainit;
3437 /* enable burst mode */
3438 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
3439 ctlr->allocate = ata_promise_allocate;
3440 ctlr->setmode = ata_promise_setmode;
3444 ctlr->allocate = ata_promise_tx2_allocate;
3445 ctlr->setmode = ata_promise_setmode;
3449 ctlr->r_type1 = SYS_RES_MEMORY;
3450 ctlr->r_rid1 = PCIR_BAR(4);
3451 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
3452 &ctlr->r_rid1, RF_ACTIVE)))
3455 ctlr->r_type2 = SYS_RES_MEMORY;
3456 ctlr->r_rid2 = PCIR_BAR(3);
3457 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
3458 &ctlr->r_rid2, RF_ACTIVE)))
3461 if (ctlr->chip->cfg2 == PRSX4X) {
3462 struct ata_promise_sx4 *hpkt;
3463 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080);
3465 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3466 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3467 ata_promise_sx4_intr, ctlr, &ctlr->handle, NULL)) {
3468 device_printf(dev, "unable to setup interrupt\n");
3472 /* print info about cache memory */
3473 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n",
3474 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4,
3475 ((dimm >> 24) & 0xff),
3476 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ?
3477 " ECC enabled" : "" );
3479 /* adjust cache memory parameters */
3480 ATA_OUTL(ctlr->r_res2, 0x000c000c,
3481 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000));
3483 /* setup host packet controls */
3484 hpkt = kmalloc(sizeof(struct ata_promise_sx4),
3485 M_TEMP, M_INTWAIT | M_ZERO);
3486 spin_init(&hpkt->mtx);
3487 TAILQ_INIT(&hpkt->queue);
3489 device_set_ivars(dev, hpkt);
3490 ctlr->allocate = ata_promise_mio_allocate;
3491 ctlr->reset = ata_promise_mio_reset;
3492 ctlr->dmainit = ata_promise_mio_dmainit;
3493 ctlr->setmode = ata_promise_setmode;
3498 /* mio type controllers need an interrupt intercept */
3499 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) ||
3500 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
3501 ata_promise_mio_intr, ctlr, &ctlr->handle, NULL)) {
3502 device_printf(dev, "unable to setup interrupt\n");
3506 switch (ctlr->chip->cfg2) {
3508 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) +
3509 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2;
3533 /* prime fake interrupt register */
3534 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3536 /* clear SATA status */
3537 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff);
3539 ctlr->allocate = ata_promise_mio_allocate;
3540 ctlr->reset = ata_promise_mio_reset;
3541 ctlr->dmainit = ata_promise_mio_dmainit;
3542 ctlr->setmode = ata_promise_mio_setmode;
3549 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
3551 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1);
3556 ata_promise_allocate(device_t dev)
3558 struct ata_channel *ch = device_get_softc(dev);
3560 if (ata_pci_allocate(dev))
3563 ch->hw.status = ata_promise_status;
3568 ata_promise_status(device_t dev)
3570 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3571 struct ata_channel *ch = device_get_softc(dev);
3573 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
3574 return ata_pci_status(dev);
3580 ata_promise_dmastart(device_t dev)
3582 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3583 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3584 struct ata_device *atadev = device_get_softc(dev);
3586 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3587 ATA_OUTB(ctlr->r_res1, 0x11,
3588 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02));
3589 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20,
3590 ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) |
3591 (ch->dma->cur_iosize >> 1));
3593 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) |
3594 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
3595 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->sg_bus);
3596 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3597 ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) |
3598 ATA_BMCMD_START_STOP);
3599 ch->flags |= ATA_DMA_ACTIVE;
3604 ata_promise_dmastop(device_t dev)
3606 struct ata_pci_controller *ctlr = device_get_softc(GRANDPARENT(dev));
3607 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3608 struct ata_device *atadev = device_get_softc(dev);
3611 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
3612 ATA_OUTB(ctlr->r_res1, 0x11,
3613 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02));
3614 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0);
3616 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT);
3617 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3618 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3619 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3620 ch->flags &= ~ATA_DMA_ACTIVE;
3625 ata_promise_dmareset(device_t dev)
3627 struct ata_channel *ch = device_get_softc(dev);
3629 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
3630 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
3631 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
3632 ch->flags &= ~ATA_DMA_ACTIVE;
3636 ata_promise_dmainit(device_t dev)
3638 struct ata_channel *ch = device_get_softc(dev);
3642 ch->dma->start = ata_promise_dmastart;
3643 ch->dma->stop = ata_promise_dmastop;
3644 ch->dma->reset = ata_promise_dmareset;
3649 ata_promise_setmode(device_t dev, int mode)
3651 device_t gparent = GRANDPARENT(dev);
3652 struct ata_pci_controller *ctlr = device_get_softc(gparent);
3653 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
3654 struct ata_device *atadev = device_get_softc(dev);
3655 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
3657 u_int32_t timings[][2] = {
3658 /* PROLD PRNEW mode */
3659 { 0x004ff329, 0x004fff2f }, /* PIO 0 */
3660 { 0x004fec25, 0x004ff82a }, /* PIO 1 */
3661 { 0x004fe823, 0x004ff026 }, /* PIO 2 */
3662 { 0x004fe622, 0x004fec24 }, /* PIO 3 */
3663 { 0x004fe421, 0x004fe822 }, /* PIO 4 */
3664 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */
3665 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */
3666 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */
3667 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */
3668 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */
3669 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */
3670 { 0, 0x00424ef6 }, /* UDMA 3 */
3671 { 0, 0x004127f3 }, /* UDMA 4 */
3672 { 0, 0x004127f3 } /* UDMA 5 */
3675 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
3677 switch (ctlr->chip->cfg1) {
3680 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x50, 2) &
3681 (ch->unit ? 1 << 11 : 1 << 10))) {
3682 ata_print_cable(dev, "controller");
3685 if (ata_atapi(dev) && mode > ATA_PIO_MAX)
3686 mode = ata_limit_mode(dev, mode, ATA_PIO_MAX);
3690 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3691 if (mode > ATA_UDMA2 &&
3692 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) {
3693 ata_print_cable(dev, "controller");
3699 if (mode > ATA_UDMA2 &&
3700 (ATA_INL(ctlr->r_res2,
3701 (ctlr->chip->cfg2 & PRSX4X ? 0x000c0260 : 0x0260) +
3702 (ch->unit << 7)) & 0x01000000)) {
3703 ata_print_cable(dev, "controller");
3709 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
3712 device_printf(dev, "%ssetting %s on %s chip\n",
3713 (error) ? "FAILURE " : "",
3714 ata_mode2str(mode), ctlr->chip->text);
3716 if (ctlr->chip->cfg1 < PRTX)
3717 pci_write_config(gparent, 0x60 + (devno << 2),
3718 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
3719 atadev->mode = mode;
3725 ata_promise_tx2_allocate(device_t dev)
3727 struct ata_channel *ch = device_get_softc(dev);
3729 if (ata_pci_allocate(dev))
3732 ch->hw.status = ata_promise_tx2_status;
3737 ata_promise_tx2_status(device_t dev)
3739 struct ata_channel *ch = device_get_softc(dev);
3741 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
3742 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
3743 return ata_pci_status(dev);
3749 ata_promise_mio_allocate(device_t dev)
3751 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3752 struct ata_channel *ch = device_get_softc(dev);
3753 int offset = (ctlr->chip->cfg2 & PRSX4X) ? 0x000c0000 : 0;
3756 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
3757 ch->r_io[i].res = ctlr->r_res2;
3758 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7);
3760 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
3761 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7);
3762 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
3763 ata_default_registers(dev);
3764 if ((ctlr->chip->cfg2 & (PRSATA | PRSATA2)) ||
3765 ((ctlr->chip->cfg2 & (PRCMBO | PRCMBO2)) && ch->unit < 2)) {
3766 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
3767 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8);
3768 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
3769 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8);
3770 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
3771 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8);
3772 ch->flags |= ATA_NO_SLAVE;
3774 ch->flags |= ATA_USE_16BIT;
3776 ata_generic_hw(dev);
3777 if (ctlr->chip->cfg2 & PRSX4X) {
3778 ch->hw.command = ata_promise_sx4_command;
3781 ch->hw.command = ata_promise_mio_command;
3782 ch->hw.status = ata_promise_mio_status;
3788 ata_promise_mio_intr(void *data)
3790 struct ata_pci_controller *ctlr = data;
3791 struct ata_channel *ch;
3795 switch (ctlr->chip->cfg2) {
3809 * since reading interrupt status register on early "mio" chips
3810 * clears the status bits we cannot read it for each channel later on
3811 * in the generic interrupt routine.
3812 * store the bits in an unused register in the chip so we can read
3813 * it from there safely to get around this "feature".
3815 vector = ATA_INL(ctlr->r_res2, 0x040);
3816 ATA_OUTL(ctlr->r_res2, 0x040, vector);
3817 ATA_OUTL(ctlr->r_res2, fake_reg, vector);
3819 for (unit = 0; unit < ctlr->channels; unit++) {
3820 if ((ch = ctlr->interrupt[unit].argument))
3821 ctlr->interrupt[unit].function(ch);
3824 ATA_OUTL(ctlr->r_res2, fake_reg, 0xffffffff);
3828 ata_promise_mio_status(device_t dev)
3830 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3831 struct ata_channel *ch = device_get_softc(dev);
3832 struct ata_connect_task *tp;
3833 u_int32_t fake_reg, stat_reg, vector, status;
3835 switch (ctlr->chip->cfg2) {
3850 /* read and acknowledge interrupt */
3851 vector = ATA_INL(ctlr->r_res2, fake_reg);
3853 /* read and clear interface status */
3854 status = ATA_INL(ctlr->r_res2, stat_reg);
3855 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit));
3857 /* check for and handle disconnect events */
3858 if ((status & (0x00000001 << ch->unit)) &&
3859 (tp = (struct ata_connect_task *)
3860 kmalloc(sizeof(struct ata_connect_task),
3861 M_ATA, M_INTWAIT | M_ZERO))) {
3864 device_printf(ch->dev, "DISCONNECT requested\n");
3865 tp->action = ATA_C_DETACH;
3867 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3868 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task);
3871 /* check for and handle connect events */
3872 if ((status & (0x00000010 << ch->unit)) &&
3873 (tp = (struct ata_connect_task *)
3874 kmalloc(sizeof(struct ata_connect_task),
3875 M_ATA, M_INTWAIT | M_ZERO))) {
3878 device_printf(ch->dev, "CONNECT requested\n");
3879 tp->action = ATA_C_ATTACH;
3881 TASK_INIT(&tp->task, 0, ata_sata_phy_event, tp);
3882 taskqueue_enqueue(taskqueue_thread[mycpuid], &tp->task);
3885 /* do we have any device action ? */
3886 return (vector & (1 << (ch->unit + 1)));
3890 ata_promise_mio_command(struct ata_request *request)
3892 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
3893 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
3894 u_int32_t *wordp = (u_int32_t *)ch->dma->work;
3896 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001);
3898 /* XXX SOS add ATAPI commands support later */
3899 switch (request->u.ata.command) {
3901 return ata_generic_command(request);
3904 case ATA_READ_DMA48:
3905 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24));
3909 case ATA_WRITE_DMA48:
3910 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24));
3913 wordp[1] = htole32(ch->dma->sg_bus);
3915 ata_promise_apkt((u_int8_t*)wordp, request);
3917 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma->work_bus);
3922 ata_promise_mio_reset(device_t dev)
3924 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
3925 struct ata_channel *ch = device_get_softc(dev);
3926 struct ata_promise_sx4 *hpktp;
3928 switch (ctlr->chip->cfg2) {
3931 /* softreset channel ATA module */
3932 hpktp = device_get_ivars(ctlr->dev);
3933 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1);
3935 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7),
3936 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) &
3937 ~0x00003f9f) | (ch->unit + 1));
3939 /* softreset HOST module */ /* XXX SOS what about other outstandings */
3940 spin_lock_wr(&hpktp->mtx);
3941 ATA_OUTL(ctlr->r_res2, 0xc012c,
3942 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11));
3944 ATA_OUTL(ctlr->r_res2, 0xc012c,
3945 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f));
3947 spin_unlock_wr(&hpktp->mtx);
3948 ata_generic_reset(dev);
3954 if ((ctlr->chip->cfg2 == PRSATA) ||
3955 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3957 /* mask plug/unplug intr */
3958 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit));
3961 /* softreset channels ATA module */
3962 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3964 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
3965 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
3966 ~0x00003f9f) | (ch->unit + 1));
3968 if ((ctlr->chip->cfg2 == PRSATA) ||
3969 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2))) {
3971 if (ata_sata_phy_reset(dev))
3972 ata_generic_reset(dev);
3974 /* reset and enable plug/unplug intr */
3975 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit));
3978 ata_generic_reset(dev);
3983 if ((ctlr->chip->cfg2 == PRSATA2) ||
3984 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
3985 /* set portmultiplier port */
3986 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f);
3988 /* mask plug/unplug intr */
3989 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit));
3992 /* softreset channels ATA module */
3993 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11));
3995 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7),
3996 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) &
3997 ~0x00003f9f) | (ch->unit + 1));
3999 if ((ctlr->chip->cfg2 == PRSATA2) ||
4000 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2))) {
4002 /* set PHY mode to "improved" */
4003 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8),
4004 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) &
4005 ~0x00000003) | 0x00000001);
4007 if (ata_sata_phy_reset(dev))
4008 ata_generic_reset(dev);
4010 /* reset and enable plug/unplug intr */
4011 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit));
4013 /* set portmultiplier port */
4014 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00);
4017 ata_generic_reset(dev);
4024 ata_promise_mio_dmainit(device_t dev)
4026 /* note start and stop are not used here */
4031 ata_promise_mio_setmode(device_t dev, int mode)
4033 device_t gparent = GRANDPARENT(dev);
4034 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4035 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4037 if ( (ctlr->chip->cfg2 == PRSATA) ||
4038 ((ctlr->chip->cfg2 == PRCMBO) && (ch->unit < 2)) ||
4039 (ctlr->chip->cfg2 == PRSATA2) ||
4040 ((ctlr->chip->cfg2 == PRCMBO2) && (ch->unit < 2)))
4041 ata_sata_setmode(dev, mode);
4043 ata_promise_setmode(dev, mode);
4047 ata_promise_sx4_intr(void *data)
4049 struct ata_pci_controller *ctlr = data;
4050 struct ata_channel *ch;
4051 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480);
4054 for (unit = 0; unit < ctlr->channels; unit++) {
4055 if (vector & (1 << (unit + 1)))
4056 if ((ch = ctlr->interrupt[unit].argument))
4057 ctlr->interrupt[unit].function(ch);
4058 if (vector & (1 << (unit + 5)))
4059 if ((ch = ctlr->interrupt[unit].argument))
4060 ata_promise_queue_hpkt(ctlr,
4061 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
4062 ATA_PDC_HPKT_OFFSET));
4063 if (vector & (1 << (unit + 9))) {
4064 ata_promise_next_hpkt(ctlr);
4065 if ((ch = ctlr->interrupt[unit].argument))
4066 ctlr->interrupt[unit].function(ch);
4068 if (vector & (1 << (unit + 13))) {
4069 ata_promise_next_hpkt(ctlr);
4070 if ((ch = ctlr->interrupt[unit].argument))
4071 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4072 htole32((ch->unit * ATA_PDC_CHN_OFFSET) +
4073 ATA_PDC_APKT_OFFSET));
4079 ata_promise_sx4_command(struct ata_request *request)
4081 device_t gparent = GRANDPARENT(request->dev);
4082 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4083 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4084 struct ata_dma_prdentry *prd = ch->dma->sg;
4085 caddr_t window = rman_get_virtual(ctlr->r_res1);
4087 int i, idx, length = 0;
4089 /* XXX SOS add ATAPI commands support later */
4090 switch (request->u.ata.command) {
4095 case ATA_ATA_IDENTIFY:
4099 case ATA_READ_MUL48:
4103 case ATA_WRITE_MUL48:
4104 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
4105 return ata_generic_command(request);
4107 case ATA_SETFEATURES:
4108 case ATA_FLUSHCACHE:
4109 case ATA_FLUSHCACHE48:
4112 wordp = (u_int32_t *)
4113 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
4114 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24));
4117 ata_promise_apkt((u_int8_t *)wordp, request);
4118 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
4119 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001);
4120 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4121 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET));
4125 case ATA_READ_DMA48:
4127 case ATA_WRITE_DMA48:
4128 wordp = (u_int32_t *)
4129 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET);
4132 wordp[idx++] = prd[i].addr;
4133 wordp[idx++] = prd[i].count;
4134 length += (prd[i].count & ~ATA_DMA_EOT);
4135 } while (!(prd[i++].count & ATA_DMA_EOT));
4137 wordp = (u_int32_t *)
4138 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET);
4139 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4140 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4142 wordp = (u_int32_t *)
4143 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET);
4144 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE);
4145 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT);
4147 wordp = (u_int32_t *)
4148 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET);
4149 if (request->flags & ATA_R_READ)
4150 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24));
4151 if (request->flags & ATA_R_WRITE)
4152 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24));
4153 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET);
4154 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET);
4157 wordp = (u_int32_t *)
4158 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET);
4159 if (request->flags & ATA_R_READ)
4160 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24));
4161 if (request->flags & ATA_R_WRITE)
4162 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24));
4163 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET);
4165 ata_promise_apkt((u_int8_t *)wordp, request);
4166 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001);
4168 if (request->flags & ATA_R_READ) {
4169 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001);
4170 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001);
4171 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7),
4172 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET));
4174 if (request->flags & ATA_R_WRITE) {
4175 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001);
4176 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001);
4177 ata_promise_queue_hpkt(ctlr,
4178 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET));
4185 ata_promise_apkt(u_int8_t *bytep, struct ata_request *request)
4187 struct ata_device *atadev = device_get_softc(request->dev);
4190 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE;
4191 bytep[i++] = ATA_D_IBM | ATA_D_LBA | atadev->unit;
4192 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL;
4193 bytep[i++] = ATA_A_4BIT;
4195 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
4196 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4197 bytep[i++] = request->u.ata.feature >> 8;
4198 bytep[i++] = request->u.ata.feature;
4199 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT;
4200 bytep[i++] = request->u.ata.count >> 8;
4201 bytep[i++] = request->u.ata.count;
4202 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4203 bytep[i++] = request->u.ata.lba >> 24;
4204 bytep[i++] = request->u.ata.lba;
4205 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4206 bytep[i++] = request->u.ata.lba >> 32;
4207 bytep[i++] = request->u.ata.lba >> 8;
4208 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4209 bytep[i++] = request->u.ata.lba >> 40;
4210 bytep[i++] = request->u.ata.lba >> 16;
4211 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4212 bytep[i++] = ATA_D_LBA | atadev->unit;
4215 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE;
4216 bytep[i++] = request->u.ata.feature;
4217 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT;
4218 bytep[i++] = request->u.ata.count;
4219 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR;
4220 bytep[i++] = request->u.ata.lba;
4221 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB;
4222 bytep[i++] = request->u.ata.lba >> 8;
4223 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB;
4224 bytep[i++] = request->u.ata.lba >> 16;
4225 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE;
4226 bytep[i++] = (atadev->flags & ATA_D_USE_CHS ? 0 : ATA_D_LBA) |
4227 ATA_D_IBM | atadev->unit | ((request->u.ata.lba >> 24)&0xf);
4229 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND;
4230 bytep[i++] = request->u.ata.command;
4235 ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt)
4237 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
4239 spin_lock_wr(&hpktp->mtx);
4241 struct host_packet *hp =
4242 kmalloc(sizeof(struct host_packet), M_TEMP, M_INTWAIT | M_ZERO);
4244 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain);
4248 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt);
4250 spin_unlock_wr(&hpktp->mtx);
4254 ata_promise_next_hpkt(struct ata_pci_controller *ctlr)
4256 struct ata_promise_sx4 *hpktp = device_get_ivars(ctlr->dev);
4257 struct host_packet *hp;
4259 spin_lock_wr(&hpktp->mtx);
4260 if ((hp = TAILQ_FIRST(&hpktp->queue))) {
4261 TAILQ_REMOVE(&hpktp->queue, hp, chain);
4262 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr);
4267 spin_unlock_wr(&hpktp->mtx);
4272 * ServerWorks chipset support functions
4275 ata_serverworks_ident(device_t dev)
4277 struct ata_pci_controller *ctlr = device_get_softc(dev);
4278 struct ata_chip_id *idx;
4279 static struct ata_chip_id ids[] =
4280 {{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" },
4281 { ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" },
4282 { ATA_CSB5, 0x00, SWKS66, 0, ATA_UDMA4, "CSB5" },
4283 { ATA_CSB6, 0x00, SWKS100, 0, ATA_UDMA5, "CSB6" },
4284 { ATA_CSB6_1, 0x00, SWKS66, 0, ATA_UDMA4, "CSB6" },
4285 { ATA_HT1000, 0x00, SWKS100, 0, ATA_UDMA5, "HT1000" },
4286 { ATA_HT1000_S1, 0x00, SWKS100, 4, ATA_SA150, "HT1000" },
4287 { ATA_HT1000_S2, 0x00, SWKSMIO, 4, ATA_SA150, "HT1000" },
4288 { ATA_K2, 0x00, SWKSMIO, 4, ATA_SA150, "K2" },
4289 { ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" },
4290 { ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" },
4291 { 0, 0, 0, 0, 0, 0}};
4294 if (!(idx = ata_match_chip(dev, ids)))
4297 ksprintf(buffer, "ServerWorks %s %s controller",
4298 idx->text, ata_mode2str(idx->max_dma));
4299 device_set_desc_copy(dev, buffer);
4301 ctlr->chipinit = ata_serverworks_chipinit;
4306 ata_serverworks_chipinit(device_t dev)
4308 struct ata_pci_controller *ctlr = device_get_softc(dev);
4310 if (ata_setup_interrupt(dev))
4313 if (ctlr->chip->cfg1 == SWKSMIO) {
4314 ctlr->r_type2 = SYS_RES_MEMORY;
4315 ctlr->r_rid2 = PCIR_BAR(5);
4316 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4317 &ctlr->r_rid2, RF_ACTIVE)))
4320 ctlr->channels = ctlr->chip->cfg2;
4321 ctlr->allocate = ata_serverworks_allocate;
4322 ctlr->setmode = ata_sata_setmode;
4325 else if (ctlr->chip->cfg1 == SWKS33) {
4329 /* locate the ISA part in the southbridge and enable UDMA33 */
4330 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
4331 for (i = 0; i < nchildren; i++) {
4332 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
4333 pci_write_config(children[i], 0x64,
4334 (pci_read_config(children[i], 0x64, 4) &
4335 ~0x00002000) | 0x00004000, 4);
4339 kfree(children, M_TEMP);
4343 pci_write_config(dev, 0x5a,
4344 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
4345 (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1);
4347 ctlr->setmode = ata_serverworks_setmode;
4352 ata_serverworks_allocate(device_t dev)
4354 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4355 struct ata_channel *ch = device_get_softc(dev);
4359 ch_offset = ch->unit * 0x100;
4361 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
4362 ch->r_io[i].res = ctlr->r_res2;
4364 /* setup ATA registers */
4365 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
4366 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04;
4367 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
4368 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
4369 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
4370 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
4371 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
4372 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c;
4373 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20;
4374 ata_default_registers(dev);
4376 /* setup DMA registers */
4377 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30;
4378 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32;
4379 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34;
4381 /* setup SATA registers */
4382 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40;
4383 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44;
4384 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48;
4386 ch->flags |= ATA_NO_SLAVE;
4392 ata_serverworks_setmode(device_t dev, int mode)
4394 device_t gparent = GRANDPARENT(dev);
4395 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4396 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4397 struct ata_device *atadev = device_get_softc(dev);
4398 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4399 int offset = (devno ^ 0x01) << 3;
4401 u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
4402 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
4403 u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 };
4405 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4407 mode = ata_check_80pin(dev, mode);
4409 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4412 device_printf(dev, "%ssetting %s on %s chip\n",
4413 (error) ? "FAILURE " : "",
4414 ata_mode2str(mode), ctlr->chip->text);
4416 if (mode >= ATA_UDMA0) {
4417 pci_write_config(gparent, 0x56,
4418 (pci_read_config(gparent, 0x56, 2) &
4419 ~(0xf << (devno << 2))) |
4420 ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
4421 pci_write_config(gparent, 0x54,
4422 pci_read_config(gparent, 0x54, 1) |
4423 (0x01 << devno), 1);
4424 pci_write_config(gparent, 0x44,
4425 (pci_read_config(gparent, 0x44, 4) &
4426 ~(0xff << offset)) |
4427 (dmatimings[2] << offset), 4);
4429 else if (mode >= ATA_WDMA0) {
4430 pci_write_config(gparent, 0x54,
4431 pci_read_config(gparent, 0x54, 1) &
4432 ~(0x01 << devno), 1);
4433 pci_write_config(gparent, 0x44,
4434 (pci_read_config(gparent, 0x44, 4) &
4435 ~(0xff << offset)) |
4436 (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
4439 pci_write_config(gparent, 0x54,
4440 pci_read_config(gparent, 0x54, 1) &
4441 ~(0x01 << devno), 1);
4443 pci_write_config(gparent, 0x40,
4444 (pci_read_config(gparent, 0x40, 4) &
4445 ~(0xff << offset)) |
4446 (piotimings[ata_mode2idx(mode)] << offset), 4);
4447 atadev->mode = mode;
4453 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
4456 ata_sii_ident(device_t dev)
4458 struct ata_pci_controller *ctlr = device_get_softc(dev);
4459 struct ata_chip_id *idx;
4460 static struct ata_chip_id ids[] =
4461 {{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" },
4462 { ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" },
4463 { ATA_SII3112, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4464 { ATA_SII3112_1, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3112" },
4465 { ATA_SII3512, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3512" },
4466 { ATA_SII3112, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4467 { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG, ATA_SA150, "SiI 3112" },
4468 { ATA_SII3124, 0x00, SIIPRBIO, SII4CH, ATA_SA300, "SiI 3124" },
4469 { ATA_SII3132, 0x00, SIIPRBIO, 0, ATA_SA300, "SiI 3132" },
4470 { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
4471 { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" },
4472 { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" },
4473 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
4474 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
4475 { 0, 0, 0, 0, 0, 0}};
4478 if (!(idx = ata_match_chip(dev, ids)))
4481 ksprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
4482 device_set_desc_copy(dev, buffer);
4484 ctlr->chipinit = ata_sii_chipinit;
4489 ata_sii_chipinit(device_t dev)
4491 struct ata_pci_controller *ctlr = device_get_softc(dev);
4493 if (ata_setup_interrupt(dev))
4496 switch (ctlr->chip->cfg1) {
4498 ctlr->r_type1 = SYS_RES_MEMORY;
4499 ctlr->r_rid1 = PCIR_BAR(0);
4500 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
4501 &ctlr->r_rid1, RF_ACTIVE)))
4504 ctlr->r_rid2 = PCIR_BAR(2);
4505 ctlr->r_type2 = SYS_RES_MEMORY;
4506 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4507 &ctlr->r_rid2, RF_ACTIVE))){
4508 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
4511 ctlr->allocate = ata_siiprb_allocate;
4512 ctlr->reset = ata_siiprb_reset;
4513 ctlr->dmainit = ata_siiprb_dmainit;
4514 ctlr->setmode = ata_sata_setmode;
4515 ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2;
4517 /* reset controller */
4518 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
4520 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
4522 /* enable PCI interrupt */
4523 pci_write_config(dev, PCIR_COMMAND,
4524 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
4528 ctlr->r_type2 = SYS_RES_MEMORY;
4529 ctlr->r_rid2 = PCIR_BAR(5);
4530 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
4531 &ctlr->r_rid2, RF_ACTIVE)))
4534 if (ctlr->chip->cfg2 & SIISETCLK) {
4535 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4536 pci_write_config(dev, 0x8a,
4537 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
4538 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
4539 device_printf(dev, "%s could not set ATA133 clock\n",
4543 /* if we have 4 channels enable the second set */
4544 if (ctlr->chip->cfg2 & SII4CH) {
4545 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
4549 /* dont block interrupts from any channel */
4550 pci_write_config(dev, 0x48,
4551 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
4553 /* enable PCI interrupt as BIOS might not */
4554 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
4556 ctlr->allocate = ata_sii_allocate;
4557 if (ctlr->chip->max_dma >= ATA_SA150) {
4558 ctlr->reset = ata_sii_reset;
4559 ctlr->setmode = ata_sata_setmode;
4562 ctlr->setmode = ata_sii_setmode;
4566 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
4567 device_printf(dev, "HW has secondary channel disabled\n");
4571 /* enable interrupt as BIOS might not */
4572 pci_write_config(dev, 0x71, 0x01, 1);
4574 ctlr->allocate = ata_cmd_allocate;
4575 ctlr->setmode = ata_cmd_setmode;
4582 ata_cmd_allocate(device_t dev)
4584 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4585 struct ata_channel *ch = device_get_softc(dev);
4587 /* setup the usual register normal pci style */
4588 if (ata_pci_allocate(dev))
4591 if (ctlr->chip->cfg2 & SIIINTR)
4592 ch->hw.status = ata_cmd_status;
4598 ata_cmd_status(device_t dev)
4600 struct ata_channel *ch = device_get_softc(dev);
4603 if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
4604 (ch->unit ? 0x08 : 0x04))) {
4605 pci_write_config(device_get_parent(ch->dev), 0x71,
4606 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
4607 return ata_pci_status(dev);
4613 ata_cmd_setmode(device_t dev, int mode)
4615 device_t gparent = GRANDPARENT(dev);
4616 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4617 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4618 struct ata_device *atadev = device_get_softc(dev);
4619 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
4622 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4624 mode = ata_check_80pin(dev, mode);
4626 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4629 device_printf(dev, "%ssetting %s on %s chip\n",
4630 (error) ? "FAILURE " : "",
4631 ata_mode2str(mode), ctlr->chip->text);
4633 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
4634 int ureg = ch->unit ? 0x7b : 0x73;
4636 if (mode >= ATA_UDMA0) {
4637 int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
4638 { 0x11, 0x42 }, { 0x25, 0x8a },
4639 { 0x15, 0x4a }, { 0x05, 0x0a } };
4641 u_int8_t umode = pci_read_config(gparent, ureg, 1);
4643 umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca);
4644 umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)];
4645 pci_write_config(gparent, ureg, umode, 1);
4647 else if (mode >= ATA_WDMA0) {
4648 int dmatimings[] = { 0x87, 0x32, 0x3f };
4650 pci_write_config(gparent, treg, dmatimings[mode & ATA_MODE_MASK],1);
4651 pci_write_config(gparent, ureg,
4652 pci_read_config(gparent, ureg, 1) &
4653 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4656 int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
4657 pci_write_config(gparent, treg,
4658 piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1);
4659 pci_write_config(gparent, ureg,
4660 pci_read_config(gparent, ureg, 1) &
4661 ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1);
4663 atadev->mode = mode;
4668 ata_sii_allocate(device_t dev)
4670 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4671 struct ata_channel *ch = device_get_softc(dev);
4672 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
4675 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
4676 ch->r_io[i].res = ctlr->r_res2;
4677 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
4679 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
4680 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
4681 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
4682 ata_default_registers(dev);
4684 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
4685 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
4686 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
4687 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
4688 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
4689 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
4691 if (ctlr->chip->max_dma >= ATA_SA150) {
4692 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4693 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
4694 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4695 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
4696 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4697 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
4698 ch->flags |= ATA_NO_SLAVE;
4700 /* enable PHY state change interrupt */
4701 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
4704 if ((ctlr->chip->cfg2 & SIIBUG) && ch->dma) {
4705 /* work around errata in early chips */
4706 ch->dma->boundary = 16 * DEV_BSIZE;
4707 ch->dma->segsize = 15 * DEV_BSIZE;
4711 ch->hw.status = ata_sii_status;
4716 ata_sii_status(device_t dev)
4718 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4719 struct ata_channel *ch = device_get_softc(dev);
4720 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
4721 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
4723 /* do we have any PHY events ? */
4724 if (ctlr->chip->max_dma >= ATA_SA150 &&
4725 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
4726 ata_sata_phy_check_events(dev);
4728 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
4729 return ata_pci_status(dev);
4735 ata_sii_reset(device_t dev)
4737 if (ata_sata_phy_reset(dev))
4738 ata_generic_reset(dev);
4742 ata_sii_setmode(device_t dev, int mode)
4744 device_t gparent = GRANDPARENT(dev);
4745 struct ata_pci_controller *ctlr = device_get_softc(gparent);
4746 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
4747 struct ata_device *atadev = device_get_softc(dev);
4748 int rego = (ch->unit << 4) + (ATA_DEV(atadev->unit) << 1);
4749 int mreg = ch->unit ? 0x84 : 0x80;
4750 int mask = 0x03 << (ATA_DEV(atadev->unit) << 2);
4751 int mval = pci_read_config(gparent, mreg, 1) & ~mask;
4754 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
4756 if (ctlr->chip->cfg2 & SIISETCLK) {
4757 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x79, 1) &
4758 (ch->unit ? 0x02 : 0x01))) {
4759 ata_print_cable(dev, "controller");
4764 mode = ata_check_80pin(dev, mode);
4766 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
4769 device_printf(dev, "%ssetting %s on %s chip\n",
4770 (error) ? "FAILURE " : "",
4771 ata_mode2str(mode), ctlr->chip->text);
4775 if (mode >= ATA_UDMA0) {
4776 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
4777 u_int8_t ureg = 0xac + rego;
4779 pci_write_config(gparent, mreg,
4780 mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1);
4781 pci_write_config(gparent, ureg,
4782 (pci_read_config(gparent, ureg, 1) & ~0x3f) |
4783 udmatimings[mode & ATA_MODE_MASK], 1);
4786 else if (mode >= ATA_WDMA0) {
4787 u_int8_t dreg = 0xa8 + rego;
4788 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
4790 pci_write_config(gparent, mreg,
4791 mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1);
4792 pci_write_config(gparent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
4796 u_int8_t preg = 0xa4 + rego;
4797 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
4799 pci_write_config(gparent, mreg,
4800 mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1);
4801 pci_write_config(gparent, preg, piotimings[mode & ATA_MODE_MASK], 2);
4803 atadev->mode = mode;
4806 struct ata_siiprb_dma_prdentry {
4812 struct ata_siiprb_ata_command {
4813 u_int32_t reserved0;
4814 struct ata_siiprb_dma_prdentry prd[126];
4817 struct ata_siiprb_atapi_command {
4819 struct ata_siiprb_dma_prdentry prd[125];
4822 struct ata_siiprb_command {
4824 u_int16_t protocol_override;
4825 u_int32_t transfer_count;
4828 struct ata_siiprb_ata_command ata;
4829 struct ata_siiprb_atapi_command atapi;
4834 ata_siiprb_allocate(device_t dev)
4836 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4837 struct ata_channel *ch = device_get_softc(dev);
4838 int offset = ch->unit * 0x2000;
4840 /* set the SATA resources */
4841 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
4842 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
4843 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
4844 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
4845 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
4846 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
4847 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
4848 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
4850 ch->hw.begin_transaction = ata_siiprb_begin_transaction;
4851 ch->hw.end_transaction = ata_siiprb_end_transaction;
4852 ch->hw.status = ata_siiprb_status;
4853 ch->hw.command = NULL; /* not used here */
4858 ata_siiprb_status(device_t dev)
4860 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4861 struct ata_channel *ch = device_get_softc(dev);
4862 int offset = ch->unit * 0x2000;
4864 if ((ATA_INL(ctlr->r_res1, 0x0044) & (1 << ch->unit))) {
4865 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
4867 /* do we have any PHY events ? */
4868 ata_sata_phy_check_events(dev);
4870 /* clear interrupt(s) */
4871 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
4873 /* do we have any device action ? */
4874 return (istatus & 0x00000001);
4880 ata_siiprb_begin_transaction(struct ata_request *request)
4882 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
4883 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4884 struct ata_siiprb_command *prb;
4885 int offset = ch->unit * 0x2000;
4889 /* check for 48 bit access and convert if needed */
4890 ata_modify_if_48bit(request);
4892 /* get a piece of the workspace for this request */
4893 prb = (struct ata_siiprb_command *)
4894 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
4896 /* set basic prd options ata/atapi etc etc */
4897 bzero(prb, sizeof(struct ata_siiprb_command));
4899 /* setup the FIS for this request */
4900 if (!ata_request2fis_h2d(request, &prb->fis[0])) {
4901 device_printf(request->dev, "setting up SATA FIS failed\n");
4902 request->result = EIO;
4903 return ATA_OP_FINISHED;
4906 /* if request moves data setup and load SG list */
4907 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
4908 struct ata_siiprb_dma_prdentry *prd;
4910 if (request->flags & ATA_R_ATAPI)
4911 prd = &prb->u.atapi.prd[0];
4913 prd = &prb->u.ata.prd[0];
4914 if (ch->dma->load(ch->dev, request->data, request->bytecount,
4915 request->flags & ATA_R_READ, prd, &dummy)) {
4916 device_printf(request->dev, "setting up DMA failed\n");
4917 request->result = EIO;
4918 return ATA_OP_FINISHED;
4922 /* activate the prb */
4923 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
4924 ATA_OUTL(ctlr->r_res2,
4925 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
4926 ATA_OUTL(ctlr->r_res2,
4927 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
4929 /* start the timeout */
4930 callout_reset(&request->callout, request->timeout * hz,
4931 (timeout_t*)ata_timeout, request);
4932 return ATA_OP_CONTINUES;
4936 ata_siiprb_end_transaction(struct ata_request *request)
4938 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
4939 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
4940 struct ata_siiprb_command *prb;
4941 int offset = ch->unit * 0x2000;
4944 /* kill the timeout */
4945 callout_stop(&request->callout);
4947 prb = (struct ata_siiprb_command *)
4948 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
4950 /* if error status get details */
4951 request->status = prb->fis[2];
4952 if (request->status & ATA_S_ERROR)
4953 request->error = prb->fis[3];
4955 /* update progress */
4956 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
4957 if (request->flags & ATA_R_READ)
4958 request->donecount = prb->transfer_count;
4960 request->donecount = request->bytecount;
4963 /* any controller errors flagged ? */
4964 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
4965 kprintf("ata_siiprb_end_transaction %s error=%08x\n",
4966 ata_cmd2str(request), error);
4969 /* release SG list etc */
4970 ch->dma->unload(ch->dev);
4972 return ATA_OP_FINISHED;
4976 ata_siiprb_reset(device_t dev)
4978 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
4979 struct ata_channel *ch = device_get_softc(dev);
4980 int offset = ch->unit * 0x2000;
4981 struct ata_siiprb_command *prb;
4983 u_int32_t status, signature;
4984 int timeout, tag = 0;
4986 /* reset channel HW */
4987 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
4989 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
4992 /* poll for channel ready */
4993 for (timeout = 0; timeout < 1000; timeout++) {
4994 if ((status = ATA_INL(ctlr->r_res2, 0x1000 + offset)) & 0x00040000)
4998 if (timeout >= 1000) {
4999 device_printf(ch->dev, "channel HW reset timeout reset failure\n");
5004 device_printf(ch->dev, "channel HW reset time=%dms\n", timeout * 1);
5007 if (!ata_sata_phy_reset(dev)) {
5009 device_printf(ch->dev, "phy reset found no device\n");
5014 /* get a piece of the workspace for a soft reset request */
5015 prb = (struct ata_siiprb_command *)
5016 (ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
5017 bzero(prb, sizeof(struct ata_siiprb_command));
5018 prb->control = htole16(0x0080);
5020 /* activate the soft reset prb */
5021 prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
5022 ATA_OUTL(ctlr->r_res2,
5023 0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
5024 ATA_OUTL(ctlr->r_res2,
5025 0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
5027 /* poll for channel ready */
5028 for (timeout = 0; timeout < 1000; timeout++) {
5030 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
5033 if (timeout >= 1000) {
5034 device_printf(ch->dev, "reset timeout - no device found\n");
5039 device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n",
5042 /* find out whats there */
5043 prb = (struct ata_siiprb_command *)
5044 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
5046 prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
5048 device_printf(ch->dev, "signature=%08x\n", signature);
5049 switch (signature) {
5051 ch->devices = ATA_ATAPI_MASTER;
5052 device_printf(ch->dev, "SATA ATAPI devices not supported yet\n");
5056 ch->devices = ATA_PORTMULTIPLIER;
5057 device_printf(ch->dev, "Portmultipliers not supported yet\n");
5061 ch->devices = ATA_ATA_MASTER;
5068 /* clear interrupt(s) */
5069 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
5071 /* require explicit interrupt ack */
5072 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
5075 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
5077 /* enable interrupts wanted */
5078 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
5082 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
5084 struct ata_dmasetprd_args *args = xsc;
5085 struct ata_siiprb_dma_prdentry *prd = args->dmatab;
5088 if ((args->error = error))
5091 for (i = 0; i < nsegs; i++) {
5092 prd[i].addr = htole64(segs[i].ds_addr);
5093 prd[i].count = htole32(segs[i].ds_len);
5095 prd[i - 1].control = htole32(ATA_DMA_EOT);
5099 ata_siiprb_dmainit(device_t dev)
5101 struct ata_channel *ch = device_get_softc(dev);
5105 /* note start and stop are not used here */
5106 ch->dma->setprd = ata_siiprb_dmasetprd;
5107 ch->dma->max_address = BUS_SPACE_MAXADDR;
5113 * Silicon Integrated Systems Corp. (SiS) chipset support functions
5116 ata_sis_ident(device_t dev)
5118 struct ata_pci_controller *ctlr = device_get_softc(dev);
5119 struct ata_chip_id *idx;
5120 static struct ata_chip_id ids[] =
5121 {{ ATA_SIS182, 0x00, SISSATA, 0, ATA_SA150, "182" }, /* south */
5122 { ATA_SIS181, 0x00, SISSATA, 0, ATA_SA150, "181" }, /* south */
5123 { ATA_SIS180, 0x00, SISSATA, 0, ATA_SA150, "180" }, /* south */
5124 { ATA_SIS965, 0x00, SIS133NEW, 0, ATA_UDMA6, "965" }, /* south */
5125 { ATA_SIS964, 0x00, SIS133NEW, 0, ATA_UDMA6, "964" }, /* south */
5126 { ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "963" }, /* south */
5127 { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "962" }, /* south */
5129 { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */
5130 { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */
5131 { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */
5132 { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */
5134 { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */
5135 { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "633" }, /* unknown */
5136 { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */
5137 { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "630" }, /* 1chip */
5138 { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "620" }, /* 1chip */
5140 { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "550" },
5141 { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "540" },
5142 { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "530" },
5144 { ATA_SIS5513, 0xc2, SIS33, 1, ATA_UDMA2, "5513" },
5145 { ATA_SIS5513, 0x00, SIS33, 1, ATA_WDMA2, "5513" },
5146 { 0, 0, 0, 0, 0, 0 }};
5150 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
5153 if (idx->cfg2 && !found) {
5154 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
5156 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
5157 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
5159 idx->cfg1 = SIS133NEW;
5160 idx->max_dma = ATA_UDMA6;
5161 ksprintf(buffer, "SiS 962/963 %s controller",
5162 ata_mode2str(idx->max_dma));
5164 pci_write_config(dev, 0x57, reg57, 1);
5166 if (idx->cfg2 && !found) {
5167 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
5169 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
5170 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
5171 struct ata_chip_id id[] =
5172 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
5175 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
5176 idx->cfg1 = SIS133OLD;
5177 idx->max_dma = ATA_UDMA6;
5180 idx->cfg1 = SIS100NEW;
5181 idx->max_dma = ATA_UDMA5;
5183 ksprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
5185 pci_write_config(dev, 0x4a, reg4a, 1);
5188 ksprintf(buffer,"SiS %s %s controller",
5189 idx->text, ata_mode2str(idx->max_dma));
5191 device_set_desc_copy(dev, buffer);
5193 ctlr->chipinit = ata_sis_chipinit;
5198 ata_sis_chipinit(device_t dev)
5200 struct ata_pci_controller *ctlr = device_get_softc(dev);
5202 if (ata_setup_interrupt(dev))
5205 switch (ctlr->chip->cfg1) {
5210 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
5214 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
5217 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
5218 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
5221 ctlr->r_type2 = SYS_RES_IOPORT;
5222 ctlr->r_rid2 = PCIR_BAR(5);
5223 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
5224 &ctlr->r_rid2, RF_ACTIVE))) {
5225 ctlr->allocate = ata_sis_allocate;
5226 ctlr->reset = ata_sis_reset;
5228 /* enable PCI interrupt */
5229 pci_write_config(dev, PCIR_COMMAND,
5230 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
5232 ctlr->setmode = ata_sata_setmode;
5237 ctlr->setmode = ata_sis_setmode;
5242 ata_sis_allocate(device_t dev)
5244 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5245 struct ata_channel *ch = device_get_softc(dev);
5246 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6);
5248 /* setup the usual register normal pci style */
5249 if (ata_pci_allocate(dev))
5252 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
5253 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset;
5254 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
5255 ch->r_io[ATA_SERROR].offset = 0x04 + offset;
5256 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
5257 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset;
5258 ch->flags |= ATA_NO_SLAVE;
5260 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */
5261 /* XXX SOS unknown how to enable PHY state change interrupt */
5266 ata_sis_reset(device_t dev)
5268 if (ata_sata_phy_reset(dev))
5269 ata_generic_reset(dev);
5273 ata_sis_setmode(device_t dev, int mode)
5275 device_t gparent = GRANDPARENT(dev);
5276 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5277 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5278 struct ata_device *atadev = device_get_softc(dev);
5279 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
5282 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
5284 if (ctlr->chip->cfg1 == SIS133NEW) {
5285 if (mode > ATA_UDMA2 &&
5286 pci_read_config(gparent, ch->unit ? 0x52 : 0x50,2) & 0x8000) {
5287 ata_print_cable(dev, "controller");
5292 if (mode > ATA_UDMA2 &&
5293 pci_read_config(gparent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) {
5294 ata_print_cable(dev, "controller");
5299 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5302 device_printf(dev, "%ssetting %s on %s chip\n",
5303 (error) ? "FAILURE " : "",
5304 ata_mode2str(mode), ctlr->chip->text);
5306 switch (ctlr->chip->cfg1) {
5308 u_int32_t timings[] =
5309 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
5310 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
5311 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
5314 reg = (pci_read_config(gparent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
5315 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 4);
5319 u_int16_t timings[] =
5320 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
5321 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
5323 u_int16_t reg = 0x40 + (devno << 1);
5325 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5329 u_int16_t timings[] =
5330 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
5331 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
5332 u_int16_t reg = 0x40 + (devno << 1);
5334 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5340 u_int16_t timings[] =
5341 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
5342 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
5343 u_int16_t reg = 0x40 + (devno << 1);
5345 pci_write_config(gparent, reg, timings[ata_mode2idx(mode)], 2);
5349 atadev->mode = mode;
5354 /* VIA Technologies Inc. chipset support functions */
5356 ata_via_ident(device_t dev)
5358 struct ata_pci_controller *ctlr = device_get_softc(dev);
5359 struct ata_chip_id *idx;
5360 static struct ata_chip_id ids[] =
5361 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" },
5362 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" },
5363 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" },
5364 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" },
5365 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"},
5366 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" },
5367 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" },
5368 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" },
5369 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" },
5370 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" },
5371 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" },
5372 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" },
5373 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
5374 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" },
5375 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" },
5376 { 0, 0, 0, 0, 0, 0 }};
5377 static struct ata_chip_id new_ids[] =
5378 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" },
5379 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" },
5380 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" },
5381 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" },
5382 { ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" },
5383 { 0, 0, 0, 0, 0, 0 }};
5386 if (pci_get_devid(dev) == ATA_VIA82C571) {
5387 if (!(idx = ata_find_chip(dev, ids, -99)))
5391 if (!(idx = ata_match_chip(dev, new_ids)))
5395 ksprintf(buffer, "VIA %s %s controller",
5396 idx->text, ata_mode2str(idx->max_dma));
5397 device_set_desc_copy(dev, buffer);
5399 ctlr->chipinit = ata_via_chipinit;
5404 ata_via_chipinit(device_t dev)
5406 struct ata_pci_controller *ctlr = device_get_softc(dev);
5408 if (ata_setup_interrupt(dev))
5411 if (ctlr->chip->max_dma >= ATA_SA150) {
5412 if (ctlr->chip->cfg2 == VIAAHCI) {
5413 ctlr->r_type2 = SYS_RES_MEMORY;
5414 ctlr->r_rid2 = PCIR_BAR(5);
5415 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
5418 return ata_ahci_chipinit(dev);
5421 ctlr->r_type2 = SYS_RES_IOPORT;
5422 ctlr->r_rid2 = PCIR_BAR(5);
5423 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
5424 &ctlr->r_rid2, RF_ACTIVE))) {
5425 ctlr->allocate = ata_via_allocate;
5426 ctlr->reset = ata_via_reset;
5428 /* enable PCI interrupt */
5429 pci_write_config(dev, PCIR_COMMAND,
5430 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
5433 if (ctlr->chip->cfg2 & VIABAR) {
5435 ctlr->setmode = ata_via_setmode;
5438 ctlr->setmode = ata_sata_setmode;
5442 /* prepare for ATA-66 on the 82C686a and 82C596b */
5443 if (ctlr->chip->cfg2 & VIACLK)
5444 pci_write_config(dev, 0x50, 0x030b030b, 4);
5446 /* the southbridge might need the data corruption fix */
5447 if (ctlr->chip->cfg2 & VIABUG)
5448 ata_via_southbridge_fixup(dev);
5450 /* set fifo configuration half'n'half */
5451 pci_write_config(dev, 0x43,
5452 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
5454 /* set status register read retry */
5455 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
5457 /* set DMA read & end-of-sector fifo flush */
5458 pci_write_config(dev, 0x46,
5459 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
5461 /* set sector size */
5462 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
5463 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
5465 ctlr->setmode = ata_via_family_setmode;
5470 ata_via_allocate(device_t dev)
5472 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5473 struct ata_channel *ch = device_get_softc(dev);
5475 /* newer SATA chips has resources in one BAR for each channel */
5476 if (ctlr->chip->cfg2 & VIABAR) {
5477 struct resource *r_io;
5480 rid = PCIR_BAR(ch->unit);
5481 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
5486 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
5487 ch->r_io[i].res = r_io;
5488 ch->r_io[i].offset = i;
5490 ch->r_io[ATA_CONTROL].res = r_io;
5491 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
5492 ch->r_io[ATA_IDX_ADDR].res = r_io;
5493 ata_default_registers(dev);
5494 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
5495 ch->r_io[i].res = ctlr->r_res1;
5496 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
5503 /* setup the usual register normal pci style */
5504 if (ata_pci_allocate(dev))
5508 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
5509 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
5510 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
5511 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
5512 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
5513 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
5514 ch->flags |= ATA_NO_SLAVE;
5516 /* XXX SOS PHY hotplug handling missing in VIA chip ?? */
5517 /* XXX SOS unknown how to enable PHY state change interrupt */
5522 ata_via_reset(device_t dev)
5524 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5525 struct ata_channel *ch = device_get_softc(dev);
5527 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1))
5528 ata_generic_reset(dev);
5530 if (ata_sata_phy_reset(dev))
5531 ata_generic_reset(dev);
5535 ata_via_setmode(device_t dev, int mode)
5537 device_t gparent = GRANDPARENT(dev);
5538 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5539 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5540 struct ata_device *atadev = device_get_softc(dev);
5543 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) {
5544 u_int8_t pio_timings[] = { 0xa8, 0x65, 0x65, 0x32, 0x20,
5546 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
5547 u_int8_t dma_timings[] = { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 };
5549 mode = ata_check_80pin(dev, ata_limit_mode(dev, mode, ATA_UDMA6));
5550 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5552 device_printf(dev, "%ssetting %s on %s chip\n",
5553 (error) ? "FAILURE " : "", ata_mode2str(mode),
5556 pci_write_config(gparent, 0xab, pio_timings[ata_mode2idx(mode)], 1);
5557 if (mode >= ATA_UDMA0)
5558 pci_write_config(gparent, 0xb3,
5559 dma_timings[mode & ATA_MODE_MASK], 1);
5560 atadev->mode = mode;
5564 ata_sata_setmode(dev, mode);
5568 ata_via_southbridge_fixup(device_t dev)
5573 if (device_get_children(device_get_parent(dev), &children, &nchildren))
5576 for (i = 0; i < nchildren; i++) {
5577 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
5578 pci_get_devid(children[i]) == ATA_VIA8371 ||
5579 pci_get_devid(children[i]) == ATA_VIA8662 ||
5580 pci_get_devid(children[i]) == ATA_VIA8361) {
5581 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
5583 if ((reg76 & 0xf0) != 0xd0) {
5585 "Correcting VIA config for southbridge data corruption bug\n");
5586 pci_write_config(children[i], 0x75, 0x80, 1);
5587 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
5592 kfree(children, M_TEMP);
5596 /* common code for VIA, AMD & nVidia */
5598 ata_via_family_setmode(device_t dev, int mode)
5600 device_t gparent = GRANDPARENT(dev);
5601 struct ata_pci_controller *ctlr = device_get_softc(gparent);
5602 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5603 struct ata_device *atadev = device_get_softc(dev);
5604 u_int8_t timings[] = { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
5605 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
5607 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
5608 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
5609 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
5610 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
5611 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
5612 int devno = (ch->unit << 1) + ATA_DEV(atadev->unit);
5613 int reg = 0x53 - devno;
5616 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
5618 if (ctlr->chip->cfg2 & AMDCABLE) {
5619 if (mode > ATA_UDMA2 &&
5620 !(pci_read_config(gparent, 0x42, 1) & (1 << devno))) {
5621 ata_print_cable(dev, "controller");
5626 mode = ata_check_80pin(dev, mode);
5628 if (ctlr->chip->cfg2 & NVIDIA)
5631 if (ctlr->chip->cfg1 != VIA133)
5632 pci_write_config(gparent, reg - 0x08, timings[ata_mode2idx(mode)], 1);
5634 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
5637 device_printf(dev, "%ssetting %s on %s chip\n",
5638 (error) ? "FAILURE " : "", ata_mode2str(mode),
5641 if (mode >= ATA_UDMA0)
5642 pci_write_config(gparent, reg,
5643 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
5645 pci_write_config(gparent, reg, 0x8b, 1);
5646 atadev->mode = mode;
5651 /* misc functions */
5652 static struct ata_chip_id *
5653 ata_match_chip(device_t dev, struct ata_chip_id *index)
5655 while (index->chipid != 0) {
5656 if (pci_get_devid(dev) == index->chipid &&
5657 pci_get_revid(dev) >= index->chiprev)
5664 static struct ata_chip_id *
5665 ata_find_chip(device_t dev, struct ata_chip_id *index, int slot)
5670 if (device_get_children(device_get_parent(dev), &children, &nchildren))
5673 while (index->chipid != 0) {
5674 for (i = 0; i < nchildren; i++) {
5675 if (((slot >= 0 && pci_get_slot(children[i]) == slot) ||
5676 (slot < 0 && pci_get_slot(children[i]) <= -slot)) &&
5677 pci_get_devid(children[i]) == index->chipid &&
5678 pci_get_revid(children[i]) >= index->chiprev) {
5679 kfree(children, M_TEMP);
5685 kfree(children, M_TEMP);
5690 ata_setup_interrupt(device_t dev)
5692 struct ata_pci_controller *ctlr = device_get_softc(dev);
5693 int rid = ATA_IRQ_RID;
5695 if (!ata_legacy(dev)) {
5696 if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
5697 RF_SHAREABLE | RF_ACTIVE))) {
5698 device_printf(dev, "unable to map interrupt\n");
5701 if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
5702 ata_generic_intr, ctlr, &ctlr->handle, NULL))) {
5703 device_printf(dev, "unable to setup interrupt\n");
5710 struct ata_serialize {
5711 struct spinlock locked_mtx;
5717 ata_serialize(device_t dev, int flags)
5719 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
5720 struct ata_channel *ch = device_get_softc(dev);
5721 struct ata_serialize *serial;
5722 static int inited = 0;
5726 serial = kmalloc(sizeof(struct ata_serialize),
5727 M_TEMP, M_INTWAIT | M_ZERO);
5728 spin_init(&serial->locked_mtx);
5729 serial->locked_ch = -1;
5730 serial->restart_ch = -1;
5731 device_set_ivars(ctlr->dev, serial);
5735 serial = device_get_ivars(ctlr->dev);
5737 spin_lock_wr(&serial->locked_mtx);
5740 if (serial->locked_ch == -1)
5741 serial->locked_ch = ch->unit;
5742 if (serial->locked_ch != ch->unit)
5743 serial->restart_ch = ch->unit;
5747 if (serial->locked_ch == ch->unit) {
5748 serial->locked_ch = -1;
5749 if (serial->restart_ch != -1) {
5750 if ((ch = ctlr->interrupt[serial->restart_ch].argument)) {
5751 serial->restart_ch = -1;
5752 spin_unlock_wr(&serial->locked_mtx);
5763 res = serial->locked_ch;
5764 spin_unlock_wr(&serial->locked_mtx);
5769 ata_print_cable(device_t dev, u_int8_t *who)
5772 "DMA limited to UDMA33, %s found non-ATA66 cable\n", who);
5776 ata_atapi(device_t dev)
5778 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
5779 struct ata_device *atadev = device_get_softc(dev);
5781 return ((atadev->unit == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) ||
5782 (atadev->unit == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE));
5786 ata_check_80pin(device_t dev, int mode)
5788 struct ata_device *atadev = device_get_softc(dev);
5790 if (mode > ATA_UDMA2 && !(atadev->param.hwres & ATA_CABLE_ID)) {
5791 ata_print_cable(dev, "device");
5798 ata_mode2idx(int mode)
5800 if ((mode & ATA_DMA_MASK) == ATA_UDMA0)
5801 return (mode & ATA_MODE_MASK) + 8;
5802 if ((mode & ATA_DMA_MASK) == ATA_WDMA0)
5803 return (mode & ATA_MODE_MASK) + 5;
5804 return (mode & ATA_MODE_MASK) - ATA_PIO0;