2 * Copyright (c) 1998 - 2006 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/dev/ata/ata-lowlevel.c,v 1.77 2006/07/04 20:36:03 sos Exp $
27 * $DragonFly: src/sys/dev/disk/nata/ata-lowlevel.c,v 1.2 2006/12/22 23:26:16 swildner Exp $
32 #include <sys/param.h>
34 #include <sys/callout.h>
35 #include <sys/libkern.h>
37 #include <sys/systm.h>
43 static int ata_generic_status(device_t dev);
44 static int ata_wait(struct ata_channel *ch, struct ata_device *, u_int8_t);
45 static void ata_pio_read(struct ata_request *, int);
46 static void ata_pio_write(struct ata_request *, int);
49 * low level ATA functions
52 ata_generic_hw(device_t dev)
54 struct ata_channel *ch = device_get_softc(dev);
56 ch->hw.begin_transaction = ata_begin_transaction;
57 ch->hw.end_transaction = ata_end_transaction;
58 ch->hw.status = ata_generic_status;
59 ch->hw.command = ata_generic_command;
62 /* must be called with ATA channel locked and state_mtx held */
64 ata_begin_transaction(struct ata_request *request)
66 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
67 struct ata_device *atadev = device_get_softc(request->dev);
70 ATA_DEBUG_RQ(request, "begin transaction");
72 /* disable ATAPI DMA writes if HW doesn't support it */
73 if ((ch->flags & ATA_ATAPI_DMA_RO) &&
74 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) ==
75 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)))
76 request->flags &= ~ATA_R_DMA;
78 /* check for 48 bit access and convert if needed */
79 ata_modify_if_48bit(request);
81 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) {
83 /* ATA PIO data transfer and control commands */
86 /* record command direction here as our request might be gone later */
87 int write = (request->flags & ATA_R_WRITE);
90 if (ch->hw.command(request)) {
91 device_printf(request->dev, "error issuing %s command\n",
92 ata_cmd2str(request));
93 request->result = EIO;
97 /* device reset doesn't interrupt */
98 if (request->u.ata.command == ATA_DEVICE_RESET) {
99 int timeout = 1000000;
102 request->status = ATA_IDX_INB(ch, ATA_STATUS);
103 } while (request->status & ATA_S_BUSY && timeout--);
104 if (request->status & ATA_S_ERROR)
105 request->error = ATA_IDX_INB(ch, ATA_ERROR);
109 /* if write command output the data */
111 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) {
112 device_printf(request->dev,
113 "timeout waiting for write DRQ\n");
114 request->result = EIO;
117 ata_pio_write(request, request->transfersize);
122 /* ATA DMA data transfer commands */
124 /* check sanity, setup SG list and DMA engine */
125 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
126 request->flags & ATA_R_READ, ch->dma->sg,
128 device_printf(request->dev, "setting up DMA failed\n");
129 request->result = error;
134 if (ch->hw.command(request)) {
135 device_printf(request->dev, "error issuing %s command\n",
136 ata_cmd2str(request));
137 request->result = EIO;
141 /* start DMA engine */
142 if (ch->dma->start && ch->dma->start(request->dev)) {
143 device_printf(request->dev, "error starting DMA\n");
144 request->result = EIO;
149 /* ATAPI PIO commands */
151 /* is this just a POLL DSC command ? */
152 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
153 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit);
155 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
156 request->result = EBUSY;
160 /* start ATAPI operation */
161 if (ch->hw.command(request)) {
162 device_printf(request->dev, "error issuing ATA PACKET command\n");
163 request->result = EIO;
168 /* ATAPI DMA commands */
169 case ATA_R_ATAPI|ATA_R_DMA:
170 /* is this just a POLL DSC command ? */
171 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
172 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit);
174 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
175 request->result = EBUSY;
179 /* check sanity, setup SG list and DMA engine */
180 if ((error = ch->dma->load(ch->dev, request->data, request->bytecount,
181 request->flags & ATA_R_READ, ch->dma->sg,
183 device_printf(request->dev, "setting up DMA failed\n");
184 request->result = error;
188 /* start ATAPI operation */
189 if (ch->hw.command(request)) {
190 device_printf(request->dev, "error issuing ATA PACKET command\n");
191 request->result = EIO;
195 /* start DMA engine */
196 if (ch->dma->start && ch->dma->start(request->dev)) {
197 request->result = EIO;
203 kprintf("ata_begin_transaction OOPS!!!\n");
206 if (ch->dma && ch->dma->flags & ATA_DMA_LOADED)
207 ch->dma->unload(ch->dev);
208 return ATA_OP_FINISHED;
211 /* caller holds ch->state_mtx */
212 callout_reset(&request->callout, request->timeout * hz,
213 (timeout_t*)ata_timeout, request);
214 return ATA_OP_CONTINUES;
217 /* must be called with ATA channel locked and state_mtx held */
219 ata_end_transaction(struct ata_request *request)
221 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
222 struct ata_device *atadev = device_get_softc(request->dev);
225 ATA_DEBUG_RQ(request, "end transaction");
227 /* clear interrupt and get status */
228 request->status = ATA_IDX_INB(ch, ATA_STATUS);
230 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) {
232 /* ATA PIO data transfer and control commands */
235 /* on timeouts we have no data or anything so just return */
236 if (request->flags & ATA_R_TIMEOUT)
239 /* on control commands read back registers to the request struct */
240 if (request->flags & ATA_R_CONTROL) {
241 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
242 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB);
243 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8);
245 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) |
246 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) |
247 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40);
249 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
250 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT);
251 request->u.ata.lba |=
252 (ATA_IDX_INB(ch, ATA_SECTOR) |
253 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
254 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16));
257 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT);
258 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) |
259 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
260 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) |
261 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24);
265 /* if we got an error we are done with the HW */
266 if (request->status & ATA_S_ERROR) {
267 request->error = ATA_IDX_INB(ch, ATA_ERROR);
271 /* are we moving data ? */
272 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
274 /* if read data get it */
275 if (request->flags & ATA_R_READ) {
276 int flags = ATA_S_DRQ;
278 if (request->u.ata.command != ATA_ATAPI_IDENTIFY)
279 flags |= ATA_S_READY;
280 if (ata_wait(ch, atadev, flags) < 0) {
281 device_printf(request->dev,
282 "timeout waiting for read DRQ\n");
283 request->result = EIO;
286 ata_pio_read(request, request->transfersize);
289 /* update how far we've gotten */
290 request->donecount += request->transfersize;
292 /* do we need a scoop more ? */
293 if (request->bytecount > request->donecount) {
295 /* set this transfer size according to HW capabilities */
296 request->transfersize =
297 min((request->bytecount - request->donecount),
298 request->transfersize);
300 /* if data write command, output the data */
301 if (request->flags & ATA_R_WRITE) {
303 /* if we get an error here we are done with the HW */
304 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) {
305 device_printf(request->dev,
306 "timeout waiting for write DRQ\n");
307 request->status = ATA_IDX_INB(ch, ATA_STATUS);
311 /* output data and return waiting for new interrupt */
312 ata_pio_write(request, request->transfersize);
316 /* if data read command, return & wait for interrupt */
317 if (request->flags & ATA_R_READ)
324 /* ATA DMA data transfer commands */
327 /* stop DMA engine and get status */
329 request->dmastat = ch->dma->stop(request->dev);
331 /* did we get error or data */
332 if (request->status & ATA_S_ERROR)
333 request->error = ATA_IDX_INB(ch, ATA_ERROR);
334 else if (request->dmastat & ATA_BMSTAT_ERROR)
335 request->status |= ATA_S_ERROR;
336 else if (!(request->flags & ATA_R_TIMEOUT))
337 request->donecount = request->bytecount;
339 /* release SG list etc */
340 ch->dma->unload(ch->dev);
345 /* ATAPI PIO commands */
347 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8);
349 /* on timeouts we have no data or anything so just return */
350 if (request->flags & ATA_R_TIMEOUT)
353 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) |
354 (request->status & ATA_S_DRQ)) {
357 /* this seems to be needed for some (slow) devices */
360 if (!(request->status & ATA_S_DRQ)) {
361 device_printf(request->dev, "command interrupt without DRQ\n");
362 request->status = ATA_S_ERROR;
365 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
366 (atadev->param.config &
367 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8);
368 /* return wait for interrupt */
372 if (request->flags & ATA_R_READ) {
373 request->status = ATA_S_ERROR;
374 device_printf(request->dev,
375 "%s trying to write on read buffer\n",
376 ata_cmd2str(request));
380 ata_pio_write(request, length);
381 request->donecount += length;
383 /* set next transfer size according to HW capabilities */
384 request->transfersize = min((request->bytecount-request->donecount),
385 request->transfersize);
386 /* return wait for interrupt */
390 if (request->flags & ATA_R_WRITE) {
391 request->status = ATA_S_ERROR;
392 device_printf(request->dev,
393 "%s trying to read on write buffer\n",
394 ata_cmd2str(request));
397 ata_pio_read(request, length);
398 request->donecount += length;
400 /* set next transfer size according to HW capabilities */
401 request->transfersize = min((request->bytecount-request->donecount),
402 request->transfersize);
403 /* return wait for interrupt */
406 case ATAPI_P_DONEDRQ:
407 device_printf(request->dev,
408 "WARNING - %s DONEDRQ non conformant device\n",
409 ata_cmd2str(request));
410 if (request->flags & ATA_R_READ) {
411 ata_pio_read(request, length);
412 request->donecount += length;
414 else if (request->flags & ATA_R_WRITE) {
415 ata_pio_write(request, length);
416 request->donecount += length;
419 request->status = ATA_S_ERROR;
424 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
425 request->error = ATA_IDX_INB(ch, ATA_ERROR);
429 device_printf(request->dev, "unknown transfer phase\n");
430 request->status = ATA_S_ERROR;
436 /* ATAPI DMA commands */
437 case ATA_R_ATAPI|ATA_R_DMA:
439 /* stop DMA engine and get status */
441 request->dmastat = ch->dma->stop(request->dev);
443 /* did we get error or data */
444 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
445 request->error = ATA_IDX_INB(ch, ATA_ERROR);
446 else if (request->dmastat & ATA_BMSTAT_ERROR)
447 request->status |= ATA_S_ERROR;
448 else if (!(request->flags & ATA_R_TIMEOUT))
449 request->donecount = request->bytecount;
451 /* release SG list etc */
452 ch->dma->unload(ch->dev);
458 kprintf("ata_end_transaction OOPS!!\n");
461 callout_stop(&request->callout);
462 return ATA_OP_FINISHED;
465 return ATA_OP_CONTINUES;
468 /* must be called with ATA channel locked and state_mtx held */
470 ata_generic_reset(device_t dev)
472 struct ata_channel *ch = device_get_softc(dev);
474 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0;
475 u_int8_t err = 0, lsb = 0, msb = 0;
476 int mask = 0, timeout;
478 /* do we have any signs of ATA/ATAPI HW being present ? */
479 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER);
481 ostat0 = ATA_IDX_INB(ch, ATA_STATUS);
482 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) {
487 /* in some setups we dont want to test for a slave */
488 if (!(ch->flags & ATA_NO_SLAVE)) {
489 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_SLAVE);
491 ostat1 = ATA_IDX_INB(ch, ATA_STATUS);
492 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) {
499 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n",
500 mask, ostat0, ostat1);
502 /* if nothing showed up there is no need to get any further */
503 /* XXX SOS is that too strong?, we just might loose devices here */
508 /* reset (both) devices on this channel */
509 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_MASTER);
511 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET);
513 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS);
515 ATA_IDX_INB(ch, ATA_ERROR);
517 /* wait for BUSY to go inactive */
518 for (timeout = 0; timeout < 310; timeout++) {
519 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) {
520 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER);
522 err = ATA_IDX_INB(ch, ATA_ERROR);
523 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
524 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
525 stat0 = ATA_IDX_INB(ch, ATA_STATUS);
528 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
529 stat0, err, lsb, msb);
530 if (stat0 == err && lsb == err && msb == err &&
531 timeout > (stat0 & ATA_S_BUSY ? 100 : 10))
533 if (!(stat0 & ATA_S_BUSY)) {
534 if ((err & 0x7f) == ATA_E_ILI) {
535 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
536 ch->devices |= ATA_ATAPI_MASTER;
538 else if (stat0 & ATA_S_READY) {
539 ch->devices |= ATA_ATA_MASTER;
542 else if ((stat0 & 0x0f) && err == lsb && err == msb) {
548 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) &&
549 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) {
550 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE);
552 err = ATA_IDX_INB(ch, ATA_ERROR);
553 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
554 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
555 stat1 = ATA_IDX_INB(ch, ATA_STATUS);
558 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
559 stat1, err, lsb, msb);
560 if (stat1 == err && lsb == err && msb == err &&
561 timeout > (stat1 & ATA_S_BUSY ? 100 : 10))
563 if (!(stat1 & ATA_S_BUSY)) {
564 if ((err & 0x7f) == ATA_E_ILI) {
565 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
566 ch->devices |= ATA_ATAPI_SLAVE;
568 else if (stat1 & ATA_S_READY) {
569 ch->devices |= ATA_ATA_SLAVE;
572 else if ((stat1 & 0x0f) && err == lsb && err == msb) {
578 if (mask == 0x00) /* nothing to wait for */
580 if (mask == 0x01) /* wait for master only */
581 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10))
583 if (mask == 0x02) /* wait for slave only */
584 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 10))
586 if (mask == 0x03) { /* wait for both master & slave */
587 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY))
589 if ((stat0 == 0xff) && (timeout > 20))
591 if ((stat1 == 0xff) && (timeout > 20))
598 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%b\n",
599 stat0, stat1, ch->devices,
600 "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER");
603 /* must be called with ATA channel locked and state_mtx held */
605 ata_generic_status(device_t dev)
607 struct ata_channel *ch = device_get_softc(dev);
609 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
611 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
618 ata_wait(struct ata_channel *ch, struct ata_device *atadev, u_int8_t mask)
625 /* wait at max 1 second for device to get !BUSY */
626 while (timeout < 1000000) {
627 status = ATA_IDX_INB(ch, ATA_ALTSTAT);
629 /* if drive fails status, reselect the drive and try again */
630 if (status == 0xff) {
631 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit);
638 if (!(status & ATA_S_BUSY))
641 if (timeout > 1000) {
650 if (timeout >= 1000000)
653 return (status & ATA_S_ERROR);
657 /* wait 50 msec for bits wanted */
660 status = ATA_IDX_INB(ch, ATA_ALTSTAT);
661 if ((status & mask) == mask)
662 return (status & ATA_S_ERROR);
669 ata_generic_command(struct ata_request *request)
671 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
672 struct ata_device *atadev = device_get_softc(request->dev);
675 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit);
677 /* ready to issue command ? */
678 if (ata_wait(ch, atadev, 0) < 0) {
679 device_printf(request->dev, "timeout waiting to issue command\n");
683 /* enable interrupt */
684 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
686 if (request->flags & ATA_R_ATAPI) {
689 /* issue packet command to controller */
690 if (request->flags & ATA_R_DMA) {
691 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA);
692 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0);
693 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0);
696 ATA_IDX_OUTB(ch, ATA_FEATURE, 0);
697 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize);
698 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8);
700 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD);
702 /* command interrupt device ? just return and wait for interrupt */
703 if ((atadev->param.config & ATA_DRQ_MASK) == ATA_DRQ_INTR)
706 /* wait for ready to write ATAPI command block */
708 int reason = ATA_IDX_INB(ch, ATA_IREASON);
709 int status = ATA_IDX_INB(ch, ATA_STATUS);
711 if (((reason & (ATA_I_CMD | ATA_I_IN)) |
712 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
717 device_printf(request->dev, "timeout waiting for ATAPI ready\n");
718 request->result = EIO;
722 /* this seems to be needed for some (slow) devices */
725 /* output command block */
726 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
727 (atadev->param.config & ATA_PROTO_MASK) ==
728 ATA_PROTO_ATAPI_12 ? 6 : 8);
731 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
732 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8);
733 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
734 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8);
735 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
736 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24);
737 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
738 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32);
739 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
740 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40);
741 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
742 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | atadev->unit);
745 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
746 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
747 if (atadev->flags & ATA_D_USE_CHS) {
750 if (atadev->param.atavalid & ATA_FLAG_54_58) {
751 heads = atadev->param.current_heads;
752 sectors = atadev->param.current_sectors;
755 heads = atadev->param.heads;
756 sectors = atadev->param.sectors;
758 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
759 ATA_IDX_OUTB(ch, ATA_CYL_LSB,
760 (request->u.ata.lba / (sectors * heads)));
761 ATA_IDX_OUTB(ch, ATA_CYL_MSB,
762 (request->u.ata.lba / (sectors * heads)) >> 8);
763 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | atadev->unit |
764 (((request->u.ata.lba% (sectors * heads)) /
768 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
769 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
770 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
771 ATA_IDX_OUTB(ch, ATA_DRIVE,
772 ATA_D_IBM | ATA_D_LBA | atadev->unit |
773 ((request->u.ata.lba >> 24) & 0x0f));
777 /* issue command to controller */
778 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
785 ata_pio_read(struct ata_request *request, int length)
787 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
788 int size = min(request->transfersize, length);
791 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
792 ATA_IDX_INSW_STRM(ch, ATA_DATA,
793 (void*)((uintptr_t)request->data+request->donecount),
794 size / sizeof(int16_t));
796 ATA_IDX_INSL_STRM(ch, ATA_DATA,
797 (void*)((uintptr_t)request->data+request->donecount),
798 size / sizeof(int32_t));
800 if (request->transfersize < length) {
801 device_printf(request->dev, "WARNING - %s read data overrun %d>%d\n",
802 ata_cmd2str(request), length, request->transfersize);
803 for (resid = request->transfersize; resid < length;
804 resid += sizeof(int16_t))
805 ATA_IDX_INW(ch, ATA_DATA);
810 ata_pio_write(struct ata_request *request, int length)
812 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
813 int size = min(request->transfersize, length);
816 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
817 ATA_IDX_OUTSW_STRM(ch, ATA_DATA,
818 (void*)((uintptr_t)request->data+request->donecount),
819 size / sizeof(int16_t));
821 ATA_IDX_OUTSL_STRM(ch, ATA_DATA,
822 (void*)((uintptr_t)request->data+request->donecount),
823 size / sizeof(int32_t));
825 if (request->transfersize < length) {
826 device_printf(request->dev, "WARNING - %s write data underrun %d>%d\n",
827 ata_cmd2str(request), length, request->transfersize);
828 for (resid = request->transfersize; resid < length;
829 resid += sizeof(int16_t))
830 ATA_IDX_OUTW(ch, ATA_DATA, 0);