2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
31 #include <linux/seq_file.h>
32 #include <linux/atomic.h>
33 #include <linux/wait.h>
34 #include <linux/kref.h>
35 #include <linux/firmware.h>
37 #include "radeon_reg.h"
39 #include "radeon_trace.h"
43 * Fences mark an event in the GPUs pipeline and are used
44 * for GPU/CPU synchronization. When the fence is written,
45 * it is expected that all buffers associated with that fence
46 * are no longer in use by the associated ring on the GPU and
47 * that the the relevant GPU caches have been flushed. Whether
48 * we use a scratch register or memory location depends on the asic
49 * and whether writeback is enabled.
53 * radeon_fence_write - write a fence value
55 * @rdev: radeon_device pointer
56 * @seq: sequence number to write
57 * @ring: ring index the fence is associated with
59 * Writes a fence value to memory or a scratch register (all asics).
61 static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
63 struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
64 if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
66 *drv->cpu_addr = cpu_to_le32(seq);
69 WREG32(drv->scratch_reg, seq);
74 * radeon_fence_read - read a fence value
76 * @rdev: radeon_device pointer
77 * @ring: ring index the fence is associated with
79 * Reads a fence value from memory or a scratch register (all asics).
80 * Returns the value of the fence read from memory or register.
82 static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
84 struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
87 if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
89 seq = le32_to_cpu(*drv->cpu_addr);
91 seq = lower_32_bits(atomic64_read(&drv->last_seq));
94 seq = RREG32(drv->scratch_reg);
100 * radeon_fence_schedule_check - schedule lockup check
102 * @rdev: radeon_device pointer
103 * @ring: ring index we should work with
105 * Queues a delayed work item to check for lockups.
107 static void radeon_fence_schedule_check(struct radeon_device *rdev, int ring)
110 * Do not reset the timer here with mod_delayed_work,
111 * this can livelock in an interaction with TTM delayed destroy.
113 queue_delayed_work(system_power_efficient_wq,
114 &rdev->fence_drv[ring].lockup_work,
115 RADEON_FENCE_JIFFIES_TIMEOUT);
119 * radeon_fence_emit - emit a fence on the requested ring
121 * @rdev: radeon_device pointer
122 * @fence: radeon fence object
123 * @ring: ring index the fence is associated with
125 * Emits a fence command on the requested ring (all asics).
126 * Returns 0 on success, -ENOMEM on failure.
128 int radeon_fence_emit(struct radeon_device *rdev,
129 struct radeon_fence **fence,
134 /* we are protected by the ring emission mutex */
135 *fence = kmalloc(sizeof(struct radeon_fence), M_DRM, M_WAITOK);
136 if ((*fence) == NULL) {
139 (*fence)->rdev = rdev;
140 (*fence)->seq = seq = ++rdev->fence_drv[ring].sync_seq[ring];
141 (*fence)->ring = ring;
142 (*fence)->is_vm_update = false;
143 fence_init(&(*fence)->base, &radeon_fence_ops,
144 &rdev->fence_queue.lock, rdev->fence_context + ring, seq);
145 radeon_fence_ring_emit(rdev, ring, *fence);
146 trace_radeon_fence_emit(rdev->ddev, ring, (*fence)->seq);
147 radeon_fence_schedule_check(rdev, ring);
152 * radeon_fence_check_signaled - callback from fence_queue
154 * this function is called with fence_queue lock held, which is also used
155 * for the fence locking itself, so unlocked variants are used for
156 * fence_signal, and remove_wait_queue.
158 static int radeon_fence_check_signaled(wait_queue_t *wait, unsigned mode, int flags, void *key)
160 struct radeon_fence *fence;
163 fence = container_of(wait, struct radeon_fence, fence_wake);
166 * We cannot use radeon_fence_process here because we're already
167 * in the waitqueue, in a call from wake_up_all.
169 seq = atomic64_read(&fence->rdev->fence_drv[fence->ring].last_seq);
170 if (seq >= fence->seq) {
171 int ret = fence_signal_locked(&fence->base);
174 FENCE_TRACE(&fence->base, "signaled from irq context\n");
176 FENCE_TRACE(&fence->base, "was already signaled\n");
178 radeon_irq_kms_sw_irq_put(fence->rdev, fence->ring);
179 __remove_wait_queue(&fence->rdev->fence_queue, &fence->fence_wake);
180 fence_put(&fence->base);
182 FENCE_TRACE(&fence->base, "pending\n");
187 * radeon_fence_activity - check for fence activity
189 * @rdev: radeon_device pointer
190 * @ring: ring index the fence is associated with
192 * Checks the current fence value and calculates the last
193 * signalled fence value. Returns true if activity occured
194 * on the ring, and the fence_queue should be waken up.
196 static bool radeon_fence_activity(struct radeon_device *rdev, int ring)
198 uint64_t seq, last_seq, last_emitted;
199 unsigned count_loop = 0;
202 /* Note there is a scenario here for an infinite loop but it's
203 * very unlikely to happen. For it to happen, the current polling
204 * process need to be interrupted by another process and another
205 * process needs to update the last_seq btw the atomic read and
206 * xchg of the current process.
208 * More over for this to go in infinite loop there need to be
209 * continuously new fence signaled ie radeon_fence_read needs
210 * to return a different value each time for both the currently
211 * polling process and the other process that xchg the last_seq
212 * btw atomic read and xchg of the current process. And the
213 * value the other process set as last seq must be higher than
214 * the seq value we just read. Which means that current process
215 * need to be interrupted after radeon_fence_read and before
218 * To be even more safe we count the number of time we loop and
219 * we bail after 10 loop just accepting the fact that we might
220 * have temporarly set the last_seq not to the true real last
221 * seq but to an older one.
223 last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
225 last_emitted = rdev->fence_drv[ring].sync_seq[ring];
226 seq = radeon_fence_read(rdev, ring);
227 seq |= last_seq & 0xffffffff00000000LL;
228 if (seq < last_seq) {
230 seq |= last_emitted & 0xffffffff00000000LL;
233 if (seq <= last_seq || seq > last_emitted) {
236 /* If we loop over we don't want to return without
237 * checking if a fence is signaled as it means that the
238 * seq we just read is different from the previous on.
242 if ((count_loop++) > 10) {
243 /* We looped over too many time leave with the
244 * fact that we might have set an older fence
245 * seq then the current real last seq as signaled
250 } while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq);
252 if (seq < last_emitted)
253 radeon_fence_schedule_check(rdev, ring);
259 * radeon_fence_check_lockup - check for hardware lockup
261 * @work: delayed work item
263 * Checks for fence activity and if there is none probe
264 * the hardware if a lockup occured.
266 static void radeon_fence_check_lockup(struct work_struct *work)
268 struct radeon_fence_driver *fence_drv;
269 struct radeon_device *rdev;
272 fence_drv = container_of(work, struct radeon_fence_driver,
274 rdev = fence_drv->rdev;
275 ring = fence_drv - &rdev->fence_drv[0];
277 if (!down_read_trylock(&rdev->exclusive_lock)) {
278 /* just reschedule the check if a reset is going on */
279 radeon_fence_schedule_check(rdev, ring);
283 if (fence_drv->delayed_irq && rdev->ddev->irq_enabled) {
284 unsigned long irqflags;
286 fence_drv->delayed_irq = false;
287 spin_lock_irqsave(&rdev->irq.lock, irqflags);
288 radeon_irq_set(rdev);
289 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
292 if (radeon_fence_activity(rdev, ring))
293 wake_up_all(&rdev->fence_queue);
295 else if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
297 /* good news we believe it's a lockup */
298 dev_warn(rdev->dev, "GPU lockup (current fence id "
299 "0x%016lx last fence id 0x%016lx on ring %d)\n",
300 (uint64_t)atomic64_read(&fence_drv->last_seq),
301 fence_drv->sync_seq[ring], ring);
303 /* remember that we need an reset */
304 rdev->needs_reset = true;
305 wake_up_all(&rdev->fence_queue);
307 up_read(&rdev->exclusive_lock);
311 * radeon_fence_process - process a fence
313 * @rdev: radeon_device pointer
314 * @ring: ring index the fence is associated with
316 * Checks the current fence value and wakes the fence queue
317 * if the sequence number has increased (all asics).
319 void radeon_fence_process(struct radeon_device *rdev, int ring)
321 if (radeon_fence_activity(rdev, ring))
322 wake_up_all(&rdev->fence_queue);
326 * radeon_fence_seq_signaled - check if a fence sequence number has signaled
328 * @rdev: radeon device pointer
329 * @seq: sequence number
330 * @ring: ring index the fence is associated with
332 * Check if the last signaled fence sequnce number is >= the requested
333 * sequence number (all asics).
334 * Returns true if the fence has signaled (current fence value
335 * is >= requested value) or false if it has not (current fence
336 * value is < the requested value. Helper function for
337 * radeon_fence_signaled().
339 static bool radeon_fence_seq_signaled(struct radeon_device *rdev,
340 u64 seq, unsigned ring)
342 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
345 /* poll new last sequence at least once */
346 radeon_fence_process(rdev, ring);
347 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
353 static bool radeon_fence_is_signaled(struct fence *f)
355 struct radeon_fence *fence = to_radeon_fence(f);
356 struct radeon_device *rdev = fence->rdev;
357 unsigned ring = fence->ring;
358 u64 seq = fence->seq;
360 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
364 if (down_read_trylock(&rdev->exclusive_lock)) {
365 radeon_fence_process(rdev, ring);
366 up_read(&rdev->exclusive_lock);
368 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
376 * radeon_fence_enable_signaling - enable signalling on fence
379 * This function is called with fence_queue lock held, and adds a callback
380 * to fence_queue that checks if this fence is signaled, and if so it
381 * signals the fence and removes itself.
383 static bool radeon_fence_enable_signaling(struct fence *f)
385 struct radeon_fence *fence = to_radeon_fence(f);
386 struct radeon_device *rdev = fence->rdev;
388 if (atomic64_read(&rdev->fence_drv[fence->ring].last_seq) >= fence->seq)
391 if (down_read_trylock(&rdev->exclusive_lock)) {
392 radeon_irq_kms_sw_irq_get(rdev, fence->ring);
394 if (radeon_fence_activity(rdev, fence->ring))
395 wake_up_all_locked(&rdev->fence_queue);
397 /* did fence get signaled after we enabled the sw irq? */
398 if (atomic64_read(&rdev->fence_drv[fence->ring].last_seq) >= fence->seq) {
399 radeon_irq_kms_sw_irq_put(rdev, fence->ring);
400 up_read(&rdev->exclusive_lock);
404 up_read(&rdev->exclusive_lock);
406 /* we're probably in a lockup, lets not fiddle too much */
407 if (radeon_irq_kms_sw_irq_get_delayed(rdev, fence->ring))
408 rdev->fence_drv[fence->ring].delayed_irq = true;
409 radeon_fence_schedule_check(rdev, fence->ring);
412 fence->fence_wake.flags = 0;
413 fence->fence_wake.private = NULL;
414 fence->fence_wake.func = radeon_fence_check_signaled;
415 __add_wait_queue(&rdev->fence_queue, &fence->fence_wake);
418 FENCE_TRACE(&fence->base, "armed on ring %i!\n", fence->ring);
423 * radeon_fence_signaled - check if a fence has signaled
425 * @fence: radeon fence object
427 * Check if the requested fence has signaled (all asics).
428 * Returns true if the fence has signaled or false if it has not.
430 bool radeon_fence_signaled(struct radeon_fence *fence)
435 if (radeon_fence_seq_signaled(fence->rdev, fence->seq, fence->ring)) {
438 ret = fence_signal(&fence->base);
440 FENCE_TRACE(&fence->base, "signaled from radeon_fence_signaled\n");
447 * radeon_fence_any_seq_signaled - check if any sequence number is signaled
449 * @rdev: radeon device pointer
450 * @seq: sequence numbers
452 * Check if the last signaled fence sequnce number is >= the requested
453 * sequence number (all asics).
454 * Returns true if any has signaled (current value is >= requested value)
455 * or false if it has not. Helper function for radeon_fence_wait_seq.
457 static bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)
461 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
462 if (seq[i] && radeon_fence_seq_signaled(rdev, seq[i], i))
469 * radeon_fence_wait_seq_timeout - wait for a specific sequence numbers
471 * @rdev: radeon device pointer
472 * @target_seq: sequence number(s) we want to wait for
473 * @intr: use interruptable sleep
474 * @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait
476 * Wait for the requested sequence number(s) to be written by any ring
477 * (all asics). Sequnce number array is indexed by ring id.
478 * @intr selects whether to use interruptable (true) or non-interruptable
479 * (false) sleep when waiting for the sequence number. Helper function
480 * for radeon_fence_wait_*().
481 * Returns remaining time if the sequence number has passed, 0 when
482 * the wait timeout, or an error for all other cases.
483 * -EDEADLK is returned when a GPU lockup has been detected.
485 static long radeon_fence_wait_seq_timeout(struct radeon_device *rdev,
486 u64 *target_seq, bool intr,
492 if (radeon_fence_any_seq_signaled(rdev, target_seq))
495 /* enable IRQs and tracing */
496 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
500 trace_radeon_fence_wait_begin(rdev->ddev, i, target_seq[i]);
501 radeon_irq_kms_sw_irq_get(rdev, i);
505 r = wait_event_interruptible_timeout(rdev->fence_queue, (
506 radeon_fence_any_seq_signaled(rdev, target_seq)
507 || rdev->needs_reset), timeout);
509 r = wait_event_timeout(rdev->fence_queue, (
510 radeon_fence_any_seq_signaled(rdev, target_seq)
511 || rdev->needs_reset), timeout);
514 if (rdev->needs_reset)
517 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
521 radeon_irq_kms_sw_irq_put(rdev, i);
522 trace_radeon_fence_wait_end(rdev->ddev, i, target_seq[i]);
529 * radeon_fence_wait_timeout - wait for a fence to signal with timeout
531 * @fence: radeon fence object
532 * @intr: use interruptible sleep
534 * Wait for the requested fence to signal (all asics).
535 * @intr selects whether to use interruptable (true) or non-interruptable
536 * (false) sleep when waiting for the fence.
537 * @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait
538 * Returns remaining time if the sequence number has passed, 0 when
539 * the wait timeout, or an error for all other cases.
541 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool intr, long timeout)
543 u64 seq[RADEON_NUM_RINGS] = {};
548 * This function should not be called on !radeon fences.
549 * If this is the case, it would mean this function can
550 * also be called on radeon fences belonging to another card.
551 * exclusive_lock is not held in that case.
553 if (WARN_ON_ONCE(!to_radeon_fence(&fence->base)))
554 return fence_wait(&fence->base, intr);
556 seq[fence->ring] = fence->seq;
557 r = radeon_fence_wait_seq_timeout(fence->rdev, seq, intr, timeout);
562 r_sig = fence_signal(&fence->base);
564 FENCE_TRACE(&fence->base, "signaled from fence_wait\n");
569 * radeon_fence_wait - wait for a fence to signal
571 * @fence: radeon fence object
572 * @intr: use interruptible sleep
574 * Wait for the requested fence to signal (all asics).
575 * @intr selects whether to use interruptable (true) or non-interruptable
576 * (false) sleep when waiting for the fence.
577 * Returns 0 if the fence has passed, error for all other cases.
579 int radeon_fence_wait(struct radeon_fence *fence, bool intr)
581 long r = radeon_fence_wait_timeout(fence, intr, MAX_SCHEDULE_TIMEOUT);
590 * radeon_fence_wait_any - wait for a fence to signal on any ring
592 * @rdev: radeon device pointer
593 * @fences: radeon fence object(s)
594 * @intr: use interruptable sleep
596 * Wait for any requested fence to signal (all asics). Fence
597 * array is indexed by ring id. @intr selects whether to use
598 * interruptable (true) or non-interruptable (false) sleep when
599 * waiting for the fences. Used by the suballocator.
600 * Returns 0 if any fence has passed, error for all other cases.
602 int radeon_fence_wait_any(struct radeon_device *rdev,
603 struct radeon_fence **fences,
606 u64 seq[RADEON_NUM_RINGS];
607 unsigned i, num_rings = 0;
610 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
617 seq[i] = fences[i]->seq;
621 /* nothing to wait for ? */
625 r = radeon_fence_wait_seq_timeout(rdev, seq, intr, MAX_SCHEDULE_TIMEOUT);
633 * radeon_fence_wait_next - wait for the next fence to signal
635 * @rdev: radeon device pointer
636 * @ring: ring index the fence is associated with
638 * Wait for the next fence on the requested ring to signal (all asics).
639 * Returns 0 if the next fence has passed, error for all other cases.
640 * Caller must hold ring lock.
642 int radeon_fence_wait_next(struct radeon_device *rdev, int ring)
644 u64 seq[RADEON_NUM_RINGS] = {};
647 seq[ring] = atomic64_read(&rdev->fence_drv[ring].last_seq) + 1ULL;
648 if (seq[ring] >= rdev->fence_drv[ring].sync_seq[ring]) {
649 /* nothing to wait for, last_seq is
650 already the last emited fence */
653 r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);
660 * radeon_fence_wait_empty - wait for all fences to signal
662 * @rdev: radeon device pointer
663 * @ring: ring index the fence is associated with
665 * Wait for all fences on the requested ring to signal (all asics).
666 * Returns 0 if the fences have passed, error for all other cases.
667 * Caller must hold ring lock.
669 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring)
671 u64 seq[RADEON_NUM_RINGS] = {};
674 seq[ring] = rdev->fence_drv[ring].sync_seq[ring];
678 r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);
683 dev_err(rdev->dev, "error waiting for ring[%d] to become idle (%ld)\n",
690 * radeon_fence_ref - take a ref on a fence
692 * @fence: radeon fence object
694 * Take a reference on a fence (all asics).
697 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
699 fence_get(&fence->base);
704 * radeon_fence_unref - remove a ref on a fence
706 * @fence: radeon fence object
708 * Remove a reference on a fence (all asics).
710 void radeon_fence_unref(struct radeon_fence **fence)
712 struct radeon_fence *tmp = *fence;
716 fence_put(&tmp->base);
721 * radeon_fence_count_emitted - get the count of emitted fences
723 * @rdev: radeon device pointer
724 * @ring: ring index the fence is associated with
726 * Get the number of fences emitted on the requested ring (all asics).
727 * Returns the number of emitted fences on the ring. Used by the
728 * dynpm code to ring track activity.
730 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring)
734 /* We are not protected by ring lock when reading the last sequence
735 * but it's ok to report slightly wrong fence count here.
737 radeon_fence_process(rdev, ring);
738 emitted = rdev->fence_drv[ring].sync_seq[ring]
739 - atomic64_read(&rdev->fence_drv[ring].last_seq);
740 /* to avoid 32bits warp around */
741 if (emitted > 0x10000000) {
742 emitted = 0x10000000;
744 return (unsigned)emitted;
748 * radeon_fence_need_sync - do we need a semaphore
750 * @fence: radeon fence object
751 * @dst_ring: which ring to check against
753 * Check if the fence needs to be synced against another ring
754 * (all asics). If so, we need to emit a semaphore.
755 * Returns true if we need to sync with another ring, false if
758 bool radeon_fence_need_sync(struct radeon_fence *fence, int dst_ring)
760 struct radeon_fence_driver *fdrv;
766 if (fence->ring == dst_ring) {
770 /* we are protected by the ring mutex */
771 fdrv = &fence->rdev->fence_drv[dst_ring];
772 if (fence->seq <= fdrv->sync_seq[fence->ring]) {
780 * radeon_fence_note_sync - record the sync point
782 * @fence: radeon fence object
783 * @dst_ring: which ring to check against
785 * Note the sequence number at which point the fence will
786 * be synced with the requested ring (all asics).
788 void radeon_fence_note_sync(struct radeon_fence *fence, int dst_ring)
790 struct radeon_fence_driver *dst, *src;
797 if (fence->ring == dst_ring) {
801 /* we are protected by the ring mutex */
802 src = &fence->rdev->fence_drv[fence->ring];
803 dst = &fence->rdev->fence_drv[dst_ring];
804 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
808 dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);
813 * radeon_fence_driver_start_ring - make the fence driver
814 * ready for use on the requested ring.
816 * @rdev: radeon device pointer
817 * @ring: ring index to start the fence driver on
819 * Make the fence driver ready for processing (all asics).
820 * Not all asics have all rings, so each asic will only
821 * start the fence driver on the rings it has.
822 * Returns 0 for success, errors for failure.
824 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
829 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
830 if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) {
831 rdev->fence_drv[ring].scratch_reg = 0;
832 if (ring != R600_RING_TYPE_UVD_INDEX) {
833 index = R600_WB_EVENT_OFFSET + ring * 4;
834 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
835 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr +
839 /* put fence directly behind firmware */
840 index = ALIGN(rdev->uvd_fw->datasize, 8);
841 rdev->fence_drv[ring].cpu_addr = (void*)((uint8_t*)rdev->uvd.cpu_addr + index);
842 rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index;
846 r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
848 dev_err(rdev->dev, "fence failed to get scratch register\n");
851 index = RADEON_WB_SCRATCH_OFFSET +
852 rdev->fence_drv[ring].scratch_reg -
853 rdev->scratch.reg_base;
854 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
855 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
857 radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring);
858 rdev->fence_drv[ring].initialized = true;
859 dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016lx and cpu addr 0x%p\n",
860 ring, rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr);
865 * radeon_fence_driver_init_ring - init the fence driver
866 * for the requested ring.
868 * @rdev: radeon device pointer
869 * @ring: ring index to start the fence driver on
871 * Init the fence driver for the requested ring (all asics).
872 * Helper function for radeon_fence_driver_init().
874 static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)
878 rdev->fence_drv[ring].scratch_reg = -1;
879 rdev->fence_drv[ring].cpu_addr = NULL;
880 rdev->fence_drv[ring].gpu_addr = 0;
881 for (i = 0; i < RADEON_NUM_RINGS; ++i)
882 rdev->fence_drv[ring].sync_seq[i] = 0;
883 atomic64_set(&rdev->fence_drv[ring].last_seq, 0);
884 rdev->fence_drv[ring].initialized = false;
885 INIT_DELAYED_WORK(&rdev->fence_drv[ring].lockup_work,
886 radeon_fence_check_lockup);
887 rdev->fence_drv[ring].rdev = rdev;
891 * radeon_fence_driver_init - init the fence driver
892 * for all possible rings.
894 * @rdev: radeon device pointer
896 * Init the fence driver for all possible rings (all asics).
897 * Not all asics have all rings, so each asic will only
898 * start the fence driver on the rings it has using
899 * radeon_fence_driver_start_ring().
900 * Returns 0 for success.
902 int radeon_fence_driver_init(struct radeon_device *rdev)
906 init_waitqueue_head(&rdev->fence_queue);
907 for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
908 radeon_fence_driver_init_ring(rdev, ring);
910 if (radeon_debugfs_fence_init(rdev)) {
911 dev_err(rdev->dev, "fence debugfs file creation failed\n");
917 * radeon_fence_driver_fini - tear down the fence driver
918 * for all possible rings.
920 * @rdev: radeon device pointer
922 * Tear down the fence driver for all possible rings (all asics).
924 void radeon_fence_driver_fini(struct radeon_device *rdev)
928 mutex_lock(&rdev->ring_lock);
929 for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
930 if (!rdev->fence_drv[ring].initialized)
932 r = radeon_fence_wait_empty(rdev, ring);
934 /* no need to trigger GPU reset as we are unloading */
935 radeon_fence_driver_force_completion(rdev, ring);
937 cancel_delayed_work_sync(&rdev->fence_drv[ring].lockup_work);
938 wake_up_all(&rdev->fence_queue);
939 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
940 rdev->fence_drv[ring].initialized = false;
942 mutex_unlock(&rdev->ring_lock);
946 * radeon_fence_driver_force_completion - force all fence waiter to complete
948 * @rdev: radeon device pointer
949 * @ring: the ring to complete
951 * In case of GPU reset failure make sure no process keep waiting on fence
952 * that will never complete.
954 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring)
956 if (rdev->fence_drv[ring].initialized) {
957 radeon_fence_write(rdev, rdev->fence_drv[ring].sync_seq[ring], ring);
958 cancel_delayed_work_sync(&rdev->fence_drv[ring].lockup_work);
966 #if defined(CONFIG_DEBUG_FS)
967 static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
969 struct drm_info_node *node = (struct drm_info_node *)m->private;
970 struct drm_device *dev = node->minor->dev;
971 struct radeon_device *rdev = dev->dev_private;
974 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
975 if (!rdev->fence_drv[i].initialized)
978 radeon_fence_process(rdev, i);
980 seq_printf(m, "--- ring %d ---\n", i);
981 seq_printf(m, "Last signaled fence 0x%016llx\n",
982 (unsigned long long)atomic64_read(&rdev->fence_drv[i].last_seq));
983 seq_printf(m, "Last emitted 0x%016llx\n",
984 rdev->fence_drv[i].sync_seq[i]);
986 for (j = 0; j < RADEON_NUM_RINGS; ++j) {
987 if (i != j && rdev->fence_drv[j].initialized)
988 seq_printf(m, "Last sync to ring %d 0x%016llx\n",
989 j, rdev->fence_drv[i].sync_seq[j]);
996 * radeon_debugfs_gpu_reset - manually trigger a gpu reset
998 * Manually trigger a gpu reset at the next fence wait.
1000 static int radeon_debugfs_gpu_reset(struct seq_file *m, void *data)
1002 struct drm_info_node *node = (struct drm_info_node *) m->private;
1003 struct drm_device *dev = node->minor->dev;
1004 struct radeon_device *rdev = dev->dev_private;
1006 down_read(&rdev->exclusive_lock);
1007 seq_printf(m, "%d\n", rdev->needs_reset);
1008 rdev->needs_reset = true;
1009 wake_up_all(&rdev->fence_queue);
1010 up_read(&rdev->exclusive_lock);
1015 static struct drm_info_list radeon_debugfs_fence_list[] = {
1016 {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
1017 {"radeon_gpu_reset", &radeon_debugfs_gpu_reset, 0, NULL}
1021 int radeon_debugfs_fence_init(struct radeon_device *rdev)
1023 #if defined(CONFIG_DEBUG_FS)
1024 return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 2);
1030 static const char *radeon_fence_get_driver_name(struct fence *fence)
1035 static const char *radeon_fence_get_timeline_name(struct fence *f)
1037 struct radeon_fence *fence = to_radeon_fence(f);
1038 switch (fence->ring) {
1039 case RADEON_RING_TYPE_GFX_INDEX: return "radeon.gfx";
1040 case CAYMAN_RING_TYPE_CP1_INDEX: return "radeon.cp1";
1041 case CAYMAN_RING_TYPE_CP2_INDEX: return "radeon.cp2";
1042 case R600_RING_TYPE_DMA_INDEX: return "radeon.dma";
1043 case CAYMAN_RING_TYPE_DMA1_INDEX: return "radeon.dma1";
1044 case R600_RING_TYPE_UVD_INDEX: return "radeon.uvd";
1045 case TN_RING_TYPE_VCE1_INDEX: return "radeon.vce1";
1046 case TN_RING_TYPE_VCE2_INDEX: return "radeon.vce2";
1047 default: WARN_ON_ONCE(1); return "radeon.unk";
1051 static inline bool radeon_test_signaled(struct radeon_fence *fence)
1053 return test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags);
1056 struct radeon_wait_cb {
1057 struct fence_cb base;
1058 struct task_struct *task;
1062 radeon_fence_wait_cb(struct fence *fence, struct fence_cb *cb)
1064 struct radeon_wait_cb *wait =
1065 container_of(cb, struct radeon_wait_cb, base);
1067 wake_up_process(wait->task);
1070 static signed long radeon_fence_default_wait(struct fence *f, bool intr,
1073 struct radeon_fence *fence = to_radeon_fence(f);
1074 struct radeon_device *rdev = fence->rdev;
1075 struct radeon_wait_cb cb;
1079 if (fence_add_callback(f, &cb.base, radeon_fence_wait_cb))
1084 set_current_state(TASK_INTERRUPTIBLE);
1086 set_current_state(TASK_UNINTERRUPTIBLE);
1089 * radeon_test_signaled must be called after
1090 * set_current_state to prevent a race with wake_up_process
1092 if (radeon_test_signaled(fence))
1095 if (rdev->needs_reset) {
1100 t = schedule_timeout(t);
1102 if (t > 0 && intr && signal_pending(current))
1106 __set_current_state(TASK_RUNNING);
1107 fence_remove_callback(f, &cb.base);
1112 const struct fence_ops radeon_fence_ops = {
1113 .get_driver_name = radeon_fence_get_driver_name,
1114 .get_timeline_name = radeon_fence_get_timeline_name,
1115 .enable_signaling = radeon_fence_enable_signaling,
1116 .signaled = radeon_fence_is_signaled,
1117 .wait = radeon_fence_default_wait,